[PATCH v8 5/7] dt-bindings: Add header file of hi6220 clock driver
Add the header file "hi6220-clock.h" used by both hi6220 clock driver and hi6220 device tree file. Suggested-by: Stephen Boyd Signed-off-by: Bintian Wang Tested-by: Will Deacon Tested-by: Tyler Baker Tested-by: Kevin Hilman --- include/dt-bindings/clock/hi6220-clock.h | 173 +++ 1 file changed, 173 insertions(+) create mode 100644 include/dt-bindings/clock/hi6220-clock.h diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h new file mode 100644 index 000..70ee383 --- /dev/null +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Bintian Wang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI6220_H +#define __DT_BINDINGS_CLOCK_HI6220_H + +/* clk in Hi6220 AO (always on) controller */ +#define HI6220_NONE_CLOCK 0 + +/* fixed rate clocks */ +#define HI6220_REF32K 1 +#define HI6220_CLK_TCXO2 +#define HI6220_MMC1_PAD3 +#define HI6220_MMC2_PAD4 +#define HI6220_MMC0_PAD5 +#define HI6220_PLL_BBP 6 +#define HI6220_PLL_GPU 7 +#define HI6220_PLL1_DDR8 +#define HI6220_PLL_SYS 9 +#define HI6220_PLL_SYS_MEDIA 10 +#define HI6220_DDR_SRC 11 +#define HI6220_PLL_MEDIA 12 +#define HI6220_PLL_DDR 13 + +/* fixed factor clocks */ +#define HI6220_300M14 +#define HI6220_150M15 +#define HI6220_PICOPHY_SRC 16 +#define HI6220_MMC0_SRC_SEL17 +#define HI6220_MMC1_SRC_SEL18 +#define HI6220_MMC2_SRC_SEL19 +#define HI6220_VPU_CODEC 20 +#define HI6220_MMC0_SMP21 +#define HI6220_MMC1_SMP22 +#define HI6220_MMC2_SMP23 + +/* gate clocks */ +#define HI6220_WDT0_PCLK 24 +#define HI6220_WDT1_PCLK 25 +#define HI6220_WDT2_PCLK 26 +#define HI6220_TIMER0_PCLK 27 +#define HI6220_TIMER1_PCLK 28 +#define HI6220_TIMER2_PCLK 29 +#define HI6220_TIMER3_PCLK 30 +#define HI6220_TIMER4_PCLK 31 +#define HI6220_TIMER5_PCLK 32 +#define HI6220_TIMER6_PCLK 33 +#define HI6220_TIMER7_PCLK 34 +#define HI6220_TIMER8_PCLK 35 +#define HI6220_UART0_PCLK 36 + +#define HI6220_AO_NR_CLKS 37 + +/* clk in Hi6220 systrl */ +/* gate clock */ +#define HI6220_MMC0_CLK1 +#define HI6220_MMC0_CIUCLK 2 +#define HI6220_MMC1_CLK3 +#define HI6220_MMC1_CIUCLK 4 +#define HI6220_MMC2_CLK5 +#define HI6220_MMC2_CIUCLK 6 +#define HI6220_USBOTG_HCLK 7 +#define HI6220_CLK_PICOPHY 8 +#define HI6220_HIFI9 +#define HI6220_DACODEC_PCLK10 +#define HI6220_EDMAC_ACLK 11 +#define HI6220_CS_ATB 12 +#define HI6220_I2C0_CLK13 +#define HI6220_I2C1_CLK14 +#define HI6220_I2C2_CLK15 +#define HI6220_I2C3_CLK16 +#define HI6220_UART1_PCLK 17 +#define HI6220_UART2_PCLK 18 +#define HI6220_UART3_PCLK 19 +#define HI6220_UART4_PCLK 20 +#define HI6220_SPI_CLK 21 +#define HI6220_TSENSOR_CLK 22 +#define HI6220_MMU_CLK 23 +#define HI6220_HIFI_SEL24 +#define HI6220_MMC0_SYSPLL 25 +#define HI6220_MMC1_SYSPLL 26 +#define HI6220_MMC2_SYSPLL 27 +#define HI6220_MMC0_SEL28 +#define HI6220_MMC1_SEL29 +#define HI6220_BBPPLL_SEL 30 +#define HI6220_MEDIA_PLL_SRC 31 +#define HI6220_MMC2_SEL32 +#define HI6220_CS_ATB_SYSPLL 33 + +/* mux clocks */ +#define HI6220_MMC0_SRC34 +#define HI6220_MMC0_SMP_IN 35 +#define HI6220_MMC1_SRC36 +#define HI6220_MMC1_SMP_IN 37 +#define HI6220_MMC2_SRC38 +#define HI6220_MMC2_SMP_IN 39 +#define HI6220_HIFI_SRC40 +#define HI6220_UART1_SRC 41 +#define HI6220_UART2_SRC 42 +#define HI6220_UART3_SRC 43 +#define HI6220_UART4_SRC 44 +#define HI6220_MMC0_MUX0 45 +#define HI6220_MMC1_MUX0 46 +#define HI6220_MMC2_MUX0 47 +#define HI6220_MMC0_MUX1 48 +#define HI6220_MMC1_MUX1 49 +#define HI6220_MMC2_MUX1 50 + +/* divider clocks */ +#define HI6220_CLK_BUS 51 +#define HI6220_MMC0_DIV52 +#define HI6220_MMC1_DIV53 +#define HI6220_MMC2_DIV54 +#define HI6220_HIFI_DIV55 +#define HI6220_BBPPLL0_DIV 56 +#define HI6220_CS_DAPB 57 +#define HI6220_CS_ATB_DIV 58 + +#define HI6220_SYS_NR_CLKS 59 + +/* clk in Hi6220 media controller */ +/* gate clocks */ +#define HI6220_DSI_PCLK1 +#define HI6220_G3D_PCLK2 +#define HI6220_ACLK_CODEC_VPU 3 +#define
[PATCH v8 5/7] dt-bindings: Add header file of hi6220 clock driver
Add the header file hi6220-clock.h used by both hi6220 clock driver and hi6220 device tree file. Suggested-by: Stephen Boyd sb...@codeaurora.org Signed-off-by: Bintian Wang bintian.w...@huawei.com Tested-by: Will Deacon will.dea...@arm.com Tested-by: Tyler Baker tyler.ba...@linaro.org Tested-by: Kevin Hilman khil...@linaro.org --- include/dt-bindings/clock/hi6220-clock.h | 173 +++ 1 file changed, 173 insertions(+) create mode 100644 include/dt-bindings/clock/hi6220-clock.h diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h new file mode 100644 index 000..70ee383 --- /dev/null +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Bintian Wang bintian.w...@huawei.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI6220_H +#define __DT_BINDINGS_CLOCK_HI6220_H + +/* clk in Hi6220 AO (always on) controller */ +#define HI6220_NONE_CLOCK 0 + +/* fixed rate clocks */ +#define HI6220_REF32K 1 +#define HI6220_CLK_TCXO2 +#define HI6220_MMC1_PAD3 +#define HI6220_MMC2_PAD4 +#define HI6220_MMC0_PAD5 +#define HI6220_PLL_BBP 6 +#define HI6220_PLL_GPU 7 +#define HI6220_PLL1_DDR8 +#define HI6220_PLL_SYS 9 +#define HI6220_PLL_SYS_MEDIA 10 +#define HI6220_DDR_SRC 11 +#define HI6220_PLL_MEDIA 12 +#define HI6220_PLL_DDR 13 + +/* fixed factor clocks */ +#define HI6220_300M14 +#define HI6220_150M15 +#define HI6220_PICOPHY_SRC 16 +#define HI6220_MMC0_SRC_SEL17 +#define HI6220_MMC1_SRC_SEL18 +#define HI6220_MMC2_SRC_SEL19 +#define HI6220_VPU_CODEC 20 +#define HI6220_MMC0_SMP21 +#define HI6220_MMC1_SMP22 +#define HI6220_MMC2_SMP23 + +/* gate clocks */ +#define HI6220_WDT0_PCLK 24 +#define HI6220_WDT1_PCLK 25 +#define HI6220_WDT2_PCLK 26 +#define HI6220_TIMER0_PCLK 27 +#define HI6220_TIMER1_PCLK 28 +#define HI6220_TIMER2_PCLK 29 +#define HI6220_TIMER3_PCLK 30 +#define HI6220_TIMER4_PCLK 31 +#define HI6220_TIMER5_PCLK 32 +#define HI6220_TIMER6_PCLK 33 +#define HI6220_TIMER7_PCLK 34 +#define HI6220_TIMER8_PCLK 35 +#define HI6220_UART0_PCLK 36 + +#define HI6220_AO_NR_CLKS 37 + +/* clk in Hi6220 systrl */ +/* gate clock */ +#define HI6220_MMC0_CLK1 +#define HI6220_MMC0_CIUCLK 2 +#define HI6220_MMC1_CLK3 +#define HI6220_MMC1_CIUCLK 4 +#define HI6220_MMC2_CLK5 +#define HI6220_MMC2_CIUCLK 6 +#define HI6220_USBOTG_HCLK 7 +#define HI6220_CLK_PICOPHY 8 +#define HI6220_HIFI9 +#define HI6220_DACODEC_PCLK10 +#define HI6220_EDMAC_ACLK 11 +#define HI6220_CS_ATB 12 +#define HI6220_I2C0_CLK13 +#define HI6220_I2C1_CLK14 +#define HI6220_I2C2_CLK15 +#define HI6220_I2C3_CLK16 +#define HI6220_UART1_PCLK 17 +#define HI6220_UART2_PCLK 18 +#define HI6220_UART3_PCLK 19 +#define HI6220_UART4_PCLK 20 +#define HI6220_SPI_CLK 21 +#define HI6220_TSENSOR_CLK 22 +#define HI6220_MMU_CLK 23 +#define HI6220_HIFI_SEL24 +#define HI6220_MMC0_SYSPLL 25 +#define HI6220_MMC1_SYSPLL 26 +#define HI6220_MMC2_SYSPLL 27 +#define HI6220_MMC0_SEL28 +#define HI6220_MMC1_SEL29 +#define HI6220_BBPPLL_SEL 30 +#define HI6220_MEDIA_PLL_SRC 31 +#define HI6220_MMC2_SEL32 +#define HI6220_CS_ATB_SYSPLL 33 + +/* mux clocks */ +#define HI6220_MMC0_SRC34 +#define HI6220_MMC0_SMP_IN 35 +#define HI6220_MMC1_SRC36 +#define HI6220_MMC1_SMP_IN 37 +#define HI6220_MMC2_SRC38 +#define HI6220_MMC2_SMP_IN 39 +#define HI6220_HIFI_SRC40 +#define HI6220_UART1_SRC 41 +#define HI6220_UART2_SRC 42 +#define HI6220_UART3_SRC 43 +#define HI6220_UART4_SRC 44 +#define HI6220_MMC0_MUX0 45 +#define HI6220_MMC1_MUX0 46 +#define HI6220_MMC2_MUX0 47 +#define HI6220_MMC0_MUX1 48 +#define HI6220_MMC1_MUX1 49 +#define HI6220_MMC2_MUX1 50 + +/* divider clocks */ +#define HI6220_CLK_BUS 51 +#define HI6220_MMC0_DIV52 +#define HI6220_MMC1_DIV53 +#define HI6220_MMC2_DIV54 +#define HI6220_HIFI_DIV55 +#define HI6220_BBPPLL0_DIV 56 +#define HI6220_CS_DAPB 57 +#define HI6220_CS_ATB_DIV 58 + +#define HI6220_SYS_NR_CLKS 59 + +/* clk in Hi6220 media controller */ +/* gate clocks */ +#define
[PATCH v8 5/7] dt-bindings: Add header file of hi6220 clock driver
Add the header file "hi6220-clock.h" used by both hi6220 clock driver and hi6220 device tree file. Suggested-by: Stephen Boyd Signed-off-by: Bintian Wang --- include/dt-bindings/clock/hi6220-clock.h | 173 +++ 1 file changed, 173 insertions(+) create mode 100644 include/dt-bindings/clock/hi6220-clock.h diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h new file mode 100644 index 000..70ee383 --- /dev/null +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Bintian Wang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI6220_H +#define __DT_BINDINGS_CLOCK_HI6220_H + +/* clk in Hi6220 AO (always on) controller */ +#define HI6220_NONE_CLOCK 0 + +/* fixed rate clocks */ +#define HI6220_REF32K 1 +#define HI6220_CLK_TCXO2 +#define HI6220_MMC1_PAD3 +#define HI6220_MMC2_PAD4 +#define HI6220_MMC0_PAD5 +#define HI6220_PLL_BBP 6 +#define HI6220_PLL_GPU 7 +#define HI6220_PLL1_DDR8 +#define HI6220_PLL_SYS 9 +#define HI6220_PLL_SYS_MEDIA 10 +#define HI6220_DDR_SRC 11 +#define HI6220_PLL_MEDIA 12 +#define HI6220_PLL_DDR 13 + +/* fixed factor clocks */ +#define HI6220_300M14 +#define HI6220_150M15 +#define HI6220_PICOPHY_SRC 16 +#define HI6220_MMC0_SRC_SEL17 +#define HI6220_MMC1_SRC_SEL18 +#define HI6220_MMC2_SRC_SEL19 +#define HI6220_VPU_CODEC 20 +#define HI6220_MMC0_SMP21 +#define HI6220_MMC1_SMP22 +#define HI6220_MMC2_SMP23 + +/* gate clocks */ +#define HI6220_WDT0_PCLK 24 +#define HI6220_WDT1_PCLK 25 +#define HI6220_WDT2_PCLK 26 +#define HI6220_TIMER0_PCLK 27 +#define HI6220_TIMER1_PCLK 28 +#define HI6220_TIMER2_PCLK 29 +#define HI6220_TIMER3_PCLK 30 +#define HI6220_TIMER4_PCLK 31 +#define HI6220_TIMER5_PCLK 32 +#define HI6220_TIMER6_PCLK 33 +#define HI6220_TIMER7_PCLK 34 +#define HI6220_TIMER8_PCLK 35 +#define HI6220_UART0_PCLK 36 + +#define HI6220_AO_NR_CLKS 37 + +/* clk in Hi6220 systrl */ +/* gate clock */ +#define HI6220_MMC0_CLK1 +#define HI6220_MMC0_CIUCLK 2 +#define HI6220_MMC1_CLK3 +#define HI6220_MMC1_CIUCLK 4 +#define HI6220_MMC2_CLK5 +#define HI6220_MMC2_CIUCLK 6 +#define HI6220_USBOTG_HCLK 7 +#define HI6220_CLK_PICOPHY 8 +#define HI6220_HIFI9 +#define HI6220_DACODEC_PCLK10 +#define HI6220_EDMAC_ACLK 11 +#define HI6220_CS_ATB 12 +#define HI6220_I2C0_CLK13 +#define HI6220_I2C1_CLK14 +#define HI6220_I2C2_CLK15 +#define HI6220_I2C3_CLK16 +#define HI6220_UART1_PCLK 17 +#define HI6220_UART2_PCLK 18 +#define HI6220_UART3_PCLK 19 +#define HI6220_UART4_PCLK 20 +#define HI6220_SPI_CLK 21 +#define HI6220_TSENSOR_CLK 22 +#define HI6220_MMU_CLK 23 +#define HI6220_HIFI_SEL24 +#define HI6220_MMC0_SYSPLL 25 +#define HI6220_MMC1_SYSPLL 26 +#define HI6220_MMC2_SYSPLL 27 +#define HI6220_MMC0_SEL28 +#define HI6220_MMC1_SEL29 +#define HI6220_BBPPLL_SEL 30 +#define HI6220_MEDIA_PLL_SRC 31 +#define HI6220_MMC2_SEL32 +#define HI6220_CS_ATB_SYSPLL 33 + +/* mux clocks */ +#define HI6220_MMC0_SRC34 +#define HI6220_MMC0_SMP_IN 35 +#define HI6220_MMC1_SRC36 +#define HI6220_MMC1_SMP_IN 37 +#define HI6220_MMC2_SRC38 +#define HI6220_MMC2_SMP_IN 39 +#define HI6220_HIFI_SRC40 +#define HI6220_UART1_SRC 41 +#define HI6220_UART2_SRC 42 +#define HI6220_UART3_SRC 43 +#define HI6220_UART4_SRC 44 +#define HI6220_MMC0_MUX0 45 +#define HI6220_MMC1_MUX0 46 +#define HI6220_MMC2_MUX0 47 +#define HI6220_MMC0_MUX1 48 +#define HI6220_MMC1_MUX1 49 +#define HI6220_MMC2_MUX1 50 + +/* divider clocks */ +#define HI6220_CLK_BUS 51 +#define HI6220_MMC0_DIV52 +#define HI6220_MMC1_DIV53 +#define HI6220_MMC2_DIV54 +#define HI6220_HIFI_DIV55 +#define HI6220_BBPPLL0_DIV 56 +#define HI6220_CS_DAPB 57 +#define HI6220_CS_ATB_DIV 58 + +#define HI6220_SYS_NR_CLKS 59 + +/* clk in Hi6220 media controller */ +/* gate clocks */ +#define HI6220_DSI_PCLK1 +#define HI6220_G3D_PCLK2 +#define HI6220_ACLK_CODEC_VPU 3 +#define HI6220_ISP_SCLK4 +#define HI6220_ADE_CORE5 +#define
[PATCH v8 5/7] dt-bindings: Add header file of hi6220 clock driver
Add the header file hi6220-clock.h used by both hi6220 clock driver and hi6220 device tree file. Suggested-by: Stephen Boyd sb...@codeaurora.org Signed-off-by: Bintian Wang bintian.w...@huawei.com --- include/dt-bindings/clock/hi6220-clock.h | 173 +++ 1 file changed, 173 insertions(+) create mode 100644 include/dt-bindings/clock/hi6220-clock.h diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h new file mode 100644 index 000..70ee383 --- /dev/null +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Bintian Wang bintian.w...@huawei.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI6220_H +#define __DT_BINDINGS_CLOCK_HI6220_H + +/* clk in Hi6220 AO (always on) controller */ +#define HI6220_NONE_CLOCK 0 + +/* fixed rate clocks */ +#define HI6220_REF32K 1 +#define HI6220_CLK_TCXO2 +#define HI6220_MMC1_PAD3 +#define HI6220_MMC2_PAD4 +#define HI6220_MMC0_PAD5 +#define HI6220_PLL_BBP 6 +#define HI6220_PLL_GPU 7 +#define HI6220_PLL1_DDR8 +#define HI6220_PLL_SYS 9 +#define HI6220_PLL_SYS_MEDIA 10 +#define HI6220_DDR_SRC 11 +#define HI6220_PLL_MEDIA 12 +#define HI6220_PLL_DDR 13 + +/* fixed factor clocks */ +#define HI6220_300M14 +#define HI6220_150M15 +#define HI6220_PICOPHY_SRC 16 +#define HI6220_MMC0_SRC_SEL17 +#define HI6220_MMC1_SRC_SEL18 +#define HI6220_MMC2_SRC_SEL19 +#define HI6220_VPU_CODEC 20 +#define HI6220_MMC0_SMP21 +#define HI6220_MMC1_SMP22 +#define HI6220_MMC2_SMP23 + +/* gate clocks */ +#define HI6220_WDT0_PCLK 24 +#define HI6220_WDT1_PCLK 25 +#define HI6220_WDT2_PCLK 26 +#define HI6220_TIMER0_PCLK 27 +#define HI6220_TIMER1_PCLK 28 +#define HI6220_TIMER2_PCLK 29 +#define HI6220_TIMER3_PCLK 30 +#define HI6220_TIMER4_PCLK 31 +#define HI6220_TIMER5_PCLK 32 +#define HI6220_TIMER6_PCLK 33 +#define HI6220_TIMER7_PCLK 34 +#define HI6220_TIMER8_PCLK 35 +#define HI6220_UART0_PCLK 36 + +#define HI6220_AO_NR_CLKS 37 + +/* clk in Hi6220 systrl */ +/* gate clock */ +#define HI6220_MMC0_CLK1 +#define HI6220_MMC0_CIUCLK 2 +#define HI6220_MMC1_CLK3 +#define HI6220_MMC1_CIUCLK 4 +#define HI6220_MMC2_CLK5 +#define HI6220_MMC2_CIUCLK 6 +#define HI6220_USBOTG_HCLK 7 +#define HI6220_CLK_PICOPHY 8 +#define HI6220_HIFI9 +#define HI6220_DACODEC_PCLK10 +#define HI6220_EDMAC_ACLK 11 +#define HI6220_CS_ATB 12 +#define HI6220_I2C0_CLK13 +#define HI6220_I2C1_CLK14 +#define HI6220_I2C2_CLK15 +#define HI6220_I2C3_CLK16 +#define HI6220_UART1_PCLK 17 +#define HI6220_UART2_PCLK 18 +#define HI6220_UART3_PCLK 19 +#define HI6220_UART4_PCLK 20 +#define HI6220_SPI_CLK 21 +#define HI6220_TSENSOR_CLK 22 +#define HI6220_MMU_CLK 23 +#define HI6220_HIFI_SEL24 +#define HI6220_MMC0_SYSPLL 25 +#define HI6220_MMC1_SYSPLL 26 +#define HI6220_MMC2_SYSPLL 27 +#define HI6220_MMC0_SEL28 +#define HI6220_MMC1_SEL29 +#define HI6220_BBPPLL_SEL 30 +#define HI6220_MEDIA_PLL_SRC 31 +#define HI6220_MMC2_SEL32 +#define HI6220_CS_ATB_SYSPLL 33 + +/* mux clocks */ +#define HI6220_MMC0_SRC34 +#define HI6220_MMC0_SMP_IN 35 +#define HI6220_MMC1_SRC36 +#define HI6220_MMC1_SMP_IN 37 +#define HI6220_MMC2_SRC38 +#define HI6220_MMC2_SMP_IN 39 +#define HI6220_HIFI_SRC40 +#define HI6220_UART1_SRC 41 +#define HI6220_UART2_SRC 42 +#define HI6220_UART3_SRC 43 +#define HI6220_UART4_SRC 44 +#define HI6220_MMC0_MUX0 45 +#define HI6220_MMC1_MUX0 46 +#define HI6220_MMC2_MUX0 47 +#define HI6220_MMC0_MUX1 48 +#define HI6220_MMC1_MUX1 49 +#define HI6220_MMC2_MUX1 50 + +/* divider clocks */ +#define HI6220_CLK_BUS 51 +#define HI6220_MMC0_DIV52 +#define HI6220_MMC1_DIV53 +#define HI6220_MMC2_DIV54 +#define HI6220_HIFI_DIV55 +#define HI6220_BBPPLL0_DIV 56 +#define HI6220_CS_DAPB 57 +#define HI6220_CS_ATB_DIV 58 + +#define HI6220_SYS_NR_CLKS 59 + +/* clk in Hi6220 media controller */ +/* gate clocks */ +#define HI6220_DSI_PCLK1 +#define HI6220_G3D_PCLK2 +#define HI6220_ACLK_CODEC_VPU 3 +#define HI6220_ISP_SCLK
