Re: [PATCH v8 6/7] arm64: dts: add dts nodes for MT6779
On 21/07/2020 08:00, Hanks Chen wrote:
On Mon, 2020-07-20 at 18:13 +0200, Matthias Brugger wrote:
On 16/07/2020 06:04, Hanks Chen wrote:
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt6779-uart",
+"mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = ;
+ clocks = <>, <_ao CLK_INFRA_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
Devicetree describes the HW we have. As far as I know, we have 4 UARTs on
MT6779. So we should list them all here.
Actually, We have only 3 UARTs HW on MT6779, but have 4 UART clk in
header file of clk.
Correct, I got confused by the four clocks.
With that clarified I'm fine with the patch and will take it as soon as the
clock driver patch is accepted.
Regards,
Matthias
Got it, I send a new serial to fix the redundant UART clk
https://lkml.org/lkml/2020/7/21/45
Ok, also I was talking about:
[PATCH v8 7/7] clk: mediatek: add UART0 clock support
Regards,
Matthias
Re: [PATCH v8 6/7] arm64: dts: add dts nodes for MT6779
On Mon, 2020-07-20 at 18:13 +0200, Matthias Brugger wrote:
>
> On 16/07/2020 06:04, Hanks Chen wrote:
> > On Tue, 2020-07-14 at 20:14 +0200, Matthias Brugger wrote:
> >>
> >> On 14/07/2020 11:20, Hanks Chen wrote:
> >>> this adds initial MT6779 dts settings for board support,
> >>> including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
> >>>
> >>> Signed-off-by: Hanks Chen
> >>> ---
> >>>arch/arm64/boot/dts/mediatek/Makefile | 1 +
> >>>arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
> >>>arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271
> >>>3 files changed, 303 insertions(+)
> >>>create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> >>>create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
> >>>
> >> [...]
> >>> +
> >>> + uart0: serial@11002000 {
> >>> + compatible = "mediatek,mt6779-uart",
> >>> + "mediatek,mt6577-uart";
> >>> + reg = <0 0x11002000 0 0x400>;
> >>> + interrupts = ;
> >>> + clocks = <>, <_ao CLK_INFRA_UART0>;
> >>> + clock-names = "baud", "bus";
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + uart1: serial@11003000 {
> >>> + compatible = "mediatek,mt6779-uart",
> >>> + "mediatek,mt6577-uart";
> >>> + reg = <0 0x11003000 0 0x400>;
> >>> + interrupts = ;
> >>> + clocks = <>, <_ao CLK_INFRA_UART1>;
> >>> + clock-names = "baud", "bus";
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + uart2: serial@11004000 {
> >>> + compatible = "mediatek,mt6779-uart",
> >>> + "mediatek,mt6577-uart";
> >>> + reg = <0 0x11004000 0 0x400>;
> >>> + interrupts = ;
> >>> + clocks = <>, <_ao CLK_INFRA_UART2>;
> >>> + clock-names = "baud", "bus";
> >>> + status = "disabled";
> >>> + };
> >>
> >> Devicetree describes the HW we have. As far as I know, we have 4 UARTs on
> >> MT6779. So we should list them all here.
> >>
> >
> > Actually, We have only 3 UARTs HW on MT6779, but have 4 UART clk in
> > header file of clk.
>
> Correct, I got confused by the four clocks.
> With that clarified I'm fine with the patch and will take it as soon as the
> clock driver patch is accepted.
>
> Regards,
> Matthias
>
Got it, I send a new serial to fix the redundant UART clk
https://lkml.org/lkml/2020/7/21/45
Thanks
Hanks Chen
> > CLK_INFRA_UART3 is a dummy clk interface, it has no effect on the
> > operation of the read/write instruction.
> >
> > If you think it is not good, I can remove it in the header file of clk.
> >
> > Thanks
> >
> >> Regards,
> >> Matthias
> >
Re: [PATCH v8 6/7] arm64: dts: add dts nodes for MT6779
On 16/07/2020 06:04, Hanks Chen wrote:
On Tue, 2020-07-14 at 20:14 +0200, Matthias Brugger wrote:
On 14/07/2020 11:20, Hanks Chen wrote:
this adds initial MT6779 dts settings for board support,
including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
Signed-off-by: Hanks Chen
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271
3 files changed, 303 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
[...]
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt6779-uart",
+"mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = ;
+ clocks = <>, <_ao CLK_INFRA_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt6779-uart",
+"mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = ;
+ clocks = <>, <_ao CLK_INFRA_UART1>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt6779-uart",
+"mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = ;
+ clocks = <>, <_ao CLK_INFRA_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
Devicetree describes the HW we have. As far as I know, we have 4 UARTs on
MT6779. So we should list them all here.
Actually, We have only 3 UARTs HW on MT6779, but have 4 UART clk in
header file of clk.
Correct, I got confused by the four clocks.
With that clarified I'm fine with the patch and will take it as soon as the
clock driver patch is accepted.
Regards,
Matthias
CLK_INFRA_UART3 is a dummy clk interface, it has no effect on the
operation of the read/write instruction.
If you think it is not good, I can remove it in the header file of clk.
Thanks
Regards,
Matthias
Re: [PATCH v8 6/7] arm64: dts: add dts nodes for MT6779
On Tue, 2020-07-14 at 20:14 +0200, Matthias Brugger wrote:
>
> On 14/07/2020 11:20, Hanks Chen wrote:
> > this adds initial MT6779 dts settings for board support,
> > including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
> >
> > Signed-off-by: Hanks Chen
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
> > arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271
> > 3 files changed, 303 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
> >
> [...]
> > +
> > + uart0: serial@11002000 {
> > + compatible = "mediatek,mt6779-uart",
> > +"mediatek,mt6577-uart";
> > + reg = <0 0x11002000 0 0x400>;
> > + interrupts = ;
> > + clocks = <>, <_ao CLK_INFRA_UART0>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + uart1: serial@11003000 {
> > + compatible = "mediatek,mt6779-uart",
> > +"mediatek,mt6577-uart";
> > + reg = <0 0x11003000 0 0x400>;
> > + interrupts = ;
> > + clocks = <>, <_ao CLK_INFRA_UART1>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@11004000 {
> > + compatible = "mediatek,mt6779-uart",
> > +"mediatek,mt6577-uart";
> > + reg = <0 0x11004000 0 0x400>;
> > + interrupts = ;
> > + clocks = <>, <_ao CLK_INFRA_UART2>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
>
> Devicetree describes the HW we have. As far as I know, we have 4 UARTs on
> MT6779. So we should list them all here.
>
Actually, We have only 3 UARTs HW on MT6779, but have 4 UART clk in
header file of clk.
CLK_INFRA_UART3 is a dummy clk interface, it has no effect on the
operation of the read/write instruction.
If you think it is not good, I can remove it in the header file of clk.
Thanks
> Regards,
> Matthias
Re: [PATCH v8 6/7] arm64: dts: add dts nodes for MT6779
On 14/07/2020 11:20, Hanks Chen wrote:
this adds initial MT6779 dts settings for board support,
including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
Signed-off-by: Hanks Chen
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271
3 files changed, 303 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
[...]
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt6779-uart",
+"mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = ;
+ clocks = <>, <_ao CLK_INFRA_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt6779-uart",
+"mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = ;
+ clocks = <>, <_ao CLK_INFRA_UART1>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt6779-uart",
+"mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = ;
+ clocks = <>, <_ao CLK_INFRA_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
Devicetree describes the HW we have. As far as I know, we have 4 UARTs on
MT6779. So we should list them all here.
Regards,
Matthias
[PATCH v8 6/7] arm64: dts: add dts nodes for MT6779
this adds initial MT6779 dts settings for board support,
including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
Signed-off-by: Hanks Chen
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
arch/arm64/boot/dts/mediatek/mt6779.dtsi| 271
3 files changed, 303 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile
b/arch/arm64/boot/dts/mediatek/Makefile
index a57af9da9f5c..4d1b0f9d8d1c 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
new file mode 100644
index ..164f5cbb3821
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+/dts-v1/;
+#include "mt6779.dtsi"
+
+/ {
+ model = "MediaTek MT6779 EVB";
+ compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x1e80>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
new file mode 100644
index ..370f309d32de
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt6779";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x200>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x300>;
+ };
+
+ cpu4: cpu@4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x400>;
+ };
+
+ cpu5: cpu@5 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x500>;
+ };
+
+ cpu6: cpu@6 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x600>;
+ };
+
+ cpu7: cpu@7 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x700>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupt-parent = <>;
+ interrupts = ;
+ };
+
+ clk26m: oscillator@0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator@1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
