Re: [PATCHv2 3/5] clk: samsung: exynos5410: Add suspend/resume handling
Hi Humberto, On 31.07.2014 13:22, Humberto Silva Naves wrote: > This patch implements all the necessary code that handles register > saving and restoring during a suspend/resume cycle. To make this > possible, the local variable reg_base from the function > exynos5410_clk_init was changed to global. In addition, new > clock register definitions were added for the majority of the relevant > clocks inside the SoC. > > Signed-off-by: Humberto Silva Naves > --- > drivers/clk/samsung/clk-exynos5410.c | 231 > +- > 1 file changed, 228 insertions(+), 3 deletions(-) Looks good, thanks. Since this patch depends on previous ones from this series, I'll wait for next revision (+some time to let people see the patches) before applying. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCHv2 3/5] clk: samsung: exynos5410: Add suspend/resume handling
This patch implements all the necessary code that handles register saving and restoring during a suspend/resume cycle. To make this possible, the local variable reg_base from the function exynos5410_clk_init was changed to global. In addition, new clock register definitions were added for the majority of the relevant clocks inside the SoC. Signed-off-by: Humberto Silva Naves --- drivers/clk/samsung/clk-exynos5410.c | 231 +- 1 file changed, 228 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index 92c56b7..a9c261c 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "clk.h" @@ -24,38 +25,134 @@ #define MPLL_LOCK 0x4000 #define MPLL_CON0 0x4100 #define CPLL_LOCK 0x10020 +#define DPLL_LOCK 0x10030 +#define EPLL_LOCK 0x10040 +#define VPLL_LOCK 0x10050 +#define IPLL_LOCK 0x10060 #define CPLL_CON0 0x10120 +#define CPLL_CON1 0x10124 +#define DPLL_CON0 0x10128 +#define DPLL_CON1 0x1012C +#define EPLL_CON0 0x10130 +#define EPLL_CON1 0x10134 +#define EPLL_CON2 0x10138 +#define VPLL_CON0 0x10140 +#define VPLL_CON1 0x10144 +#define VPLL_CON2 0x10148 +#define IPLL_CON0 0x10150 +#define IPLL_CON1 0x10154 #define BPLL_LOCK 0x20010 #define BPLL_CON0 0x20110 #define KPLL_LOCK 0x28000 #define KPLL_CON0 0x28100 #define SRC_CPU0x200 +#define SRC_CPERI0 0x4200 #define SRC_CPERI1 0x4204 #define SRC_TOP0 0x10210 #define SRC_TOP1 0x10214 #define SRC_TOP2 0x10218 +#define SRC_TOP3 0x1021C +#define SRC_GSCL 0x10220 +#define SRC_DISP0_00x10224 +#define SRC_DISP0_10x10228 +#define SRC_DISP1_00x1022C +#define SRC_DISP1_10x10230 +#define SRC_MAU0x10240 #define SRC_FSYS 0x10244 #define SRC_PERIC0 0x10250 +#define SRC_PERIC1 0x10254 #define SRC_CDREX 0x20200 #define SRC_KFC0x28200 +#define SRC_MASK_TOP 0x10310 +#define SRC_MASK_GSCL 0x10320 +#define SRC_MASK_DISP0_0 0x10324 +#define SRC_MASK_DISP0_1 0x10328 +#define SRC_MASK_DISP1_0 0x1032C +#define SRC_MASK_DISP1_1 0x10330 +#define SRC_MASK_MAU 0x10334 #define SRC_MASK_FSYS 0x10340 +#define SRC_MASK_GEN 0x10344 #define SRC_MASK_PERIC00x10350 +#define SRC_MASK_PERIC10x10354 #define DIV_CPU0 0x500 +#define DIV_CPU1 0x504 +#define DIV_CPERI0 0x4500 +#define DIV_CPERI1 0x4504 +#define DIV_G2D0x8500 +#define DIV_ISP0 0xC300 +#define DIV_ISP1 0xC304 +#define DIV_ISP2 0xC308 #define DIV_TOP0 0x10510 #define DIV_TOP1 0x10514 -#define DIV_FSYS1 0x1054c +#define DIV_TOP2 0x10518 +#define DIV_TOP3 0x1051C +#define DIV_GSCL 0x10520 +#define DIV_DISP0_00x10524 +#define DIV_DISP0_10x10528 +#define DIV_DISP1_00x1052C +#define DIV_DISP1_10x10530 +#define DIV_GEN0x1053C +#define DIV_MAU0x10544 +#define DIV_FSYS0 0x10548 +#define DIV_FSYS1 0x1054C #define DIV_FSYS2 0x10550 +#define DIV_FSYS3 0x10554 #define DIV_PERIC0 0x10558 +#define DIV_PERIC1 0x1055C +#define DIV_PERIC2 0x10560 +#define DIV_PERIC3 0x10564 +#define DIV_PERIC4 0x10568 +#define DIV_PERIC5 0x1056C +#define DIV2_RATIO00x10590 +#define DIV2_RATIO10x10594 +#define DIV_CDREX 0x20500 +#define DIV_CDREX2 0x20504 #define DIV_KFC0 0x28500 +#define GATE_BUS_CPU 0x700 +#define GATE_BUS_GSCL0 0x10710 +#define GATE_BUS_GSCL1 0x10720 +#define GATE_BUS_DISP0 0x10724 +#define GATE_BUS_DISP1 0x10728 +#define GATE_BUS_MFC 0x10734 +#define GATE_BUS_G3D 0x10738 +#define GATE_BUS_GEN 0x1073C #define GATE_BUS_FSYS0 0x10740 - +#define GATE_BUS_FSYS1 0x10744 +#define GATE_BUS_CDREX 0x20700 + +#define GATE_IP_CORE 0x4900 +#define GATE_IP_G2D0x8800 +#define GATE_IP_ISP0 0xC800 +#define GATE_IP_ISP1 0xC804 +#define GATE_IP_GSCL0 0x1091
