Re: [PATCHv3 14/27] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number

2019-02-08 Thread Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou  wrote:
>
> From: Hou Zhiqiang 
>
> The reset value is all zero, so set a workable value for Primary,
> Secondary and Subordinate bus numbers.
>
> Signed-off-by: Hou Zhiqiang 
> Reviewed-by: Minghuan Lian 
> ---
> V3:
>  - No change
>
>  drivers/pci/controller/pcie-mobiveil.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c 
> b/drivers/pci/controller/pcie-mobiveil.c
> index db7ecb021c63..9210165fe8c0 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -582,6 +582,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> u32 value, pab_ctrl, type;
> struct resource_entry *win;
>
> +   /* setup bus numbers */
> +   value = csr_readl(pcie, PCI_PRIMARY_BUS);
> +   value &= 0xff00;
> +   value |= 0x00ff0100;
> +   csr_writel(pcie, value, PCI_PRIMARY_BUS);
> +
> /*
>  * program Bus Master Enable Bit in Command Register in PAB Config
>  * Space
> --
> 2.17.1
>
Reviewed-by: Subrahmanya Lingappa 


[PATCHv3 14/27] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number

2019-01-29 Thread Z.q. Hou
From: Hou Zhiqiang 

The reset value is all zero, so set a workable value for Primary,
Secondary and Subordinate bus numbers.

Signed-off-by: Hou Zhiqiang 
Reviewed-by: Minghuan Lian 
---
V3:
 - No change

 drivers/pci/controller/pcie-mobiveil.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/pci/controller/pcie-mobiveil.c 
b/drivers/pci/controller/pcie-mobiveil.c
index db7ecb021c63..9210165fe8c0 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -582,6 +582,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
u32 value, pab_ctrl, type;
struct resource_entry *win;
 
+   /* setup bus numbers */
+   value = csr_readl(pcie, PCI_PRIMARY_BUS);
+   value &= 0xff00;
+   value |= 0x00ff0100;
+   csr_writel(pcie, value, PCI_PRIMARY_BUS);
+
/*
 * program Bus Master Enable Bit in Command Register in PAB Config
 * Space
-- 
2.17.1