subject:"\[PATCHv3 23\/27\] PCI\: mobiveil\: add PCIe Gen4 RC driver for NXP Layerscape SoCs"

RE: [PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs

2019-02-17 Thread Z.q. Hou

Hi Subbu,

Thanks a lot for your comments!

> -Original Message-
> From: Subrahmanya Lingappa 
> Sent: 2019年2月8日 20:50
> To: Z.q. Hou 
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ;
> lorenzo.pieral...@arm.com; catalin.mari...@arm.com;
> will.dea...@arm.com; Mingkai Hu ; M.h. Lian
> ; Xiaowei Bao 
> Subject: Re: [PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP
> Layerscape SoCs
> 
> ZQ,
> 
> 
> On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou  wrote:
> >
> > From: Hou Zhiqiang 
> >
> > This PCIe controller is based on the Mobiveil GPEX IP, which is
> > compatible with the PCI Express™ Base Specification, Revision 4.0.
> >
> > Signed-off-by: Hou Zhiqiang 
> > Reviewed-by: Minghuan Lian 
> > ---
> > V3:
> >  - No change
> >
> >  drivers/pci/controller/mobiveil/Kconfig   |  10 +
> >  drivers/pci/controller/mobiveil/Makefile  |   1 +
> >  .../controller/mobiveil/pci-layerscape-gen4.c | 254 ++
> >  .../pci/controller/mobiveil/pcie-mobiveil.h   |  16 +-
> >  4 files changed, 279 insertions(+), 2 deletions(-)  create mode
> > 100644 drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> >
> > diff --git a/drivers/pci/controller/mobiveil/Kconfig
> > b/drivers/pci/controller/mobiveil/Kconfig
> > index 64343c07bfed..3ddb7d6163a9 100644
> > --- a/drivers/pci/controller/mobiveil/Kconfig
> > +++ b/drivers/pci/controller/mobiveil/Kconfig
> > @@ -21,4 +21,14 @@ config PCIE_MOBIVEIL_PLAT
> >   Soft IP. It has up to 8 outbound and inbound windows
> >   for address translation and it is a PCIe Gen4 IP.
> >
> > +config PCI_LAYERSCAPE_GEN4
> > +   bool "Freescale Layerscpe PCIe Gen4 controller"
> > +   depends on PCI
> > +   depends on OF && (ARM64 || ARCH_LAYERSCAPE)
> > +   depends on PCI_MSI_IRQ_DOMAIN
> > +   select PCIE_MOBIVEIL_HOST
> > +   help
> > + Say Y here if you want PCIe Gen4 controller support on
> > + Layerscape SoCs. The PCIe controller can work in RC or
> > + EP mode according to RCW[HOST_AGT_PEX] setting.
> >  endmenu
> > diff --git a/drivers/pci/controller/mobiveil/Makefile
> > b/drivers/pci/controller/mobiveil/Makefile
> > index 9fb6d1c6504d..ff66774ccac4 100644
> > --- a/drivers/pci/controller/mobiveil/Makefile
> > +++ b/drivers/pci/controller/mobiveil/Makefile
> > @@ -2,3 +2,4 @@
> >  obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> >  obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
> >  obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
> > +obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o
> > diff --git a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> > b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> > new file mode 100644
> > index ..174cbcac4059
> > --- /dev/null
> > +++ b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> > @@ -0,0 +1,254 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * PCIe host controller driver for NXP Layerscape SoCs
> > + *
> > + * Copyright 2018 NXP
> > + *
> > + * Author: Zhiqiang Hou   */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "pcie-mobiveil.h"
> > +
> > +/* LUT and PF control registers */
> > +#define PCIE_LUT_OFF   (0x8)
> > +#define PCIE_PF_OFF(0xc)
> > +#define PCIE_PF_INT_STAT   (0x18)
> > +#define PF_INT_STAT_PABRST (31)
> > +
> > +#define PCIE_PF_DBG(0x7fc)
> > +#define PF_DBG_LTSSM_MASK  (0x3f)
> > +#define PF_DBG_WE  (31)
> > +#define PF_DBG_PABR(27)
> > +
> > +#define LS_PCIE_G4_LTSSM_L00x2d /* L0 state */
> > +
> > +#define to_ls_pcie_g4(x)
> platform_get_drvdata((x)->pdev)
> > +
> > +struct ls_pcie_g4 {
> > +   struct mobiveil_pcie *pci;
> > +   struct delayed_work dwork;
> > +   int irq;
> > +};
> > +
> > +static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32
> > +off) {
> > +

Re: [PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs

2019-02-08 Thread Subrahmanya Lingappa

ZQ,


On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou  wrote:
>
> From: Hou Zhiqiang 
>
> This PCIe controller is based on the Mobiveil GPEX IP, which is
> compatible with the PCI Express™ Base Specification, Revision 4.0.
>
> Signed-off-by: Hou Zhiqiang 
> Reviewed-by: Minghuan Lian 
> ---
> V3:
>  - No change
>
>  drivers/pci/controller/mobiveil/Kconfig   |  10 +
>  drivers/pci/controller/mobiveil/Makefile  |   1 +
>  .../controller/mobiveil/pci-layerscape-gen4.c | 254 ++
>  .../pci/controller/mobiveil/pcie-mobiveil.h   |  16 +-
>  4 files changed, 279 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
>
> diff --git a/drivers/pci/controller/mobiveil/Kconfig 
> b/drivers/pci/controller/mobiveil/Kconfig
> index 64343c07bfed..3ddb7d6163a9 100644
> --- a/drivers/pci/controller/mobiveil/Kconfig
> +++ b/drivers/pci/controller/mobiveil/Kconfig
> @@ -21,4 +21,14 @@ config PCIE_MOBIVEIL_PLAT
>   Soft IP. It has up to 8 outbound and inbound windows
>   for address translation and it is a PCIe Gen4 IP.
>
> +config PCI_LAYERSCAPE_GEN4
> +   bool "Freescale Layerscpe PCIe Gen4 controller"
> +   depends on PCI
> +   depends on OF && (ARM64 || ARCH_LAYERSCAPE)
> +   depends on PCI_MSI_IRQ_DOMAIN
> +   select PCIE_MOBIVEIL_HOST
> +   help
> + Say Y here if you want PCIe Gen4 controller support on
> + Layerscape SoCs. The PCIe controller can work in RC or
> + EP mode according to RCW[HOST_AGT_PEX] setting.
>  endmenu
> diff --git a/drivers/pci/controller/mobiveil/Makefile 
> b/drivers/pci/controller/mobiveil/Makefile
> index 9fb6d1c6504d..ff66774ccac4 100644
> --- a/drivers/pci/controller/mobiveil/Makefile
> +++ b/drivers/pci/controller/mobiveil/Makefile
> @@ -2,3 +2,4 @@
>  obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
>  obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
>  obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
> +obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o
> diff --git a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c 
> b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> new file mode 100644
> index ..174cbcac4059
> --- /dev/null
> +++ b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> @@ -0,0 +1,254 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PCIe host controller driver for NXP Layerscape SoCs
> + *
> + * Copyright 2018 NXP
> + *
> + * Author: Zhiqiang Hou 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "pcie-mobiveil.h"
> +
> +/* LUT and PF control registers */
> +#define PCIE_LUT_OFF   (0x8)
> +#define PCIE_PF_OFF(0xc)
> +#define PCIE_PF_INT_STAT   (0x18)
> +#define PF_INT_STAT_PABRST (31)
> +
> +#define PCIE_PF_DBG(0x7fc)
> +#define PF_DBG_LTSSM_MASK  (0x3f)
> +#define PF_DBG_WE  (31)
> +#define PF_DBG_PABR(27)
> +
> +#define LS_PCIE_G4_LTSSM_L00x2d /* L0 state */
> +
> +#define to_ls_pcie_g4(x)   platform_get_drvdata((x)->pdev)
> +
> +struct ls_pcie_g4 {
> +   struct mobiveil_pcie *pci;
> +   struct delayed_work dwork;
> +   int irq;
> +};
> +
> +static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off)
> +{
> +   return ioread32(pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
> +}
> +
> +static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie,
> +u32 off, u32 val)
> +{
> +   iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
> +}
> +
> +static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off)
> +{
> +   return ioread32(pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
> +}
> +
> +static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie,
> +   u32 off, u32 val)
> +{
> +   iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
> +}
> +
> +static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
> +{
> +   struct mobiveil_pcie *mv_pci = pcie->pci;
> +   u32 header_type;
> +
> +   header_type = csr_readb(mv_pci, PCI_HEADER_TYPE);
> +   header_type &= 0x7f;
> +
> +   return header_type == PCI_HEADER_TYPE_BRIDGE;
> +}
> +
> +static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci)
> +{
> +   struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
> +   u32 state;
> +
> +   state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
> +   state = state & PF_DBG_LTSSM_MASK;
> +
> +   if (state == LS_PCIE_G4_LTSSM_L0)
> +   return 1;
> +
> +   return 0;
> +}
> +
> +static void ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie)
> +{
> +   struct mobiveil_pcie *mv_pci = pcie->pci;
> +   u32

[PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs

2019-01-29 Thread Z.q. Hou

From: Hou Zhiqiang 

This PCIe controller is based on the Mobiveil GPEX IP, which is
compatible with the PCI Express™ Base Specification, Revision 4.0.

Signed-off-by: Hou Zhiqiang 
Reviewed-by: Minghuan Lian 
---
V3:
 - No change

 drivers/pci/controller/mobiveil/Kconfig   |  10 +
 drivers/pci/controller/mobiveil/Makefile  |   1 +
 .../controller/mobiveil/pci-layerscape-gen4.c | 254 ++
 .../pci/controller/mobiveil/pcie-mobiveil.h   |  16 +-
 4 files changed, 279 insertions(+), 2 deletions(-)
 create mode 100644 drivers/pci/controller/mobiveil/pci-layerscape-gen4.c

diff --git a/drivers/pci/controller/mobiveil/Kconfig 
b/drivers/pci/controller/mobiveil/Kconfig
index 64343c07bfed..3ddb7d6163a9 100644
--- a/drivers/pci/controller/mobiveil/Kconfig
+++ b/drivers/pci/controller/mobiveil/Kconfig
@@ -21,4 +21,14 @@ config PCIE_MOBIVEIL_PLAT
  Soft IP. It has up to 8 outbound and inbound windows
  for address translation and it is a PCIe Gen4 IP.
 
+config PCI_LAYERSCAPE_GEN4
+   bool "Freescale Layerscpe PCIe Gen4 controller"
+   depends on PCI
+   depends on OF && (ARM64 || ARCH_LAYERSCAPE)
+   depends on PCI_MSI_IRQ_DOMAIN
+   select PCIE_MOBIVEIL_HOST
+   help
+ Say Y here if you want PCIe Gen4 controller support on
+ Layerscape SoCs. The PCIe controller can work in RC or
+ EP mode according to RCW[HOST_AGT_PEX] setting.
 endmenu
diff --git a/drivers/pci/controller/mobiveil/Makefile 
b/drivers/pci/controller/mobiveil/Makefile
index 9fb6d1c6504d..ff66774ccac4 100644
--- a/drivers/pci/controller/mobiveil/Makefile
+++ b/drivers/pci/controller/mobiveil/Makefile
@@ -2,3 +2,4 @@
 obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
 obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
 obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
+obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o
diff --git a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c 
b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
new file mode 100644
index ..174cbcac4059
--- /dev/null
+++ b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for NXP Layerscape SoCs
+ *
+ * Copyright 2018 NXP
+ *
+ * Author: Zhiqiang Hou 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pcie-mobiveil.h"
+
+/* LUT and PF control registers */
+#define PCIE_LUT_OFF   (0x8)
+#define PCIE_PF_OFF(0xc)
+#define PCIE_PF_INT_STAT   (0x18)
+#define PF_INT_STAT_PABRST (31)
+
+#define PCIE_PF_DBG(0x7fc)
+#define PF_DBG_LTSSM_MASK  (0x3f)
+#define PF_DBG_WE  (31)
+#define PF_DBG_PABR(27)
+
+#define LS_PCIE_G4_LTSSM_L00x2d /* L0 state */
+
+#define to_ls_pcie_g4(x)   platform_get_drvdata((x)->pdev)
+
+struct ls_pcie_g4 {
+   struct mobiveil_pcie *pci;
+   struct delayed_work dwork;
+   int irq;
+};
+
+static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off)
+{
+   return ioread32(pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
+}
+
+static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie,
+u32 off, u32 val)
+{
+   iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
+}
+
+static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off)
+{
+   return ioread32(pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
+}
+
+static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie,
+   u32 off, u32 val)
+{
+   iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
+}
+
+static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
+{
+   struct mobiveil_pcie *mv_pci = pcie->pci;
+   u32 header_type;
+
+   header_type = csr_readb(mv_pci, PCI_HEADER_TYPE);
+   header_type &= 0x7f;
+
+   return header_type == PCI_HEADER_TYPE_BRIDGE;
+}
+
+static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci)
+{
+   struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
+   u32 state;
+
+   state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
+   state = state & PF_DBG_LTSSM_MASK;
+
+   if (state == LS_PCIE_G4_LTSSM_L0)
+   return 1;
+
+   return 0;
+}
+
+static void ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie)
+{
+   struct mobiveil_pcie *mv_pci = pcie->pci;
+   u32 val, act_stat;
+   int to = 100;
+
+   /* Poll for pab_csb_reset to set and PAB activity to clear */
+   do {
+   usleep_range(10, 15);
+   val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_INT_STAT);
+   act_stat = csr_readl(mv_pci, PAB_ACTIVITY_STAT);
+   } while (((val & 1 << PF_INT_STAT_PABRST) == 0 ||

RE: [PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs

Re: [PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs

[PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs

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