[PATCHv3 4/4] Documentation: Add device tree bindings for Freescale FTM PWM.
This adds the Document for Freescale FTM PWM driver under
Documentation/devicetree/bindings/pwm/.
Signed-off-by: Xiubo Li
---
.../devicetree/bindings/pwm/pwm-fsl-ftm.txt| 36 ++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
new file mode 100644
index 000..e736806
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
@@ -0,0 +1,36 @@
+Freescale FTM PWM controller
+
+Required properties:
+- compatible: Should be "fsl,vf610-ftm-pwm"
+- reg: Physical base address and length of the controller's registers
+- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
+ the cells format.
+- clock-names : Includes the following module clock source entries:
+"ftm0" (system clock),
+"ftm0_fix_sel" (fixed frequency clock),
+"ftm0_ext_sel" (external clock)
+- clocks : Must contain an entry list for entries in clock-names.
+- fsl,pwm-counter-clk: The FTM PWM counter clock source, should be one of the
+ entries in clock-names.
+- For each channel's pinctrl, the "chN-active" and "chN-idle" states should be
+ implemented at the same time.
+
+Example:
+
+pwm0: pwm@40038000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ reg = <0x40038000 0x1000>;
+ #pwm-cells = <3>;
+ clock-names = "ftm0", "ftm0_fix_sel", "ftm0_ext_sel";
+ clocks = < VF610_CLK_FTM0>,
+ < VF610_CLK_FTM0_FIX_SEL>,
+ < VF610_CLK_FTM0_EXT_SEL>;
+ pinctrl-names = "ch0-active", "ch0-idle", "ch1-active",
"ch1-idle",
+ ;
+ pinctrl-0 = <_pwm0_ch0_active>;
+ pinctrl-1 = <_pwm0_ch0_idle>;
+ pinctrl-2 = <_pwm0_ch1_active>;
+ pinctrl-3 = <_pwm0_ch1_idle>;
+ ...
+ fsl,pwm-counter-clk = "ftm0_ext_sel";
+};
--
1.8.0
--
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[PATCHv3 4/4] Documentation: Add device tree bindings for Freescale FTM PWM.
This adds the Document for Freescale FTM PWM driver under
Documentation/devicetree/bindings/pwm/.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
.../devicetree/bindings/pwm/pwm-fsl-ftm.txt| 36 ++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
new file mode 100644
index 000..e736806
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
@@ -0,0 +1,36 @@
+Freescale FTM PWM controller
+
+Required properties:
+- compatible: Should be fsl,vf610-ftm-pwm
+- reg: Physical base address and length of the controller's registers
+- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
+ the cells format.
+- clock-names : Includes the following module clock source entries:
+ftm0 (system clock),
+ftm0_fix_sel (fixed frequency clock),
+ftm0_ext_sel (external clock)
+- clocks : Must contain an entry list for entries in clock-names.
+- fsl,pwm-counter-clk: The FTM PWM counter clock source, should be one of the
+ entries in clock-names.
+- For each channel's pinctrl, the chN-active and chN-idle states should be
+ implemented at the same time.
+
+Example:
+
+pwm0: pwm@40038000 {
+ compatible = fsl,vf610-ftm-pwm;
+ reg = 0x40038000 0x1000;
+ #pwm-cells = 3;
+ clock-names = ftm0, ftm0_fix_sel, ftm0_ext_sel;
+ clocks = clks VF610_CLK_FTM0,
+ clks VF610_CLK_FTM0_FIX_SEL,
+ clks VF610_CLK_FTM0_EXT_SEL;
+ pinctrl-names = ch0-active, ch0-idle, ch1-active,
ch1-idle,
+ ;
+ pinctrl-0 = pinctrl_pwm0_ch0_active;
+ pinctrl-1 = pinctrl_pwm0_ch0_idle;
+ pinctrl-2 = pinctrl_pwm0_ch1_active;
+ pinctrl-3 = pinctrl_pwm0_ch1_idle;
+ ...
+ fsl,pwm-counter-clk = ftm0_ext_sel;
+};
--
1.8.0
--
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Please read the FAQ at http://www.tux.org/lkml/
