Re: [PATCHv4 5/7] clk: samsung: exynos3250: Add clocks using common clock framework
Hi Chanwoo
On 14.05.2014 08:57, Chanwoo Choi wrote:
> On 05/14/2014 01:28 AM, Tomasz Figa wrote:
>> On 13.05.2014 13:49, Chanwoo Choi wrote:
>>> On 04/26/2014 09:39 AM, Tomasz Figa wrote:
On 25.04.2014 03:16, Chanwoo Choi wrote:
> +/* GATE_BLOCK */
> +GATE(CLK_BLOCK_LCD, "block_lcd", "div_aclk_160", GATE_BLOCK, 4, 0,
> 0),
> +GATE(CLK_BLOCK_G3D, "block_g3d", "div_aclk_200", GATE_BLOCK, 3, 0,
> 0),
Are there only 2 gate block clocks? By the way, how are they going to be
handled by respective drivers? There is no mainline support for them right
now, but you should be aware that adding them will cause common clock
framework to disable them if not claimed by any driver.
>>>
>>> OK, I'll add remaing clock gate of GATE_BLOCK as following.
>>> - CLK_BLOCK_MFC MFC_BLK
>>> - CLK_BLOCK_CAM CAM_BLK
>>>
>>
>> I agree that in the end the block gates will have to be added. However
>> currently drivers do not request block gates and enable them.
>> Considering that common clock framework disables all unused clocks by
>> default, this will lead to all the gate block clocks being disabled,
>> which is not desired.
>
> You're right.
>
>>
>> My opinion on this is that block gate clocks should be added in separate
>> patch along with patches adding code to get and enable them.
>
> OK, I'll remove the clocks of GATE_BLOCK on next posting(v6)
>
OK, thanks.
By the way, if there are no other comments to v5 series than to this
patch, then you can simply send v6 of this single patch as a reply to v5.
>>
> +};
> +
> +/* APLL & MPLL & BPLL & UPLL */
> +static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
> +PLL_35XX_RATE(12, 400, 4, 1),
> +PLL_35XX_RATE(11, 275, 3, 1),
> +PLL_35XX_RATE(106600, 533, 6, 1),
> +PLL_35XX_RATE(10, 250, 3, 1),
> +PLL_35XX_RATE( 96000, 320, 4, 1),
> +PLL_35XX_RATE( 9, 300, 4, 1),
> +PLL_35XX_RATE( 85000, 425, 6, 1),
> +PLL_35XX_RATE( 8, 200, 3, 1),
> +PLL_35XX_RATE( 7, 175, 3, 1),
> +PLL_35XX_RATE( 66700, 667, 12, 1),
> +PLL_35XX_RATE( 6, 400, 4, 2),
> +PLL_35XX_RATE( 53300, 533, 6, 2),
> +PLL_35XX_RATE( 52000, 260, 3, 2),
> +PLL_35XX_RATE( 5, 250, 3, 2),
> +PLL_35XX_RATE( 4, 200, 3, 2),
> +PLL_35XX_RATE( 2, 200, 3, 3),
> +PLL_35XX_RATE( 1, 200, 3, 4),
> +{ /* sentinel */ }
> +};
> +
> +/* VPLL */
> +static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
> +PLL_36XX_RATE(6, 100, 2, 1, 0),
> +PLL_36XX_RATE(53300, 267, 3, 2, 32668),
>>
>> The TRM actually lists this as 267, 3, 2, 32768, and according to the
>> equation it will be 53515 Hz. Looks like a typo in the data sheet,
>> as 266, 3, 2, 32768 gives 53315, which is almost exactly 533 MHz.
>>
> +PLL_36XX_RATE(519231000, 173, 2, 2, 5046),
>>
>> 519230991
>>
> +PLL_36XX_RATE(5, 250, 3, 2, 0),
> +PLL_36XX_RATE(44550, 149, 2, 2, 32768),
>>
>> 448500022
>>
>> Also looks like a typo in the TRM, as 148, 2, 2, 32768 gives 445500022,
>> which is almost exactly 445.5 MHz.
>>
>>
> +PLL_36XX_RATE(445055000, 148, 2, 2, 23047),
>>
>> 445055024
>>
> +PLL_36XX_RATE(4, 200, 3, 2, 0),
> +PLL_36XX_RATE(37125, 124, 2, 2, 49512),
>>
>> The TRM lists this as 124, 2, 2, 49152 and calculated frequency is
>> 374250034. This one also looks like a typo. 123, 2, 2, 49512 would give
>> 371250034.
>
> When I calculated fout with following data:
> - 124, 2, 2, 49512 would give 374266514.1
> - 123, 2, 2, 49512 would give 371266514.1.
>
> I think below value is proper.
> - 123, 2, 2, 49512 would give 371266514.1.
>
Sorry, my bad, I made a typo as well ;). It should be 123, 2, 2, 49152.
The value I got was correct - 371250034.
>>
> +PLL_36XX_RATE(370879000, 185, 3, 2, 28803),
>>
>> 370879011
>>
> +PLL_36XX_RATE(34000, 170, 3, 2, 0),
> +PLL_36XX_RATE(33500, 112, 2, 2, 43691),
>>
>> 33845
>>
>> 111, 2, 2, 43691 would give 33545. A typo in TRM?
>>
> +PLL_36XX_RATE(33300, 111, 2, 2, 0),
> +PLL_36XX_RATE(33000, 110, 2, 2, 0),
> +PLL_36XX_RATE(32000, 107, 2, 2, 43691),
>>
>> 32345
>>
>> 106, 2, 2, 43691 would give 32045.
>>
> +PLL_36XX_RATE(3, 100, 2, 2, 0),
> +PLL_36XX_RATE(27500, 275, 3, 3, 0),
> +PLL_36XX_RATE(22275, 149, 2, 3, 32768),
>>
>> 224250011
>>
>> 148, 2, 3, 32768 would give 222750011.
>>
> +PLL_36XX_RATE(222528000, 148, 2, 3, 23069),
>>
>> 222528015
>>
> +PLL_36XX_RATE(16000, 160, 3, 3, 0),
> +PLL_36XX_RATE(14850, 99, 2, 3, 0),
> +PLL_36XX_RATE(148352000, 99, 2, 3, 59070),
>>
>> 14985
Re: [PATCHv4 5/7] clk: samsung: exynos3250: Add clocks using common clock framework
Hi Tomasz, On 05/14/2014 01:28 AM, Tomasz Figa wrote: > Hi Chanwoo, > > On 13.05.2014 13:49, Chanwoo Choi wrote: >> Hi Tomasz, >> >> On 04/26/2014 09:39 AM, Tomasz Figa wrote: >>> Hi Chanwoo, >>> >>> On 25.04.2014 03:16, Chanwoo Choi wrote: From: Tomasz Figa This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7 using common clock framework. The CMU (Clock Management Unit) of Exynos3250 control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses, and function clocks for individual IPs. The CMU of Exynos3250 includes following clock doamins: - CPU block for Cortex-A7 MPCore processor - LEFTBUS/RIGHTBUS block - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR >>> >>> In original driver present in our internal tree I have separated several >>> CMUs to account for certain factors caused by hardware design, which >>> require such separation. Is there any reason why they were merged together >>> into a single CMU again? >> >> This patch just include clocks in CMU clocks without CMU_DMC/CMU_ISP. >> I'll send a further patches to support CMU_DMC/CMU_ISP after verifying it. >> >>> Cc: Mike Turquette Cc: Kukjin Kim Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Signed-off-by: Tomasz Figa Signed-off-by: Chanwoo Choi Signed-off-by: Hyunhee Kim Signed-off-by: Sylwester Nawrocki Signed-off-by: Inki Dae Signed-off-by: Seung-Woo Kim Signed-off-by: Jaehoon Chung Signed-off-by: Karol Wrona Signed-off-by: YoungJun Cho Signed-off-by: Kyungmin Park --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos3250.c | 785 + include/dt-bindings/clock/exynos3250.h | 256 +++ 3 files changed, 1042 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos3250.c create mode 100644 include/dt-bindings/clock/exynos3250.h diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 8eb4799..d120797 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_COMMON_CLK)+= clk.o clk-pll.o +obj-$(CONFIG_SOC_EXYNOS3250)+= clk-exynos3250.o obj-$(CONFIG_ARCH_EXYNOS4)+= clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS5250)+= clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5420)+= clk-exynos5420.o diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c new file mode 100644 index 000..0574a76 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -0,0 +1,785 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos3250 SoC. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk.h" +#include "clk-pll.h" + +#define SRC_LEFTBUS0x4200 +#define DIV_LEFTBUS0x4500 +#define GATE_IP_LEFTBUS0x4800 +#define SRC_RIGHTBUS0x8200 +#define DIV_RIGHTBUS0x8500 +#define GATE_IP_RIGHTBUS0x8800 +#define GATE_IP_PERIR0x8960 +#define MPLL_LOCK0xc010 +#define MPLL_CON00xc110 +#define VPLL_LOCK0xc020 +#define VPLL_CON00xc120 +#define UPLL_LOCK0xc030 +#define UPLL_CON00xc130 +#define SRC_TOP00xc210 +#define SRC_TOP10xc214 +#define SRC_CAM0xc220 +#define SRC_MFC0xc228 +#define SRC_G3D0xc22c +#define SRC_LCD0xc234 +#define SRC_ISP0xc238 +#define SRC_FSYS0xc240 +#define SRC_PERIL00xc250 +#define SRC_PERIL10xc254 +#define SRC_MASK_TOP0xc310 +#define SRC_MASK_CAM0xc320 +#define SRC_MASK_LCD0xc334 +#define SRC_MASK_ISP0xc338 +#define SRC_MASK_FSYS0xc340 +#define SRC_MASK_PERIL00xc350 +#define SRC_MASK_PERIL10xc354 +#define DIV_TOP0xc510 +#define DIV_CAM0xc520 +#define DIV_MFC0xc528 +#define DIV_G3D0xc52c +#define DIV_LCD0xc534 +#define DIV_ISP0xc538 +#define DIV_FSYS00xc540 +#define DIV_FSYS10xc544 +#define DIV_FSYS20xc548 +#define DIV_PERIL00xc
Re: [PATCHv4 5/7] clk: samsung: exynos3250: Add clocks using common clock framework
Hi Chanwoo, On 13.05.2014 13:49, Chanwoo Choi wrote: > Hi Tomasz, > > On 04/26/2014 09:39 AM, Tomasz Figa wrote: >> Hi Chanwoo, >> >> On 25.04.2014 03:16, Chanwoo Choi wrote: >>> From: Tomasz Figa >>> >>> This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7 >>> using common clock framework. The CMU (Clock Management Unit) of Exynos3250 >>> control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses, >>> and function clocks for individual IPs. >>> >>> The CMU of Exynos3250 includes following clock doamins: >>> - CPU block for Cortex-A7 MPCore processor >>> - LEFTBUS/RIGHTBUS block >>> - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR >> >> In original driver present in our internal tree I have separated several >> CMUs to account for certain factors caused by hardware design, which require >> such separation. Is there any reason why they were merged together into a >> single CMU again? > > This patch just include clocks in CMU clocks without CMU_DMC/CMU_ISP. > I'll send a further patches to support CMU_DMC/CMU_ISP after verifying it. > >> >>> >>> Cc: Mike Turquette >>> Cc: Kukjin Kim >>> Cc: Rob Herring >>> Cc: Pawel Moll >>> Cc: Mark Rutland >>> Cc: Ian Campbell >>> Cc: Kumar Gala >>> Signed-off-by: Tomasz Figa >>> Signed-off-by: Chanwoo Choi >>> Signed-off-by: Hyunhee Kim >>> Signed-off-by: Sylwester Nawrocki >>> Signed-off-by: Inki Dae >>> Signed-off-by: Seung-Woo Kim >>> Signed-off-by: Jaehoon Chung >>> Signed-off-by: Karol Wrona >>> Signed-off-by: YoungJun Cho >>> Signed-off-by: Kyungmin Park >>> --- >>> drivers/clk/samsung/Makefile | 1 + >>> drivers/clk/samsung/clk-exynos3250.c | 785 >>> + >>> include/dt-bindings/clock/exynos3250.h | 256 +++ >>> 3 files changed, 1042 insertions(+) >>> create mode 100644 drivers/clk/samsung/clk-exynos3250.c >>> create mode 100644 include/dt-bindings/clock/exynos3250.h >>> >>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile >>> index 8eb4799..d120797 100644 >>> --- a/drivers/clk/samsung/Makefile >>> +++ b/drivers/clk/samsung/Makefile >>> @@ -3,6 +3,7 @@ >>> # >>> >>> obj-$(CONFIG_COMMON_CLK)+= clk.o clk-pll.o >>> +obj-$(CONFIG_SOC_EXYNOS3250)+= clk-exynos3250.o >>> obj-$(CONFIG_ARCH_EXYNOS4)+= clk-exynos4.o >>> obj-$(CONFIG_SOC_EXYNOS5250)+= clk-exynos5250.o >>> obj-$(CONFIG_SOC_EXYNOS5420)+= clk-exynos5420.o >>> diff --git a/drivers/clk/samsung/clk-exynos3250.c >>> b/drivers/clk/samsung/clk-exynos3250.c >>> new file mode 100644 >>> index 000..0574a76 >>> --- /dev/null >>> +++ b/drivers/clk/samsung/clk-exynos3250.c >>> @@ -0,0 +1,785 @@ >>> +/* >>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd. >>> + * >>> + * This program is free software; you can redistribute it and/or modify >>> + * it under the terms of the GNU General Public License version 2 as >>> + * published by the Free Software Foundation. >>> + * >>> + * Common Clock Framework support for Exynos3250 SoC. >>> + */ >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +#include >>> + >>> +#include "clk.h" >>> +#include "clk-pll.h" >>> + >>> +#define SRC_LEFTBUS0x4200 >>> +#define DIV_LEFTBUS0x4500 >>> +#define GATE_IP_LEFTBUS0x4800 >>> +#define SRC_RIGHTBUS0x8200 >>> +#define DIV_RIGHTBUS0x8500 >>> +#define GATE_IP_RIGHTBUS0x8800 >>> +#define GATE_IP_PERIR0x8960 >>> +#define MPLL_LOCK0xc010 >>> +#define MPLL_CON00xc110 >>> +#define VPLL_LOCK0xc020 >>> +#define VPLL_CON00xc120 >>> +#define UPLL_LOCK0xc030 >>> +#define UPLL_CON00xc130 >>> +#define SRC_TOP00xc210 >>> +#define SRC_TOP10xc214 >>> +#define SRC_CAM0xc220 >>> +#define SRC_MFC0xc228 >>> +#define SRC_G3D0xc22c >>> +#define SRC_LCD0xc234 >>> +#define SRC_ISP0xc238 >>> +#define SRC_FSYS0xc240 >>> +#define SRC_PERIL00xc250 >>> +#define SRC_PERIL10xc254 >>> +#define SRC_MASK_TOP0xc310 >>> +#define SRC_MASK_CAM0xc320 >>> +#define SRC_MASK_LCD0xc334 >>> +#define SRC_MASK_ISP0xc338 >>> +#define SRC_MASK_FSYS0xc340 >>> +#define SRC_MASK_PERIL00xc350 >>> +#define SRC_MASK_PERIL10xc354 >>> +#define DIV_TOP0xc510 >>> +#define DIV_CAM0xc520 >>> +#define DIV_MFC0xc528 >>> +#define DIV_G3D0xc52c >>> +#define DIV_LCD0xc534 >>> +#define DIV_ISP0xc538 >>> +#define DIV_FSYS00xc540 >>> +#define DIV_FSYS10xc544 >>> +#define DIV_FSYS20xc548 >>> +#define DIV_PERIL00xc550 >>> +#define DIV_PERIL10xc554 >>> +#define DIV_PERIL30xc55c >>> +#define DIV_PERIL40xc560 >>> +#define DIV_PERIL50xc564 >>> +#define DIV_CAM10xc568 >>
Re: [PATCHv4 5/7] clk: samsung: exynos3250: Add clocks using common clock framework
Hi Tomasz, On 04/26/2014 09:39 AM, Tomasz Figa wrote: > Hi Chanwoo, > > On 25.04.2014 03:16, Chanwoo Choi wrote: >> From: Tomasz Figa >> >> This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7 >> using common clock framework. The CMU (Clock Management Unit) of Exynos3250 >> control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses, >> and function clocks for individual IPs. >> >> The CMU of Exynos3250 includes following clock doamins: >> - CPU block for Cortex-A7 MPCore processor >> - LEFTBUS/RIGHTBUS block >> - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR > > In original driver present in our internal tree I have separated several CMUs > to account for certain factors caused by hardware design, which require such > separation. Is there any reason why they were merged together into a single > CMU again? This patch just include clocks in CMU clocks without CMU_DMC/CMU_ISP. I'll send a further patches to support CMU_DMC/CMU_ISP after verifying it. > >> >> Cc: Mike Turquette >> Cc: Kukjin Kim >> Cc: Rob Herring >> Cc: Pawel Moll >> Cc: Mark Rutland >> Cc: Ian Campbell >> Cc: Kumar Gala >> Signed-off-by: Tomasz Figa >> Signed-off-by: Chanwoo Choi >> Signed-off-by: Hyunhee Kim >> Signed-off-by: Sylwester Nawrocki >> Signed-off-by: Inki Dae >> Signed-off-by: Seung-Woo Kim >> Signed-off-by: Jaehoon Chung >> Signed-off-by: Karol Wrona >> Signed-off-by: YoungJun Cho >> Signed-off-by: Kyungmin Park >> --- >> drivers/clk/samsung/Makefile | 1 + >> drivers/clk/samsung/clk-exynos3250.c | 785 >> + >> include/dt-bindings/clock/exynos3250.h | 256 +++ >> 3 files changed, 1042 insertions(+) >> create mode 100644 drivers/clk/samsung/clk-exynos3250.c >> create mode 100644 include/dt-bindings/clock/exynos3250.h >> >> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile >> index 8eb4799..d120797 100644 >> --- a/drivers/clk/samsung/Makefile >> +++ b/drivers/clk/samsung/Makefile >> @@ -3,6 +3,7 @@ >> # >> >> obj-$(CONFIG_COMMON_CLK)+= clk.o clk-pll.o >> +obj-$(CONFIG_SOC_EXYNOS3250)+= clk-exynos3250.o >> obj-$(CONFIG_ARCH_EXYNOS4)+= clk-exynos4.o >> obj-$(CONFIG_SOC_EXYNOS5250)+= clk-exynos5250.o >> obj-$(CONFIG_SOC_EXYNOS5420)+= clk-exynos5420.o >> diff --git a/drivers/clk/samsung/clk-exynos3250.c >> b/drivers/clk/samsung/clk-exynos3250.c >> new file mode 100644 >> index 000..0574a76 >> --- /dev/null >> +++ b/drivers/clk/samsung/clk-exynos3250.c >> @@ -0,0 +1,785 @@ >> +/* >> + * Copyright (c) 2014 Samsung Electronics Co., Ltd. >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> + * >> + * Common Clock Framework support for Exynos3250 SoC. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include >> + >> +#include "clk.h" >> +#include "clk-pll.h" >> + >> +#define SRC_LEFTBUS0x4200 >> +#define DIV_LEFTBUS0x4500 >> +#define GATE_IP_LEFTBUS0x4800 >> +#define SRC_RIGHTBUS0x8200 >> +#define DIV_RIGHTBUS0x8500 >> +#define GATE_IP_RIGHTBUS0x8800 >> +#define GATE_IP_PERIR0x8960 >> +#define MPLL_LOCK0xc010 >> +#define MPLL_CON00xc110 >> +#define VPLL_LOCK0xc020 >> +#define VPLL_CON00xc120 >> +#define UPLL_LOCK0xc030 >> +#define UPLL_CON00xc130 >> +#define SRC_TOP00xc210 >> +#define SRC_TOP10xc214 >> +#define SRC_CAM0xc220 >> +#define SRC_MFC0xc228 >> +#define SRC_G3D0xc22c >> +#define SRC_LCD0xc234 >> +#define SRC_ISP0xc238 >> +#define SRC_FSYS0xc240 >> +#define SRC_PERIL00xc250 >> +#define SRC_PERIL10xc254 >> +#define SRC_MASK_TOP0xc310 >> +#define SRC_MASK_CAM0xc320 >> +#define SRC_MASK_LCD0xc334 >> +#define SRC_MASK_ISP0xc338 >> +#define SRC_MASK_FSYS0xc340 >> +#define SRC_MASK_PERIL00xc350 >> +#define SRC_MASK_PERIL10xc354 >> +#define DIV_TOP0xc510 >> +#define DIV_CAM0xc520 >> +#define DIV_MFC0xc528 >> +#define DIV_G3D0xc52c >> +#define DIV_LCD0xc534 >> +#define DIV_ISP0xc538 >> +#define DIV_FSYS00xc540 >> +#define DIV_FSYS10xc544 >> +#define DIV_FSYS20xc548 >> +#define DIV_PERIL00xc550 >> +#define DIV_PERIL10xc554 >> +#define DIV_PERIL30xc55c >> +#define DIV_PERIL40xc560 >> +#define DIV_PERIL50xc564 >> +#define DIV_CAM10xc568 >> +#define CLKDIV2_RATIO0xc580 >> +#define GATE_SCLK_CAM0xc820 >> +#define GATE_SCLK_MFC0xc828 >> +#define GATE_SCLK_G3D0xc82c >> +#define GATE_SCLK_LCD0xc834 >
Re: [PATCHv4 5/7] clk: samsung: exynos3250: Add clocks using common clock framework
Hi Chanwoo, On 25.04.2014 03:16, Chanwoo Choi wrote: From: Tomasz Figa This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7 using common clock framework. The CMU (Clock Management Unit) of Exynos3250 control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses, and function clocks for individual IPs. The CMU of Exynos3250 includes following clock doamins: - CPU block for Cortex-A7 MPCore processor - LEFTBUS/RIGHTBUS block - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR In original driver present in our internal tree I have separated several CMUs to account for certain factors caused by hardware design, which require such separation. Is there any reason why they were merged together into a single CMU again? Cc: Mike Turquette Cc: Kukjin Kim Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Signed-off-by: Tomasz Figa Signed-off-by: Chanwoo Choi Signed-off-by: Hyunhee Kim Signed-off-by: Sylwester Nawrocki Signed-off-by: Inki Dae Signed-off-by: Seung-Woo Kim Signed-off-by: Jaehoon Chung Signed-off-by: Karol Wrona Signed-off-by: YoungJun Cho Signed-off-by: Kyungmin Park --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos3250.c | 785 + include/dt-bindings/clock/exynos3250.h | 256 +++ 3 files changed, 1042 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos3250.c create mode 100644 include/dt-bindings/clock/exynos3250.h diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 8eb4799..d120797 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o +obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o obj-$(CONFIG_ARCH_EXYNOS4)+= clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c new file mode 100644 index 000..0574a76 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -0,0 +1,785 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos3250 SoC. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk.h" +#include "clk-pll.h" + +#define SRC_LEFTBUS0x4200 +#define DIV_LEFTBUS0x4500 +#define GATE_IP_LEFTBUS0x4800 +#define SRC_RIGHTBUS 0x8200 +#define DIV_RIGHTBUS 0x8500 +#define GATE_IP_RIGHTBUS 0x8800 +#define GATE_IP_PERIR 0x8960 +#define MPLL_LOCK 0xc010 +#define MPLL_CON0 0xc110 +#define VPLL_LOCK 0xc020 +#define VPLL_CON0 0xc120 +#define UPLL_LOCK 0xc030 +#define UPLL_CON0 0xc130 +#define SRC_TOP0 0xc210 +#define SRC_TOP1 0xc214 +#define SRC_CAM0xc220 +#define SRC_MFC0xc228 +#define SRC_G3D0xc22c +#define SRC_LCD0xc234 +#define SRC_ISP0xc238 +#define SRC_FSYS 0xc240 +#define SRC_PERIL0 0xc250 +#define SRC_PERIL1 0xc254 +#define SRC_MASK_TOP 0xc310 +#define SRC_MASK_CAM 0xc320 +#define SRC_MASK_LCD 0xc334 +#define SRC_MASK_ISP 0xc338 +#define SRC_MASK_FSYS 0xc340 +#define SRC_MASK_PERIL00xc350 +#define SRC_MASK_PERIL10xc354 +#define DIV_TOP0xc510 +#define DIV_CAM0xc520 +#define DIV_MFC0xc528 +#define DIV_G3D0xc52c +#define DIV_LCD0xc534 +#define DIV_ISP0xc538 +#define DIV_FSYS0 0xc540 +#define DIV_FSYS1 0xc544 +#define DIV_FSYS2 0xc548 +#define DIV_PERIL0 0xc550 +#define DIV_PERIL1 0xc554 +#define DIV_PERIL3 0xc55c +#define DIV_PERIL4 0xc560 +#define DIV_PERIL5 0xc564 +#define DIV_CAM1 0xc568 +#define CLKDIV2_RATIO 0xc580 +#define GATE_SCLK_CAM 0xc820 +#define GATE_SCLK_MFC 0xc828 +#define GATE_SCLK_G3D 0xc82c +#define GATE_SCLK_LCD 0xc834 +#define GATE_SCLK_ISP_TOP 0xc838 +#define GATE_SCLK_FSYS 0xc840 +#define GATE_SCLK_PERIL0xc850 +#define GATE_IP_CAM0xc920 +#define GATE_IP_MFC0xc928 +#define GATE_IP_G3D0xc92c +#define GATE_IP_LCD0xc934 +#define
[PATCHv4 5/7] clk: samsung: exynos3250: Add clocks using common clock framework
From: Tomasz Figa This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7 using common clock framework. The CMU (Clock Management Unit) of Exynos3250 control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses, and function clocks for individual IPs. The CMU of Exynos3250 includes following clock doamins: - CPU block for Cortex-A7 MPCore processor - LEFTBUS/RIGHTBUS block - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR Cc: Mike Turquette Cc: Kukjin Kim Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Signed-off-by: Tomasz Figa Signed-off-by: Chanwoo Choi Signed-off-by: Hyunhee Kim Signed-off-by: Sylwester Nawrocki Signed-off-by: Inki Dae Signed-off-by: Seung-Woo Kim Signed-off-by: Jaehoon Chung Signed-off-by: Karol Wrona Signed-off-by: YoungJun Cho Signed-off-by: Kyungmin Park --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos3250.c | 785 + include/dt-bindings/clock/exynos3250.h | 256 +++ 3 files changed, 1042 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos3250.c create mode 100644 include/dt-bindings/clock/exynos3250.h diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 8eb4799..d120797 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o +obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c new file mode 100644 index 000..0574a76 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -0,0 +1,785 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos3250 SoC. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk.h" +#include "clk-pll.h" + +#define SRC_LEFTBUS0x4200 +#define DIV_LEFTBUS0x4500 +#define GATE_IP_LEFTBUS0x4800 +#define SRC_RIGHTBUS 0x8200 +#define DIV_RIGHTBUS 0x8500 +#define GATE_IP_RIGHTBUS 0x8800 +#define GATE_IP_PERIR 0x8960 +#define MPLL_LOCK 0xc010 +#define MPLL_CON0 0xc110 +#define VPLL_LOCK 0xc020 +#define VPLL_CON0 0xc120 +#define UPLL_LOCK 0xc030 +#define UPLL_CON0 0xc130 +#define SRC_TOP0 0xc210 +#define SRC_TOP1 0xc214 +#define SRC_CAM0xc220 +#define SRC_MFC0xc228 +#define SRC_G3D0xc22c +#define SRC_LCD0xc234 +#define SRC_ISP0xc238 +#define SRC_FSYS 0xc240 +#define SRC_PERIL0 0xc250 +#define SRC_PERIL1 0xc254 +#define SRC_MASK_TOP 0xc310 +#define SRC_MASK_CAM 0xc320 +#define SRC_MASK_LCD 0xc334 +#define SRC_MASK_ISP 0xc338 +#define SRC_MASK_FSYS 0xc340 +#define SRC_MASK_PERIL00xc350 +#define SRC_MASK_PERIL10xc354 +#define DIV_TOP0xc510 +#define DIV_CAM0xc520 +#define DIV_MFC0xc528 +#define DIV_G3D0xc52c +#define DIV_LCD0xc534 +#define DIV_ISP0xc538 +#define DIV_FSYS0 0xc540 +#define DIV_FSYS1 0xc544 +#define DIV_FSYS2 0xc548 +#define DIV_PERIL0 0xc550 +#define DIV_PERIL1 0xc554 +#define DIV_PERIL3 0xc55c +#define DIV_PERIL4 0xc560 +#define DIV_PERIL5 0xc564 +#define DIV_CAM1 0xc568 +#define CLKDIV2_RATIO 0xc580 +#define GATE_SCLK_CAM 0xc820 +#define GATE_SCLK_MFC 0xc828 +#define GATE_SCLK_G3D 0xc82c +#define GATE_SCLK_LCD 0xc834 +#define GATE_SCLK_ISP_TOP 0xc838 +#define GATE_SCLK_FSYS 0xc840 +#define GATE_SCLK_PERIL0xc850 +#define GATE_IP_CAM0xc920 +#define GATE_IP_MFC0xc928 +#define GATE_IP_G3D0xc92c +#define GATE_IP_LCD0xc934 +#define GATE_IP_ISP0xc938 +#define GATE_IP_FSYS 0xc940 +#define GATE_IP_PERIL 0xc950 +#define GATE_BLOCK 0xc970 +#define APLL_LOCK 0x14000 +#define APLL_CON0 0x14100 +#define SRC_CPU0x14200 +#define DIV_CPU0 0x14
