Re: [RESEND PATCH 1/2 v6] clk/axs10x: Add I2S PLL clock driver
On 05/02, Jose Abreu wrote: > The ARC SDP I2S clock can be programmed using a > specific PLL. > > This patch has the goal of adding a clock driver > that programs this PLL. > > At this moment the rate values are hardcoded in > a table but in the future it would be ideal to > use a function which determines the PLL values > given the desired rate. > > Signed-off-by: Jose Abreu> --- Applied to clk-next I'm not applying the arc dts file (patch #2 in this series). -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [RESEND PATCH 1/2 v6] clk/axs10x: Add I2S PLL clock driver
On 05/02, Jose Abreu wrote: > The ARC SDP I2S clock can be programmed using a > specific PLL. > > This patch has the goal of adding a clock driver > that programs this PLL. > > At this moment the rate values are hardcoded in > a table but in the future it would be ideal to > use a function which determines the PLL values > given the desired rate. > > Signed-off-by: Jose Abreu > --- Applied to clk-next I'm not applying the arc dts file (patch #2 in this series). -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [RESEND PATCH 1/2 v6] clk/axs10x: Add I2S PLL clock driver
On Mon, May 02, 2016 at 10:39:05AM +0100, Jose Abreu wrote: > The ARC SDP I2S clock can be programmed using a > specific PLL. > > This patch has the goal of adding a clock driver > that programs this PLL. > > At this moment the rate values are hardcoded in > a table but in the future it would be ideal to > use a function which determines the PLL values > given the desired rate. > > Signed-off-by: Jose Abreu> --- > > Changes v5 -> v6: > * Use parent clock to determine PLL input rate instead of using hardcoded > values > * Documentation update (added 'clocks' field) > > Changes v4 -> v5: > * Documentation update (as suggested by Alexey Brodkin) > * Changed compatible string to "snps,axs10x-i2s-pll-clock" (as suggested by > Alexey Brodkin) > > Changes v3 -> v4: > * Added binding document (as suggested by Stephen Boyd) > * Minor code style fixes (as suggested by Stephen Boyd) > * Use ioremap (as suggested by Stephen Boyd) > * Implement round_rate (as suggested by Stephen Boyd) > * Change to platform driver (as suggested by Stephen Boyd) > * Use {readl/writel}_relaxed (as suggested by Vineet Gupta) > > Changes v2 -> v3: > * Implemented recalc_rate > > Changes v1 -> v2: > * Renamed folder to axs10x (as suggested by Alexey Brodkin) > * Added more supported rates > > Cc: Carlos Palminha > Cc: Rob Herring > Cc: Pawel Moll > Cc: Mark Rutland > Cc: Ian Campbell > Cc: Kumar Gala > Cc: Michael Turquette > Cc: Stephen Boyd > Cc: Alexey Brodkin > Cc: Vineet Gupta > Cc: linux-snps-...@lists.infradead.org > Cc: devicet...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: linux-...@vger.kernel.org > > .../bindings/clock/axs10x-i2s-pll-clock.txt| 25 +++ Acked-by: Rob Herring > drivers/clk/Makefile | 1 + > drivers/clk/axs10x/Makefile| 1 + > drivers/clk/axs10x/i2s_pll_clock.c | 228 > + > 4 files changed, 255 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt > create mode 100644 drivers/clk/axs10x/Makefile > create mode 100644 drivers/clk/axs10x/i2s_pll_clock.c
Re: [RESEND PATCH 1/2 v6] clk/axs10x: Add I2S PLL clock driver
On Mon, May 02, 2016 at 10:39:05AM +0100, Jose Abreu wrote: > The ARC SDP I2S clock can be programmed using a > specific PLL. > > This patch has the goal of adding a clock driver > that programs this PLL. > > At this moment the rate values are hardcoded in > a table but in the future it would be ideal to > use a function which determines the PLL values > given the desired rate. > > Signed-off-by: Jose Abreu > --- > > Changes v5 -> v6: > * Use parent clock to determine PLL input rate instead of using hardcoded > values > * Documentation update (added 'clocks' field) > > Changes v4 -> v5: > * Documentation update (as suggested by Alexey Brodkin) > * Changed compatible string to "snps,axs10x-i2s-pll-clock" (as suggested by > Alexey Brodkin) > > Changes v3 -> v4: > * Added binding document (as suggested by Stephen Boyd) > * Minor code style fixes (as suggested by Stephen Boyd) > * Use ioremap (as suggested by Stephen Boyd) > * Implement round_rate (as suggested by Stephen Boyd) > * Change to platform driver (as suggested by Stephen Boyd) > * Use {readl/writel}_relaxed (as suggested by Vineet Gupta) > > Changes v2 -> v3: > * Implemented recalc_rate > > Changes v1 -> v2: > * Renamed folder to axs10x (as suggested by Alexey Brodkin) > * Added more supported rates > > Cc: Carlos Palminha > Cc: Rob Herring > Cc: Pawel Moll > Cc: Mark Rutland > Cc: Ian Campbell > Cc: Kumar Gala > Cc: Michael Turquette > Cc: Stephen Boyd > Cc: Alexey Brodkin > Cc: Vineet Gupta > Cc: linux-snps-...@lists.infradead.org > Cc: devicet...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: linux-...@vger.kernel.org > > .../bindings/clock/axs10x-i2s-pll-clock.txt| 25 +++ Acked-by: Rob Herring > drivers/clk/Makefile | 1 + > drivers/clk/axs10x/Makefile| 1 + > drivers/clk/axs10x/i2s_pll_clock.c | 228 > + > 4 files changed, 255 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt > create mode 100644 drivers/clk/axs10x/Makefile > create mode 100644 drivers/clk/axs10x/i2s_pll_clock.c
[RESEND PATCH 1/2 v6] clk/axs10x: Add I2S PLL clock driver
The ARC SDP I2S clock can be programmed using a specific PLL. This patch has the goal of adding a clock driver that programs this PLL. At this moment the rate values are hardcoded in a table but in the future it would be ideal to use a function which determines the PLL values given the desired rate. Signed-off-by: Jose Abreu--- Changes v5 -> v6: * Use parent clock to determine PLL input rate instead of using hardcoded values * Documentation update (added 'clocks' field) Changes v4 -> v5: * Documentation update (as suggested by Alexey Brodkin) * Changed compatible string to "snps,axs10x-i2s-pll-clock" (as suggested by Alexey Brodkin) Changes v3 -> v4: * Added binding document (as suggested by Stephen Boyd) * Minor code style fixes (as suggested by Stephen Boyd) * Use ioremap (as suggested by Stephen Boyd) * Implement round_rate (as suggested by Stephen Boyd) * Change to platform driver (as suggested by Stephen Boyd) * Use {readl/writel}_relaxed (as suggested by Vineet Gupta) Changes v2 -> v3: * Implemented recalc_rate Changes v1 -> v2: * Renamed folder to axs10x (as suggested by Alexey Brodkin) * Added more supported rates Cc: Carlos Palminha Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Michael Turquette Cc: Stephen Boyd Cc: Alexey Brodkin Cc: Vineet Gupta Cc: linux-snps-...@lists.infradead.org Cc: devicet...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-...@vger.kernel.org .../bindings/clock/axs10x-i2s-pll-clock.txt| 25 +++ drivers/clk/Makefile | 1 + drivers/clk/axs10x/Makefile| 1 + drivers/clk/axs10x/i2s_pll_clock.c | 228 + 4 files changed, 255 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt create mode 100644 drivers/clk/axs10x/Makefile create mode 100644 drivers/clk/axs10x/i2s_pll_clock.c diff --git a/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt b/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt new file mode 100644 index 000..5ffc8df --- /dev/null +++ b/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt @@ -0,0 +1,25 @@ +Binding for the AXS10X I2S PLL clock + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: shall be "snps,axs10x-i2s-pll-clock" +- reg : address and length of the I2S PLL register set. +- clocks: shall be the input parent clock phandle for the PLL. +- #clock-cells: from common clock binding; Should always be set to 0. + +Example: + pll_clock: pll_clock { + compatible = "fixed-clock"; + clock-frequency = <2700>; + #clock-cells = <0>; + }; + + i2s_clock@100a0 { + compatible = "snps,axs10x-i2s-pll-clock"; + reg = <0x100a0 0x10>; + clocks = <_clock>; + #clock-cells = <0>; + }; diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 46869d6..2ca62dc6 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -84,3 +84,4 @@ obj-$(CONFIG_X86) += x86/ obj-$(CONFIG_ARCH_ZX) += zte/ obj-$(CONFIG_ARCH_ZYNQ)+= zynq/ obj-$(CONFIG_H8300)+= h8300/ +obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ diff --git a/drivers/clk/axs10x/Makefile b/drivers/clk/axs10x/Makefile new file mode 100644 index 000..01996b8 --- /dev/null +++ b/drivers/clk/axs10x/Makefile @@ -0,0 +1 @@ +obj-y += i2s_pll_clock.o diff --git a/drivers/clk/axs10x/i2s_pll_clock.c b/drivers/clk/axs10x/i2s_pll_clock.c new file mode 100644 index 000..411310d --- /dev/null +++ b/drivers/clk/axs10x/i2s_pll_clock.c @@ -0,0 +1,228 @@ +/* + * Synopsys AXS10X SDP I2S PLL clock driver + * + * Copyright (C) 2016 Synopsys + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* PLL registers addresses */ +#define PLL_IDIV_REG 0x0 +#define PLL_FBDIV_REG 0x4 +#define PLL_ODIV0_REG 0x8 +#define PLL_ODIV1_REG 0xC + +struct i2s_pll_cfg { + unsigned int rate; + unsigned int idiv; + unsigned int fbdiv; + unsigned int odiv0; + unsigned int odiv1; +}; + +static const struct i2s_pll_cfg i2s_pll_cfg_27m[] = { + /* 27 Mhz */ + { 1024000, 0x104, 0x451, 0x10E38, 0x2000 }, + { 1411200, 0x104, 0x596, 0x10D35, 0x2000 }, + {
[RESEND PATCH 1/2 v6] clk/axs10x: Add I2S PLL clock driver
The ARC SDP I2S clock can be programmed using a specific PLL. This patch has the goal of adding a clock driver that programs this PLL. At this moment the rate values are hardcoded in a table but in the future it would be ideal to use a function which determines the PLL values given the desired rate. Signed-off-by: Jose Abreu --- Changes v5 -> v6: * Use parent clock to determine PLL input rate instead of using hardcoded values * Documentation update (added 'clocks' field) Changes v4 -> v5: * Documentation update (as suggested by Alexey Brodkin) * Changed compatible string to "snps,axs10x-i2s-pll-clock" (as suggested by Alexey Brodkin) Changes v3 -> v4: * Added binding document (as suggested by Stephen Boyd) * Minor code style fixes (as suggested by Stephen Boyd) * Use ioremap (as suggested by Stephen Boyd) * Implement round_rate (as suggested by Stephen Boyd) * Change to platform driver (as suggested by Stephen Boyd) * Use {readl/writel}_relaxed (as suggested by Vineet Gupta) Changes v2 -> v3: * Implemented recalc_rate Changes v1 -> v2: * Renamed folder to axs10x (as suggested by Alexey Brodkin) * Added more supported rates Cc: Carlos Palminha Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Michael Turquette Cc: Stephen Boyd Cc: Alexey Brodkin Cc: Vineet Gupta Cc: linux-snps-...@lists.infradead.org Cc: devicet...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-...@vger.kernel.org .../bindings/clock/axs10x-i2s-pll-clock.txt| 25 +++ drivers/clk/Makefile | 1 + drivers/clk/axs10x/Makefile| 1 + drivers/clk/axs10x/i2s_pll_clock.c | 228 + 4 files changed, 255 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt create mode 100644 drivers/clk/axs10x/Makefile create mode 100644 drivers/clk/axs10x/i2s_pll_clock.c diff --git a/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt b/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt new file mode 100644 index 000..5ffc8df --- /dev/null +++ b/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt @@ -0,0 +1,25 @@ +Binding for the AXS10X I2S PLL clock + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: shall be "snps,axs10x-i2s-pll-clock" +- reg : address and length of the I2S PLL register set. +- clocks: shall be the input parent clock phandle for the PLL. +- #clock-cells: from common clock binding; Should always be set to 0. + +Example: + pll_clock: pll_clock { + compatible = "fixed-clock"; + clock-frequency = <2700>; + #clock-cells = <0>; + }; + + i2s_clock@100a0 { + compatible = "snps,axs10x-i2s-pll-clock"; + reg = <0x100a0 0x10>; + clocks = <_clock>; + #clock-cells = <0>; + }; diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 46869d6..2ca62dc6 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -84,3 +84,4 @@ obj-$(CONFIG_X86) += x86/ obj-$(CONFIG_ARCH_ZX) += zte/ obj-$(CONFIG_ARCH_ZYNQ)+= zynq/ obj-$(CONFIG_H8300)+= h8300/ +obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ diff --git a/drivers/clk/axs10x/Makefile b/drivers/clk/axs10x/Makefile new file mode 100644 index 000..01996b8 --- /dev/null +++ b/drivers/clk/axs10x/Makefile @@ -0,0 +1 @@ +obj-y += i2s_pll_clock.o diff --git a/drivers/clk/axs10x/i2s_pll_clock.c b/drivers/clk/axs10x/i2s_pll_clock.c new file mode 100644 index 000..411310d --- /dev/null +++ b/drivers/clk/axs10x/i2s_pll_clock.c @@ -0,0 +1,228 @@ +/* + * Synopsys AXS10X SDP I2S PLL clock driver + * + * Copyright (C) 2016 Synopsys + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* PLL registers addresses */ +#define PLL_IDIV_REG 0x0 +#define PLL_FBDIV_REG 0x4 +#define PLL_ODIV0_REG 0x8 +#define PLL_ODIV1_REG 0xC + +struct i2s_pll_cfg { + unsigned int rate; + unsigned int idiv; + unsigned int fbdiv; + unsigned int odiv0; + unsigned int odiv1; +}; + +static const struct i2s_pll_cfg i2s_pll_cfg_27m[] = { + /* 27 Mhz */ + { 1024000, 0x104, 0x451, 0x10E38, 0x2000 }, + { 1411200, 0x104, 0x596, 0x10D35, 0x2000 }, + { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 }, + { 2048000, 0x82, 0x451, 0x10E38, 0x2000 }, + { 2822400, 0x82, 0x596, 0x10D35, 0x2000 }, + { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 }, + { 2116800, 0x82, 0x3CF, 0x10C30, 0x2000 }, +