Re: [RFC 1/3] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
On 5/8/2020 5:45 AM, Felipe Balbi wrote:
>
> Hi,
>
> Wesley Cheng writes:
>> Some devices have USB compositions which may require multiple endpoints
>> that support EP bursting. HW defined TX FIFO sizes may not always be
>> sufficient for these compositions. By utilizing flexible TX FIFO
>> allocation, this allows for endpoints to request the required FIFO depth to
>> achieve higher bandwidth. With some higher bMaxBurst configurations, using
>> a larger TX FIFO size results in better TX throughput.
>
> This needs to be carefully thought out as it can introduce situations
> where gadget drivers that worked previously stop working.
>
Hi Felipe,
Thanks for the feedback. I agree, the TX FIFO resizing logic should be
reviewed carefully to, in order not to cause any regressions. Would you
be willing to shed some light on some of the failures you've seen
previously where the gadget drivers stopped working? (would help
possibly come up with better approaches, etc...)
>> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
>> index 4c171a8..e815c13 100644
>> --- a/drivers/usb/dwc3/core.h
>> +++ b/drivers/usb/dwc3/core.h
>> @@ -675,6 +675,7 @@ struct dwc3_event_buffer {
>> * isochronous START TRANSFER command failure workaround
>> * @start_cmd_status: the status of testing START TRANSFER command with
>> * combo_num = 'b00
>> + * @fifo_depth: allocated TXFIFO depth
>> */
>> struct dwc3_ep {
>> struct usb_ep endpoint;
>> @@ -718,6 +719,7 @@ struct dwc3_ep {
>> u8 resource_index;
>> u32 frame_number;
>> u32 interval;
>> +int fifo_depth;
>>
>> charname[20];
>>
>> @@ -1004,6 +1006,7 @@ struct dwc3_scratchpad_array {
>> * 1 - utmi_l1_suspend_n
>> * @is_fpga: true when we are using the FPGA board
>> * @pending_events: true when we have pending IRQs to be handled
>> + * @needs_fifo_resize: not all users might want fifo resizing, flag it
>> * @pullups_connected: true when Run/Stop bit is set
>> * @setup_packet_pending: true when there's a Setup Packet in FIFO.
>> Workaround
>> * @three_stage_setup: set if we perform a three phase setup
>> @@ -1044,6 +1047,7 @@ struct dwc3_scratchpad_array {
>> * @dis_metastability_quirk: set to disable metastability quirk.
>> * @imod_interval: set the interrupt moderation interval in 250ns
>> * increments or 0 to disable.
>> + * @last_fifo_depth: total TXFIFO depth of all enabled USB IN/INT endpoints
>> */
>> struct dwc3 {
>> struct work_struct drd_work;
>> @@ -1204,6 +1208,7 @@ struct dwc3 {
>> unsignedis_utmi_l1_suspend:1;
>> unsignedis_fpga:1;
>> unsignedpending_events:1;
>> +unsignedneeds_fifo_resize:1;
>
> Instead of passing a flag, this could be detected in runtime during
> ->udc_start()
>
The flag was going to serve the purpose of allowing platforms to define
if they want to enable the TX FIFO resizing logic or not. Maybe in
their particular HW platform, the HW default FIFO settings are sufficient.
>> diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
>> index 6dee4da..7ee2302 100644
>> --- a/drivers/usb/dwc3/ep0.c
>> +++ b/drivers/usb/dwc3/ep0.c
>> @@ -611,6 +612,43 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct
>> usb_ctrlrequest *ctrl)
>> return -EINVAL;
>>
>> case USB_STATE_ADDRESS:
>
> are you sure it's safe to fiddle with TX FIFO allocation at SetAddress()
> time?
>
It should be acceptable, as the function drivers shouldn't be calling
usb_ep_enable() until we receive a SET_CONFIG from the host to enable
the configuration. __dwc3_gadget_ep_enable() -->
dwc3_gadget_set_ep_config() is where we'd assign the EP to a particular
TX FIFO.
>> +/*
>> + * If tx-fifo-resize flag is not set for the controller, then
>> + * do not clear existing allocated TXFIFO since we do not
>> + * allocate it again in dwc3_gadget_resize_tx_fifos
>> + */
>> +if (dwc->needs_fifo_resize) {
>> +/* Read ep0IN related TXFIFO size */
>> +dep = dwc->eps[1];
>> +size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
>> +if (dwc3_is_usb31(dwc))
>> +dep->fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
>> +else
>> +dep->fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
>> +
>> +dwc->last_fifo_depth = dep->fifo_depth;
>> +/* Clear existing TXFIFO for all IN eps except ep0 */
>> +for (num = 3; num < min_t(int, dwc->num_eps,
>> +DWC3_ENDPOINTS_NUM); num += 2) {
>> +dep = dwc->eps[num];
>> +
Re: [RFC 1/3] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
Hi,
Wesley Cheng writes:
> Some devices have USB compositions which may require multiple endpoints
> that support EP bursting. HW defined TX FIFO sizes may not always be
> sufficient for these compositions. By utilizing flexible TX FIFO
> allocation, this allows for endpoints to request the required FIFO depth to
> achieve higher bandwidth. With some higher bMaxBurst configurations, using
> a larger TX FIFO size results in better TX throughput.
This needs to be carefully thought out as it can introduce situations
where gadget drivers that worked previously stop working.
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 4c171a8..e815c13 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -675,6 +675,7 @@ struct dwc3_event_buffer {
> * isochronous START TRANSFER command failure workaround
> * @start_cmd_status: the status of testing START TRANSFER command with
> * combo_num = 'b00
> + * @fifo_depth: allocated TXFIFO depth
> */
> struct dwc3_ep {
> struct usb_ep endpoint;
> @@ -718,6 +719,7 @@ struct dwc3_ep {
> u8 resource_index;
> u32 frame_number;
> u32 interval;
> + int fifo_depth;
>
> charname[20];
>
> @@ -1004,6 +1006,7 @@ struct dwc3_scratchpad_array {
> * 1 - utmi_l1_suspend_n
> * @is_fpga: true when we are using the FPGA board
> * @pending_events: true when we have pending IRQs to be handled
> + * @needs_fifo_resize: not all users might want fifo resizing, flag it
> * @pullups_connected: true when Run/Stop bit is set
> * @setup_packet_pending: true when there's a Setup Packet in FIFO.
> Workaround
> * @three_stage_setup: set if we perform a three phase setup
> @@ -1044,6 +1047,7 @@ struct dwc3_scratchpad_array {
> * @dis_metastability_quirk: set to disable metastability quirk.
> * @imod_interval: set the interrupt moderation interval in 250ns
> * increments or 0 to disable.
> + * @last_fifo_depth: total TXFIFO depth of all enabled USB IN/INT endpoints
> */
> struct dwc3 {
> struct work_struct drd_work;
> @@ -1204,6 +1208,7 @@ struct dwc3 {
> unsignedis_utmi_l1_suspend:1;
> unsignedis_fpga:1;
> unsignedpending_events:1;
> + unsignedneeds_fifo_resize:1;
Instead of passing a flag, this could be detected in runtime during
->udc_start()
> diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
> index 6dee4da..7ee2302 100644
> --- a/drivers/usb/dwc3/ep0.c
> +++ b/drivers/usb/dwc3/ep0.c
> @@ -611,6 +612,43 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct
> usb_ctrlrequest *ctrl)
> return -EINVAL;
>
> case USB_STATE_ADDRESS:
are you sure it's safe to fiddle with TX FIFO allocation at SetAddress()
time?
> + /*
> + * If tx-fifo-resize flag is not set for the controller, then
> + * do not clear existing allocated TXFIFO since we do not
> + * allocate it again in dwc3_gadget_resize_tx_fifos
> + */
> + if (dwc->needs_fifo_resize) {
> + /* Read ep0IN related TXFIFO size */
> + dep = dwc->eps[1];
> + size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
> + if (dwc3_is_usb31(dwc))
> + dep->fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
> + else
> + dep->fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
> +
> + dwc->last_fifo_depth = dep->fifo_depth;
> + /* Clear existing TXFIFO for all IN eps except ep0 */
> + for (num = 3; num < min_t(int, dwc->num_eps,
> + DWC3_ENDPOINTS_NUM); num += 2) {
> + dep = dwc->eps[num];
> + /* Don't change TXFRAMNUM on usb31 version */
> + size = dwc3_is_usb31(dwc) ?
> + dwc3_readl(dwc->regs,
> +DWC3_GTXFIFOSIZ(num >> 1)) &
> +DWC31_GTXFIFOSIZ_TXFRAMNUM :
> +0;
> +
> + dwc3_writel(dwc->regs,
> + DWC3_GTXFIFOSIZ(num >> 1),
> + size);
> + dep->fifo_depth = 0;
> +
> + dev_dbg(dwc->dev, "%s(): %s fifo_depth:%x\n",
> + __func__, dep->name,
> + dep->fifo_depth);
no dev_dbg() calls in this driver, please.
> diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
> index 00746c2.
[RFC 1/3] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
Some devices have USB compositions which may require multiple endpoints
that support EP bursting. HW defined TX FIFO sizes may not always be
sufficient for these compositions. By utilizing flexible TX FIFO
allocation, this allows for endpoints to request the required FIFO depth to
achieve higher bandwidth. With some higher bMaxBurst configurations, using
a larger TX FIFO size results in better TX throughput.
Signed-off-by: Wesley Cheng
---
drivers/usb/dwc3/core.c | 2 +
drivers/usb/dwc3/core.h | 6 +++
drivers/usb/dwc3/ep0.c| 40 +++-
drivers/usb/dwc3/gadget.c | 95 +++
4 files changed, 142 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index edc1715..cca5554 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1304,6 +1304,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
&tx_thr_num_pkt_prd);
device_property_read_u8(dev, "snps,tx-max-burst-prd",
&tx_max_burst_prd);
+ dwc->needs_fifo_resize = device_property_read_bool(dev,
+ "tx-fifo-resize");
dwc->disable_scramble_quirk = device_property_read_bool(dev,
"snps,disable_scramble_quirk");
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4c171a8..e815c13 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -675,6 +675,7 @@ struct dwc3_event_buffer {
* isochronous START TRANSFER command failure workaround
* @start_cmd_status: the status of testing START TRANSFER command with
* combo_num = 'b00
+ * @fifo_depth: allocated TXFIFO depth
*/
struct dwc3_ep {
struct usb_ep endpoint;
@@ -718,6 +719,7 @@ struct dwc3_ep {
u8 resource_index;
u32 frame_number;
u32 interval;
+ int fifo_depth;
charname[20];
@@ -1004,6 +1006,7 @@ struct dwc3_scratchpad_array {
* 1 - utmi_l1_suspend_n
* @is_fpga: true when we are using the FPGA board
* @pending_events: true when we have pending IRQs to be handled
+ * @needs_fifo_resize: not all users might want fifo resizing, flag it
* @pullups_connected: true when Run/Stop bit is set
* @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
* @three_stage_setup: set if we perform a three phase setup
@@ -1044,6 +1047,7 @@ struct dwc3_scratchpad_array {
* @dis_metastability_quirk: set to disable metastability quirk.
* @imod_interval: set the interrupt moderation interval in 250ns
* increments or 0 to disable.
+ * @last_fifo_depth: total TXFIFO depth of all enabled USB IN/INT endpoints
*/
struct dwc3 {
struct work_struct drd_work;
@@ -1204,6 +1208,7 @@ struct dwc3 {
unsignedis_utmi_l1_suspend:1;
unsignedis_fpga:1;
unsignedpending_events:1;
+ unsignedneeds_fifo_resize:1;
unsignedpullups_connected:1;
unsignedsetup_packet_pending:1;
unsignedthree_stage_setup:1;
@@ -1236,6 +1241,7 @@ struct dwc3 {
unsigneddis_metastability_quirk:1;
u16 imod_interval;
+ int last_fifo_depth;
};
#define INCRX_BURST_MODE 0
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 6dee4da..7ee2302 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -601,8 +601,9 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct
usb_ctrlrequest *ctrl)
{
enum usb_device_state state = dwc->gadget.state;
u32 cfg;
- int ret;
+ int ret, num, size;
u32 reg;
+ struct dwc3_ep *dep;
cfg = le16_to_cpu(ctrl->wValue);
@@ -611,6 +612,43 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct
usb_ctrlrequest *ctrl)
return -EINVAL;
case USB_STATE_ADDRESS:
+ /*
+* If tx-fifo-resize flag is not set for the controller, then
+* do not clear existing allocated TXFIFO since we do not
+* allocate it again in dwc3_gadget_resize_tx_fifos
+*/
+ if (dwc->needs_fifo_resize) {
+ /* Read ep0IN related TXFIFO size */
+ dep = dwc->eps[1];
+ size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+ if (dwc3_is_usb31(dwc))
+ dep->fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
+ else
+ dep->fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
+
+ dwc->last_fifo_depth = dep->fifo_depth;
+
