Re: [RFC PATCH 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver

2021-03-08 Thread Greentime Hu 
Philipp Zabel  於 2021年3月4日 週四 下午7:58寫道：
>
> On Tue, 2021-03-02 at 18:59 +0800, Greentime Hu wrote:
> > We use reset-simple in this patch so that pcie driver can use
> > devm_reset_control_get() to get this reset data structure and use
> > reset_control_deassert() to deassert pcie_power_up_rst_n.
> >
> > Signed-off-by: Greentime Hu 
> > ---
> >  drivers/clk/sifive/Kconfig   |  2 ++
> >  drivers/clk/sifive/sifive-prci.c | 14 ++
> >  drivers/clk/sifive/sifive-prci.h |  4 
> >  drivers/reset/Kconfig|  3 ++-
> >  4 files changed, 22 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
> > index 1c14eb20c066..9132c3c4aa86 100644
> > --- a/drivers/clk/sifive/Kconfig
> > +++ b/drivers/clk/sifive/Kconfig
> > @@ -10,6 +10,8 @@ if CLK_SIFIVE
> >
> >  config CLK_SIFIVE_PRCI
> >   bool "PRCI driver for SiFive SoCs"
> > + select RESET_CONTROLLER
> > + select RESET_SIMPLE
> >   select CLK_ANALOGBITS_WRPLL_CLN28HPC
> >   help
> > Supports the Power Reset Clock interface (PRCI) IP block found in
> > diff --git a/drivers/clk/sifive/sifive-prci.c 
> > b/drivers/clk/sifive/sifive-prci.c
> > index baf7313dac92..925affc6de55 100644
> > --- a/drivers/clk/sifive/sifive-prci.c
> > +++ b/drivers/clk/sifive/sifive-prci.c
> > @@ -583,7 +583,21 @@ static int sifive_prci_probe(struct platform_device 
> > *pdev)
> >   if (IS_ERR(pd->va))
> >   return PTR_ERR(pd->va);
> >
> > + pd->reset.rcdev.owner = THIS_MODULE;
> > + pd->reset.rcdev.nr_resets = PRCI_RST_NR;
> > + pd->reset.rcdev.ops = _simple_ops;
> > + pd->reset.rcdev.of_node = pdev->dev.of_node;
> > + pd->reset.active_low = true;
> > + pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;
> > + spin_lock_init(>reset.lock);
> > +
> > + r = devm_reset_controller_register(>dev, >reset.rcdev);
> > + if (r) {
> > + dev_err(dev, "could not register reset controller: %d\n", r);
> > + return r;
> > + }
> >   r = __prci_register_clocks(dev, pd, desc);
> > +
>
> Accidental whitespace?
>
> Otherwise,
>
> Reviewed-by: Philipp Zabel 

Thank you, Philipp.
Yes, it is an accidental whitespace. I'll remove it in my next version patch.

Re: [RFC PATCH 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver

2021-03-04 Thread Philipp Zabel 
On Tue, 2021-03-02 at 18:59 +0800, Greentime Hu wrote:
> We use reset-simple in this patch so that pcie driver can use
> devm_reset_control_get() to get this reset data structure and use
> reset_control_deassert() to deassert pcie_power_up_rst_n.
> 
> Signed-off-by: Greentime Hu 
> ---
>  drivers/clk/sifive/Kconfig   |  2 ++
>  drivers/clk/sifive/sifive-prci.c | 14 ++
>  drivers/clk/sifive/sifive-prci.h |  4 
>  drivers/reset/Kconfig|  3 ++-
>  4 files changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
> index 1c14eb20c066..9132c3c4aa86 100644
> --- a/drivers/clk/sifive/Kconfig
> +++ b/drivers/clk/sifive/Kconfig
> @@ -10,6 +10,8 @@ if CLK_SIFIVE
>  
>  config CLK_SIFIVE_PRCI
>   bool "PRCI driver for SiFive SoCs"
> + select RESET_CONTROLLER
> + select RESET_SIMPLE
>   select CLK_ANALOGBITS_WRPLL_CLN28HPC
>   help
> Supports the Power Reset Clock interface (PRCI) IP block found in
> diff --git a/drivers/clk/sifive/sifive-prci.c 
> b/drivers/clk/sifive/sifive-prci.c
> index baf7313dac92..925affc6de55 100644
> --- a/drivers/clk/sifive/sifive-prci.c
> +++ b/drivers/clk/sifive/sifive-prci.c
> @@ -583,7 +583,21 @@ static int sifive_prci_probe(struct platform_device 
> *pdev)
>   if (IS_ERR(pd->va))
>   return PTR_ERR(pd->va);
>  
> + pd->reset.rcdev.owner = THIS_MODULE;
> + pd->reset.rcdev.nr_resets = PRCI_RST_NR;
> + pd->reset.rcdev.ops = _simple_ops;
> + pd->reset.rcdev.of_node = pdev->dev.of_node;
> + pd->reset.active_low = true;
> + pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;
> + spin_lock_init(>reset.lock);
> +
> + r = devm_reset_controller_register(>dev, >reset.rcdev);
> + if (r) {
> + dev_err(dev, "could not register reset controller: %d\n", r);
> + return r;
> + }
>   r = __prci_register_clocks(dev, pd, desc);
> +

Accidental whitespace?

Otherwise,

Reviewed-by: Philipp Zabel 

regards
Philipp

[RFC PATCH 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver

2021-03-02 Thread Greentime Hu 
We use reset-simple in this patch so that pcie driver can use
devm_reset_control_get() to get this reset data structure and use
reset_control_deassert() to deassert pcie_power_up_rst_n.

Signed-off-by: Greentime Hu 
---
 drivers/clk/sifive/Kconfig   |  2 ++
 drivers/clk/sifive/sifive-prci.c | 14 ++
 drivers/clk/sifive/sifive-prci.h |  4 
 drivers/reset/Kconfig|  3 ++-
 4 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
index 1c14eb20c066..9132c3c4aa86 100644
--- a/drivers/clk/sifive/Kconfig
+++ b/drivers/clk/sifive/Kconfig
@@ -10,6 +10,8 @@ if CLK_SIFIVE
 
 config CLK_SIFIVE_PRCI
bool "PRCI driver for SiFive SoCs"
+   select RESET_CONTROLLER
+   select RESET_SIMPLE
select CLK_ANALOGBITS_WRPLL_CLN28HPC
help
  Supports the Power Reset Clock interface (PRCI) IP block found in
diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
index baf7313dac92..925affc6de55 100644
--- a/drivers/clk/sifive/sifive-prci.c
+++ b/drivers/clk/sifive/sifive-prci.c
@@ -583,7 +583,21 @@ static int sifive_prci_probe(struct platform_device *pdev)
if (IS_ERR(pd->va))
return PTR_ERR(pd->va);
 
+   pd->reset.rcdev.owner = THIS_MODULE;
+   pd->reset.rcdev.nr_resets = PRCI_RST_NR;
+   pd->reset.rcdev.ops = _simple_ops;
+   pd->reset.rcdev.of_node = pdev->dev.of_node;
+   pd->reset.active_low = true;
+   pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;
+   spin_lock_init(>reset.lock);
+
+   r = devm_reset_controller_register(>dev, >reset.rcdev);
+   if (r) {
+   dev_err(dev, "could not register reset controller: %d\n", r);
+   return r;
+   }
r = __prci_register_clocks(dev, pd, desc);
+
if (r) {
dev_err(dev, "could not register clocks: %d\n", r);
return r;
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
index 022c67cf053c..91658a88af4e 100644
--- a/drivers/clk/sifive/sifive-prci.h
+++ b/drivers/clk/sifive/sifive-prci.h
@@ -11,6 +11,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 /*
@@ -121,6 +122,8 @@
 #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK   \
(0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT)
 
+#define PRCI_RST_NR7
+
 /* CLKMUXSTATUSREG */
 #define PRCI_CLKMUXSTATUSREG_OFFSET0x2c
 #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
@@ -221,6 +224,7 @@
  */
 struct __prci_data {
void __iomem *va;
+   struct reset_simple_data reset;
struct clk_hw_onecell_data hw_clks;
 };
 
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..f094df93d911 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -173,7 +173,7 @@ config RESET_SCMI
 
 config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
-   default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || 
ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
+   default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || 
ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC || RISCV
help
  This enables a simple reset controller driver for reset lines that
  that can be asserted and deasserted by toggling bits in a contiguous,
@@ -187,6 +187,7 @@ config RESET_SIMPLE
   - RCC reset controller in STM32 MCUs
   - Allwinner SoCs
   - ZTE's zx2967 family
+  - SiFive FU740 SoCs
 
 config RESET_STM32MP157
bool "STM32MP157 Reset Driver" if COMPILE_TEST
-- 
2.30.0