subject:"\[RFC PATCH 4\/6\] PCI\: exynos5433\: Add new exynos pci host controller for Exynos5433"

Re: [RFC PATCH 4/6] PCI: exynos5433: Add new exynos pci host controller for Exynos5433

2016-12-26 Thread Jaehoon Chung

On 12/26/2016 08:49 PM, Joao Pinto wrote:
> 
> Hello Jaehoon,
> 
> Às 5:20 AM de 12/26/2016, Jaehoon Chung escreveu:
>> Exynos5433 supports the PCIe.
>> This patch adds new pci-exynos5433.c file for Exynos ARM64.
>>
>> Signed-off-by: Jaehoon Chung 
>> ---
>>  drivers/pci/host/Kconfig  |   9 +
>>  drivers/pci/host/Makefile |   1 +
>>  drivers/pci/host/pci-exynos5433.c | 338 
>> ++
>>  3 files changed, 348 insertions(+)
>>  create mode 100644 drivers/pci/host/pci-exynos5433.c
>>
>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> index d7e7c0a..3d77d0b 100644
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>> @@ -60,6 +60,15 @@ config PCI_EXYNOS
>>  select PCIEPORTBUS
>>  select PCIE_DW
>>  
>> +config PCI_EXYNOS5433
>> +bool "Samsung Exynos5433 PCIe controller"
>> +depends on ARCH_EXYNOS && ARM64
>> +depends on PCI_MSI_IRQ_DOMAIN
>> +select PCIEPORTBUS
>> +select PCIE_DW
>> +help
>> +  If you want support for Exynos5433 PCIe host controller, say Y.
>> +
>>  config PCI_IMX6
>>  bool "Freescale i.MX6 PCIe controller"
>>  depends on SOC_IMX6Q
>> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
>> index 084cb49..2168de2 100644
>> --- a/drivers/pci/host/Makefile
>> +++ b/drivers/pci/host/Makefile
>> @@ -2,6 +2,7 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o
>>  obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
>>  obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
>>  obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
>> +obj-$(CONFIG_PCI_EXYNOS5433) += pci-exynos5433.o
>>  obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
>>  obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o
>>  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
>> diff --git a/drivers/pci/host/pci-exynos5433.c 
>> b/drivers/pci/host/pci-exynos5433.c
>> new file mode 100644
>> index 000..ff254ca
>> --- /dev/null
>> +++ b/drivers/pci/host/pci-exynos5433.c
>> @@ -0,0 +1,338 @@
>> +/*
>> + * PCIe host controller driver for Samsung EXYNOS5433 SoCs
>> + *
>> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
>> + *  
>> https://urldefense.proofpoint.com/v2/url?u=http-3A__www.samsung.com&d=DgIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=s2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=fUwnZks1U2AwaOxMkLdSnE700sfQXpB3WAg_EJw7NaE&s=IwRYD8maTuXG57Q0qlAmFNh3_TSfUTE27xq8p13FFKI&e=
>>  
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include "pcie-designware.h"
>> +
>> +#define to_exynos_pcie(x)   container_of(x, struct exynos_pcie, pp)
>> +
>> +/* Pcie structure for Exynos specific data */
>> +struct exynos_pcie {
>> +void __iomem*elbi_base;
>> +struct clk  *clk;
>> +struct clk  *bus_clk;
>> +struct pcie_portpp;
>> +struct phy  *phy;
>> +};
>> +
>> +/* PCIe ELBI registers */
>> +#define PCIE_IRQ_PULSE  0x000
>> +#define IRQ_INTA_ASSERT BIT(0)
>> +#define IRQ_INTB_ASSERT BIT(2)
>> +#define IRQ_INTC_ASSERT BIT(4)
>> +#define IRQ_INTD_ASSERT BIT(6)
>> +#define IRQ_INTX_ASSERT (IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | \
>> +IRQ_INTC_ASSERT | IRQ_INTD_ASSERT)
>> +#define PCIE_IRQ_EN_PULSE   0x00c
>> +#define PCIE_IRQ_EN_LEVEL   0x010
>> +#define PCIE_SW_WAKE0x018
>> +#define PCIE_BUS_EN BIT(1)
>> +#define PCIE_APP_LTSSM_ENABLE   0x02c
>> +#define PCIE_ELBI_LTSSM_ENABLE  0x1
>> +#define PCIE_ELBI_DEBUG_L   0x074
>> +#define PCIE_ELBI_XMLH_LINK_UP  BIT(4)
>> +#define PCIE_ELBI_SLV_AWMISC0x11c
>> +#define PCIE_ELBI_SLV_ARMISC0x120
>> +#define PCIE_ELBI_SLV_DBI_ENABLEBIT(21)
>> +
>> +/* DBI register */
>> +#define PCIE_MISC_CONTROL_1_OFF 0x8BC
>> +#define DBI_RO_WR_ENBIT(0)
>> +
>> +static inline void exynos_pcie_writel(void __iomem *base, u32 val, u32 
>> offset)
>> +{
>> +writel(val, base + offset);
>> +}
>> +
>> +static inline u32 exynos_pcie_readl(void __iomem *base, u32 offset)
>> +{
>> +return readl(base + offset);
>> +}
>> +
>> +static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
>> +{
>> +u32 val;
>> +
>> +val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE);
>> +val &= ~IRQ_INTX_ASSERT;
>> +exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE);
>> +}
>> +
>> +static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
>> +{
>> +exynos_pcie_writel(ep->elbi_base, IRQ_IN

Re: [RFC PATCH 4/6] PCI: exynos5433: Add new exynos pci host controller for Exynos5433

2016-12-26 Thread Joao Pinto


Hello Jaehoon,

Às 5:20 AM de 12/26/2016, Jaehoon Chung escreveu:
> Exynos5433 supports the PCIe.
> This patch adds new pci-exynos5433.c file for Exynos ARM64.
> 
> Signed-off-by: Jaehoon Chung 
> ---
>  drivers/pci/host/Kconfig  |   9 +
>  drivers/pci/host/Makefile |   1 +
>  drivers/pci/host/pci-exynos5433.c | 338 
> ++
>  3 files changed, 348 insertions(+)
>  create mode 100644 drivers/pci/host/pci-exynos5433.c
> 
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index d7e7c0a..3d77d0b 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -60,6 +60,15 @@ config PCI_EXYNOS
>   select PCIEPORTBUS
>   select PCIE_DW
>  
> +config PCI_EXYNOS5433
> + bool "Samsung Exynos5433 PCIe controller"
> + depends on ARCH_EXYNOS && ARM64
> + depends on PCI_MSI_IRQ_DOMAIN
> + select PCIEPORTBUS
> + select PCIE_DW
> + help
> +   If you want support for Exynos5433 PCIe host controller, say Y.
> +
>  config PCI_IMX6
>   bool "Freescale i.MX6 PCIe controller"
>   depends on SOC_IMX6Q
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index 084cb49..2168de2 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -2,6 +2,7 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o
>  obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
>  obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
>  obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> +obj-$(CONFIG_PCI_EXYNOS5433) += pci-exynos5433.o
>  obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
>  obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o
>  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
> diff --git a/drivers/pci/host/pci-exynos5433.c 
> b/drivers/pci/host/pci-exynos5433.c
> new file mode 100644
> index 000..ff254ca
> --- /dev/null
> +++ b/drivers/pci/host/pci-exynos5433.c
> @@ -0,0 +1,338 @@
> +/*
> + * PCIe host controller driver for Samsung EXYNOS5433 SoCs
> + *
> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
> + *   
> https://urldefense.proofpoint.com/v2/url?u=http-3A__www.samsung.com&d=DgIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=s2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=fUwnZks1U2AwaOxMkLdSnE700sfQXpB3WAg_EJw7NaE&s=IwRYD8maTuXG57Q0qlAmFNh3_TSfUTE27xq8p13FFKI&e=
>  
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "pcie-designware.h"
> +
> +#define to_exynos_pcie(x)container_of(x, struct exynos_pcie, pp)
> +
> +/* Pcie structure for Exynos specific data */
> +struct exynos_pcie {
> + void __iomem*elbi_base;
> + struct clk  *clk;
> + struct clk  *bus_clk;
> + struct pcie_portpp;
> + struct phy  *phy;
> +};
> +
> +/* PCIe ELBI registers */
> +#define PCIE_IRQ_PULSE   0x000
> +#define IRQ_INTA_ASSERT  BIT(0)
> +#define IRQ_INTB_ASSERT  BIT(2)
> +#define IRQ_INTC_ASSERT  BIT(4)
> +#define IRQ_INTD_ASSERT  BIT(6)
> +#define IRQ_INTX_ASSERT  (IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | \
> + IRQ_INTC_ASSERT | IRQ_INTD_ASSERT)
> +#define PCIE_IRQ_EN_PULSE0x00c
> +#define PCIE_IRQ_EN_LEVEL0x010
> +#define PCIE_SW_WAKE 0x018
> +#define PCIE_BUS_EN  BIT(1)
> +#define PCIE_APP_LTSSM_ENABLE0x02c
> +#define PCIE_ELBI_LTSSM_ENABLE   0x1
> +#define PCIE_ELBI_DEBUG_L0x074
> +#define PCIE_ELBI_XMLH_LINK_UP   BIT(4)
> +#define PCIE_ELBI_SLV_AWMISC 0x11c
> +#define PCIE_ELBI_SLV_ARMISC 0x120
> +#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
> +
> +/* DBI register */
> +#define PCIE_MISC_CONTROL_1_OFF  0x8BC
> +#define DBI_RO_WR_EN BIT(0)
> +
> +static inline void exynos_pcie_writel(void __iomem *base, u32 val, u32 
> offset)
> +{
> + writel(val, base + offset);
> +}
> +
> +static inline u32 exynos_pcie_readl(void __iomem *base, u32 offset)
> +{
> + return readl(base + offset);
> +}
> +
> +static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
> +{
> + u32 val;
> +
> + val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE);
> + val &= ~IRQ_INTX_ASSERT;
> + exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE);
> +}
> +
> +static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
> +{
> + exynos_pcie_writel(ep->elbi_base, IRQ_INTX_ASSERT, PCIE_IRQ_EN_PULSE);
> +
> + /* Clear PCIE_IRQ_EN_LEVEL register */
> + exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL);
> +}
> +
> +static irqreturn

[RFC PATCH 4/6] PCI: exynos5433: Add new exynos pci host controller for Exynos5433

2016-12-25 Thread Jaehoon Chung

Exynos5433 supports the PCIe.
This patch adds new pci-exynos5433.c file for Exynos ARM64.

Signed-off-by: Jaehoon Chung 
---
 drivers/pci/host/Kconfig  |   9 +
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pci-exynos5433.c | 338 ++
 3 files changed, 348 insertions(+)
 create mode 100644 drivers/pci/host/pci-exynos5433.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d7e7c0a..3d77d0b 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -60,6 +60,15 @@ config PCI_EXYNOS
select PCIEPORTBUS
select PCIE_DW
 
+config PCI_EXYNOS5433
+   bool "Samsung Exynos5433 PCIe controller"
+   depends on ARCH_EXYNOS && ARM64
+   depends on PCI_MSI_IRQ_DOMAIN
+   select PCIEPORTBUS
+   select PCIE_DW
+   help
+ If you want support for Exynos5433 PCIe host controller, say Y.
+
 config PCI_IMX6
bool "Freescale i.MX6 PCIe controller"
depends on SOC_IMX6Q
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..2168de2 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o
 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
+obj-$(CONFIG_PCI_EXYNOS5433) += pci-exynos5433.o
 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
 obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o
 obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
diff --git a/drivers/pci/host/pci-exynos5433.c 
b/drivers/pci/host/pci-exynos5433.c
new file mode 100644
index 000..ff254ca
--- /dev/null
+++ b/drivers/pci/host/pci-exynos5433.c
@@ -0,0 +1,338 @@
+/*
+ * PCIe host controller driver for Samsung EXYNOS5433 SoCs
+ *
+ * Copyright (C) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pcie-designware.h"
+
+#define to_exynos_pcie(x)  container_of(x, struct exynos_pcie, pp)
+
+/* Pcie structure for Exynos specific data */
+struct exynos_pcie {
+   void __iomem*elbi_base;
+   struct clk  *clk;
+   struct clk  *bus_clk;
+   struct pcie_portpp;
+   struct phy  *phy;
+};
+
+/* PCIe ELBI registers */
+#define PCIE_IRQ_PULSE 0x000
+#define IRQ_INTA_ASSERTBIT(0)
+#define IRQ_INTB_ASSERTBIT(2)
+#define IRQ_INTC_ASSERTBIT(4)
+#define IRQ_INTD_ASSERTBIT(6)
+#define IRQ_INTX_ASSERT(IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | \
+   IRQ_INTC_ASSERT | IRQ_INTD_ASSERT)
+#define PCIE_IRQ_EN_PULSE  0x00c
+#define PCIE_IRQ_EN_LEVEL  0x010
+#define PCIE_SW_WAKE   0x018
+#define PCIE_BUS_ENBIT(1)
+#define PCIE_APP_LTSSM_ENABLE  0x02c
+#define PCIE_ELBI_LTSSM_ENABLE 0x1
+#define PCIE_ELBI_DEBUG_L  0x074
+#define PCIE_ELBI_XMLH_LINK_UP BIT(4)
+#define PCIE_ELBI_SLV_AWMISC   0x11c
+#define PCIE_ELBI_SLV_ARMISC   0x120
+#define PCIE_ELBI_SLV_DBI_ENABLE   BIT(21)
+
+/* DBI register */
+#define PCIE_MISC_CONTROL_1_OFF0x8BC
+#define DBI_RO_WR_EN   BIT(0)
+
+static inline void exynos_pcie_writel(void __iomem *base, u32 val, u32 offset)
+{
+   writel(val, base + offset);
+}
+
+static inline u32 exynos_pcie_readl(void __iomem *base, u32 offset)
+{
+   return readl(base + offset);
+}
+
+static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
+{
+   u32 val;
+
+   val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE);
+   val &= ~IRQ_INTX_ASSERT;
+   exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE);
+}
+
+static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
+{
+   exynos_pcie_writel(ep->elbi_base, IRQ_INTX_ASSERT, PCIE_IRQ_EN_PULSE);
+
+   /* Clear PCIE_IRQ_EN_LEVEL register */
+   exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL);
+}
+
+static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
+{
+   struct pcie_port *pp = arg;
+   struct exynos_pcie *ep = to_exynos_pcie(pp);
+
+   exynos_pcie_clear_irq_pulse(ep);
+
+   return IRQ_HANDLED;
+}
+
+static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
+{
+   u32 val;
+
+   val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
+   if (on)
+   val |= PCIE_ELBI_SLV_DBI_ENABLE;
+   else
+   val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
+

Re: [RFC PATCH 4/6] PCI: exynos5433: Add new exynos pci host controller for Exynos5433

Re: [RFC PATCH 4/6] PCI: exynos5433: Add new exynos pci host controller for Exynos5433

[RFC PATCH 4/6] PCI: exynos5433: Add new exynos pci host controller for Exynos5433

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