On Fri, Mar 05, 2021 at 06:38:40AM +0900, Hector Martin wrote:
> The implementor will be used to condition the FIQ support quirk.
>
> The specific CPU types are not used at the moment, but let's add them
> for documentation purposes.
>
> Signed-off-by: Hector Martin
> ---
> arch/arm64/include/asm/cputype.h | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cputype.h
> b/arch/arm64/include/asm/cputype.h
> index ef5b040dee44..6231e1f0abe7 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -59,6 +59,7 @@
> #define ARM_CPU_IMP_NVIDIA 0x4E
> #define ARM_CPU_IMP_FUJITSU 0x46
> #define ARM_CPU_IMP_HISI 0x48
> +#define ARM_CPU_IMP_APPLE0x61
>
> #define ARM_CPU_PART_AEM_V8 0xD0F
> #define ARM_CPU_PART_FOUNDATION 0xD00
> @@ -99,6 +100,9 @@
>
> #define HISI_CPU_PART_TSV110 0xD01
>
> +#define APPLE_CPU_PART_M1_ICESTORM 0x022
> +#define APPLE_CPU_PART_M1_FIRESTORM 0x023
> +
> #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM,
> ARM_CPU_PART_CORTEX_A53)
> #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM,
> ARM_CPU_PART_CORTEX_A57)
> #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM,
> ARM_CPU_PART_CORTEX_A72)
> @@ -127,6 +131,8 @@
> #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA,
> NVIDIA_CPU_PART_CARMEL)
> #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU,
> FUJITSU_CPU_PART_A64FX)
> #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI,
> HISI_CPU_PART_TSV110)
> +#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE,
> APPLE_CPU_PART_M1_ICESTORM)
> +#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE,
> APPLE_CPU_PART_M1_FIRESTORM)
We usually only merge these when they're needed, but this SoC seems broken
enough that I can see the value in having them from the start :(
Acked-by: Will Deacon
Will
