subject:"\[alsa\-devel\] \[PATCH v4 5\/9\] ASoC\: mediatek\: add structure define and clock control for 2701"

[alsa-devel] [PATCH v4 5/9] ASoC: mediatek: add structure define and clock control for 2701

2016-06-13 Thread Garlic Tseng

add structure define and clock control function for 2701.

Signed-off-by: Garlic Tseng 
---
 sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 464 ++
 sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h |  38 ++
 sound/soc/mediatek/mt2701/mt2701-afe-common.h | 181 +
 sound/soc/mediatek/mt2701/mt2701-reg.h| 186 +
 4 files changed, 869 insertions(+)
 create mode 100644 sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
 create mode 100644 sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h
 create mode 100644 sound/soc/mediatek/mt2701/mt2701-afe-common.h
 create mode 100644 sound/soc/mediatek/mt2701/mt2701-reg.h

diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c 
b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
new file mode 100644
index 000..b815ecc
--- /dev/null
+++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
@@ -0,0 +1,464 @@
+/*
+ * mt2701-afe-clock-ctrl.c  --  Mediatek 2701 afe clock ctrl
+ *
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: Garlic Tseng 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+
+#include "mt2701-afe-common.h"
+#include "mt2701-afe-clock-ctrl.h"
+
+static const char *aud_clks[MT2701_CLOCK_NUM] = {
+   [MT2701_AUD_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
+   [MT2701_AUD_AUD_MUX1_SEL] = "top_audio_mux1_sel",
+   [MT2701_AUD_AUD_MUX2_SEL] = "top_audio_mux2_sel",
+   [MT2701_AUD_AUD_MUX1_DIV] = "top_audio_mux1_div",
+   [MT2701_AUD_AUD_MUX2_DIV] = "top_audio_mux2_div",
+   [MT2701_AUD_AUD_48K_TIMING] = "top_audio_48k_timing",
+   [MT2701_AUD_AUD_44K_TIMING] = "top_audio_44k_timing",
+   [MT2701_AUD_AUDPLL_MUX_SEL] = "top_audpll_mux_sel",
+   [MT2701_AUD_APLL_SEL] = "top_apll_sel",
+   [MT2701_AUD_AUD1PLL_98M] = "top_aud1_pll_98M",
+   [MT2701_AUD_AUD2PLL_90M] = "top_aud2_pll_90M",
+   [MT2701_AUD_HADDS2PLL_98M] = "top_hadds2_pll_98M",
+   [MT2701_AUD_HADDS2PLL_294M] = "top_hadds2_pll_294M",
+   [MT2701_AUD_AUDPLL] = "top_audpll",
+   [MT2701_AUD_AUDPLL_D4] = "top_audpll_d4",
+   [MT2701_AUD_AUDPLL_D8] = "top_audpll_d8",
+   [MT2701_AUD_AUDPLL_D16] = "top_audpll_d16",
+   [MT2701_AUD_AUDPLL_D24] = "top_audpll_d24",
+   [MT2701_AUD_AUDINTBUS] = "top_audintbus_sel",
+   [MT2701_AUD_CLK_26M] = "clk_26m",
+   [MT2701_AUD_SYSPLL1_D4] = "top_syspll1_d4",
+   [MT2701_AUD_AUD_K1_SRC_SEL] = "top_aud_k1_src_sel",
+   [MT2701_AUD_AUD_K2_SRC_SEL] = "top_aud_k2_src_sel",
+   [MT2701_AUD_AUD_K3_SRC_SEL] = "top_aud_k3_src_sel",
+   [MT2701_AUD_AUD_K4_SRC_SEL] = "top_aud_k4_src_sel",
+   [MT2701_AUD_AUD_K5_SRC_SEL] = "top_aud_k5_src_sel",
+   [MT2701_AUD_AUD_K6_SRC_SEL] = "top_aud_k6_src_sel",
+   [MT2701_AUD_AUD_K1_SRC_DIV] = "top_aud_k1_src_div",
+   [MT2701_AUD_AUD_K2_SRC_DIV] = "top_aud_k2_src_div",
+   [MT2701_AUD_AUD_K3_SRC_DIV] = "top_aud_k3_src_div",
+   [MT2701_AUD_AUD_K4_SRC_DIV] = "top_aud_k4_src_div",
+   [MT2701_AUD_AUD_K5_SRC_DIV] = "top_aud_k5_src_div",
+   [MT2701_AUD_AUD_K6_SRC_DIV] = "top_aud_k6_src_div",
+   [MT2701_AUD_AUD_I2S1_MCLK] = "top_aud_i2s1_mclk",
+   [MT2701_AUD_AUD_I2S2_MCLK] = "top_aud_i2s2_mclk",
+   [MT2701_AUD_AUD_I2S3_MCLK] = "top_aud_i2s3_mclk",
+   [MT2701_AUD_AUD_I2S4_MCLK] = "top_aud_i2s4_mclk",
+   [MT2701_AUD_AUD_I2S5_MCLK] = "top_aud_i2s5_mclk",
+   [MT2701_AUD_AUD_I2S6_MCLK] = "top_aud_i2s6_mclk",
+   [MT2701_AUD_ASM_M_SEL] = "top_asm_m_sel",
+   [MT2701_AUD_ASM_H_SEL] = "top_asm_h_sel",
+   [MT2701_AUD_UNIVPLL2_D4] = "top_univpll2_d4",
+   [MT2701_AUD_UNIVPLL2_D2] = "top_univpll2_d2",
+   [MT2701_AUD_SYSPLL_D5] = "top_syspll_d5",
+};
+
+int mt2701_init_clock(struct mtk_base_afe *afe)
+{
+   struct mt2701_afe_private *afe_priv = afe->platform_priv;
+   int i = 0;
+
+   for (i = 0; i < MT2701_CLOCK_NUM; i++) {
+   afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
+   if (IS_ERR(aud_clks[i])) {
+   dev_warn(afe->dev, "%s devm_clk_get %s fail\n",
+__func__, aud_clks[i]);
+   return PTR_ERR(aud_clks[i]);
+   }
+   }
+
+   return 0;
+}
+
+int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
+{
+   int ret = 0;
+
+   ret = mt2701_turn_on_a1sys_clock(afe);
+   if (ret) {
+   dev_err(afe->dev, "%s turn_on_a1sys_clock fail %d\n",
+

[alsa-devel] [PATCH v4 5/9] ASoC: mediatek: add structure define and clock control for 2701

2016-06-13 Thread Garlic Tseng

add structure define and clock control function for 2701.

Signed-off-by: Garlic Tseng 
---
 sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 464 ++
 sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h |  38 ++
 sound/soc/mediatek/mt2701/mt2701-afe-common.h | 181 +
 sound/soc/mediatek/mt2701/mt2701-reg.h| 186 +
 4 files changed, 869 insertions(+)
 create mode 100644 sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
 create mode 100644 sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h
 create mode 100644 sound/soc/mediatek/mt2701/mt2701-afe-common.h
 create mode 100644 sound/soc/mediatek/mt2701/mt2701-reg.h

diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c 
b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
new file mode 100644
index 000..b815ecc
--- /dev/null
+++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
@@ -0,0 +1,464 @@
+/*
+ * mt2701-afe-clock-ctrl.c  --  Mediatek 2701 afe clock ctrl
+ *
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: Garlic Tseng 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+
+#include "mt2701-afe-common.h"
+#include "mt2701-afe-clock-ctrl.h"
+
+static const char *aud_clks[MT2701_CLOCK_NUM] = {
+   [MT2701_AUD_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
+   [MT2701_AUD_AUD_MUX1_SEL] = "top_audio_mux1_sel",
+   [MT2701_AUD_AUD_MUX2_SEL] = "top_audio_mux2_sel",
+   [MT2701_AUD_AUD_MUX1_DIV] = "top_audio_mux1_div",
+   [MT2701_AUD_AUD_MUX2_DIV] = "top_audio_mux2_div",
+   [MT2701_AUD_AUD_48K_TIMING] = "top_audio_48k_timing",
+   [MT2701_AUD_AUD_44K_TIMING] = "top_audio_44k_timing",
+   [MT2701_AUD_AUDPLL_MUX_SEL] = "top_audpll_mux_sel",
+   [MT2701_AUD_APLL_SEL] = "top_apll_sel",
+   [MT2701_AUD_AUD1PLL_98M] = "top_aud1_pll_98M",
+   [MT2701_AUD_AUD2PLL_90M] = "top_aud2_pll_90M",
+   [MT2701_AUD_HADDS2PLL_98M] = "top_hadds2_pll_98M",
+   [MT2701_AUD_HADDS2PLL_294M] = "top_hadds2_pll_294M",
+   [MT2701_AUD_AUDPLL] = "top_audpll",
+   [MT2701_AUD_AUDPLL_D4] = "top_audpll_d4",
+   [MT2701_AUD_AUDPLL_D8] = "top_audpll_d8",
+   [MT2701_AUD_AUDPLL_D16] = "top_audpll_d16",
+   [MT2701_AUD_AUDPLL_D24] = "top_audpll_d24",
+   [MT2701_AUD_AUDINTBUS] = "top_audintbus_sel",
+   [MT2701_AUD_CLK_26M] = "clk_26m",
+   [MT2701_AUD_SYSPLL1_D4] = "top_syspll1_d4",
+   [MT2701_AUD_AUD_K1_SRC_SEL] = "top_aud_k1_src_sel",
+   [MT2701_AUD_AUD_K2_SRC_SEL] = "top_aud_k2_src_sel",
+   [MT2701_AUD_AUD_K3_SRC_SEL] = "top_aud_k3_src_sel",
+   [MT2701_AUD_AUD_K4_SRC_SEL] = "top_aud_k4_src_sel",
+   [MT2701_AUD_AUD_K5_SRC_SEL] = "top_aud_k5_src_sel",
+   [MT2701_AUD_AUD_K6_SRC_SEL] = "top_aud_k6_src_sel",
+   [MT2701_AUD_AUD_K1_SRC_DIV] = "top_aud_k1_src_div",
+   [MT2701_AUD_AUD_K2_SRC_DIV] = "top_aud_k2_src_div",
+   [MT2701_AUD_AUD_K3_SRC_DIV] = "top_aud_k3_src_div",
+   [MT2701_AUD_AUD_K4_SRC_DIV] = "top_aud_k4_src_div",
+   [MT2701_AUD_AUD_K5_SRC_DIV] = "top_aud_k5_src_div",
+   [MT2701_AUD_AUD_K6_SRC_DIV] = "top_aud_k6_src_div",
+   [MT2701_AUD_AUD_I2S1_MCLK] = "top_aud_i2s1_mclk",
+   [MT2701_AUD_AUD_I2S2_MCLK] = "top_aud_i2s2_mclk",
+   [MT2701_AUD_AUD_I2S3_MCLK] = "top_aud_i2s3_mclk",
+   [MT2701_AUD_AUD_I2S4_MCLK] = "top_aud_i2s4_mclk",
+   [MT2701_AUD_AUD_I2S5_MCLK] = "top_aud_i2s5_mclk",
+   [MT2701_AUD_AUD_I2S6_MCLK] = "top_aud_i2s6_mclk",
+   [MT2701_AUD_ASM_M_SEL] = "top_asm_m_sel",
+   [MT2701_AUD_ASM_H_SEL] = "top_asm_h_sel",
+   [MT2701_AUD_UNIVPLL2_D4] = "top_univpll2_d4",
+   [MT2701_AUD_UNIVPLL2_D2] = "top_univpll2_d2",
+   [MT2701_AUD_SYSPLL_D5] = "top_syspll_d5",
+};
+
+int mt2701_init_clock(struct mtk_base_afe *afe)
+{
+   struct mt2701_afe_private *afe_priv = afe->platform_priv;
+   int i = 0;
+
+   for (i = 0; i < MT2701_CLOCK_NUM; i++) {
+   afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
+   if (IS_ERR(aud_clks[i])) {
+   dev_warn(afe->dev, "%s devm_clk_get %s fail\n",
+__func__, aud_clks[i]);
+   return PTR_ERR(aud_clks[i]);
+   }
+   }
+
+   return 0;
+}
+
+int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
+{
+   int ret = 0;
+
+   ret = mt2701_turn_on_a1sys_clock(afe);
+   if (ret) {
+   dev_err(afe->dev, "%s turn_on_a1sys_clock fail %d\n",
+   __func__, ret);
+   return ret;
+   }

[alsa-devel] [PATCH v4 5/9] ASoC: mediatek: add structure define and clock control for 2701

[alsa-devel] [PATCH v4 5/9] ASoC: mediatek: add structure define and clock control for 2701

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