Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors
On Wed, Feb 13, 2013 at 10:06:25AM +0200, Pekka Enberg wrote: > On Wed, Feb 13, 2013 at 2:21 AM, H. Peter Anvin wrote: > >>> + rdmsrl(MSR_AMD64_BU_CFG2, value); > >>> + value &= ~(1ULL << 24); > >>> + wrmsrl(MSR_AMD64_BU_CFG2, value); > >>> + } > >>> } > >>> > >>> rdmsr_safe(MSR_AMD64_PATCH_LEVEL, >microcode, ); > >> > >> > >> However, the more serious issue is that that same kernel #GPs when > >> booted in kvm. It seems it cannot stomach that specific MSR, see the > >> second "<-- trapping instruction" below and that BU_CFG2 MSR landing in > >> %ecx in the line before that. > >> > >> Oh, and this happens only with the kvm executable (/usr/bin/kvm) in > >> debian testing. If I use qemu from git, it passes over init_amd just > >> fine. > >> > >> Hmmm.. > > > > It #GPs on an MSR, which tends to be a bug in the VMM; RDMSR/WRMSR generally > > kick out to the VMM. There isn't a huge lot of work we can do about that... > > > > I think Qemu defaults to ignoring unknown-to-it MSRs whereas maybe kvmtool > > croaks? Pekka? > > I think we should also be fine. Cyrill? Never was #gp on unknown msr register access, so I think we're safe. But maybe Borislav may give lkvm a shot just to be sure? -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors
On Wed, Feb 13, 2013 at 2:21 AM, H. Peter Anvin wrote: >>> + rdmsrl(MSR_AMD64_BU_CFG2, value); >>> + value &= ~(1ULL << 24); >>> + wrmsrl(MSR_AMD64_BU_CFG2, value); >>> + } >>> } >>> >>> rdmsr_safe(MSR_AMD64_PATCH_LEVEL, >microcode, ); >> >> >> However, the more serious issue is that that same kernel #GPs when >> booted in kvm. It seems it cannot stomach that specific MSR, see the >> second "<-- trapping instruction" below and that BU_CFG2 MSR landing in >> %ecx in the line before that. >> >> Oh, and this happens only with the kvm executable (/usr/bin/kvm) in >> debian testing. If I use qemu from git, it passes over init_amd just >> fine. >> >> Hmmm.. > > It #GPs on an MSR, which tends to be a bug in the VMM; RDMSR/WRMSR generally > kick out to the VMM. There isn't a huge lot of work we can do about that... > > I think Qemu defaults to ignoring unknown-to-it MSRs whereas maybe kvmtool > croaks? Pekka? I think we should also be fine. Cyrillos? -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors
On Wed, Feb 13, 2013 at 2:21 AM, H. Peter Anvin h...@zytor.com wrote: + rdmsrl(MSR_AMD64_BU_CFG2, value); + value = ~(1ULL 24); + wrmsrl(MSR_AMD64_BU_CFG2, value); + } } rdmsr_safe(MSR_AMD64_PATCH_LEVEL, c-microcode, dummy); However, the more serious issue is that that same kernel #GPs when booted in kvm. It seems it cannot stomach that specific MSR, see the second -- trapping instruction below and that BU_CFG2 MSR landing in %ecx in the line before that. Oh, and this happens only with the kvm executable (/usr/bin/kvm) in debian testing. If I use qemu from git, it passes over init_amd just fine. Hmmm.. It #GPs on an MSR, which tends to be a bug in the VMM; RDMSR/WRMSR generally kick out to the VMM. There isn't a huge lot of work we can do about that... I think Qemu defaults to ignoring unknown-to-it MSRs whereas maybe kvmtool croaks? Pekka? I think we should also be fine. Cyrillos? -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors
On Wed, Feb 13, 2013 at 10:06:25AM +0200, Pekka Enberg wrote: On Wed, Feb 13, 2013 at 2:21 AM, H. Peter Anvin h...@zytor.com wrote: + rdmsrl(MSR_AMD64_BU_CFG2, value); + value = ~(1ULL 24); + wrmsrl(MSR_AMD64_BU_CFG2, value); + } } rdmsr_safe(MSR_AMD64_PATCH_LEVEL, c-microcode, dummy); However, the more serious issue is that that same kernel #GPs when booted in kvm. It seems it cannot stomach that specific MSR, see the second -- trapping instruction below and that BU_CFG2 MSR landing in %ecx in the line before that. Oh, and this happens only with the kvm executable (/usr/bin/kvm) in debian testing. If I use qemu from git, it passes over init_amd just fine. Hmmm.. It #GPs on an MSR, which tends to be a bug in the VMM; RDMSR/WRMSR generally kick out to the VMM. There isn't a huge lot of work we can do about that... I think Qemu defaults to ignoring unknown-to-it MSRs whereas maybe kvmtool croaks? Pekka? I think we should also be fine. Cyrill? Never was #gp on unknown msr register access, so I think we're safe. But maybe Borislav may give lkvm a shot just to be sure? -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors
On Tue, Feb 12, 2013 at 04:21:13PM -0800, H. Peter Anvin wrote: > On 02/12/2013 04:16 PM, Borislav Petkov wrote: > > > >This family check is redundant, we're already in a 0x10 if-branch > >above. Boris had sent a second version which doesn't have that check: > >http://marc.info/?l=linux-kernel=135949774114910 but I don't know how this > >other version has gotten in. > > > >@hpa: maybe replace - patch is still at the top of tip:x86/cpu? > > > > I'll check with Ingo if that is doable. > > >>+ rdmsrl(MSR_AMD64_BU_CFG2, value); > >>+ value &= ~(1ULL << 24); > >>+ wrmsrl(MSR_AMD64_BU_CFG2, value); > >>+ } > >>} > >> > >>rdmsr_safe(MSR_AMD64_PATCH_LEVEL, >microcode, ); > > > >However, the more serious issue is that that same kernel #GPs when > >booted in kvm. It seems it cannot stomach that specific MSR, see the > >second "<-- trapping instruction" below and that BU_CFG2 MSR landing in > >%ecx in the line before that. > > > >Oh, and this happens only with the kvm executable (/usr/bin/kvm) in > >debian testing. If I use qemu from git, it passes over init_amd just > >fine. > > > >Hmmm.. > > > > It #GPs on an MSR, which tends to be a bug in the VMM; RDMSR/WRMSR > generally kick out to the VMM. There isn't a huge lot of work we > can do about that... Yeah, kvm.ko which runs on the host says that it ignores this MSR: [160716.170333] kvm [29093]: vcpu0 unhandled rdmsr: 0xc001102a > I think Qemu defaults to ignoring unknown-to-it MSRs whereas maybe > kvmtool croaks? Pekka? Actually that's the qemu kvm thing you get from http://www.linux-kvm.org not the kvmtool. Let me add the kvm ML to CC. Guys, when I start the guest in kvm, it #GPs early when it tries to RDMSR 0xc001102a. Here's the oops message: http://marc.info/?l=linux-kernel=136071460803452 qemu-kvm is qemu-kvm (1.1.2+dfsg-5) from debian testing. Command line is: kvm -snapshot -gdb tcp::1234 -cpu phenom -hda /home/boris/kvm/debian/sid-x86_64.img -name "Debian x86_64:1235" -boot menu=off,order=c -m 2048 -localtime -net nic -net user,hostfwd=tcp::1235-:22 -usbdevice tablet -kernel /w/kernel/linux-2.6/arch/x86/boot/bzImage -append "vga=0 root=/dev/sda1 debug ignore_loglevel console=ttyS0,115200 console=tty0" -serial file:/home/boris/kvm/test-x86_64.log Any ideas? -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. -- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors
On 02/12/2013 04:16 PM, Borislav Petkov wrote: This family check is redundant, we're already in a 0x10 if-branch above. Boris had sent a second version which doesn't have that check: http://marc.info/?l=linux-kernel=135949774114910 but I don't know how this other version has gotten in. @hpa: maybe replace - patch is still at the top of tip:x86/cpu? I'll check with Ingo if that is doable. + rdmsrl(MSR_AMD64_BU_CFG2, value); + value &= ~(1ULL << 24); + wrmsrl(MSR_AMD64_BU_CFG2, value); + } } rdmsr_safe(MSR_AMD64_PATCH_LEVEL, >microcode, ); However, the more serious issue is that that same kernel #GPs when booted in kvm. It seems it cannot stomach that specific MSR, see the second "<-- trapping instruction" below and that BU_CFG2 MSR landing in %ecx in the line before that. Oh, and this happens only with the kvm executable (/usr/bin/kvm) in debian testing. If I use qemu from git, it passes over init_amd just fine. Hmmm.. It #GPs on an MSR, which tends to be a bug in the VMM; RDMSR/WRMSR generally kick out to the VMM. There isn't a huge lot of work we can do about that... I think Qemu defaults to ignoring unknown-to-it MSRs whereas maybe kvmtool croaks? Pekka? -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors
Two issues I got with this one, see below.
On Thu, Jan 31, 2013 at 02:45:06PM -0800, tip-bot for Boris Ostrovsky wrote:
> Commit-ID: f0322bd341fd63261527bf84afd3272bcc2e8dd3
> Gitweb: http://git.kernel.org/tip/f0322bd341fd63261527bf84afd3272bcc2e8dd3
> Author: Boris Ostrovsky
> AuthorDate: Tue, 29 Jan 2013 16:32:49 -0500
> Committer: H. Peter Anvin
> CommitDate: Thu, 31 Jan 2013 13:35:38 -0800
>
> x86, AMD: Enable WC+ memory type on family 10 processors
>
> In some cases BIOS may not enable WC+ memory type on family 10
> processors, instead converting what would be WC+ memory to CD type.
> On guests using nested pages this could result in performance
> degradation. This patch enables WC+.
>
> Signed-off-by: Boris Ostrovsky
> Link:
> http://lkml.kernel.org/r/1359495169-23278-1-git-send-email-o...@amd64.org
> Signed-off-by: H. Peter Anvin
> ---
> arch/x86/include/uapi/asm/msr-index.h | 1 +
> arch/x86/kernel/cpu/amd.c | 21 -
> 2 files changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/arch/x86/include/uapi/asm/msr-index.h
> b/arch/x86/include/uapi/asm/msr-index.h
> index 433a59f..158cde9 100644
> --- a/arch/x86/include/uapi/asm/msr-index.h
> +++ b/arch/x86/include/uapi/asm/msr-index.h
> @@ -173,6 +173,7 @@
> #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
> #define MSR_AMD64_OSVW_STATUS0xc0010141
> #define MSR_AMD64_DC_CFG 0xc0011022
> +#define MSR_AMD64_BU_CFG20xc001102a
> #define MSR_AMD64_IBSFETCHCTL0xc0011030
> #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
> #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
> index dd4a5b6..721ef32 100644
> --- a/arch/x86/kernel/cpu/amd.c
> +++ b/arch/x86/kernel/cpu/amd.c
> @@ -698,13 +698,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
> if (c->x86 > 0x11)
> set_cpu_cap(c, X86_FEATURE_ARAT);
>
> - /*
> - * Disable GART TLB Walk Errors on Fam10h. We do this here
> - * because this is always needed when GART is enabled, even in a
> - * kernel which has no MCE support built in.
> - */
> if (c->x86 == 0x10) {
> /*
> + * Disable GART TLB Walk Errors on Fam10h. We do this here
> + * because this is always needed when GART is enabled, even in a
> + * kernel which has no MCE support built in.
>* BIOS should disable GartTlbWlk Errors themself. If
>* it doesn't do it here as suggested by the BKDG.
>*
> @@ -718,6 +716,19 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
> mask |= (1 << 10);
> wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
> }
> +
> + /*
> + * On family 10h BIOS may not have properly enabled WC+ support,
> + * causing it to be converted to CD memtype. This may result in
> + * performance degradation for certain nested-paging guests.
> + * Prevent this conversion by clearing bit 24 in
> + * MSR_AMD64_BU_CFG2.
> + */
> + if (c->x86 == 0x10) {
This family check is redundant, we're already in a 0x10 if-branch
above. Boris had sent a second version which doesn't have that check:
http://marc.info/?l=linux-kernel=135949774114910 but I don't know how this
other version has gotten in.
@hpa: maybe replace - patch is still at the top of tip:x86/cpu?
> + rdmsrl(MSR_AMD64_BU_CFG2, value);
> + value &= ~(1ULL << 24);
> + wrmsrl(MSR_AMD64_BU_CFG2, value);
> + }
> }
>
> rdmsr_safe(MSR_AMD64_PATCH_LEVEL, >microcode, );
However, the more serious issue is that that same kernel #GPs when
booted in kvm. It seems it cannot stomach that specific MSR, see the
second "<-- trapping instruction" below and that BU_CFG2 MSR landing in
%ecx in the line before that.
Oh, and this happens only with the kvm executable (/usr/bin/kvm) in
debian testing. If I use qemu from git, it passes over init_amd just
fine.
Hmmm..
[0.018000] general protection fault: [#1] PREEMPT SMP
[0.018000] Modules linked in:
[0.018000] CPU 0
[0.018000] Pid: 0, comm: swapper/0 Not tainted 3.8.0-rc6+ #3 Bochs Bochs
[0.018000] RIP: 0010:[] []
init_amd+0x4d6/0x50d
[0.018000] RSP: :81813ed8 EFLAGS: 00010246
[0.018000] RAX: RBX: 00726f73 RCX: c001102a
[0.018000] RDX: 8268b021 RSI: fffb RDI: 0005
[0.018000] RBP: 81813f28 R08: R09:
[0.018000] R10: 0001 R11: R12: 8189e140
[0.018000] R13: 81af82e0 R14: 88007ffd0300 R15:
[0.018000] FS: () GS:88007fc0()
Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors
Two issues I got with this one, see below.
On Thu, Jan 31, 2013 at 02:45:06PM -0800, tip-bot for Boris Ostrovsky wrote:
Commit-ID: f0322bd341fd63261527bf84afd3272bcc2e8dd3
Gitweb: http://git.kernel.org/tip/f0322bd341fd63261527bf84afd3272bcc2e8dd3
Author: Boris Ostrovsky boris.ostrov...@amd.com
AuthorDate: Tue, 29 Jan 2013 16:32:49 -0500
Committer: H. Peter Anvin h...@linux.intel.com
CommitDate: Thu, 31 Jan 2013 13:35:38 -0800
x86, AMD: Enable WC+ memory type on family 10 processors
In some cases BIOS may not enable WC+ memory type on family 10
processors, instead converting what would be WC+ memory to CD type.
On guests using nested pages this could result in performance
degradation. This patch enables WC+.
Signed-off-by: Boris Ostrovsky boris.ostrov...@amd.com
Link:
http://lkml.kernel.org/r/1359495169-23278-1-git-send-email-o...@amd64.org
Signed-off-by: H. Peter Anvin h...@linux.intel.com
---
arch/x86/include/uapi/asm/msr-index.h | 1 +
arch/x86/kernel/cpu/amd.c | 21 -
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/uapi/asm/msr-index.h
b/arch/x86/include/uapi/asm/msr-index.h
index 433a59f..158cde9 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -173,6 +173,7 @@
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
#define MSR_AMD64_OSVW_STATUS0xc0010141
#define MSR_AMD64_DC_CFG 0xc0011022
+#define MSR_AMD64_BU_CFG20xc001102a
#define MSR_AMD64_IBSFETCHCTL0xc0011030
#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index dd4a5b6..721ef32 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -698,13 +698,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
if (c-x86 0x11)
set_cpu_cap(c, X86_FEATURE_ARAT);
- /*
- * Disable GART TLB Walk Errors on Fam10h. We do this here
- * because this is always needed when GART is enabled, even in a
- * kernel which has no MCE support built in.
- */
if (c-x86 == 0x10) {
/*
+ * Disable GART TLB Walk Errors on Fam10h. We do this here
+ * because this is always needed when GART is enabled, even in a
+ * kernel which has no MCE support built in.
* BIOS should disable GartTlbWlk Errors themself. If
* it doesn't do it here as suggested by the BKDG.
*
@@ -718,6 +716,19 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
mask |= (1 10);
wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
}
+
+ /*
+ * On family 10h BIOS may not have properly enabled WC+ support,
+ * causing it to be converted to CD memtype. This may result in
+ * performance degradation for certain nested-paging guests.
+ * Prevent this conversion by clearing bit 24 in
+ * MSR_AMD64_BU_CFG2.
+ */
+ if (c-x86 == 0x10) {
This family check is redundant, we're already in a 0x10 if-branch
above. Boris had sent a second version which doesn't have that check:
http://marc.info/?l=linux-kernelm=135949774114910 but I don't know how this
other version has gotten in.
@hpa: maybe replace - patch is still at the top of tip:x86/cpu?
+ rdmsrl(MSR_AMD64_BU_CFG2, value);
+ value = ~(1ULL 24);
+ wrmsrl(MSR_AMD64_BU_CFG2, value);
+ }
}
rdmsr_safe(MSR_AMD64_PATCH_LEVEL, c-microcode, dummy);
However, the more serious issue is that that same kernel #GPs when
booted in kvm. It seems it cannot stomach that specific MSR, see the
second -- trapping instruction below and that BU_CFG2 MSR landing in
%ecx in the line before that.
Oh, and this happens only with the kvm executable (/usr/bin/kvm) in
debian testing. If I use qemu from git, it passes over init_amd just
fine.
Hmmm..
[0.018000] general protection fault: [#1] PREEMPT SMP
[0.018000] Modules linked in:
[0.018000] CPU 0
[0.018000] Pid: 0, comm: swapper/0 Not tainted 3.8.0-rc6+ #3 Bochs Bochs
[0.018000] RIP: 0010:[81581a48] [81581a48]
init_amd+0x4d6/0x50d
[0.018000] RSP: :81813ed8 EFLAGS: 00010246
[0.018000] RAX: RBX: 00726f73 RCX: c001102a
[0.018000] RDX: 8268b021 RSI: fffb RDI: 0005
[0.018000] RBP: 81813f28 R08: R09:
[0.018000] R10: 0001 R11: R12: 8189e140
[0.018000] R13: 81af82e0 R14: 88007ffd0300 R15:
[0.018000] FS:
Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors
On 02/12/2013 04:16 PM, Borislav Petkov wrote: This family check is redundant, we're already in a 0x10 if-branch above. Boris had sent a second version which doesn't have that check: http://marc.info/?l=linux-kernelm=135949774114910 but I don't know how this other version has gotten in. @hpa: maybe replace - patch is still at the top of tip:x86/cpu? I'll check with Ingo if that is doable. + rdmsrl(MSR_AMD64_BU_CFG2, value); + value = ~(1ULL 24); + wrmsrl(MSR_AMD64_BU_CFG2, value); + } } rdmsr_safe(MSR_AMD64_PATCH_LEVEL, c-microcode, dummy); However, the more serious issue is that that same kernel #GPs when booted in kvm. It seems it cannot stomach that specific MSR, see the second -- trapping instruction below and that BU_CFG2 MSR landing in %ecx in the line before that. Oh, and this happens only with the kvm executable (/usr/bin/kvm) in debian testing. If I use qemu from git, it passes over init_amd just fine. Hmmm.. It #GPs on an MSR, which tends to be a bug in the VMM; RDMSR/WRMSR generally kick out to the VMM. There isn't a huge lot of work we can do about that... I think Qemu defaults to ignoring unknown-to-it MSRs whereas maybe kvmtool croaks? Pekka? -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors
On Tue, Feb 12, 2013 at 04:21:13PM -0800, H. Peter Anvin wrote: On 02/12/2013 04:16 PM, Borislav Petkov wrote: This family check is redundant, we're already in a 0x10 if-branch above. Boris had sent a second version which doesn't have that check: http://marc.info/?l=linux-kernelm=135949774114910 but I don't know how this other version has gotten in. @hpa: maybe replace - patch is still at the top of tip:x86/cpu? I'll check with Ingo if that is doable. + rdmsrl(MSR_AMD64_BU_CFG2, value); + value = ~(1ULL 24); + wrmsrl(MSR_AMD64_BU_CFG2, value); + } } rdmsr_safe(MSR_AMD64_PATCH_LEVEL, c-microcode, dummy); However, the more serious issue is that that same kernel #GPs when booted in kvm. It seems it cannot stomach that specific MSR, see the second -- trapping instruction below and that BU_CFG2 MSR landing in %ecx in the line before that. Oh, and this happens only with the kvm executable (/usr/bin/kvm) in debian testing. If I use qemu from git, it passes over init_amd just fine. Hmmm.. It #GPs on an MSR, which tends to be a bug in the VMM; RDMSR/WRMSR generally kick out to the VMM. There isn't a huge lot of work we can do about that... Yeah, kvm.ko which runs on the host says that it ignores this MSR: [160716.170333] kvm [29093]: vcpu0 unhandled rdmsr: 0xc001102a I think Qemu defaults to ignoring unknown-to-it MSRs whereas maybe kvmtool croaks? Pekka? Actually that's the qemu kvm thing you get from http://www.linux-kvm.org not the kvmtool. Let me add the kvm ML to CC. Guys, when I start the guest in kvm, it #GPs early when it tries to RDMSR 0xc001102a. Here's the oops message: http://marc.info/?l=linux-kernelm=136071460803452 qemu-kvm is qemu-kvm (1.1.2+dfsg-5) from debian testing. Command line is: kvm -snapshot -gdb tcp::1234 -cpu phenom -hda /home/boris/kvm/debian/sid-x86_64.img -name Debian x86_64:1235 -boot menu=off,order=c -m 2048 -localtime -net nic -net user,hostfwd=tcp::1235-:22 -usbdevice tablet -kernel /w/kernel/linux-2.6/arch/x86/boot/bzImage -append vga=0 root=/dev/sda1 debug ignore_loglevel console=ttyS0,115200 console=tty0 -serial file:/home/boris/kvm/test-x86_64.log Any ideas? -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. -- -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors
Commit-ID: f0322bd341fd63261527bf84afd3272bcc2e8dd3
Gitweb: http://git.kernel.org/tip/f0322bd341fd63261527bf84afd3272bcc2e8dd3
Author: Boris Ostrovsky
AuthorDate: Tue, 29 Jan 2013 16:32:49 -0500
Committer: H. Peter Anvin
CommitDate: Thu, 31 Jan 2013 13:35:38 -0800
x86, AMD: Enable WC+ memory type on family 10 processors
In some cases BIOS may not enable WC+ memory type on family 10
processors, instead converting what would be WC+ memory to CD type.
On guests using nested pages this could result in performance
degradation. This patch enables WC+.
Signed-off-by: Boris Ostrovsky
Link: http://lkml.kernel.org/r/1359495169-23278-1-git-send-email-o...@amd64.org
Signed-off-by: H. Peter Anvin
---
arch/x86/include/uapi/asm/msr-index.h | 1 +
arch/x86/kernel/cpu/amd.c | 21 -
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/uapi/asm/msr-index.h
b/arch/x86/include/uapi/asm/msr-index.h
index 433a59f..158cde9 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -173,6 +173,7 @@
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
#define MSR_AMD64_OSVW_STATUS 0xc0010141
#define MSR_AMD64_DC_CFG 0xc0011022
+#define MSR_AMD64_BU_CFG2 0xc001102a
#define MSR_AMD64_IBSFETCHCTL 0xc0011030
#define MSR_AMD64_IBSFETCHLINAD0xc0011031
#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index dd4a5b6..721ef32 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -698,13 +698,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
if (c->x86 > 0x11)
set_cpu_cap(c, X86_FEATURE_ARAT);
- /*
-* Disable GART TLB Walk Errors on Fam10h. We do this here
-* because this is always needed when GART is enabled, even in a
-* kernel which has no MCE support built in.
-*/
if (c->x86 == 0x10) {
/*
+* Disable GART TLB Walk Errors on Fam10h. We do this here
+* because this is always needed when GART is enabled, even in a
+* kernel which has no MCE support built in.
* BIOS should disable GartTlbWlk Errors themself. If
* it doesn't do it here as suggested by the BKDG.
*
@@ -718,6 +716,19 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
mask |= (1 << 10);
wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
}
+
+ /*
+* On family 10h BIOS may not have properly enabled WC+ support,
+* causing it to be converted to CD memtype. This may result in
+* performance degradation for certain nested-paging guests.
+* Prevent this conversion by clearing bit 24 in
+* MSR_AMD64_BU_CFG2.
+*/
+ if (c->x86 == 0x10) {
+ rdmsrl(MSR_AMD64_BU_CFG2, value);
+ value &= ~(1ULL << 24);
+ wrmsrl(MSR_AMD64_BU_CFG2, value);
+ }
}
rdmsr_safe(MSR_AMD64_PATCH_LEVEL, >microcode, );
--
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[tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors
Commit-ID: f0322bd341fd63261527bf84afd3272bcc2e8dd3
Gitweb: http://git.kernel.org/tip/f0322bd341fd63261527bf84afd3272bcc2e8dd3
Author: Boris Ostrovsky boris.ostrov...@amd.com
AuthorDate: Tue, 29 Jan 2013 16:32:49 -0500
Committer: H. Peter Anvin h...@linux.intel.com
CommitDate: Thu, 31 Jan 2013 13:35:38 -0800
x86, AMD: Enable WC+ memory type on family 10 processors
In some cases BIOS may not enable WC+ memory type on family 10
processors, instead converting what would be WC+ memory to CD type.
On guests using nested pages this could result in performance
degradation. This patch enables WC+.
Signed-off-by: Boris Ostrovsky boris.ostrov...@amd.com
Link: http://lkml.kernel.org/r/1359495169-23278-1-git-send-email-o...@amd64.org
Signed-off-by: H. Peter Anvin h...@linux.intel.com
---
arch/x86/include/uapi/asm/msr-index.h | 1 +
arch/x86/kernel/cpu/amd.c | 21 -
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/uapi/asm/msr-index.h
b/arch/x86/include/uapi/asm/msr-index.h
index 433a59f..158cde9 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -173,6 +173,7 @@
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
#define MSR_AMD64_OSVW_STATUS 0xc0010141
#define MSR_AMD64_DC_CFG 0xc0011022
+#define MSR_AMD64_BU_CFG2 0xc001102a
#define MSR_AMD64_IBSFETCHCTL 0xc0011030
#define MSR_AMD64_IBSFETCHLINAD0xc0011031
#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index dd4a5b6..721ef32 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -698,13 +698,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
if (c-x86 0x11)
set_cpu_cap(c, X86_FEATURE_ARAT);
- /*
-* Disable GART TLB Walk Errors on Fam10h. We do this here
-* because this is always needed when GART is enabled, even in a
-* kernel which has no MCE support built in.
-*/
if (c-x86 == 0x10) {
/*
+* Disable GART TLB Walk Errors on Fam10h. We do this here
+* because this is always needed when GART is enabled, even in a
+* kernel which has no MCE support built in.
* BIOS should disable GartTlbWlk Errors themself. If
* it doesn't do it here as suggested by the BKDG.
*
@@ -718,6 +716,19 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
mask |= (1 10);
wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
}
+
+ /*
+* On family 10h BIOS may not have properly enabled WC+ support,
+* causing it to be converted to CD memtype. This may result in
+* performance degradation for certain nested-paging guests.
+* Prevent this conversion by clearing bit 24 in
+* MSR_AMD64_BU_CFG2.
+*/
+ if (c-x86 == 0x10) {
+ rdmsrl(MSR_AMD64_BU_CFG2, value);
+ value = ~(1ULL 24);
+ wrmsrl(MSR_AMD64_BU_CFG2, value);
+ }
}
rdmsr_safe(MSR_AMD64_PATCH_LEVEL, c-microcode, dummy);
--
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