Re: [v2 PATCH 1/3] clk: rockchip: Fractional dividers can't set parent rates

[Heiko Stuebner]

Am Donnerstag, 1. September 2016, 20:26:23 CEST schrieb Chris Zhong:
> From: Douglas Anderson 
> 
> Currently the fractional divider clock time can't handle the
> CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers,
> there is no clk_divider_bestdiv() function to try speeding up the parent
> to see if it helps things.
> 
> Eventually someone could try to figure out how to make fractional
> dividers able to use CLK_SET_RATE_PARENT, but until they do let's not
> confuse the common clock framework (and anyone using it) by setting the
> flag.
> 
> Signed-off-by: Douglas Anderson 
> Signed-off-by: Chris Zhong 

applied to my clk-branch for 4.9, after changing the subject to
clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers


Heiko

[v2 PATCH 1/3] clk: rockchip: Fractional dividers can't set parent rates

[Chris Zhong]

From: Douglas Anderson 

Currently the fractional divider clock time can't handle the
CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers,
there is no clk_divider_bestdiv() function to try speeding up the parent
to see if it helps things.

Eventually someone could try to figure out how to make fractional
dividers able to use CLK_SET_RATE_PARENT, but until they do let's not
confuse the common clock framework (and anyone using it) by setting the
flag.

Signed-off-by: Douglas Anderson 
Signed-off-by: Chris Zhong 
---

 drivers/clk/rockchip/clk-rk3399.c | 26 +-
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index ea32b7e..59417c5 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -585,7 +585,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 13, GFLAGS),
-   COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 
CLK_SET_RATE_PARENT,
+   COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0,
RK3399_CLKSEL_CON(99), 0,
RK3399_CLKGATE_CON(8), 14, GFLAGS,
&rk3399_spdif_fracmux),
@@ -599,7 +599,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 3, GFLAGS),
-   COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 
CLK_SET_RATE_PARENT,
+   COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
RK3399_CLKSEL_CON(96), 0,
RK3399_CLKGATE_CON(8), 4, GFLAGS,
&rk3399_i2s0_fracmux),
@@ -609,7 +609,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 6, GFLAGS),
-   COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 
CLK_SET_RATE_PARENT,
+   COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
RK3399_CLKSEL_CON(97), 0,
RK3399_CLKGATE_CON(8), 7, GFLAGS,
&rk3399_i2s1_fracmux),
@@ -619,7 +619,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 9, GFLAGS),
-   COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 
CLK_SET_RATE_PARENT,
+   COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
RK3399_CLKSEL_CON(98), 0,
RK3399_CLKGATE_CON(8), 10, GFLAGS,
&rk3399_i2s2_fracmux),
@@ -638,7 +638,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
RK3399_CLKGATE_CON(9), 0, GFLAGS),
-   COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 
CLK_SET_RATE_PARENT,
+   COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0,
RK3399_CLKSEL_CON(100), 0,
RK3399_CLKGATE_CON(9), 1, GFLAGS,
&rk3399_uart0_fracmux),
@@ -648,7 +648,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
RK3399_CLKGATE_CON(9), 2, GFLAGS),
-   COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 
CLK_SET_RATE_PARENT,
+   COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0,
RK3399_CLKSEL_CON(101), 0,
RK3399_CLKGATE_CON(9), 3, GFLAGS,
&rk3399_uart1_fracmux),
@@ -656,7 +656,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
RK3399_CLKGATE_CON(9), 4, GFLAGS),
-   COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 
CLK_SET_RATE_PARENT,
+   COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0,
RK3399_CLKSEL_CON(102), 0,
RK3399_CLKGATE_CON(9), 5, GFLAGS,
&rk3399_uart2_fracmux),
@@ -66