Re: [v5 1/2] mtd: nand: Add new Cadence NAND driver to MTD subsystem
Hi Piotr,
Piotr Sroka wrote on Wed, 11 Sep 2019 10:43:56
+0100:
> The 08/30/2019 11:46, Miquel Raynal wrote:
> >EXTERNAL MAIL
> >
> >
> >Hi Piotr,
> >
> >Piotr Sroka wrote on Thu, 25 Jul 2019 16:00:12
> >+0100:
> >
> >Subject should be: mtd: rawnand:
> >
> >Last few nits in your driver which overall looks good (see below).
> >
> >Now I'm waiting for Rob's ack on the bindings. This driver should be a
> >good candidate for 5.5.
>
> I think that Rob alredy review it. You can find hist review on
> https://patchwork.ozlabs.org/patch/1136932/
> Let me know if something else should be improved or fixed.
Oh right I missed it. Then just don't forget to carry the tag in your
next iteration and we'll be fine!
[...]
> >> +static irqreturn_t cadence_nand_isr(int irq, void *dev_id)
> >> +{
> >> + struct cdns_nand_ctrl *cdns_ctrl = dev_id;
> >> + struct cadence_nand_irq_status irq_status;
> >> + irqreturn_t result = IRQ_NONE;
> >> +
> >> + spin_lock(_ctrl->irq_lock);
> >> +
> >> + if (irq_detected(cdns_ctrl, _status)) {
> >> + /* Handle interrupt. */
> >> + /* First acknowledge it. */
> >> + cadence_nand_clear_interrupt(cdns_ctrl, _status);
> >> + /* Status in the device context for someone to read. */
> >> + cdns_ctrl->irq_status.status |= irq_status.status;
> >> + cdns_ctrl->irq_status.trd_status |= irq_status.trd_status;
> >> + cdns_ctrl->irq_status.trd_error |= irq_status.trd_error;
> >> + /* Notify anyone who cares that it happened. */
> >> + complete(_ctrl->complete);
> >> + /* Tell the OS that we've handled this. */
> >> + result = IRQ_HANDLED;
> >> + }
> >> + spin_unlock(_ctrl->irq_lock);
> >
> >Your locking scheme seems wrong (maybe I'm not going deep enough in the
> >code), can you please try with LOCKDEP enabled?
> >
> I will check it.
> At the time I can see only one problem: the cadence_nand_reset_irq function
> should use spin_lock_irqsave instead of spin_lock.
> Can you see any other problems?
It just felt bizarre. Just run with LOCKDEP enabled and we'll be fixed.
[...]
> >> +/* Hardware initialization. */
> >> +static int cadence_nand_hw_init(struct cdns_nand_ctrl *cdns_ctrl)
> >> +{
> >> + int status;
> >> + u32 reg;
> >> +
> >> + status = cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
> >> + 100,
> >> + CTRL_STATUS_INIT_COMP, false);
> >> + if (status)
> >> + return status;
> >> +
> >> + reg = readl_relaxed(cdns_ctrl->reg + CTRL_VERSION);
> >> +
> >> + dev_info(cdns_ctrl->dev,
> >> + "%s: cadence nand controller version reg %x\n",
> >> + __func__, reg);
> >> +
> >> + /* Disable cache and multiplane. */
> >> + writel_relaxed(0, cdns_ctrl->reg + MULTIPLANE_CFG);
> >> + writel_relaxed(0, cdns_ctrl->reg + CACHE_CFG);
> >
> >Cache?
> >
> If feature is enabled then The NAND Flash Controller will sequence the
> multi-page read commands as cache read or cache program sequence. Not used by
> Linux driver because driver has possibility to program/read only a single
> page.
Indeed, that's fine then.
[...]
> >> +
> >> + switch (status) {
> >> + case STAT_ECC_UNCORR:
> >> + mtd->ecc_stats.failed++;
> >> + ecc_err_count++;
> >> + break;
> >> + case STAT_ECC_CORR:
> >> + ecc_err_count = FIELD_GET(CDMA_CS_MAXERR,
> >> +cdns_ctrl->cdma_desc->status);
> >> + mtd->ecc_stats.corrected += ecc_err_count;
> >
> >Is this value the maximum number of bitflips in each chunk of the page?
> >If it returns the total number of bitflips corrected in the entire page
> >we have a problem.
> >
> It is a maximum number of corrections applied to any ECC sector in the
> transaction.
> it looks like folowing.
> mtd->ecc_stats.corrected += max(bitflips_chunk1, bitflips_chunk2, )
>
> Transaction will be marked uncorrectable if any one of the sectors is
> uncorrectable.
> It looks like following.
> if (is_chunk1_fail || is_chunk2_fail .)
> mtd->ecc_stats.failed++;
Fine
>
> >> + break;
> >> + case STAT_ERASED:
> >> + case STAT_OK:
> >> + break;
> >> + default:
> >> + dev_err(cdns_ctrl->dev, "read page failed\n");
> >> + return -EIO;
> >> + }
> >> +
> >> + if (oob_required)
> >> + if (cadence_nand_read_bbm(chip, page, chip->oob_poi))
> >> + return -EIO;
> >
> >Do we really care about the BBM at this level? If we are requested to
> >read the page, I suppose we must do what is in our hands to return the
> >data? Normally this is handled in userspace directly.
> It is because when ECC is enabled then position of "logic" spare area is
> moved.
That's sad.
> Lets say we have page size 4096 and sector size is 1024.
> Manufacturer use begining of spare area as BBM. Spare area started at
> 4096.
> In case ECC is enabled.
Re: [v5 1/2] mtd: nand: Add new Cadence NAND driver to MTD subsystem
The 08/30/2019 11:46, Miquel Raynal wrote: EXTERNAL MAIL Hi Piotr, Piotr Sroka wrote on Thu, 25 Jul 2019 16:00:12 +0100: Subject should be: mtd: rawnand: Last few nits in your driver which overall looks good (see below). Now I'm waiting for Rob's ack on the bindings. This driver should be a good candidate for 5.5. I think that Rob alredy review it. You can find hist review on https://patchwork.ozlabs.org/patch/1136932/ Let me know if something else should be improved or fixed. Add new Cadence NAND driver to MTD subsystem Signed-off-by: Piotr Sroka --- Changes for v5: - fix "ecc config strength" field size - remove unused macros - fix address of timing2 register - add guard for accessing data_control_size register - simplify the driver by use the same function for accessing main area and oob area - add comment to the driver describing main controller modes - change compatible name from cdns,hpnfc to cdns,hp-nfc Changes for v4: - fix comments issues like typos, missing capitals, missing dots etc. - remove unnecessary PHY options phy_dll_aging and phy_per_bit_deskew - replace all register access functions to "relaxed" version - remove all unnecessary variables initializations - handle error inside cadence_nand_get_ecc_strength_idx function in case correnction strength is not found - add commit message Changes for v3: - remove definitions of unused registers - remove configuring registers which are not expected to be configured in asynchronous mode - remove not needed function reading timing registers - remove information about oob size and write size from cdns_nand_chip type and use vales from mtd_info directly - use nand_cleanup instead of nand_release if mtd device is not registered yet - fix cadence_nand_chips_init function add garbage collection if a chip init fails - simplify PHY calculations Changes for v2: - create one universal wait function for all events instead of one function per event. - split one big function executing nand operations to separate functions one per each type of operation. - add erase atomic operation to nand operation parser - remove unnecessary includes. - remove unused register defines - add support for multiple nand chips - remove all code using legacy functions - remove chip dependents parameters from dts bindings, they were attached to the SoC specific compatible at the driver level - simplify interrupt handling - simplify timing calculations - fix calculation of maximum supported cs signals - simplify ecc size calculation - remove header file and put whole code to one c file --- drivers/mtd/nand/raw/Kconfig |7 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/cadence-nand-controller.c | 3021 3 files changed, 3029 insertions(+) create mode 100644 drivers/mtd/nand/raw/cadence-nand-controller.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index e604625e2dfa..4d2ce3b5b2ae 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -557,5 +557,12 @@ config MTD_NAND_MESON help Enables support for NAND controller on Amlogic's Meson SoCs. This controller is found on Meson SoCs. Missing space? +config MTD_NAND_CADENCE + tristate "Support Cadence NAND (HPNFC) controller" + depends on OF || COMPILE_TEST + help + Enable the driver for NAND flash on platforms using a Cadence NAND + controller. + endif # MTD_NAND diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 5a5a72f0793e..f4b099f276f7 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_MTK)+= mtk_ecc.o mtk_nand.o obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o +obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_onfi.o diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/nand/raw/cadence-nand-controller.c new file mode 100644 index ..a7ff4e4585d3 --- /dev/null +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c @@ -0,0 +1,3021 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Cadence NAND flash controller driver + * + * Copyright (C) 2019 Cadence I guess you deserve the Author: entry here :) Right. Thanks :) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * HPNFC can work in 3 modes: + * - PIO - can work in master or slave DMA. + * - CDMA - needs Master DMA for accessing command descriptors. + * - Generic mode - can use only slave DMA. + * CDMA and PIO modes can be used to execute only base commands. + * Generic mode can be used to execute
Re: [v5 1/2] mtd: nand: Add new Cadence NAND driver to MTD subsystem
Hi Piotr, Piotr Sroka wrote on Thu, 25 Jul 2019 16:00:12 +0100: Subject should be: mtd: rawnand: Last few nits in your driver which overall looks good (see below). Now I'm waiting for Rob's ack on the bindings. This driver should be a good candidate for 5.5. > Add new Cadence NAND driver to MTD subsystem > > Signed-off-by: Piotr Sroka > --- > Changes for v5: > - fix "ecc config strength" field size > - remove unused macros > - fix address of timing2 register > - add guard for accessing data_control_size register > - simplify the driver by use the same function > for accessing main area and oob area > - add comment to the driver describing main controller modes > - change compatible name from cdns,hpnfc to cdns,hp-nfc > Changes for v4: > - fix comments issues like typos, missing capitals, missing dots etc. > - remove unnecessary PHY options phy_dll_aging and phy_per_bit_deskew > - replace all register access functions to "relaxed" version > - remove all unnecessary variables initializations > - handle error inside cadence_nand_get_ecc_strength_idx function in case > correnction strength is not found > - add commit message > Changes for v3: > - remove definitions of unused registers > - remove configuring registers which are not expected to be configured in > asynchronous mode > - remove not needed function reading timing registers > - remove information about oob size and write size from cdns_nand_chip type > and use vales from mtd_info directly > - use nand_cleanup instead of nand_release if mtd device is not registered yet > - fix cadence_nand_chips_init function add garbage collection > if a chip init fails > - simplify PHY calculations > Changes for v2: > - create one universal wait function for all events instead of one > function per event. > - split one big function executing nand operations to separate > functions one per each type of operation. > - add erase atomic operation to nand operation parser > - remove unnecessary includes. > - remove unused register defines > - add support for multiple nand chips > - remove all code using legacy functions > - remove chip dependents parameters from dts bindings, they were > attached to the SoC specific compatible at the driver level > - simplify interrupt handling > - simplify timing calculations > - fix calculation of maximum supported cs signals > - simplify ecc size calculation > - remove header file and put whole code to one c file > --- > drivers/mtd/nand/raw/Kconfig |7 + > drivers/mtd/nand/raw/Makefile |1 + > drivers/mtd/nand/raw/cadence-nand-controller.c | 3021 > > 3 files changed, 3029 insertions(+) > create mode 100644 drivers/mtd/nand/raw/cadence-nand-controller.c > > diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig > index e604625e2dfa..4d2ce3b5b2ae 100644 > --- a/drivers/mtd/nand/raw/Kconfig > +++ b/drivers/mtd/nand/raw/Kconfig > @@ -557,5 +557,12 @@ config MTD_NAND_MESON > help > Enables support for NAND controller on Amlogic's Meson SoCs. > This controller is found on Meson SoCs. Missing space? > +config MTD_NAND_CADENCE > + tristate "Support Cadence NAND (HPNFC) controller" > + depends on OF || COMPILE_TEST > + help > + Enable the driver for NAND flash on platforms using a Cadence NAND > + controller. > + > > endif # MTD_NAND > diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile > index 5a5a72f0793e..f4b099f276f7 100644 > --- a/drivers/mtd/nand/raw/Makefile > +++ b/drivers/mtd/nand/raw/Makefile > @@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o > obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o > obj-$(CONFIG_MTD_NAND_STM32_FMC2)+= stm32_fmc2_nand.o > obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o > +obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o > > nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o > nand-objs += nand_onfi.o > diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c > b/drivers/mtd/nand/raw/cadence-nand-controller.c > new file mode 100644 > index ..a7ff4e4585d3 > --- /dev/null > +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c > @@ -0,0 +1,3021 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Cadence NAND flash controller driver > + * > + * Copyright (C) 2019 Cadence I guess you deserve the Author: entry here :) > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/* > + * HPNFC can work in 3 modes: > + * - PIO - can work in master or slave DMA. > + * - CDMA - needs Master DMA for accessing command descriptors. > + * - Generic mode - can use only slave DMA. > + * CDMA and PIO modes can be used to execute only base commands. > + * Generic mode can be used to execute any command > + * on NAND flash
Re: [v5 1/2] mtd: nand: Add new Cadence NAND driver to MTD subsystem
Hello Miquèl, 24.08.2019 13:49, Miquel Raynal пишет: > Hi Dmitry, > > Dmitry Osipenko wrote on Thu, 25 Jul 2019 18:11:43 > +0300: > >> 25.07.2019 18:00, Piotr Sroka пишет: >>> Add new Cadence NAND driver to MTD subsystem >>> >>> Signed-off-by: Piotr Sroka >>> --- >>> Changes for v5: >>> - fix "ecc config strength" field size >>> - remove unused macros >>> - fix address of timing2 register >>> - add guard for accessing data_control_size register >>> - simplify the driver by use the same function >>> for accessing main area and oob area >>> - add comment to the driver describing main controller modes >>> - change compatible name from cdns,hpnfc to cdns,hp-nfc >>> Changes for v4: >>> - fix comments issues like typos, missing capitals, missing dots etc. >>> - remove unnecessary PHY options phy_dll_aging and phy_per_bit_deskew >>> - replace all register access functions to "relaxed" version >>> - remove all unnecessary variables initializations >>> - handle error inside cadence_nand_get_ecc_strength_idx function in case >>> correnction strength is not found >>> - add commit message >>> Changes for v3: >>> - remove definitions of unused registers >>> - remove configuring registers which are not expected to be configured in >>> asynchronous mode >>> - remove not needed function reading timing registers >>> - remove information about oob size and write size from cdns_nand_chip type >>> and use vales from mtd_info directly >>> - use nand_cleanup instead of nand_release if mtd device is not registered >>> yet >>> - fix cadence_nand_chips_init function add garbage collection >>> if a chip init fails >>> - simplify PHY calculations >>> Changes for v2: >>> - create one universal wait function for all events instead of one >>> function per event. >>> - split one big function executing nand operations to separate >>> functions one per each type of operation. >>> - add erase atomic operation to nand operation parser >>> - remove unnecessary includes. >>> - remove unused register defines >>> - add support for multiple nand chips >>> - remove all code using legacy functions >>> - remove chip dependents parameters from dts bindings, they were >>> attached to the SoC specific compatible at the driver level >>> - simplify interrupt handling >>> - simplify timing calculations >>> - fix calculation of maximum supported cs signals >>> - simplify ecc size calculation >>> - remove header file and put whole code to one c file >>> --- >>> drivers/mtd/nand/raw/Kconfig |7 + >>> drivers/mtd/nand/raw/Makefile |1 + >>> drivers/mtd/nand/raw/cadence-nand-controller.c | 3021 >>> >>> 3 files changed, 3029 insertions(+) >>> create mode 100644 drivers/mtd/nand/raw/cadence-nand-controller.c >>> >>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig >>> index e604625e2dfa..4d2ce3b5b2ae 100644 >>> --- a/drivers/mtd/nand/raw/Kconfig >>> +++ b/drivers/mtd/nand/raw/Kconfig >>> @@ -557,5 +557,12 @@ config MTD_NAND_MESON >>> help >>> Enables support for NAND controller on Amlogic's Meson SoCs. >>> This controller is found on Meson SoCs. >>> +config MTD_NAND_CADENCE >>> + tristate "Support Cadence NAND (HPNFC) controller" >>> + depends on OF >>> + help >>> + Enable the driver for NAND flash on platforms using a Cadence NAND >>> + controller. >>> + >>> >>> endif # MTD_NAND >>> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile >>> index 5a5a72f0793e..f4b099f276f7 100644 >>> --- a/drivers/mtd/nand/raw/Makefile >>> +++ b/drivers/mtd/nand/raw/Makefile >>> @@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_MTK)+= mtk_ecc.o >>> mtk_nand.o >>> obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o >>> obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o >>> obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o >>> +obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o >>> >>> nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o >>> nand-objs += nand_onfi.o >>> diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c >>> b/drivers/mtd/nand/raw/cadence-nand-controller.c >>> new file mode 100644 >>> index ..a7ff4e4585d3 >>> --- /dev/null >>> +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c >>> @@ -0,0 +1,3021 @@ >>> +// SPDX-License-Identifier: GPL-2.0+ >>> +/* >>> + * Cadence NAND flash controller driver >>> + * >>> + * Copyright (C) 2019 Cadence >>> + */ >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +/* >>> + * HPNFC can work in 3 modes: >>> + * - PIO - can work in master or slave DMA. >>> + * - CDMA - needs Master DMA for accessing command descriptors. >>> + * - Generic mode - can use only slave DMA. >>> + * CDMA and PIO modes can be used to execute only base commands. >>> + *
Re: [v5 1/2] mtd: nand: Add new Cadence NAND driver to MTD subsystem
Hi Dmitry, Dmitry Osipenko wrote on Thu, 25 Jul 2019 18:11:43 +0300: > 25.07.2019 18:00, Piotr Sroka пишет: > > Add new Cadence NAND driver to MTD subsystem > > > > Signed-off-by: Piotr Sroka > > --- > > Changes for v5: > > - fix "ecc config strength" field size > > - remove unused macros > > - fix address of timing2 register > > - add guard for accessing data_control_size register > > - simplify the driver by use the same function > > for accessing main area and oob area > > - add comment to the driver describing main controller modes > > - change compatible name from cdns,hpnfc to cdns,hp-nfc > > Changes for v4: > > - fix comments issues like typos, missing capitals, missing dots etc. > > - remove unnecessary PHY options phy_dll_aging and phy_per_bit_deskew > > - replace all register access functions to "relaxed" version > > - remove all unnecessary variables initializations > > - handle error inside cadence_nand_get_ecc_strength_idx function in case > > correnction strength is not found > > - add commit message > > Changes for v3: > > - remove definitions of unused registers > > - remove configuring registers which are not expected to be configured in > > asynchronous mode > > - remove not needed function reading timing registers > > - remove information about oob size and write size from cdns_nand_chip type > > and use vales from mtd_info directly > > - use nand_cleanup instead of nand_release if mtd device is not registered > > yet > > - fix cadence_nand_chips_init function add garbage collection > > if a chip init fails > > - simplify PHY calculations > > Changes for v2: > > - create one universal wait function for all events instead of one > > function per event. > > - split one big function executing nand operations to separate > > functions one per each type of operation. > > - add erase atomic operation to nand operation parser > > - remove unnecessary includes. > > - remove unused register defines > > - add support for multiple nand chips > > - remove all code using legacy functions > > - remove chip dependents parameters from dts bindings, they were > > attached to the SoC specific compatible at the driver level > > - simplify interrupt handling > > - simplify timing calculations > > - fix calculation of maximum supported cs signals > > - simplify ecc size calculation > > - remove header file and put whole code to one c file > > --- > > drivers/mtd/nand/raw/Kconfig |7 + > > drivers/mtd/nand/raw/Makefile |1 + > > drivers/mtd/nand/raw/cadence-nand-controller.c | 3021 > > > > 3 files changed, 3029 insertions(+) > > create mode 100644 drivers/mtd/nand/raw/cadence-nand-controller.c > > > > diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig > > index e604625e2dfa..4d2ce3b5b2ae 100644 > > --- a/drivers/mtd/nand/raw/Kconfig > > +++ b/drivers/mtd/nand/raw/Kconfig > > @@ -557,5 +557,12 @@ config MTD_NAND_MESON > > help > > Enables support for NAND controller on Amlogic's Meson SoCs. > > This controller is found on Meson SoCs. > > +config MTD_NAND_CADENCE > > + tristate "Support Cadence NAND (HPNFC) controller" > > + depends on OF > > + help > > + Enable the driver for NAND flash on platforms using a Cadence NAND > > + controller. > > + > > > > endif # MTD_NAND > > diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile > > index 5a5a72f0793e..f4b099f276f7 100644 > > --- a/drivers/mtd/nand/raw/Makefile > > +++ b/drivers/mtd/nand/raw/Makefile > > @@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_MTK)+= mtk_ecc.o > > mtk_nand.o > > obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o > > obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o > > obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o > > +obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o > > > > nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o > > nand-objs += nand_onfi.o > > diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c > > b/drivers/mtd/nand/raw/cadence-nand-controller.c > > new file mode 100644 > > index ..a7ff4e4585d3 > > --- /dev/null > > +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c > > @@ -0,0 +1,3021 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Cadence NAND flash controller driver > > + * > > + * Copyright (C) 2019 Cadence > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* > > + * HPNFC can work in 3 modes: > > + * - PIO - can work in master or slave DMA. > > + * - CDMA - needs Master DMA for accessing command descriptors. > > + * - Generic mode - can use only slave DMA. > > + * CDMA and PIO modes can be used to execute only base commands. > > + * Generic mode can be used to execute any command > > + * on NAND
Re: [v5 1/2] mtd: nand: Add new Cadence NAND driver to MTD subsystem
25.07.2019 18:00, Piotr Sroka пишет: > Add new Cadence NAND driver to MTD subsystem > > Signed-off-by: Piotr Sroka > --- > Changes for v5: > - fix "ecc config strength" field size > - remove unused macros > - fix address of timing2 register > - add guard for accessing data_control_size register > - simplify the driver by use the same function > for accessing main area and oob area > - add comment to the driver describing main controller modes > - change compatible name from cdns,hpnfc to cdns,hp-nfc > Changes for v4: > - fix comments issues like typos, missing capitals, missing dots etc. > - remove unnecessary PHY options phy_dll_aging and phy_per_bit_deskew > - replace all register access functions to "relaxed" version > - remove all unnecessary variables initializations > - handle error inside cadence_nand_get_ecc_strength_idx function in case > correnction strength is not found > - add commit message > Changes for v3: > - remove definitions of unused registers > - remove configuring registers which are not expected to be configured in > asynchronous mode > - remove not needed function reading timing registers > - remove information about oob size and write size from cdns_nand_chip type > and use vales from mtd_info directly > - use nand_cleanup instead of nand_release if mtd device is not registered yet > - fix cadence_nand_chips_init function add garbage collection > if a chip init fails > - simplify PHY calculations > Changes for v2: > - create one universal wait function for all events instead of one > function per event. > - split one big function executing nand operations to separate > functions one per each type of operation. > - add erase atomic operation to nand operation parser > - remove unnecessary includes. > - remove unused register defines > - add support for multiple nand chips > - remove all code using legacy functions > - remove chip dependents parameters from dts bindings, they were > attached to the SoC specific compatible at the driver level > - simplify interrupt handling > - simplify timing calculations > - fix calculation of maximum supported cs signals > - simplify ecc size calculation > - remove header file and put whole code to one c file > --- > drivers/mtd/nand/raw/Kconfig |7 + > drivers/mtd/nand/raw/Makefile |1 + > drivers/mtd/nand/raw/cadence-nand-controller.c | 3021 > > 3 files changed, 3029 insertions(+) > create mode 100644 drivers/mtd/nand/raw/cadence-nand-controller.c > > diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig > index e604625e2dfa..4d2ce3b5b2ae 100644 > --- a/drivers/mtd/nand/raw/Kconfig > +++ b/drivers/mtd/nand/raw/Kconfig > @@ -557,5 +557,12 @@ config MTD_NAND_MESON > help > Enables support for NAND controller on Amlogic's Meson SoCs. > This controller is found on Meson SoCs. > +config MTD_NAND_CADENCE > + tristate "Support Cadence NAND (HPNFC) controller" > + depends on OF > + help > + Enable the driver for NAND flash on platforms using a Cadence NAND > + controller. > + > > endif # MTD_NAND > diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile > index 5a5a72f0793e..f4b099f276f7 100644 > --- a/drivers/mtd/nand/raw/Makefile > +++ b/drivers/mtd/nand/raw/Makefile > @@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o > obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o > obj-$(CONFIG_MTD_NAND_STM32_FMC2)+= stm32_fmc2_nand.o > obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o > +obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o > > nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o > nand-objs += nand_onfi.o > diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c > b/drivers/mtd/nand/raw/cadence-nand-controller.c > new file mode 100644 > index ..a7ff4e4585d3 > --- /dev/null > +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c > @@ -0,0 +1,3021 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Cadence NAND flash controller driver > + * > + * Copyright (C) 2019 Cadence > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/* > + * HPNFC can work in 3 modes: > + * - PIO - can work in master or slave DMA. > + * - CDMA - needs Master DMA for accessing command descriptors. > + * - Generic mode - can use only slave DMA. > + * CDMA and PIO modes can be used to execute only base commands. > + * Generic mode can be used to execute any command > + * on NAND flash memory. Driver uses CDMA mode for > + * block erasing, page reading, page programing. > + * Generic mode is used for executing rest of commands. > + */ > + > +#define MAX_OOB_SIZE_PER_SECTOR 32 > +#define MAX_ADDRESS_CYC 6 > +#define MAX_ERASE_ADDRESS_CYC3 > +#define MAX_DATA_SIZE
[v5 1/2] mtd: nand: Add new Cadence NAND driver to MTD subsystem
Add new Cadence NAND driver to MTD subsystem Signed-off-by: Piotr Sroka --- Changes for v5: - fix "ecc config strength" field size - remove unused macros - fix address of timing2 register - add guard for accessing data_control_size register - simplify the driver by use the same function for accessing main area and oob area - add comment to the driver describing main controller modes - change compatible name from cdns,hpnfc to cdns,hp-nfc Changes for v4: - fix comments issues like typos, missing capitals, missing dots etc. - remove unnecessary PHY options phy_dll_aging and phy_per_bit_deskew - replace all register access functions to "relaxed" version - remove all unnecessary variables initializations - handle error inside cadence_nand_get_ecc_strength_idx function in case correnction strength is not found - add commit message Changes for v3: - remove definitions of unused registers - remove configuring registers which are not expected to be configured in asynchronous mode - remove not needed function reading timing registers - remove information about oob size and write size from cdns_nand_chip type and use vales from mtd_info directly - use nand_cleanup instead of nand_release if mtd device is not registered yet - fix cadence_nand_chips_init function add garbage collection if a chip init fails - simplify PHY calculations Changes for v2: - create one universal wait function for all events instead of one function per event. - split one big function executing nand operations to separate functions one per each type of operation. - add erase atomic operation to nand operation parser - remove unnecessary includes. - remove unused register defines - add support for multiple nand chips - remove all code using legacy functions - remove chip dependents parameters from dts bindings, they were attached to the SoC specific compatible at the driver level - simplify interrupt handling - simplify timing calculations - fix calculation of maximum supported cs signals - simplify ecc size calculation - remove header file and put whole code to one c file --- drivers/mtd/nand/raw/Kconfig |7 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/cadence-nand-controller.c | 3021 3 files changed, 3029 insertions(+) create mode 100644 drivers/mtd/nand/raw/cadence-nand-controller.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index e604625e2dfa..4d2ce3b5b2ae 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -557,5 +557,12 @@ config MTD_NAND_MESON help Enables support for NAND controller on Amlogic's Meson SoCs. This controller is found on Meson SoCs. +config MTD_NAND_CADENCE + tristate "Support Cadence NAND (HPNFC) controller" + depends on OF + help + Enable the driver for NAND flash on platforms using a Cadence NAND + controller. + endif # MTD_NAND diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 5a5a72f0793e..f4b099f276f7 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_MTK)+= mtk_ecc.o mtk_nand.o obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o +obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_onfi.o diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/nand/raw/cadence-nand-controller.c new file mode 100644 index ..a7ff4e4585d3 --- /dev/null +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c @@ -0,0 +1,3021 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Cadence NAND flash controller driver + * + * Copyright (C) 2019 Cadence + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * HPNFC can work in 3 modes: + * - PIO - can work in master or slave DMA. + * - CDMA - needs Master DMA for accessing command descriptors. + * - Generic mode - can use only slave DMA. + * CDMA and PIO modes can be used to execute only base commands. + * Generic mode can be used to execute any command + * on NAND flash memory. Driver uses CDMA mode for + * block erasing, page reading, page programing. + * Generic mode is used for executing rest of commands. + */ + +#define MAX_OOB_SIZE_PER_SECTOR32 +#define MAX_ADDRESS_CYC6 +#define MAX_ERASE_ADDRESS_CYC 3 +#define MAX_DATA_SIZE 0xFFFC + +/* Register definition. */ +/* + * Command register 0. + * Writing data to this register will initiate a new transaction + * of the NF controller. + */ +#define CMD_REG0 0x +/* Command type field mask. */ +#define
