> -Original Message-
> From: Andrey Smirnov [mailto:andrew.smir...@gmail.com]
> Sent: Monday, December 17, 2018 10:38 AM
> To: linux-kernel@vger.kernel.org
> Cc: Andrey Smirnov ; p.za...@pengutronix.de;
> Fabio Estevam ; cphe...@gmail.com;
> l.st...@pengutronix.de; Leonard Crestez ; Aisheng
> Dong ; Richard Zhu ; Rob
> Herring ; devicet...@vger.kernel.org; dl-linux-imx
> ; linux-arm-ker...@lists.infradead.org
> Subject: [PATCH v3 3/3] reset: imx7: Add support for i.MX8MQ IP block variant
>
> Add bits and pieces needed to support IP block variant found on i.MX8MQ
> SoCs.
>
> Cc: p.za...@pengutronix.de
> Cc: Fabio Estevam
> Cc: cphe...@gmail.com
> Cc: l.st...@pengutronix.de
> Cc: Leonard Crestez
> Cc: "A.s. Dong"
> Cc: Richard Zhu
> Cc: Rob Herring
> Cc: devicet...@vger.kernel.org
> Cc: linux-...@nxp.com
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Andrey Smirnov
> ---
> drivers/reset/Kconfig | 2 +-
> drivers/reset/reset-imx7.c | 106
> +
> 2 files changed, 107 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index
> c21da9fe51ec..4909aab7401b 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -50,7 +50,7 @@ config RESET_HSDK
> config RESET_IMX7
> bool "i.MX7 Reset Driver" if COMPILE_TEST
> depends on HAS_IOMEM
> - default SOC_IMX7D
> + default SOC_IMX7D || SOC_IMX8MQ
SOC_IMX8MQ has been removed in Shawn's tree.
I'd suggest simply using ARCH_MXC.
Regards
Dong Aisheng
> select MFD_SYSCON
> help
> This enables the reset controller driver for i.MX7 SoCs.
> diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index
> 3a36d5863891..bb826935db6d 100644
> --- a/drivers/reset/reset-imx7.c
> +++ b/drivers/reset/reset-imx7.c
> @@ -22,6 +22,7 @@
> #include
> #include
> #include
> +#include
>
> struct imx7_src_signal {
> unsigned int offset, bit;
> @@ -113,6 +114,110 @@ static const struct imx7_src_variant variant_imx7 =
> {
> .prepare = imx7_src_prepare,
> };
>
> +enum imx8mq_src_registers {
> + SRC_A53RCR0 = 0x0004,
> + SRC_HDMI_RCR= 0x0030,
> + SRC_DISP_RCR= 0x0034,
> + SRC_GPU_RCR = 0x0040,
> + SRC_VPU_RCR = 0x0044,
> + SRC_PCIE2_RCR = 0x0048,
> + SRC_MIPIPHY1_RCR= 0x004c,
> + SRC_MIPIPHY2_RCR= 0x0050,
> + SRC_DDRC2_RCR = 0x1004,
> +};
> +
> +static const struct imx7_src_signal
> imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
> + [IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
> + [IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
> + [IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
> + [IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
> + [IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
> + [IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
> + [IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
> + [IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
> + [IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
> + [IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
> + [IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
> + [IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
> + [IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
> + [IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
> + [IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
> + [IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
> + [IMX8MQ_RESET_A53_SOC_DBG_RESET]= { SRC_A53RCR0, BIT(20) },
> + [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
> + [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) },
> + [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR,
> BIT(0) },
> + [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR,
> BIT(0) },
> + [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N]= { SRC_MIPIPHY_RCR,
> BIT(1) },
> + [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR,
> BIT(2) },
> + [IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N] = { SRC_MIPIPHY_RCR,
> BIT(3) },
> + [IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N] = { SRC_MIPIPHY_RCR,
> BIT(4) },
> + [IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N]= { SRC_MIPIPHY_RCR,
> BIT(5) },
> + [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
> + BIT(2) | BIT(1) },
> + [IMX8MQ_RESET_PCIEPHY_PERST]= { SRC_PCIEPHY_RCR,
> BIT(3) },
> + [IMX8MQ_RESET_PCIE_CTRL_APPS_EN]= { SRC_PCIEPHY_RCR,
> BIT(6) },
> + [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = {
