Re: [PATCH v4 0/4] x86/bus_lock: Enable bus lock detection

[Fenghua Yu]

Hi, Dear X86 Maintainers,

>On Mon, Jan 04, 2021 at 07:42:28PM +, Fenghua Yu wrote:
> 
> On Tue, Nov 24, 2020 at 08:52:41PM +, Fenghua Yu wrote:
> > A bus lock [1] is acquired through either split locked access to
> > writeback (WB) memory or any locked access to non-WB memory. This is
> > typically >1000 cycles slower than an atomic operation within
> > a cache line. It also disrupts performance on other cores.
 
Just a friendly reminder. Any comment on this series? There hasn't been
any comment since it was posted.

This series can be applied cleanly to v5.11-rc5 and pass all of our
tests. If you want me to repost this series, I can do that too.

Thanks!

-Fenghua

Re: [PATCH v4 0/4] x86/bus_lock: Enable bus lock detection

[Fenghua Yu]

Hi, Dear X86 Maintainers,

On Tue, Nov 24, 2020 at 08:52:41PM +, Fenghua Yu wrote:
> A bus lock [1] is acquired through either split locked access to
> writeback (WB) memory or any locked access to non-WB memory. This is
> typically >1000 cycles slower than an atomic operation within
> a cache line. It also disrupts performance on other cores.

This is a friendly reminder. Any comment on this series?

Thanks.

-Fenghua

RE: [PATCH v4 0/4] x86/bus_lock: Enable bus lock detection

[Yu, Fenghua]

Hi, Dear maintainers,

> A bus lock [1] is acquired through either split locked access to writeback 
> (WB)
> memory or any locked access to non-WB memory. This is typically >1000
> cycles slower than an atomic operation within a cache line. It also disrupts
> performance on other cores.

...

> Change Log:
> v4:
> - Fix a ratelimit wording issue in the doc (Randy).
> - Patch 4 is acked by Randy (Randy).

Friendly reminder about this series...

Thank you very much in advance for your time!

-Fenghua