Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
On Mon, Jul 27, 2015 at 01:55:56PM +, Ranjit Abhimanyu Waghmode wrote: > > As I think you've been asked before please fix your mail client to word wrap > > within paragraphs so your mails are more legible. > Sorry about this, I did some changes but it's kind of broken. Will fix this. Still not working... > > I'm not entirely sure what you're asking here from the point of view of > > SPI, sorry > > - what exactly are you requesting? If you want to add support for new SPI > > bus > > modes please go ahead and do that, you need to clearly document what any > > new modes you're adding are so that other people can understand them. > Ok, my description was too short to get it completely. > For adding dual parallel mode support to current driver: > Are following points enough? Or do you want to suggest something better on > top of it? > Driver: > 1) Controller needs to know in which mode it is working. > 2) As there are more than one chip selects, may need to add code for handling > that as well. That's probably about right. signature.asc Description: Digital signature
RE: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Hi Mark, > -Original Message- > From: Mark Brown [mailto:broo...@kernel.org] > Sent: Friday, July 24, 2015 4:22 PM > To: Ranjit Abhimanyu Waghmode > Cc: Michal Simek; Soren Brinkmann; zaj...@gmail.com; ma...@denx.de; > shijie.hu...@intel.com; juh...@openwrt.org; b...@decadent.org.uk; linux- > m...@lists.infradead.org; linux-...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Harini Katakam; > Punnaiah Choudary Kalluri; ran27...@gmail.com; dw...@infradead.org; > computersforpe...@gmail.com > Subject: Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in > Zynq MPSoC GQSPI controller > > On Fri, Jul 24, 2015 at 10:42:35AM +, Ranjit Abhimanyu Waghmode wrote: > > As I think you've been asked before please fix your mail client to word wrap > within paragraphs so your mails are more legible. > Sorry about this, I did some changes but it's kind of broken. Will fix this. > > To support the dual parallel mode in this controller, following minor > > things can be added to the driver. > > > 1) Controller needs to know in which mode it is working, then it's > > obvious to set the appropriate flag for the same > > 2) There are more than one chip selects, so need to set the same > > > > So kindly suggest your view on the above request. > > I'm not entirely sure what you're asking here from the point of view of SPI, > sorry > - what exactly are you requesting? If you want to add support for new SPI bus > modes please go ahead and do that, you need to clearly document what any > new modes you're adding are so that other people can understand them. Ok, my description was too short to get it completely. For adding dual parallel mode support to current driver: Are following points enough? Or do you want to suggest something better on top of it? Driver: 1) Controller needs to know in which mode it is working. 2) As there are more than one chip selects, may need to add code for handling that as well. MTD: 1) Adding TWO_FLASH support 2) Adding DATA_STRIPE support 3) For reading array size needs to be doubled. 4) Need to access even addresses. Basically address/2. Please suggest your view on above points. Regards, Ranjit -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
Hi Mark, -Original Message- From: Mark Brown [mailto:broo...@kernel.org] Sent: Friday, July 24, 2015 4:22 PM To: Ranjit Abhimanyu Waghmode Cc: Michal Simek; Soren Brinkmann; zaj...@gmail.com; ma...@denx.de; shijie.hu...@intel.com; juh...@openwrt.org; b...@decadent.org.uk; linux- m...@lists.infradead.org; linux-...@vger.kernel.org; linux-arm- ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Harini Katakam; Punnaiah Choudary Kalluri; ran27...@gmail.com; dw...@infradead.org; computersforpe...@gmail.com Subject: Re: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller On Fri, Jul 24, 2015 at 10:42:35AM +, Ranjit Abhimanyu Waghmode wrote: As I think you've been asked before please fix your mail client to word wrap within paragraphs so your mails are more legible. Sorry about this, I did some changes but it's kind of broken. Will fix this. To support the dual parallel mode in this controller, following minor things can be added to the driver. 1) Controller needs to know in which mode it is working, then it's obvious to set the appropriate flag for the same 2) There are more than one chip selects, so need to set the same So kindly suggest your view on the above request. I'm not entirely sure what you're asking here from the point of view of SPI, sorry - what exactly are you requesting? If you want to add support for new SPI bus modes please go ahead and do that, you need to clearly document what any new modes you're adding are so that other people can understand them. Ok, my description was too short to get it completely. For adding dual parallel mode support to current driver: Are following points enough? Or do you want to suggest something better on top of it? Driver: 1) Controller needs to know in which mode it is working. 2) As there are more than one chip selects, may need to add code for handling that as well. MTD: 1) Adding TWO_FLASH support 2) Adding DATA_STRIPE support 3) For reading array size needs to be doubled. 4) Need to access even addresses. Basically address/2. Please suggest your view on above points. Regards, Ranjit -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
On Mon, Jul 27, 2015 at 01:55:56PM +, Ranjit Abhimanyu Waghmode wrote: As I think you've been asked before please fix your mail client to word wrap within paragraphs so your mails are more legible. Sorry about this, I did some changes but it's kind of broken. Will fix this. Still not working... I'm not entirely sure what you're asking here from the point of view of SPI, sorry - what exactly are you requesting? If you want to add support for new SPI bus modes please go ahead and do that, you need to clearly document what any new modes you're adding are so that other people can understand them. Ok, my description was too short to get it completely. For adding dual parallel mode support to current driver: Are following points enough? Or do you want to suggest something better on top of it? Driver: 1) Controller needs to know in which mode it is working. 2) As there are more than one chip selects, may need to add code for handling that as well. That's probably about right. signature.asc Description: Digital signature
Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
On Fri, Jul 24, 2015 at 10:42:35AM +, Ranjit Abhimanyu Waghmode wrote: As I think you've been asked before please fix your mail client to word wrap within paragraphs so your mails are more legible. > To support the dual parallel mode in this controller, following minor > things can be added to the driver. > 1) Controller needs to know in which mode it is working, then it's > obvious to set the appropriate flag for the same > 2) There are more than one chip selects, so need to set the same > > So kindly suggest your view on the above request. I'm not entirely sure what you're asking here from the point of view of SPI, sorry - what exactly are you requesting? If you want to add support for new SPI bus modes please go ahead and do that, you need to clearly document what any new modes you're adding are so that other people can understand them. signature.asc Description: Digital signature
RE: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Hi Mark, > > > For an example take two flashes connected in stacked mode. > > > For user it doesn't matter whether how many flashes are really connected. > > > There will be situation like, single partition is spread across two > > > flashes > > (partition staring at the end of one flash and continued to the second > > flash). But it has to be shown contiguous to user. > > > In this scenario, I am not clear how MTD layer will handle the case. > > > It would be great if you could just put some light on it. > > > > That's something for the MTD layer or possibly even a layer above it > > to worry about - this situation is the same as we have with disks > > where we have md which combines other devices, if something similar is > > needed for flash we should use a similar pattern. To support the dual parallel mode in this controller, following minor things can be added to the driver. 1) Controller needs to know in which mode it is working, then it's obvious to set the appropriate flag for the same 2) There are more than one chip selects, so need to set the same And for supporting the same dual parallel mode, MTD layer may need to update for: 1) Adding TWO_FLASH support 2) Adding DATA_STRIPE support 3) For reading array size needs to be doubled. 4) Need to access even addresses. Basically address/2. So kindly suggest your view on the above request. Regards, Ranjit > > Kindly help in understanding, how can we represent the stacked mode and > parallel mode changes in MTD layer? > > Thanks & Regards, > Ranjit -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
Hi Mark, For an example take two flashes connected in stacked mode. For user it doesn't matter whether how many flashes are really connected. There will be situation like, single partition is spread across two flashes (partition staring at the end of one flash and continued to the second flash). But it has to be shown contiguous to user. In this scenario, I am not clear how MTD layer will handle the case. It would be great if you could just put some light on it. That's something for the MTD layer or possibly even a layer above it to worry about - this situation is the same as we have with disks where we have md which combines other devices, if something similar is needed for flash we should use a similar pattern. To support the dual parallel mode in this controller, following minor things can be added to the driver. 1) Controller needs to know in which mode it is working, then it's obvious to set the appropriate flag for the same 2) There are more than one chip selects, so need to set the same And for supporting the same dual parallel mode, MTD layer may need to update for: 1) Adding TWO_FLASH support 2) Adding DATA_STRIPE support 3) For reading array size needs to be doubled. 4) Need to access even addresses. Basically address/2. So kindly suggest your view on the above request. Regards, Ranjit Kindly help in understanding, how can we represent the stacked mode and parallel mode changes in MTD layer? Thanks Regards, Ranjit -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
On Fri, Jul 24, 2015 at 10:42:35AM +, Ranjit Abhimanyu Waghmode wrote: As I think you've been asked before please fix your mail client to word wrap within paragraphs so your mails are more legible. To support the dual parallel mode in this controller, following minor things can be added to the driver. 1) Controller needs to know in which mode it is working, then it's obvious to set the appropriate flag for the same 2) There are more than one chip selects, so need to set the same So kindly suggest your view on the above request. I'm not entirely sure what you're asking here from the point of view of SPI, sorry - what exactly are you requesting? If you want to add support for new SPI bus modes please go ahead and do that, you need to clearly document what any new modes you're adding are so that other people can understand them. signature.asc Description: Digital signature
RE: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Hi, > -Original Message- > From: Mark Brown [mailto:broo...@kernel.org] > Sent: Thursday, July 16, 2015 2:28 PM > To: Ranjit Abhimanyu Waghmode > Cc: Michal Simek; Soren Brinkmann; dw...@infradead.org; > computersforpe...@gmail.com; zaj...@gmail.com; ma...@denx.de; > shijie.hu...@intel.com; juh...@openwrt.org; b...@decadent.org.uk; linux- > m...@lists.infradead.org; linux-...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Harini Katakam; > Punnaiah Choudary Kalluri; ran27...@gmail.com > Subject: Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in > Zynq MPSoC GQSPI controller > > On Thu, Jul 16, 2015 at 07:27:34AM +, Ranjit Abhimanyu Waghmode wrote: > > > For an example take two flashes connected in stacked mode. > > For user it doesn't matter whether how many flashes are really connected. > > There will be situation like, single partition is spread across two flashes > (partition staring at the end of one flash and continued to the second > flash). But > it has to be shown contiguous to user. > > In this scenario, I am not clear how MTD layer will handle the case. > > It would be great if you could just put some light on it. > > That's something for the MTD layer or possibly even a layer above it to worry > about - this situation is the same as we have with disks where we have md > which > combines other devices, if something similar is needed for flash we should > use a > similar pattern. Kindly help in understanding, how can we represent the stacked mode and parallel mode changes in MTD layer? Thanks & Regards, Ranjit This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
Hi, -Original Message- From: Mark Brown [mailto:broo...@kernel.org] Sent: Thursday, July 16, 2015 2:28 PM To: Ranjit Abhimanyu Waghmode Cc: Michal Simek; Soren Brinkmann; dw...@infradead.org; computersforpe...@gmail.com; zaj...@gmail.com; ma...@denx.de; shijie.hu...@intel.com; juh...@openwrt.org; b...@decadent.org.uk; linux- m...@lists.infradead.org; linux-...@vger.kernel.org; linux-arm- ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Harini Katakam; Punnaiah Choudary Kalluri; ran27...@gmail.com Subject: Re: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller On Thu, Jul 16, 2015 at 07:27:34AM +, Ranjit Abhimanyu Waghmode wrote: For an example take two flashes connected in stacked mode. For user it doesn't matter whether how many flashes are really connected. There will be situation like, single partition is spread across two flashes (partition staring at the end of one flash and continued to the second flash). But it has to be shown contiguous to user. In this scenario, I am not clear how MTD layer will handle the case. It would be great if you could just put some light on it. That's something for the MTD layer or possibly even a layer above it to worry about - this situation is the same as we have with disks where we have md which combines other devices, if something similar is needed for flash we should use a similar pattern. Kindly help in understanding, how can we represent the stacked mode and parallel mode changes in MTD layer? Thanks Regards, Ranjit This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
On Thu, Jul 16, 2015 at 07:27:34AM +, Ranjit Abhimanyu Waghmode wrote: > For an example take two flashes connected in stacked mode. > For user it doesn't matter whether how many flashes are really connected. > There will be situation like, single partition is spread across two flashes > (partition staring at the end of one flash and continued to the second > flash). But it has to be shown contiguous to user. > In this scenario, I am not clear how MTD layer will handle the case. > It would be great if you could just put some light on it. That's something for the MTD layer or possibly even a layer above it to worry about - this situation is the same as we have with disks where we have md which combines other devices, if something similar is needed for flash we should use a similar pattern. signature.asc Description: Digital signature
RE: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Hi Mark, > > > > What is stacked mode? > > > > - > > > > ZynqMP GQSPI controller supports stacked mode with following > > > functionalities: > > > > 1) The Generic Quad-SPI controller also supports two SPI flash memories > > > >in a shared bus arrangement to reduce IO pin count. > > > > 2) Separate chip select lines > > > > 3) Shared I/O lines > > > > 4) This mode is targeted for increasing the flash memory and no > performance > > > >improvement when compared with single. > > > > This is just a normal SPI controller from a SPI point of view. > > > How can we really represent the stacked mode in current configuration? > > In the same way as any other controller with two chip selects... there are > quite > a few other drivers that provide examples of this, you should look for one > that > has hardware control similar to yours. Thanks Mark for your suggestion. But I have minor doubts. For an example take two flashes connected in stacked mode. For user it doesn't matter whether how many flashes are really connected. There will be situation like, single partition is spread across two flashes (partition staring at the end of one flash and continued to the second flash). But it has to be shown contiguous to user. In this scenario, I am not clear how MTD layer will handle the case. It would be great if you could just put some light on it. Regards, Ranjit -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
Hi Mark, What is stacked mode? - ZynqMP GQSPI controller supports stacked mode with following functionalities: 1) The Generic Quad-SPI controller also supports two SPI flash memories in a shared bus arrangement to reduce IO pin count. 2) Separate chip select lines 3) Shared I/O lines 4) This mode is targeted for increasing the flash memory and no performance improvement when compared with single. This is just a normal SPI controller from a SPI point of view. How can we really represent the stacked mode in current configuration? In the same way as any other controller with two chip selects... there are quite a few other drivers that provide examples of this, you should look for one that has hardware control similar to yours. Thanks Mark for your suggestion. But I have minor doubts. For an example take two flashes connected in stacked mode. For user it doesn't matter whether how many flashes are really connected. There will be situation like, single partition is spread across two flashes (partition staring at the end of one flash and continued to the second flash). But it has to be shown contiguous to user. In this scenario, I am not clear how MTD layer will handle the case. It would be great if you could just put some light on it. Regards, Ranjit -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
On Thu, Jul 16, 2015 at 07:27:34AM +, Ranjit Abhimanyu Waghmode wrote: For an example take two flashes connected in stacked mode. For user it doesn't matter whether how many flashes are really connected. There will be situation like, single partition is spread across two flashes (partition staring at the end of one flash and continued to the second flash). But it has to be shown contiguous to user. In this scenario, I am not clear how MTD layer will handle the case. It would be great if you could just put some light on it. That's something for the MTD layer or possibly even a layer above it to worry about - this situation is the same as we have with disks where we have md which combines other devices, if something similar is needed for flash we should use a similar pattern. signature.asc Description: Digital signature
Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
On Wed, Jul 15, 2015 at 02:12:54PM +, Ranjit Abhimanyu Waghmode wrote: > > > What is stacked mode? > > > - > > > ZynqMP GQSPI controller supports stacked mode with following > > functionalities: > > > 1) The Generic Quad-SPI controller also supports two SPI flash memories > > >in a shared bus arrangement to reduce IO pin count. > > > 2) Separate chip select lines > > > 3) Shared I/O lines > > > 4) This mode is targeted for increasing the flash memory and no > > > performance > > >improvement when compared with single. > > This is just a normal SPI controller from a SPI point of view. > How can we really represent the stacked mode in current configuration? In the same way as any other controller with two chip selects... there are quite a few other drivers that provide examples of this, you should look for one that has hardware control similar to yours. signature.asc Description: Digital signature
RE: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Hi Mark, > > What is dual parallel mode? > > --- > > ZynqMP GQSPI controller supports Dual Parallel mode with following > functionalities: > > 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines. > > 2) Chip selects and clock are shared to both the flash devices > > 3) This mode is targeted for faster read/write speed and also doubles the > > size > > 4) Commands/data can be transmitted/received from both the devices(mirror), > >or only upper or only lower flash memory devices. > > 5) Data arrangement: > >With stripe enabled, > >Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus > >Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus. > > For the SPI code this just seems like SPI with an 8 bit data width. > > > What is stacked mode? > > - > > ZynqMP GQSPI controller supports stacked mode with following > functionalities: > > 1) The Generic Quad-SPI controller also supports two SPI flash memories > >in a shared bus arrangement to reduce IO pin count. > > 2) Separate chip select lines > > 3) Shared I/O lines > > 4) This mode is targeted for increasing the flash memory and no performance > >improvement when compared with single. > > This is just a normal SPI controller from a SPI point of view. How can we really represent the stacked mode in current configuration? Thanks & Regards, Ranjit -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
Hi Mark, What is dual parallel mode? --- ZynqMP GQSPI controller supports Dual Parallel mode with following functionalities: 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines. 2) Chip selects and clock are shared to both the flash devices 3) This mode is targeted for faster read/write speed and also doubles the size 4) Commands/data can be transmitted/received from both the devices(mirror), or only upper or only lower flash memory devices. 5) Data arrangement: With stripe enabled, Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus. For the SPI code this just seems like SPI with an 8 bit data width. What is stacked mode? - ZynqMP GQSPI controller supports stacked mode with following functionalities: 1) The Generic Quad-SPI controller also supports two SPI flash memories in a shared bus arrangement to reduce IO pin count. 2) Separate chip select lines 3) Shared I/O lines 4) This mode is targeted for increasing the flash memory and no performance improvement when compared with single. This is just a normal SPI controller from a SPI point of view. How can we really represent the stacked mode in current configuration? Thanks Regards, Ranjit -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
On Wed, Jul 15, 2015 at 02:12:54PM +, Ranjit Abhimanyu Waghmode wrote: What is stacked mode? - ZynqMP GQSPI controller supports stacked mode with following functionalities: 1) The Generic Quad-SPI controller also supports two SPI flash memories in a shared bus arrangement to reduce IO pin count. 2) Separate chip select lines 3) Shared I/O lines 4) This mode is targeted for increasing the flash memory and no performance improvement when compared with single. This is just a normal SPI controller from a SPI point of view. How can we really represent the stacked mode in current configuration? In the same way as any other controller with two chip selects... there are quite a few other drivers that provide examples of this, you should look for one that has hardware control similar to yours. signature.asc Description: Digital signature
Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
On Thu, Jul 09, 2015 at 06:14:53PM +0530, Ranjit Waghmode wrote: > What is dual parallel mode? > --- > ZynqMP GQSPI controller supports Dual Parallel mode with following > functionalities: > 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines. > 2) Chip selects and clock are shared to both the flash devices > 3) This mode is targeted for faster read/write speed and also doubles the size > 4) Commands/data can be transmitted/received from both the devices(mirror), >or only upper or only lower flash memory devices. > 5) Data arrangement: >With stripe enabled, >Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus >Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus. For the SPI code this just seems like SPI with an 8 bit data width. > What is stacked mode? > - > ZynqMP GQSPI controller supports stacked mode with following functionalities: > 1) The Generic Quad-SPI controller also supports two SPI flash memories >in a shared bus arrangement to reduce IO pin count. > 2) Separate chip select lines > 3) Shared I/O lines > 4) This mode is targeted for increasing the flash memory and no performance >improvement when compared with single. This is just a normal SPI controller from a SPI point of view. signature.asc Description: Digital signature
Re: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
On Thu, Jul 09, 2015 at 06:14:53PM +0530, Ranjit Waghmode wrote: What is dual parallel mode? --- ZynqMP GQSPI controller supports Dual Parallel mode with following functionalities: 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines. 2) Chip selects and clock are shared to both the flash devices 3) This mode is targeted for faster read/write speed and also doubles the size 4) Commands/data can be transmitted/received from both the devices(mirror), or only upper or only lower flash memory devices. 5) Data arrangement: With stripe enabled, Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus. For the SPI code this just seems like SPI with an 8 bit data width. What is stacked mode? - ZynqMP GQSPI controller supports stacked mode with following functionalities: 1) The Generic Quad-SPI controller also supports two SPI flash memories in a shared bus arrangement to reduce IO pin count. 2) Separate chip select lines 3) Shared I/O lines 4) This mode is targeted for increasing the flash memory and no performance improvement when compared with single. This is just a normal SPI controller from a SPI point of view. signature.asc Description: Digital signature
Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Hi Thomas, On Mon, Jul 13, 2015 at 3:34 PM, wrote: > Hello Ranjit: > >> What is dual parallel mode? >> --- >> ZynqMP GQSPI controller supports Dual Parallel mode with following >> functionalities: >> 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines. >> 2) Chip selects and clock are shared to both the flash devices >> 3) This mode is targeted for faster read/write speed and also doubles > the size >> 4) Commands/data can be transmitted/received from both the > devices(mirror), >>or only upper or only lower flash memory devices. >> 5) Data arrangement: >>With stripe enabled, >>Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus >>Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus. > > In the dual-parallel configuration, odd and even _bits_ of each byte are > distributed over the flash chips; I am assuming this works just as in Zynq > QSPI (apparently, the TRM for ZynqMP isn't out yet). > > Striping seems to be a different mechanism, though. Can you explain it a > bit more? Also, the wording seems to indicate that it belongs to > dual-stacked rather than dual-parallel. This differs between Zynq and ZynqMP. Bytes are alternated between the two flash devices in ZynqMP. In Zynq, bits were alternated. This is dual parallel because both the chips can be selected at the same time and have two separate data bus connected. One of the two can be done: 1. Enable Stripe - data bytes 0,2,4... to one flash and data bytes 1,3,5.. to the other This is typically used for read and write memory operations. 2. Disable Stripe (Mirror) - all the bytes are sent to both flash devices. This is typically used for control operations such as WriteEnable etc. > >> Suggestions on MTD layer support >> >> In order to add above two specified modes, we may required to get some >> support from MTD layer. >> >> I'm trying to list the dependencies as follows: >> 1) Support for two flashes >> 2) Enable/Disable data stripe as and when required. >> 3) May need to update read_sr() to get status of both flashes >> 4) May also need to update read_fsr() to get status of both flashes >> 5) Adjustment of offset value based on the parallel/stacked mode > configuration >> 6) Setting either parallel or stacked mode during the scan process. >> 7) In case of stacked mode, is there a MTD concatenation support? > > In addition to 5), the MTD driver using a dual-parallel QSPI flash has to > 5a) add padding at the start of data for unaligned addresses, > 5b) add padding at the end of data for unaligned lengths. In dual-parallel in ZynqMP, we no longer stripe bits, eliminating the need for padding unaligned lengths. Regards, Harini > > Best regards, > Thomas Betker > > __ > Linux MTD discussion mailing list > http://lists.infradead.org/mailman/listinfo/linux-mtd/ -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
On Fri, Jul 10, 2015 at 10:28:59AM +0200, Mike Looijmans wrote: > On 09-07-15 14:44, Ranjit Waghmode wrote: > >ZynqMP GQSPI controller supports stacked mode with following functionalities: > >1) The Generic Quad-SPI controller also supports two SPI flash memories > >in a shared bus arrangement to reduce IO pin count. > >2) Separate chip select lines > >3) Shared I/O lines > >4) This mode is targeted for increasing the flash memory and no performance > >improvement when compared with single. > One could also model the stacked mode as having two distinct flash chips > with separate chip selects and shared lines. Well, quite. I'm confused about how the above differs from a just a SPI controller with two chip selects which is perfectly standard. signature.asc Description: Digital signature
Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Hello Ranjit: > What is dual parallel mode? > --- > ZynqMP GQSPI controller supports Dual Parallel mode with following > functionalities: > 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines. > 2) Chip selects and clock are shared to both the flash devices > 3) This mode is targeted for faster read/write speed and also doubles the size > 4) Commands/data can be transmitted/received from both the devices(mirror), >or only upper or only lower flash memory devices. > 5) Data arrangement: >With stripe enabled, >Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus >Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus. In the dual-parallel configuration, odd and even _bits_ of each byte are distributed over the flash chips; I am assuming this works just as in Zynq QSPI (apparently, the TRM for ZynqMP isn't out yet). Striping seems to be a different mechanism, though. Can you explain it a bit more? Also, the wording seems to indicate that it belongs to dual-stacked rather than dual-parallel. > Suggestions on MTD layer support > > In order to add above two specified modes, we may required to get some > support from MTD layer. > > I'm trying to list the dependencies as follows: > 1) Support for two flashes > 2) Enable/Disable data stripe as and when required. > 3) May need to update read_sr() to get status of both flashes > 4) May also need to update read_fsr() to get status of both flashes > 5) Adjustment of offset value based on the parallel/stacked mode configuration > 6) Setting either parallel or stacked mode during the scan process. > 7) In case of stacked mode, is there a MTD concatenation support? In addition to 5), the MTD driver using a dual-parallel QSPI flash has to 5a) add padding at the start of data for unaligned addresses, 5b) add padding at the end of data for unaligned lengths. Best regards, Thomas Betker -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
Hello Ranjit: What is dual parallel mode? --- ZynqMP GQSPI controller supports Dual Parallel mode with following functionalities: 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines. 2) Chip selects and clock are shared to both the flash devices 3) This mode is targeted for faster read/write speed and also doubles the size 4) Commands/data can be transmitted/received from both the devices(mirror), or only upper or only lower flash memory devices. 5) Data arrangement: With stripe enabled, Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus. In the dual-parallel configuration, odd and even _bits_ of each byte are distributed over the flash chips; I am assuming this works just as in Zynq QSPI (apparently, the TRM for ZynqMP isn't out yet). Striping seems to be a different mechanism, though. Can you explain it a bit more? Also, the wording seems to indicate that it belongs to dual-stacked rather than dual-parallel. Suggestions on MTD layer support In order to add above two specified modes, we may required to get some support from MTD layer. I'm trying to list the dependencies as follows: 1) Support for two flashes 2) Enable/Disable data stripe as and when required. 3) May need to update read_sr() to get status of both flashes 4) May also need to update read_fsr() to get status of both flashes 5) Adjustment of offset value based on the parallel/stacked mode configuration 6) Setting either parallel or stacked mode during the scan process. 7) In case of stacked mode, is there a MTD concatenation support? In addition to 5), the MTD driver using a dual-parallel QSPI flash has to 5a) add padding at the start of data for unaligned addresses, 5b) add padding at the end of data for unaligned lengths. Best regards, Thomas Betker -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
Hi Thomas, On Mon, Jul 13, 2015 at 3:34 PM, thomas.bet...@rohde-schwarz.com wrote: Hello Ranjit: What is dual parallel mode? --- ZynqMP GQSPI controller supports Dual Parallel mode with following functionalities: 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines. 2) Chip selects and clock are shared to both the flash devices 3) This mode is targeted for faster read/write speed and also doubles the size 4) Commands/data can be transmitted/received from both the devices(mirror), or only upper or only lower flash memory devices. 5) Data arrangement: With stripe enabled, Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus. In the dual-parallel configuration, odd and even _bits_ of each byte are distributed over the flash chips; I am assuming this works just as in Zynq QSPI (apparently, the TRM for ZynqMP isn't out yet). Striping seems to be a different mechanism, though. Can you explain it a bit more? Also, the wording seems to indicate that it belongs to dual-stacked rather than dual-parallel. This differs between Zynq and ZynqMP. Bytes are alternated between the two flash devices in ZynqMP. In Zynq, bits were alternated. This is dual parallel because both the chips can be selected at the same time and have two separate data bus connected. One of the two can be done: 1. Enable Stripe - data bytes 0,2,4... to one flash and data bytes 1,3,5.. to the other This is typically used for read and write memory operations. 2. Disable Stripe (Mirror) - all the bytes are sent to both flash devices. This is typically used for control operations such as WriteEnable etc. Suggestions on MTD layer support In order to add above two specified modes, we may required to get some support from MTD layer. I'm trying to list the dependencies as follows: 1) Support for two flashes 2) Enable/Disable data stripe as and when required. 3) May need to update read_sr() to get status of both flashes 4) May also need to update read_fsr() to get status of both flashes 5) Adjustment of offset value based on the parallel/stacked mode configuration 6) Setting either parallel or stacked mode during the scan process. 7) In case of stacked mode, is there a MTD concatenation support? In addition to 5), the MTD driver using a dual-parallel QSPI flash has to 5a) add padding at the start of data for unaligned addresses, 5b) add padding at the end of data for unaligned lengths. In dual-parallel in ZynqMP, we no longer stripe bits, eliminating the need for padding unaligned lengths. Regards, Harini Best regards, Thomas Betker __ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
On Fri, Jul 10, 2015 at 10:28:59AM +0200, Mike Looijmans wrote: On 09-07-15 14:44, Ranjit Waghmode wrote: ZynqMP GQSPI controller supports stacked mode with following functionalities: 1) The Generic Quad-SPI controller also supports two SPI flash memories in a shared bus arrangement to reduce IO pin count. 2) Separate chip select lines 3) Shared I/O lines 4) This mode is targeted for increasing the flash memory and no performance improvement when compared with single. One could also model the stacked mode as having two distinct flash chips with separate chip selects and shared lines. Well, quite. I'm confused about how the above differs from a just a SPI controller with two chip selects which is perfectly standard. signature.asc Description: Digital signature
Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
On 09-07-15 14:44, Ranjit Waghmode wrote: This series of patches is to add dual parallel and stacked mode support for Zynq Ultrascale+ MPSoC GQSPI controller driver. These are all very high level changes and expected to make an idea clear. Comments and suggestions are welcomed. ... What is stacked mode? - ZynqMP GQSPI controller supports stacked mode with following functionalities: 1) The Generic Quad-SPI controller also supports two SPI flash memories in a shared bus arrangement to reduce IO pin count. 2) Separate chip select lines 3) Shared I/O lines 4) This mode is targeted for increasing the flash memory and no performance improvement when compared with single. One could also model the stacked mode as having two distinct flash chips with separate chip selects and shared lines. Merging them into a single storage device can be done on block layer or higher level. This allows the flash chips to be used in any configuration using existing support for concatenating multiple devices. I think this would be a more generic way of doing this. It also allows much more flexibility, for example the devices could be used in a mirror setup, or in combination with additional devices on other controllers. Kind regards, Mike Looijmans System Expert TOPIC Embedded Products Eindhovenseweg 32-C, NL-5683 KH Best Postbus 440, NL-5680 AK Best Telefoon: +31 (0) 499 33 69 79 Telefax: +31 (0) 499 33 69 70 E-mail: mike.looijm...@topicproducts.com Website: www.topicproducts.com Please consider the environment before printing this e-mail -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 0/2] spi: add dual parallel stacked mode support in Zynq MPSoC GQSPI controller
On 09-07-15 14:44, Ranjit Waghmode wrote: This series of patches is to add dual parallel and stacked mode support for Zynq Ultrascale+ MPSoC GQSPI controller driver. These are all very high level changes and expected to make an idea clear. Comments and suggestions are welcomed. ... What is stacked mode? - ZynqMP GQSPI controller supports stacked mode with following functionalities: 1) The Generic Quad-SPI controller also supports two SPI flash memories in a shared bus arrangement to reduce IO pin count. 2) Separate chip select lines 3) Shared I/O lines 4) This mode is targeted for increasing the flash memory and no performance improvement when compared with single. One could also model the stacked mode as having two distinct flash chips with separate chip selects and shared lines. Merging them into a single storage device can be done on block layer or higher level. This allows the flash chips to be used in any configuration using existing support for concatenating multiple devices. I think this would be a more generic way of doing this. It also allows much more flexibility, for example the devices could be used in a mirror setup, or in combination with additional devices on other controllers. Kind regards, Mike Looijmans System Expert TOPIC Embedded Products Eindhovenseweg 32-C, NL-5683 KH Best Postbus 440, NL-5680 AK Best Telefoon: +31 (0) 499 33 69 79 Telefax: +31 (0) 499 33 69 70 E-mail: mike.looijm...@topicproducts.com Website: www.topicproducts.com Please consider the environment before printing this e-mail -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
