Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Rafal Ozieblo]

>+static inline void macb_handle_txtstamp(struct macb *bp, struct sk_buff *skb,
>+   struct macb_dma_desc *desc)
>+{
>+   u32 ts_s, ts_ns;
>+   u8 msg_type;
>+
>+   skb_copy_from_linear_data_offset(skb, GEM_TX_PTPHDR_OFFSET,
>+_type, 1);
>+
>+   /* Bit[32:6] of TS secs from register
>+* Bit[5:0] of TS secs from BD
>+* TS nano secs is available in BD
>+*/
>+   if (msg_type & 0x2) {
>+   /* PTP Peer Event Frame packets */
>+   ts_s = (gem_readl(bp, 1588PEERTXSEC) & GEM_SEC_MASK) |
>+  ((desc->tsl >> GEM_TSL_SEC_RS) |
>+  (desc->tsh << GEM_TSH_SEC_LS));
>+   ts_ns = desc->tsl & GEM_TSL_NSEC_MASK;
>+   } else {
>+   /* PTP Event Frame packets */
>+   ts_s = (gem_readl(bp, 1588TXSEC) & GEM_SEC_MASK) |
>+  ((desc->tsl >> GEM_TSL_SEC_RS) |
>+  (desc->tsh << GEM_TSH_SEC_LS));
>+   ts_ns = desc->tsl & GEM_TSL_NSEC_MASK;
>+   }
>+
>+   struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
>+
>+   memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
>+   shhwtstamps->hwtstamp = ns_to_ktime((ts_s * NS_PER_SEC) + ts_ns);
>+   skb_tstamp_tx(skb, skb_hwtstamps(skb));
>+}
>+
> static void macb_tx_interrupt(struct macb_queue *queue)
> {
>unsigned int tail;
>@@ -703,6 +745,10 @@ static void macb_tx_interrupt(struct macb_queue *queue)
>bp->stats.tx_bytes += skb->len;
>}
>
>+#ifdef CONFIG_MACB_EXT_BD
>+   if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
>+   macb_handle_txtstamp(bp, skb, desc);
>+#endif
>/* Now we can safely release resources */
>macb_tx_unmap(bp, tx_skb);
>
>@@ -796,6 +842,39 @@ static void discard_partial_frame(struct macb *bp,
>unsigned int begin,
> */
> }

I think, you can not do it in that way. 
It will hold two locks. If you enable appropriate option in kernel (as far as I 
remember CONFIG_DEBUG_SPINLOCK) you will get a warning here.

Please look at following call-stack:

1. macb_interrupt()   // spin_lock(>lock) is taken
2. macb_tx_interrupt()
3. macb_handle_txtstamp()
4. skb_tstamp_tx()
5. __skb_tstamp_tx()
6. skb_may_tx_timestamp()
7. read_lock_bh() // second lock is taken

I know that those are different locks and different types. But this could lead 
to deadlocks. This is the reason of warning I could see.
And this is the reason why I get timestamp in interrupt routine but pass it to 
skb outside interrupt (using circular buffer). 

Best regards,

Rafal Ozieblo   |   Firmware System Engineer, 
phone nbr.: +48 32 5085469 

www.cadence.com

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Rafal Ozieblo]

>+static inline void macb_handle_txtstamp(struct macb *bp, struct sk_buff *skb,
>+   struct macb_dma_desc *desc)
>+{
>+   u32 ts_s, ts_ns;
>+   u8 msg_type;
>+
>+   skb_copy_from_linear_data_offset(skb, GEM_TX_PTPHDR_OFFSET,
>+_type, 1);
>+
>+   /* Bit[32:6] of TS secs from register
>+* Bit[5:0] of TS secs from BD
>+* TS nano secs is available in BD
>+*/
>+   if (msg_type & 0x2) {
>+   /* PTP Peer Event Frame packets */
>+   ts_s = (gem_readl(bp, 1588PEERTXSEC) & GEM_SEC_MASK) |
>+  ((desc->tsl >> GEM_TSL_SEC_RS) |
>+  (desc->tsh << GEM_TSH_SEC_LS));
>+   ts_ns = desc->tsl & GEM_TSL_NSEC_MASK;
>+   } else {
>+   /* PTP Event Frame packets */
>+   ts_s = (gem_readl(bp, 1588TXSEC) & GEM_SEC_MASK) |
>+  ((desc->tsl >> GEM_TSL_SEC_RS) |
>+  (desc->tsh << GEM_TSH_SEC_LS));
>+   ts_ns = desc->tsl & GEM_TSL_NSEC_MASK;
>+   }
>+
>+   struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
>+
>+   memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
>+   shhwtstamps->hwtstamp = ns_to_ktime((ts_s * NS_PER_SEC) + ts_ns);
>+   skb_tstamp_tx(skb, skb_hwtstamps(skb));
>+}
>+
> static void macb_tx_interrupt(struct macb_queue *queue)
> {
>unsigned int tail;
>@@ -703,6 +745,10 @@ static void macb_tx_interrupt(struct macb_queue *queue)
>bp->stats.tx_bytes += skb->len;
>}
>
>+#ifdef CONFIG_MACB_EXT_BD
>+   if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
>+   macb_handle_txtstamp(bp, skb, desc);
>+#endif
>/* Now we can safely release resources */
>macb_tx_unmap(bp, tx_skb);
>
>@@ -796,6 +842,39 @@ static void discard_partial_frame(struct macb *bp,
>unsigned int begin,
> */
> }

I think, you can not do it in that way. 
It will hold two locks. If you enable appropriate option in kernel (as far as I 
remember CONFIG_DEBUG_SPINLOCK) you will get a warning here.

Please look at following call-stack:

1. macb_interrupt()   // spin_lock(>lock) is taken
2. macb_tx_interrupt()
3. macb_handle_txtstamp()
4. skb_tstamp_tx()
5. __skb_tstamp_tx()
6. skb_may_tx_timestamp()
7. read_lock_bh() // second lock is taken

I know that those are different locks and different types. But this could lead 
to deadlocks. This is the reason of warning I could see.
And this is the reason why I get timestamp in interrupt routine but pass it to 
skb outside interrupt (using circular buffer). 

Best regards,

Rafal Ozieblo   |   Firmware System Engineer, 
phone nbr.: +48 32 5085469 

www.cadence.com

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Andrei Pistirica]

Hi Punnaiah,

cpts_match(...) has a way to parse frames, while ptp_classify_raw 
identifies the underlying protocol (in case the frames are parsed on 
data path), or tx/rxtstamp callbacks can be used with PTP events. But, 
there is comment in ptp_classify.h which worries me.


Unfortunately,  I cannot access https://gitenterprise.xilinx.com.

Best regards,
Andrei

On 09.08.2016 18:56, Punnaiah Choudary Kalluri wrote:

Hi Nicolas,

 1588 implementation in cadence GEM IP we have in Zynq Ultascale+ MPSoC is
Different to the one in Zynq SOC.

In earlier version, all timestamp values will be stored in registers and there 
is no specific
Mechanism to distinguish the received ethernet frame that contains time stamp 
information
Other than parsing the frame for PTP packet type.

We have basic implementation for earlier version in our out of tree driver, 
which is going to be deprecated
Soon. You could also check the below driver for 1588 support.
https://gitenterprise.xilinx.com/Linux/linux-xlnx/blob/master/drivers/net/ethernet/xilinx/xilinx_emacps.c


Regards,
Punnaiah


-Original Message-
From: Nicolas Ferre [mailto:nicolas.fe...@atmel.com]
Sent: Tuesday, August 09, 2016 10:10 PM
To: Harini Katakam <harinikatakamli...@gmail.com>; Harini Katakam
<hari...@xilinx.com>; Andrei Pistirica <andrei.pistir...@microchip.com>
Cc: da...@davemloft.net; Boris Brezillon <boris.brezillon@free-
electrons.com>; alexandre.bell...@free-electrons.com;
net...@vger.kernel.org; linux-kernel@vger.kernel.org;
devicet...@vger.kernel.org; Punnaiah Choudary Kalluri
<punn...@xilinx.com>; Michal Simek <mich...@xilinx.com>; Anirudha
Sarangi <anir...@xilinx.com>
Subject: Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq
Ultrascale+ MPSoC

Le 21/09/2015 à 19:49, Harini Katakam a écrit :

On Fri, Sep 11, 2015 at 1:27 PM, Harini Katakam
<harini.kata...@xilinx.com> wrote:

Cadence GEM in Zynq Ultrascale+ MPSoC supports 1588 and provides a
102 bit time counter with 48 bits for seconds, 30 bits for nsecs and
24 bits for sub-nsecs. The timestamp is made available to the SW through
registers as well as (more precisely) through upper two words in
an extended BD.

This patch does the following:
- Adds MACB_CAPS_TSU in zynqmp_config.
- Registers to ptp clock framework (after checking for timestamp support

in

  IP and capability in config).
- TX BD and RX BD control registers are written to populate timestamp in
  extended BD words.
- Timer initialization is done by writing time of day to the timer counter.
- ns increment register is programmed as NS_PER_SEC/TSU_CLK.
  For a 24 bit subns precision, the subns increment equals
  remainder of (NS_PER_SEC/TSU_CLK) * (2^24).
  TSU (Time stamp unit) clock is obtained by the  driver from devicetree.
- HW time stamp capabilities are advertised via ethtool and macb ioctl is
  updated accordingly.
- For all PTP event frames, nanoseconds and the lower 5 bits of seconds

are

  obtained from the BD. This offers a precise timestamp. The upper bits
  (which dont vary between consecutive packets) are obtained from the
  TX/RX PTP event/PEER registers. The timestamp obtained thus is

updated

  in skb for upper layers to access.
- The drivers register functions with ptp to perform time and frequency
  adjustment.
- Time adjustment is done by writing to the 1558_ADJUST register.
  The controller will read the delta in this register and update the timer
  counter register. Alternatively, for large time offset adjustments,
  the driver reads the secs and nsecs counter values, adds/subtracts the
  delta and updates the timer counter. In order to be as precise as

possible,

  nsecs counter is read again if secs has incremented during the counter

read.

- Frequency adjustment is not directly supported by this IP.
  addend is the initial value ns increment and similarly addendesub.
  The ppb (parts per billion) provided is used as
  ns_incr = addend +/- (ppb/rate).
  Similarly the remainder of the above is used to populate subns

increment.

  In case the ppb requested is negative AND subns adjustment greater

than

  the addendsub, ns_incr is reduced by 1 and subns_incr is adjusted in
  positive accordingly.

Signed-off-by: Harini Katakam <hari...@xilinx.com>:
---
 drivers/net/ethernet/cadence/macb.c |  372

++-

 drivers/net/ethernet/cadence/macb.h |   64 ++
 2 files changed, 428 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ethernet/cadence/macb.c

b/drivers/net/ethernet/cadence/macb.c

index bb2932c..b531008 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -30,6 +30,8 @@
 #include 
 #include 


[..]


+   unsigned intns_incr;
+   unsigned intsubns_incr;
 };

 static inline bool macb_is_gem(struct macb *bp)
--
1.7.9.5


Ping

Thanks.


Harini,

I come back to this patch of last year and I'm sorry about being so late
answering

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Andrei Pistirica]

Hi Punnaiah,

cpts_match(...) has a way to parse frames, while ptp_classify_raw 
identifies the underlying protocol (in case the frames are parsed on 
data path), or tx/rxtstamp callbacks can be used with PTP events. But, 
there is comment in ptp_classify.h which worries me.


Unfortunately,  I cannot access https://gitenterprise.xilinx.com.

Best regards,
Andrei

On 09.08.2016 18:56, Punnaiah Choudary Kalluri wrote:

Hi Nicolas,

 1588 implementation in cadence GEM IP we have in Zynq Ultascale+ MPSoC is
Different to the one in Zynq SOC.

In earlier version, all timestamp values will be stored in registers and there 
is no specific
Mechanism to distinguish the received ethernet frame that contains time stamp 
information
Other than parsing the frame for PTP packet type.

We have basic implementation for earlier version in our out of tree driver, 
which is going to be deprecated
Soon. You could also check the below driver for 1588 support.
https://gitenterprise.xilinx.com/Linux/linux-xlnx/blob/master/drivers/net/ethernet/xilinx/xilinx_emacps.c


Regards,
Punnaiah


-Original Message-
From: Nicolas Ferre [mailto:nicolas.fe...@atmel.com]
Sent: Tuesday, August 09, 2016 10:10 PM
To: Harini Katakam ; Harini Katakam
; Andrei Pistirica 
Cc: da...@davemloft.net; Boris Brezillon ; alexandre.bell...@free-electrons.com;
net...@vger.kernel.org; linux-kernel@vger.kernel.org;
devicet...@vger.kernel.org; Punnaiah Choudary Kalluri
; Michal Simek ; Anirudha
Sarangi 
Subject: Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq
Ultrascale+ MPSoC

Le 21/09/2015 à 19:49, Harini Katakam a écrit :

On Fri, Sep 11, 2015 at 1:27 PM, Harini Katakam
 wrote:

Cadence GEM in Zynq Ultrascale+ MPSoC supports 1588 and provides a
102 bit time counter with 48 bits for seconds, 30 bits for nsecs and
24 bits for sub-nsecs. The timestamp is made available to the SW through
registers as well as (more precisely) through upper two words in
an extended BD.

This patch does the following:
- Adds MACB_CAPS_TSU in zynqmp_config.
- Registers to ptp clock framework (after checking for timestamp support

in

  IP and capability in config).
- TX BD and RX BD control registers are written to populate timestamp in
  extended BD words.
- Timer initialization is done by writing time of day to the timer counter.
- ns increment register is programmed as NS_PER_SEC/TSU_CLK.
  For a 24 bit subns precision, the subns increment equals
  remainder of (NS_PER_SEC/TSU_CLK) * (2^24).
  TSU (Time stamp unit) clock is obtained by the  driver from devicetree.
- HW time stamp capabilities are advertised via ethtool and macb ioctl is
  updated accordingly.
- For all PTP event frames, nanoseconds and the lower 5 bits of seconds

are

  obtained from the BD. This offers a precise timestamp. The upper bits
  (which dont vary between consecutive packets) are obtained from the
  TX/RX PTP event/PEER registers. The timestamp obtained thus is

updated

  in skb for upper layers to access.
- The drivers register functions with ptp to perform time and frequency
  adjustment.
- Time adjustment is done by writing to the 1558_ADJUST register.
  The controller will read the delta in this register and update the timer
  counter register. Alternatively, for large time offset adjustments,
  the driver reads the secs and nsecs counter values, adds/subtracts the
  delta and updates the timer counter. In order to be as precise as

possible,

  nsecs counter is read again if secs has incremented during the counter

read.

- Frequency adjustment is not directly supported by this IP.
  addend is the initial value ns increment and similarly addendesub.
  The ppb (parts per billion) provided is used as
  ns_incr = addend +/- (ppb/rate).
  Similarly the remainder of the above is used to populate subns

increment.

  In case the ppb requested is negative AND subns adjustment greater

than

  the addendsub, ns_incr is reduced by 1 and subns_incr is adjusted in
  positive accordingly.

Signed-off-by: Harini Katakam :
---
 drivers/net/ethernet/cadence/macb.c |  372

++-

 drivers/net/ethernet/cadence/macb.h |   64 ++
 2 files changed, 428 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ethernet/cadence/macb.c

b/drivers/net/ethernet/cadence/macb.c

index bb2932c..b531008 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -30,6 +30,8 @@
 #include 
 #include 


[..]


+   unsigned intns_incr;
+   unsigned intsubns_incr;
 };

 static inline bool macb_is_gem(struct macb *bp)
--
1.7.9.5


Ping

Thanks.


Harini,

I come back to this patch of last year and I'm sorry about being so late
answering you.

Andrei who is added to the discussion will have some time to deal with
this feature and we would like to make some progress with it. He already
had some work done on his side before I recall your email.

So, could you please re-send your original 1588 patch with Andrei

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Michal Simek]

Hi Nicolas,

just a note: Here is the link to public Linux repo
https://github.com/Xilinx/linux-xlnx

Thanks,
Michal


On 9.8.2016 18:56, Punnaiah Choudary Kalluri wrote:
> Hi Nicolas,
> 
>  1588 implementation in cadence GEM IP we have in Zynq Ultascale+ MPSoC is
> Different to the one in Zynq SOC.
> 
> In earlier version, all timestamp values will be stored in registers and 
> there is no specific
> Mechanism to distinguish the received ethernet frame that contains time stamp 
> information
> Other than parsing the frame for PTP packet type.
> 
> We have basic implementation for earlier version in our out of tree driver, 
> which is going to be deprecated
> Soon. You could also check the below driver for 1588 support.
> https://gitenterprise.xilinx.com/Linux/linux-xlnx/blob/master/drivers/net/ethernet/xilinx/xilinx_emacps.c
> 
> 
> Regards,
> Punnaiah
> 
>> -Original Message-
>> From: Nicolas Ferre [mailto:nicolas.fe...@atmel.com]
>> Sent: Tuesday, August 09, 2016 10:10 PM
>> To: Harini Katakam <harinikatakamli...@gmail.com>; Harini Katakam
>> <hari...@xilinx.com>; Andrei Pistirica <andrei.pistir...@microchip.com>
>> Cc: da...@davemloft.net; Boris Brezillon <boris.brezillon@free-
>> electrons.com>; alexandre.bell...@free-electrons.com;
>> net...@vger.kernel.org; linux-kernel@vger.kernel.org;
>> devicet...@vger.kernel.org; Punnaiah Choudary Kalluri
>> <punn...@xilinx.com>; Michal Simek <mich...@xilinx.com>; Anirudha
>> Sarangi <anir...@xilinx.com>
>> Subject: Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq
>> Ultrascale+ MPSoC
>>
>> Le 21/09/2015 à 19:49, Harini Katakam a écrit :
>>> On Fri, Sep 11, 2015 at 1:27 PM, Harini Katakam
>>> <harini.kata...@xilinx.com> wrote:
>>>> Cadence GEM in Zynq Ultrascale+ MPSoC supports 1588 and provides a
>>>> 102 bit time counter with 48 bits for seconds, 30 bits for nsecs and
>>>> 24 bits for sub-nsecs. The timestamp is made available to the SW through
>>>> registers as well as (more precisely) through upper two words in
>>>> an extended BD.
>>>>
>>>> This patch does the following:
>>>> - Adds MACB_CAPS_TSU in zynqmp_config.
>>>> - Registers to ptp clock framework (after checking for timestamp support
>> in
>>>>   IP and capability in config).
>>>> - TX BD and RX BD control registers are written to populate timestamp in
>>>>   extended BD words.
>>>> - Timer initialization is done by writing time of day to the timer counter.
>>>> - ns increment register is programmed as NS_PER_SEC/TSU_CLK.
>>>>   For a 24 bit subns precision, the subns increment equals
>>>>   remainder of (NS_PER_SEC/TSU_CLK) * (2^24).
>>>>   TSU (Time stamp unit) clock is obtained by the  driver from devicetree.
>>>> - HW time stamp capabilities are advertised via ethtool and macb ioctl is
>>>>   updated accordingly.
>>>> - For all PTP event frames, nanoseconds and the lower 5 bits of seconds
>> are
>>>>   obtained from the BD. This offers a precise timestamp. The upper bits
>>>>   (which dont vary between consecutive packets) are obtained from the
>>>>   TX/RX PTP event/PEER registers. The timestamp obtained thus is
>> updated
>>>>   in skb for upper layers to access.
>>>> - The drivers register functions with ptp to perform time and frequency
>>>>   adjustment.
>>>> - Time adjustment is done by writing to the 1558_ADJUST register.
>>>>   The controller will read the delta in this register and update the timer
>>>>   counter register. Alternatively, for large time offset adjustments,
>>>>   the driver reads the secs and nsecs counter values, adds/subtracts the
>>>>   delta and updates the timer counter. In order to be as precise as
>> possible,
>>>>   nsecs counter is read again if secs has incremented during the counter
>> read.
>>>> - Frequency adjustment is not directly supported by this IP.
>>>>   addend is the initial value ns increment and similarly addendesub.
>>>>   The ppb (parts per billion) provided is used as
>>>>   ns_incr = addend +/- (ppb/rate).
>>>>   Similarly the remainder of the above is used to populate subns
>> increment.
>>>>   In case the ppb requested is negative AND subns adjustment greater
>> than
>>>>   the addendsub, ns_incr is reduced by 1 and subns_incr is adjusted in
>>>>   positive accordingly.
>>>>
>>>

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Michal Simek]

Hi Nicolas,

just a note: Here is the link to public Linux repo
https://github.com/Xilinx/linux-xlnx

Thanks,
Michal


On 9.8.2016 18:56, Punnaiah Choudary Kalluri wrote:
> Hi Nicolas,
> 
>  1588 implementation in cadence GEM IP we have in Zynq Ultascale+ MPSoC is
> Different to the one in Zynq SOC.
> 
> In earlier version, all timestamp values will be stored in registers and 
> there is no specific
> Mechanism to distinguish the received ethernet frame that contains time stamp 
> information
> Other than parsing the frame for PTP packet type.
> 
> We have basic implementation for earlier version in our out of tree driver, 
> which is going to be deprecated
> Soon. You could also check the below driver for 1588 support.
> https://gitenterprise.xilinx.com/Linux/linux-xlnx/blob/master/drivers/net/ethernet/xilinx/xilinx_emacps.c
> 
> 
> Regards,
> Punnaiah
> 
>> -Original Message-
>> From: Nicolas Ferre [mailto:nicolas.fe...@atmel.com]
>> Sent: Tuesday, August 09, 2016 10:10 PM
>> To: Harini Katakam ; Harini Katakam
>> ; Andrei Pistirica 
>> Cc: da...@davemloft.net; Boris Brezillon > electrons.com>; alexandre.bell...@free-electrons.com;
>> net...@vger.kernel.org; linux-kernel@vger.kernel.org;
>> devicet...@vger.kernel.org; Punnaiah Choudary Kalluri
>> ; Michal Simek ; Anirudha
>> Sarangi 
>> Subject: Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq
>> Ultrascale+ MPSoC
>>
>> Le 21/09/2015 à 19:49, Harini Katakam a écrit :
>>> On Fri, Sep 11, 2015 at 1:27 PM, Harini Katakam
>>>  wrote:
>>>> Cadence GEM in Zynq Ultrascale+ MPSoC supports 1588 and provides a
>>>> 102 bit time counter with 48 bits for seconds, 30 bits for nsecs and
>>>> 24 bits for sub-nsecs. The timestamp is made available to the SW through
>>>> registers as well as (more precisely) through upper two words in
>>>> an extended BD.
>>>>
>>>> This patch does the following:
>>>> - Adds MACB_CAPS_TSU in zynqmp_config.
>>>> - Registers to ptp clock framework (after checking for timestamp support
>> in
>>>>   IP and capability in config).
>>>> - TX BD and RX BD control registers are written to populate timestamp in
>>>>   extended BD words.
>>>> - Timer initialization is done by writing time of day to the timer counter.
>>>> - ns increment register is programmed as NS_PER_SEC/TSU_CLK.
>>>>   For a 24 bit subns precision, the subns increment equals
>>>>   remainder of (NS_PER_SEC/TSU_CLK) * (2^24).
>>>>   TSU (Time stamp unit) clock is obtained by the  driver from devicetree.
>>>> - HW time stamp capabilities are advertised via ethtool and macb ioctl is
>>>>   updated accordingly.
>>>> - For all PTP event frames, nanoseconds and the lower 5 bits of seconds
>> are
>>>>   obtained from the BD. This offers a precise timestamp. The upper bits
>>>>   (which dont vary between consecutive packets) are obtained from the
>>>>   TX/RX PTP event/PEER registers. The timestamp obtained thus is
>> updated
>>>>   in skb for upper layers to access.
>>>> - The drivers register functions with ptp to perform time and frequency
>>>>   adjustment.
>>>> - Time adjustment is done by writing to the 1558_ADJUST register.
>>>>   The controller will read the delta in this register and update the timer
>>>>   counter register. Alternatively, for large time offset adjustments,
>>>>   the driver reads the secs and nsecs counter values, adds/subtracts the
>>>>   delta and updates the timer counter. In order to be as precise as
>> possible,
>>>>   nsecs counter is read again if secs has incremented during the counter
>> read.
>>>> - Frequency adjustment is not directly supported by this IP.
>>>>   addend is the initial value ns increment and similarly addendesub.
>>>>   The ppb (parts per billion) provided is used as
>>>>   ns_incr = addend +/- (ppb/rate).
>>>>   Similarly the remainder of the above is used to populate subns
>> increment.
>>>>   In case the ppb requested is negative AND subns adjustment greater
>> than
>>>>   the addendsub, ns_incr is reduced by 1 and subns_incr is adjusted in
>>>>   positive accordingly.
>>>>
>>>> Signed-off-by: Harini Katakam :
>>>> ---
>>>>  drivers/net/ethernet/cadence/macb.c |  372
>> ++-
>>>>  drivers/net/ethernet/cadence/macb.h |   64 +

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Harini Katakam]

Hi Andrei,

On Wed, Aug 10, 2016 at 3:42 PM, Andrei Pistirica
 wrote:
> Hi Punnaiah,
>
> cpts_match(...) has a way to parse frames, while ptp_classify_raw identifies
> the underlying protocol (in case the frames are parsed on data path), or
> tx/rxtstamp callbacks can be used with PTP events. But, there is comment in
> ptp_classify.h which worries me.
>
> Unfortunately,  I cannot access https://gitenterprise.xilinx.com.

Please access this public repo:
https://github.com/Xilinx/linux-xlnx

Regards,
Harini

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Harini Katakam]

Hi Andrei,

On Wed, Aug 10, 2016 at 3:42 PM, Andrei Pistirica
 wrote:
> Hi Punnaiah,
>
> cpts_match(...) has a way to parse frames, while ptp_classify_raw identifies
> the underlying protocol (in case the frames are parsed on data path), or
> tx/rxtstamp callbacks can be used with PTP events. But, there is comment in
> ptp_classify.h which worries me.
>
> Unfortunately,  I cannot access https://gitenterprise.xilinx.com.

Please access this public repo:
https://github.com/Xilinx/linux-xlnx

Regards,
Harini

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Harini Katakam]

Hi Nicolas,

Thanks for your reply

On Tue, Aug 9, 2016 at 10:26 PM, Punnaiah Choudary Kalluri
<punnaiah.choudary.kall...@xilinx.com> wrote:
> Hi Nicolas,
>
>  1588 implementation in cadence GEM IP we have in Zynq Ultascale+ MPSoC is
> Different to the one in Zynq SOC.
>
> In earlier version, all timestamp values will be stored in registers and 
> there is no specific
> Mechanism to distinguish the received ethernet frame that contains time stamp 
> information
> Other than parsing the frame for PTP packet type.
>
> We have basic implementation for earlier version in our out of tree driver, 
> which is going to be deprecated
> Soon. You could also check the below driver for 1588 support.
> https://gitenterprise.xilinx.com/Linux/linux-xlnx/blob/master/drivers/net/ethernet/xilinx/xilinx_emacps.c
>
>
> Regards,
> Punnaiah
>
>> -Original Message-
>> From: Nicolas Ferre [mailto:nicolas.fe...@atmel.com]
>> Sent: Tuesday, August 09, 2016 10:10 PM
>> To: Harini Katakam <harinikatakamli...@gmail.com>; Harini Katakam
>> <hari...@xilinx.com>; Andrei Pistirica <andrei.pistir...@microchip.com>
>> Cc: da...@davemloft.net; Boris Brezillon <boris.brezillon@free-
>> electrons.com>; alexandre.bell...@free-electrons.com;
>> net...@vger.kernel.org; linux-kernel@vger.kernel.org;
>> devicet...@vger.kernel.org; Punnaiah Choudary Kalluri
>> <punn...@xilinx.com>; Michal Simek <mich...@xilinx.com>; Anirudha
>> Sarangi <anir...@xilinx.com>
>> Subject: Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq
>> Ultrascale+ MPSoC
>>
>> Le 21/09/2015 à 19:49, Harini Katakam a écrit :
>> > On Fri, Sep 11, 2015 at 1:27 PM, Harini Katakam
>> > <harini.kata...@xilinx.com> wrote:
>> >> Cadence GEM in Zynq Ultrascale+ MPSoC supports 1588 and provides a
>> >> 102 bit time counter with 48 bits for seconds, 30 bits for nsecs and
>> >> 24 bits for sub-nsecs. The timestamp is made available to the SW through
>> >> registers as well as (more precisely) through upper two words in
>> >> an extended BD.
>> >>
>> >> This patch does the following:
>> >> - Adds MACB_CAPS_TSU in zynqmp_config.
>> >> - Registers to ptp clock framework (after checking for timestamp support
>> in
>> >>   IP and capability in config).
>> >> - TX BD and RX BD control registers are written to populate timestamp in
>> >>   extended BD words.
>> >> - Timer initialization is done by writing time of day to the timer 
>> >> counter.
>> >> - ns increment register is programmed as NS_PER_SEC/TSU_CLK.
>> >>   For a 24 bit subns precision, the subns increment equals
>> >>   remainder of (NS_PER_SEC/TSU_CLK) * (2^24).
>> >>   TSU (Time stamp unit) clock is obtained by the  driver from devicetree.
>> >> - HW time stamp capabilities are advertised via ethtool and macb ioctl is
>> >>   updated accordingly.
>> >> - For all PTP event frames, nanoseconds and the lower 5 bits of seconds
>> are
>> >>   obtained from the BD. This offers a precise timestamp. The upper bits
>> >>   (which dont vary between consecutive packets) are obtained from the
>> >>   TX/RX PTP event/PEER registers. The timestamp obtained thus is
>> updated
>> >>   in skb for upper layers to access.
>> >> - The drivers register functions with ptp to perform time and frequency
>> >>   adjustment.
>> >> - Time adjustment is done by writing to the 1558_ADJUST register.
>> >>   The controller will read the delta in this register and update the timer
>> >>   counter register. Alternatively, for large time offset adjustments,
>> >>   the driver reads the secs and nsecs counter values, adds/subtracts the
>> >>   delta and updates the timer counter. In order to be as precise as
>> possible,
>> >>   nsecs counter is read again if secs has incremented during the counter
>> read.
>> >> - Frequency adjustment is not directly supported by this IP.
>> >>   addend is the initial value ns increment and similarly addendesub.
>> >>   The ppb (parts per billion) provided is used as
>> >>   ns_incr = addend +/- (ppb/rate).
>> >>   Similarly the remainder of the above is used to populate subns
>> increment.
>> >>   In case the ppb requested is negative AND subns adjustment greater
>> than
>> >>   the addendsub, ns_incr is reduced by 1 and subns_incr is adjusted in
>> >>   positive accordi

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Harini Katakam]

Hi Nicolas,

Thanks for your reply

On Tue, Aug 9, 2016 at 10:26 PM, Punnaiah Choudary Kalluri
 wrote:
> Hi Nicolas,
>
>  1588 implementation in cadence GEM IP we have in Zynq Ultascale+ MPSoC is
> Different to the one in Zynq SOC.
>
> In earlier version, all timestamp values will be stored in registers and 
> there is no specific
> Mechanism to distinguish the received ethernet frame that contains time stamp 
> information
> Other than parsing the frame for PTP packet type.
>
> We have basic implementation for earlier version in our out of tree driver, 
> which is going to be deprecated
> Soon. You could also check the below driver for 1588 support.
> https://gitenterprise.xilinx.com/Linux/linux-xlnx/blob/master/drivers/net/ethernet/xilinx/xilinx_emacps.c
>
>
> Regards,
> Punnaiah
>
>> -Original Message-
>> From: Nicolas Ferre [mailto:nicolas.fe...@atmel.com]
>> Sent: Tuesday, August 09, 2016 10:10 PM
>> To: Harini Katakam ; Harini Katakam
>> ; Andrei Pistirica 
>> Cc: da...@davemloft.net; Boris Brezillon > electrons.com>; alexandre.bell...@free-electrons.com;
>> net...@vger.kernel.org; linux-kernel@vger.kernel.org;
>> devicet...@vger.kernel.org; Punnaiah Choudary Kalluri
>> ; Michal Simek ; Anirudha
>> Sarangi 
>> Subject: Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq
>> Ultrascale+ MPSoC
>>
>> Le 21/09/2015 à 19:49, Harini Katakam a écrit :
>> > On Fri, Sep 11, 2015 at 1:27 PM, Harini Katakam
>> >  wrote:
>> >> Cadence GEM in Zynq Ultrascale+ MPSoC supports 1588 and provides a
>> >> 102 bit time counter with 48 bits for seconds, 30 bits for nsecs and
>> >> 24 bits for sub-nsecs. The timestamp is made available to the SW through
>> >> registers as well as (more precisely) through upper two words in
>> >> an extended BD.
>> >>
>> >> This patch does the following:
>> >> - Adds MACB_CAPS_TSU in zynqmp_config.
>> >> - Registers to ptp clock framework (after checking for timestamp support
>> in
>> >>   IP and capability in config).
>> >> - TX BD and RX BD control registers are written to populate timestamp in
>> >>   extended BD words.
>> >> - Timer initialization is done by writing time of day to the timer 
>> >> counter.
>> >> - ns increment register is programmed as NS_PER_SEC/TSU_CLK.
>> >>   For a 24 bit subns precision, the subns increment equals
>> >>   remainder of (NS_PER_SEC/TSU_CLK) * (2^24).
>> >>   TSU (Time stamp unit) clock is obtained by the  driver from devicetree.
>> >> - HW time stamp capabilities are advertised via ethtool and macb ioctl is
>> >>   updated accordingly.
>> >> - For all PTP event frames, nanoseconds and the lower 5 bits of seconds
>> are
>> >>   obtained from the BD. This offers a precise timestamp. The upper bits
>> >>   (which dont vary between consecutive packets) are obtained from the
>> >>   TX/RX PTP event/PEER registers. The timestamp obtained thus is
>> updated
>> >>   in skb for upper layers to access.
>> >> - The drivers register functions with ptp to perform time and frequency
>> >>   adjustment.
>> >> - Time adjustment is done by writing to the 1558_ADJUST register.
>> >>   The controller will read the delta in this register and update the timer
>> >>   counter register. Alternatively, for large time offset adjustments,
>> >>   the driver reads the secs and nsecs counter values, adds/subtracts the
>> >>   delta and updates the timer counter. In order to be as precise as
>> possible,
>> >>   nsecs counter is read again if secs has incremented during the counter
>> read.
>> >> - Frequency adjustment is not directly supported by this IP.
>> >>   addend is the initial value ns increment and similarly addendesub.
>> >>   The ppb (parts per billion) provided is used as
>> >>   ns_incr = addend +/- (ppb/rate).
>> >>   Similarly the remainder of the above is used to populate subns
>> increment.
>> >>   In case the ppb requested is negative AND subns adjustment greater
>> than
>> >>   the addendsub, ns_incr is reduced by 1 and subns_incr is adjusted in
>> >>   positive accordingly.
>> >>
>> >> Signed-off-by: Harini Katakam :
>> >> ---
>> >>  drivers/net/ethernet/cadence/macb.c |  372
>> ++-
>> >>  drivers/net/ethernet/cadence/macb.h |   64 ++
&g

RE: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Punnaiah Choudary Kalluri]

Hi Nicolas,

 1588 implementation in cadence GEM IP we have in Zynq Ultascale+ MPSoC is
Different to the one in Zynq SOC.

In earlier version, all timestamp values will be stored in registers and there 
is no specific
Mechanism to distinguish the received ethernet frame that contains time stamp 
information
Other than parsing the frame for PTP packet type.

We have basic implementation for earlier version in our out of tree driver, 
which is going to be deprecated
Soon. You could also check the below driver for 1588 support.
https://gitenterprise.xilinx.com/Linux/linux-xlnx/blob/master/drivers/net/ethernet/xilinx/xilinx_emacps.c


Regards,
Punnaiah

> -Original Message-
> From: Nicolas Ferre [mailto:nicolas.fe...@atmel.com]
> Sent: Tuesday, August 09, 2016 10:10 PM
> To: Harini Katakam <harinikatakamli...@gmail.com>; Harini Katakam
> <hari...@xilinx.com>; Andrei Pistirica <andrei.pistir...@microchip.com>
> Cc: da...@davemloft.net; Boris Brezillon <boris.brezillon@free-
> electrons.com>; alexandre.bell...@free-electrons.com;
> net...@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicet...@vger.kernel.org; Punnaiah Choudary Kalluri
> <punn...@xilinx.com>; Michal Simek <mich...@xilinx.com>; Anirudha
> Sarangi <anir...@xilinx.com>
> Subject: Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq
> Ultrascale+ MPSoC
>
> Le 21/09/2015 à 19:49, Harini Katakam a écrit :
> > On Fri, Sep 11, 2015 at 1:27 PM, Harini Katakam
> > <harini.kata...@xilinx.com> wrote:
> >> Cadence GEM in Zynq Ultrascale+ MPSoC supports 1588 and provides a
> >> 102 bit time counter with 48 bits for seconds, 30 bits for nsecs and
> >> 24 bits for sub-nsecs. The timestamp is made available to the SW through
> >> registers as well as (more precisely) through upper two words in
> >> an extended BD.
> >>
> >> This patch does the following:
> >> - Adds MACB_CAPS_TSU in zynqmp_config.
> >> - Registers to ptp clock framework (after checking for timestamp support
> in
> >>   IP and capability in config).
> >> - TX BD and RX BD control registers are written to populate timestamp in
> >>   extended BD words.
> >> - Timer initialization is done by writing time of day to the timer counter.
> >> - ns increment register is programmed as NS_PER_SEC/TSU_CLK.
> >>   For a 24 bit subns precision, the subns increment equals
> >>   remainder of (NS_PER_SEC/TSU_CLK) * (2^24).
> >>   TSU (Time stamp unit) clock is obtained by the  driver from devicetree.
> >> - HW time stamp capabilities are advertised via ethtool and macb ioctl is
> >>   updated accordingly.
> >> - For all PTP event frames, nanoseconds and the lower 5 bits of seconds
> are
> >>   obtained from the BD. This offers a precise timestamp. The upper bits
> >>   (which dont vary between consecutive packets) are obtained from the
> >>   TX/RX PTP event/PEER registers. The timestamp obtained thus is
> updated
> >>   in skb for upper layers to access.
> >> - The drivers register functions with ptp to perform time and frequency
> >>   adjustment.
> >> - Time adjustment is done by writing to the 1558_ADJUST register.
> >>   The controller will read the delta in this register and update the timer
> >>   counter register. Alternatively, for large time offset adjustments,
> >>   the driver reads the secs and nsecs counter values, adds/subtracts the
> >>   delta and updates the timer counter. In order to be as precise as
> possible,
> >>   nsecs counter is read again if secs has incremented during the counter
> read.
> >> - Frequency adjustment is not directly supported by this IP.
> >>   addend is the initial value ns increment and similarly addendesub.
> >>   The ppb (parts per billion) provided is used as
> >>   ns_incr = addend +/- (ppb/rate).
> >>   Similarly the remainder of the above is used to populate subns
> increment.
> >>   In case the ppb requested is negative AND subns adjustment greater
> than
> >>   the addendsub, ns_incr is reduced by 1 and subns_incr is adjusted in
> >>   positive accordingly.
> >>
> >> Signed-off-by: Harini Katakam <hari...@xilinx.com>:
> >> ---
> >>  drivers/net/ethernet/cadence/macb.c |  372
> ++-
> >>  drivers/net/ethernet/cadence/macb.h |   64 ++
> >>  2 files changed, 428 insertions(+), 8 deletions(-)
> >>
> >> diff --git a/drivers/net/ethernet/cadence/macb.c
> b/drivers/net/ethernet/cadence/macb.c
> >> index bb2932c..b531008 100644
> >> -

RE: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Punnaiah Choudary Kalluri]

Hi Nicolas,

 1588 implementation in cadence GEM IP we have in Zynq Ultascale+ MPSoC is
Different to the one in Zynq SOC.

In earlier version, all timestamp values will be stored in registers and there 
is no specific
Mechanism to distinguish the received ethernet frame that contains time stamp 
information
Other than parsing the frame for PTP packet type.

We have basic implementation for earlier version in our out of tree driver, 
which is going to be deprecated
Soon. You could also check the below driver for 1588 support.
https://gitenterprise.xilinx.com/Linux/linux-xlnx/blob/master/drivers/net/ethernet/xilinx/xilinx_emacps.c


Regards,
Punnaiah

> -Original Message-
> From: Nicolas Ferre [mailto:nicolas.fe...@atmel.com]
> Sent: Tuesday, August 09, 2016 10:10 PM
> To: Harini Katakam ; Harini Katakam
> ; Andrei Pistirica 
> Cc: da...@davemloft.net; Boris Brezillon  electrons.com>; alexandre.bell...@free-electrons.com;
> net...@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicet...@vger.kernel.org; Punnaiah Choudary Kalluri
> ; Michal Simek ; Anirudha
> Sarangi 
> Subject: Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq
> Ultrascale+ MPSoC
>
> Le 21/09/2015 à 19:49, Harini Katakam a écrit :
> > On Fri, Sep 11, 2015 at 1:27 PM, Harini Katakam
> >  wrote:
> >> Cadence GEM in Zynq Ultrascale+ MPSoC supports 1588 and provides a
> >> 102 bit time counter with 48 bits for seconds, 30 bits for nsecs and
> >> 24 bits for sub-nsecs. The timestamp is made available to the SW through
> >> registers as well as (more precisely) through upper two words in
> >> an extended BD.
> >>
> >> This patch does the following:
> >> - Adds MACB_CAPS_TSU in zynqmp_config.
> >> - Registers to ptp clock framework (after checking for timestamp support
> in
> >>   IP and capability in config).
> >> - TX BD and RX BD control registers are written to populate timestamp in
> >>   extended BD words.
> >> - Timer initialization is done by writing time of day to the timer counter.
> >> - ns increment register is programmed as NS_PER_SEC/TSU_CLK.
> >>   For a 24 bit subns precision, the subns increment equals
> >>   remainder of (NS_PER_SEC/TSU_CLK) * (2^24).
> >>   TSU (Time stamp unit) clock is obtained by the  driver from devicetree.
> >> - HW time stamp capabilities are advertised via ethtool and macb ioctl is
> >>   updated accordingly.
> >> - For all PTP event frames, nanoseconds and the lower 5 bits of seconds
> are
> >>   obtained from the BD. This offers a precise timestamp. The upper bits
> >>   (which dont vary between consecutive packets) are obtained from the
> >>   TX/RX PTP event/PEER registers. The timestamp obtained thus is
> updated
> >>   in skb for upper layers to access.
> >> - The drivers register functions with ptp to perform time and frequency
> >>   adjustment.
> >> - Time adjustment is done by writing to the 1558_ADJUST register.
> >>   The controller will read the delta in this register and update the timer
> >>   counter register. Alternatively, for large time offset adjustments,
> >>   the driver reads the secs and nsecs counter values, adds/subtracts the
> >>   delta and updates the timer counter. In order to be as precise as
> possible,
> >>   nsecs counter is read again if secs has incremented during the counter
> read.
> >> - Frequency adjustment is not directly supported by this IP.
> >>   addend is the initial value ns increment and similarly addendesub.
> >>   The ppb (parts per billion) provided is used as
> >>   ns_incr = addend +/- (ppb/rate).
> >>   Similarly the remainder of the above is used to populate subns
> increment.
> >>   In case the ppb requested is negative AND subns adjustment greater
> than
> >>   the addendsub, ns_incr is reduced by 1 and subns_incr is adjusted in
> >>   positive accordingly.
> >>
> >> Signed-off-by: Harini Katakam :
> >> ---
> >>  drivers/net/ethernet/cadence/macb.c |  372
> ++-
> >>  drivers/net/ethernet/cadence/macb.h |   64 ++
> >>  2 files changed, 428 insertions(+), 8 deletions(-)
> >>
> >> diff --git a/drivers/net/ethernet/cadence/macb.c
> b/drivers/net/ethernet/cadence/macb.c
> >> index bb2932c..b531008 100644
> >> --- a/drivers/net/ethernet/cadence/macb.c
> >> +++ b/drivers/net/ethernet/cadence/macb.c
> >> @@ -30,6 +30,8 @@
> >>  #include 
> >>  #include 
>
> [..]
>
> >> +   unsigned intns_incr;
> 

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Nicolas Ferre]

Le 21/09/2015 à 19:49, Harini Katakam a écrit :
> On Fri, Sep 11, 2015 at 1:27 PM, Harini Katakam
>  wrote:
>> Cadence GEM in Zynq Ultrascale+ MPSoC supports 1588 and provides a
>> 102 bit time counter with 48 bits for seconds, 30 bits for nsecs and
>> 24 bits for sub-nsecs. The timestamp is made available to the SW through
>> registers as well as (more precisely) through upper two words in
>> an extended BD.
>>
>> This patch does the following:
>> - Adds MACB_CAPS_TSU in zynqmp_config.
>> - Registers to ptp clock framework (after checking for timestamp support in
>>   IP and capability in config).
>> - TX BD and RX BD control registers are written to populate timestamp in
>>   extended BD words.
>> - Timer initialization is done by writing time of day to the timer counter.
>> - ns increment register is programmed as NS_PER_SEC/TSU_CLK.
>>   For a 24 bit subns precision, the subns increment equals
>>   remainder of (NS_PER_SEC/TSU_CLK) * (2^24).
>>   TSU (Time stamp unit) clock is obtained by the  driver from devicetree.
>> - HW time stamp capabilities are advertised via ethtool and macb ioctl is
>>   updated accordingly.
>> - For all PTP event frames, nanoseconds and the lower 5 bits of seconds are
>>   obtained from the BD. This offers a precise timestamp. The upper bits
>>   (which dont vary between consecutive packets) are obtained from the
>>   TX/RX PTP event/PEER registers. The timestamp obtained thus is updated
>>   in skb for upper layers to access.
>> - The drivers register functions with ptp to perform time and frequency
>>   adjustment.
>> - Time adjustment is done by writing to the 1558_ADJUST register.
>>   The controller will read the delta in this register and update the timer
>>   counter register. Alternatively, for large time offset adjustments,
>>   the driver reads the secs and nsecs counter values, adds/subtracts the
>>   delta and updates the timer counter. In order to be as precise as possible,
>>   nsecs counter is read again if secs has incremented during the counter 
>> read.
>> - Frequency adjustment is not directly supported by this IP.
>>   addend is the initial value ns increment and similarly addendesub.
>>   The ppb (parts per billion) provided is used as
>>   ns_incr = addend +/- (ppb/rate).
>>   Similarly the remainder of the above is used to populate subns increment.
>>   In case the ppb requested is negative AND subns adjustment greater than
>>   the addendsub, ns_incr is reduced by 1 and subns_incr is adjusted in
>>   positive accordingly.
>>
>> Signed-off-by: Harini Katakam :
>> ---
>>  drivers/net/ethernet/cadence/macb.c |  372 
>> ++-
>>  drivers/net/ethernet/cadence/macb.h |   64 ++
>>  2 files changed, 428 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/cadence/macb.c 
>> b/drivers/net/ethernet/cadence/macb.c
>> index bb2932c..b531008 100644
>> --- a/drivers/net/ethernet/cadence/macb.c
>> +++ b/drivers/net/ethernet/cadence/macb.c
>> @@ -30,6 +30,8 @@
>>  #include 
>>  #include 

[..]

>> +   unsigned intns_incr;
>> +   unsigned intsubns_incr;
>>  };
>>
>>  static inline bool macb_is_gem(struct macb *bp)
>> --
>> 1.7.9.5
> 
> Ping
> 
> Thanks.

Harini,

I come back to this patch of last year and I'm sorry about being so late
answering you.

Andrei who is added to the discussion will have some time to deal with
this feature and we would like to make some progress with it. He already
had some work done on his side before I recall your email.

So, could you please re-send your original 1588 patch with Andrei in
copy so that we can all (re-)start the discussion and progress for
adding this feature.

We must also note that some hardware differences between our platforms
may have an impact on the code and how we implement things (as
highlighted on this forum:
http://www.at91.com/discussions/viewtopic.php/f,12/t,25462.html).
Anyway, we'll overcome this and have a widely tested solution at the end
of the day!

Thanks for your patience, bye!

PS: for some reason, I only have this "ping" part of your email but not
the original one
-- 
Nicolas Ferre

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Nicolas Ferre]

Le 21/09/2015 à 19:49, Harini Katakam a écrit :
> On Fri, Sep 11, 2015 at 1:27 PM, Harini Katakam
>  wrote:
>> Cadence GEM in Zynq Ultrascale+ MPSoC supports 1588 and provides a
>> 102 bit time counter with 48 bits for seconds, 30 bits for nsecs and
>> 24 bits for sub-nsecs. The timestamp is made available to the SW through
>> registers as well as (more precisely) through upper two words in
>> an extended BD.
>>
>> This patch does the following:
>> - Adds MACB_CAPS_TSU in zynqmp_config.
>> - Registers to ptp clock framework (after checking for timestamp support in
>>   IP and capability in config).
>> - TX BD and RX BD control registers are written to populate timestamp in
>>   extended BD words.
>> - Timer initialization is done by writing time of day to the timer counter.
>> - ns increment register is programmed as NS_PER_SEC/TSU_CLK.
>>   For a 24 bit subns precision, the subns increment equals
>>   remainder of (NS_PER_SEC/TSU_CLK) * (2^24).
>>   TSU (Time stamp unit) clock is obtained by the  driver from devicetree.
>> - HW time stamp capabilities are advertised via ethtool and macb ioctl is
>>   updated accordingly.
>> - For all PTP event frames, nanoseconds and the lower 5 bits of seconds are
>>   obtained from the BD. This offers a precise timestamp. The upper bits
>>   (which dont vary between consecutive packets) are obtained from the
>>   TX/RX PTP event/PEER registers. The timestamp obtained thus is updated
>>   in skb for upper layers to access.
>> - The drivers register functions with ptp to perform time and frequency
>>   adjustment.
>> - Time adjustment is done by writing to the 1558_ADJUST register.
>>   The controller will read the delta in this register and update the timer
>>   counter register. Alternatively, for large time offset adjustments,
>>   the driver reads the secs and nsecs counter values, adds/subtracts the
>>   delta and updates the timer counter. In order to be as precise as possible,
>>   nsecs counter is read again if secs has incremented during the counter 
>> read.
>> - Frequency adjustment is not directly supported by this IP.
>>   addend is the initial value ns increment and similarly addendesub.
>>   The ppb (parts per billion) provided is used as
>>   ns_incr = addend +/- (ppb/rate).
>>   Similarly the remainder of the above is used to populate subns increment.
>>   In case the ppb requested is negative AND subns adjustment greater than
>>   the addendsub, ns_incr is reduced by 1 and subns_incr is adjusted in
>>   positive accordingly.
>>
>> Signed-off-by: Harini Katakam :
>> ---
>>  drivers/net/ethernet/cadence/macb.c |  372 
>> ++-
>>  drivers/net/ethernet/cadence/macb.h |   64 ++
>>  2 files changed, 428 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/cadence/macb.c 
>> b/drivers/net/ethernet/cadence/macb.c
>> index bb2932c..b531008 100644
>> --- a/drivers/net/ethernet/cadence/macb.c
>> +++ b/drivers/net/ethernet/cadence/macb.c
>> @@ -30,6 +30,8 @@
>>  #include 
>>  #include 

[..]

>> +   unsigned intns_incr;
>> +   unsigned intsubns_incr;
>>  };
>>
>>  static inline bool macb_is_gem(struct macb *bp)
>> --
>> 1.7.9.5
> 
> Ping
> 
> Thanks.

Harini,

I come back to this patch of last year and I'm sorry about being so late
answering you.

Andrei who is added to the discussion will have some time to deal with
this feature and we would like to make some progress with it. He already
had some work done on his side before I recall your email.

So, could you please re-send your original 1588 patch with Andrei in
copy so that we can all (re-)start the discussion and progress for
adding this feature.

We must also note that some hardware differences between our platforms
may have an impact on the code and how we implement things (as
highlighted on this forum:
http://www.at91.com/discussions/viewtopic.php/f,12/t,25462.html).
Anyway, we'll overcome this and have a widely tested solution at the end
of the day!

Thanks for your patience, bye!

PS: for some reason, I only have this "ping" part of your email but not
the original one
-- 
Nicolas Ferre

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Harini Katakam]

Hi Richard,

On Tue, Sep 22, 2015 at 12:09 AM, Richard Cochran
 wrote:
> On Mon, Sep 21, 2015 at 11:19:32PM +0530, Harini Katakam wrote:
>> Ping
>
> 1) trim your replies
>
> 2) put the PTP maintainer on PTP patches for review
>

I'm sorry I missed that. Will do so in the future.

Regards,
Harini
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Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Richard Cochran]

On Mon, Sep 21, 2015 at 11:19:32PM +0530, Harini Katakam wrote:
> Ping

1) trim your replies

2) put the PTP maintainer on PTP patches for review


Thanks,
Richard
--
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Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Harini Katakam]

On Fri, Sep 11, 2015 at 1:27 PM, Harini Katakam
 wrote:
> Cadence GEM in Zynq Ultrascale+ MPSoC supports 1588 and provides a
> 102 bit time counter with 48 bits for seconds, 30 bits for nsecs and
> 24 bits for sub-nsecs. The timestamp is made available to the SW through
> registers as well as (more precisely) through upper two words in
> an extended BD.
>
> This patch does the following:
> - Adds MACB_CAPS_TSU in zynqmp_config.
> - Registers to ptp clock framework (after checking for timestamp support in
>   IP and capability in config).
> - TX BD and RX BD control registers are written to populate timestamp in
>   extended BD words.
> - Timer initialization is done by writing time of day to the timer counter.
> - ns increment register is programmed as NS_PER_SEC/TSU_CLK.
>   For a 24 bit subns precision, the subns increment equals
>   remainder of (NS_PER_SEC/TSU_CLK) * (2^24).
>   TSU (Time stamp unit) clock is obtained by the  driver from devicetree.
> - HW time stamp capabilities are advertised via ethtool and macb ioctl is
>   updated accordingly.
> - For all PTP event frames, nanoseconds and the lower 5 bits of seconds are
>   obtained from the BD. This offers a precise timestamp. The upper bits
>   (which dont vary between consecutive packets) are obtained from the
>   TX/RX PTP event/PEER registers. The timestamp obtained thus is updated
>   in skb for upper layers to access.
> - The drivers register functions with ptp to perform time and frequency
>   adjustment.
> - Time adjustment is done by writing to the 1558_ADJUST register.
>   The controller will read the delta in this register and update the timer
>   counter register. Alternatively, for large time offset adjustments,
>   the driver reads the secs and nsecs counter values, adds/subtracts the
>   delta and updates the timer counter. In order to be as precise as possible,
>   nsecs counter is read again if secs has incremented during the counter read.
> - Frequency adjustment is not directly supported by this IP.
>   addend is the initial value ns increment and similarly addendesub.
>   The ppb (parts per billion) provided is used as
>   ns_incr = addend +/- (ppb/rate).
>   Similarly the remainder of the above is used to populate subns increment.
>   In case the ppb requested is negative AND subns adjustment greater than
>   the addendsub, ns_incr is reduced by 1 and subns_incr is adjusted in
>   positive accordingly.
>
> Signed-off-by: Harini Katakam :
> ---
>  drivers/net/ethernet/cadence/macb.c |  372 
> ++-
>  drivers/net/ethernet/cadence/macb.h |   64 ++
>  2 files changed, 428 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb.c 
> b/drivers/net/ethernet/cadence/macb.c
> index bb2932c..b531008 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -30,6 +30,8 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>
>  #include "macb.h"
>
> @@ -56,6 +58,9 @@
>
>  #define GEM_MTU_MIN_SIZE   68
>
> +#define GEM_TX_PTPHDR_OFFSET   42
> +#define GEM_RX_PTPHDR_OFFSET   28
> +
>  /*
>   * Graceful stop timeouts in us. We should allow up to
>   * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
> @@ -165,6 +170,9 @@ static void macb_set_hwaddr(struct macb *bp)
> top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
> macb_or_gem_writel(bp, SA1T, top);
>
> +   gem_writel(bp, RXPTPUNI, bottom);
> +   gem_writel(bp, TXPTPUNI, bottom);
> +
> /* Clear unused address register sets */
> macb_or_gem_writel(bp, SA2B, 0);
> macb_or_gem_writel(bp, SA2T, 0);
> @@ -653,6 +661,40 @@ static void macb_tx_error_task(struct work_struct *work)
> spin_unlock_irqrestore(>lock, flags);
>  }
>
> +static inline void macb_handle_txtstamp(struct macb *bp, struct sk_buff *skb,
> +   struct macb_dma_desc *desc)
> +{
> +   u32 ts_s, ts_ns;
> +   u8 msg_type;
> +
> +   skb_copy_from_linear_data_offset(skb, GEM_TX_PTPHDR_OFFSET,
> +_type, 1);
> +
> +   /* Bit[32:6] of TS secs from register
> +* Bit[5:0] of TS secs from BD
> +* TS nano secs is available in BD
> +*/
> +   if (msg_type & 0x2) {
> +   /* PTP Peer Event Frame packets */
> +   ts_s = (gem_readl(bp, 1588PEERTXSEC) & GEM_SEC_MASK) |
> +  ((desc->tsl >> GEM_TSL_SEC_RS) |
> +  (desc->tsh << GEM_TSH_SEC_LS));
> +   ts_ns = desc->tsl & GEM_TSL_NSEC_MASK;
> +   } else {
> +   /* PTP Event Frame packets */
> +   ts_s = (gem_readl(bp, 1588TXSEC) & GEM_SEC_MASK) |
> +  ((desc->tsl >> GEM_TSL_SEC_RS) |
> +  (desc->tsh << GEM_TSH_SEC_LS));
> +   ts_ns = desc->tsl & GEM_TSL_NSEC_MASK;
> +   }
> +
> +   struct skb_shared_hwtstamps *shhwtstamps = 

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Harini Katakam]

Hi Richard,

On Tue, Sep 22, 2015 at 12:09 AM, Richard Cochran
 wrote:
> On Mon, Sep 21, 2015 at 11:19:32PM +0530, Harini Katakam wrote:
>> Ping
>
> 1) trim your replies
>
> 2) put the PTP maintainer on PTP patches for review
>

I'm sorry I missed that. Will do so in the future.

Regards,
Harini
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Harini Katakam]

On Fri, Sep 11, 2015 at 1:27 PM, Harini Katakam
 wrote:
> Cadence GEM in Zynq Ultrascale+ MPSoC supports 1588 and provides a
> 102 bit time counter with 48 bits for seconds, 30 bits for nsecs and
> 24 bits for sub-nsecs. The timestamp is made available to the SW through
> registers as well as (more precisely) through upper two words in
> an extended BD.
>
> This patch does the following:
> - Adds MACB_CAPS_TSU in zynqmp_config.
> - Registers to ptp clock framework (after checking for timestamp support in
>   IP and capability in config).
> - TX BD and RX BD control registers are written to populate timestamp in
>   extended BD words.
> - Timer initialization is done by writing time of day to the timer counter.
> - ns increment register is programmed as NS_PER_SEC/TSU_CLK.
>   For a 24 bit subns precision, the subns increment equals
>   remainder of (NS_PER_SEC/TSU_CLK) * (2^24).
>   TSU (Time stamp unit) clock is obtained by the  driver from devicetree.
> - HW time stamp capabilities are advertised via ethtool and macb ioctl is
>   updated accordingly.
> - For all PTP event frames, nanoseconds and the lower 5 bits of seconds are
>   obtained from the BD. This offers a precise timestamp. The upper bits
>   (which dont vary between consecutive packets) are obtained from the
>   TX/RX PTP event/PEER registers. The timestamp obtained thus is updated
>   in skb for upper layers to access.
> - The drivers register functions with ptp to perform time and frequency
>   adjustment.
> - Time adjustment is done by writing to the 1558_ADJUST register.
>   The controller will read the delta in this register and update the timer
>   counter register. Alternatively, for large time offset adjustments,
>   the driver reads the secs and nsecs counter values, adds/subtracts the
>   delta and updates the timer counter. In order to be as precise as possible,
>   nsecs counter is read again if secs has incremented during the counter read.
> - Frequency adjustment is not directly supported by this IP.
>   addend is the initial value ns increment and similarly addendesub.
>   The ppb (parts per billion) provided is used as
>   ns_incr = addend +/- (ppb/rate).
>   Similarly the remainder of the above is used to populate subns increment.
>   In case the ppb requested is negative AND subns adjustment greater than
>   the addendsub, ns_incr is reduced by 1 and subns_incr is adjusted in
>   positive accordingly.
>
> Signed-off-by: Harini Katakam :
> ---
>  drivers/net/ethernet/cadence/macb.c |  372 
> ++-
>  drivers/net/ethernet/cadence/macb.h |   64 ++
>  2 files changed, 428 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb.c 
> b/drivers/net/ethernet/cadence/macb.c
> index bb2932c..b531008 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -30,6 +30,8 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>
>  #include "macb.h"
>
> @@ -56,6 +58,9 @@
>
>  #define GEM_MTU_MIN_SIZE   68
>
> +#define GEM_TX_PTPHDR_OFFSET   42
> +#define GEM_RX_PTPHDR_OFFSET   28
> +
>  /*
>   * Graceful stop timeouts in us. We should allow up to
>   * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
> @@ -165,6 +170,9 @@ static void macb_set_hwaddr(struct macb *bp)
> top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
> macb_or_gem_writel(bp, SA1T, top);
>
> +   gem_writel(bp, RXPTPUNI, bottom);
> +   gem_writel(bp, TXPTPUNI, bottom);
> +
> /* Clear unused address register sets */
> macb_or_gem_writel(bp, SA2B, 0);
> macb_or_gem_writel(bp, SA2T, 0);
> @@ -653,6 +661,40 @@ static void macb_tx_error_task(struct work_struct *work)
> spin_unlock_irqrestore(>lock, flags);
>  }
>
> +static inline void macb_handle_txtstamp(struct macb *bp, struct sk_buff *skb,
> +   struct macb_dma_desc *desc)
> +{
> +   u32 ts_s, ts_ns;
> +   u8 msg_type;
> +
> +   skb_copy_from_linear_data_offset(skb, GEM_TX_PTPHDR_OFFSET,
> +_type, 1);
> +
> +   /* Bit[32:6] of TS secs from register
> +* Bit[5:0] of TS secs from BD
> +* TS nano secs is available in BD
> +*/
> +   if (msg_type & 0x2) {
> +   /* PTP Peer Event Frame packets */
> +   ts_s = (gem_readl(bp, 1588PEERTXSEC) & GEM_SEC_MASK) |
> +  ((desc->tsl >> GEM_TSL_SEC_RS) |
> +  (desc->tsh << GEM_TSH_SEC_LS));
> +   ts_ns = desc->tsl & GEM_TSL_NSEC_MASK;
> +   } else {
> +   /* PTP Event Frame packets */
> +   ts_s = (gem_readl(bp, 1588TXSEC) & GEM_SEC_MASK) |
> +  ((desc->tsl >> GEM_TSL_SEC_RS) |
> +  (desc->tsh << GEM_TSH_SEC_LS));
> +   ts_ns = desc->tsl & GEM_TSL_NSEC_MASK;
> +   }
> +
> +   struct 

Re: [RFC PATCH 2/3] net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC

[Richard Cochran]

On Mon, Sep 21, 2015 at 11:19:32PM +0530, Harini Katakam wrote:
> Ping

1) trim your replies

2) put the PTP maintainer on PTP patches for review


Thanks,
Richard
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/