Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Thursday, August 20, 2015 at 10:06:29 AM, Viet Nga Dao wrote: > On Thu, Aug 20, 2015 at 3:55 PM, Marek Vasut wrote: > > On Thursday, August 20, 2015 at 09:37:33 AM, Viet Nga Dao wrote: > >> Hi, > > > > Hi, > > > >> >> On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: > >> >>> I'm not very helpful here, so hopefully Viet can be of more use: > >> >> Yup :) > >> >> > >> >>> On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: > >> >>> > On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: > >> >>> > Also, I cannot find any documentation for this IP block even if I > >> >>> > search through Quartus/QSys, is there any proper documentation > >> >>> > available anywhere? > >> >>> > >> >>> I never found proper documentation, but I didn't look too hard. I've > >> >>> mostly been going off of Viet's comments and code. > >> >> > >> >> Me neither, and I looked through the altera stuff in fact. I'm trying > >> >> to learn whether this is just an Soft IP, in which case it certainly > >> >> can be fixed ; or if there is actually some chip shipping with this > >> >> crap synthesised into actual silicon. > >> >> > >> >>> But FWIW, I did find some relevant info for the peculiar Altera EPCQ > >> >>> flash here: > >> >>> > >> >>> https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/lite > >> >>> ra ture/ > >> >>> hb/cfg/cfg_cf52012.pdf > >> >> > >> >> Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just > >> >> have different JEDEC >ID and are a bit more expensive. > >> > > >> > You can find the document at here > >> > (https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/liter > >> > atu re/ug/ug_embedded_ip.pdf) > >> > > >> > Chapter 42.Page 407. > >> > > >> > For the soft IP issue, i've requested hardware engineer to come out > >> > the solution. > > > > That's good :) > > > >> > So in the mean way, our driver will NOT support Micron > >> > flashes until hardware fix is completed. > > > > This doesn't answer my question, so let me reiterate. Is this controller > > only Soft IP (as in, FPGA core) or is this controller shipping in some > > chip as Hard IP (as in, piece of silicon) ? > > This is new soft IP. I see, thanks ! Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Thu, Aug 20, 2015 at 3:55 PM, Marek Vasut wrote: > On Thursday, August 20, 2015 at 09:37:33 AM, Viet Nga Dao wrote: >> Hi, > > Hi, > >> >> On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: >> >>> I'm not very helpful here, so hopefully Viet can be of more use: >> >> Yup :) >> >> >> >>> On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: >> >>> > On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: >> >>> > Also, I cannot find any documentation for this IP block even if I >> >>> > search through Quartus/QSys, is there any proper documentation >> >>> > available anywhere? >> >>> >> >>> I never found proper documentation, but I didn't look too hard. I've >> >>> mostly been going off of Viet's comments and code. >> >> >> >> Me neither, and I looked through the altera stuff in fact. I'm trying to >> >> learn whether this is just an Soft IP, in which case it certainly can >> >> be fixed ; or if there is actually some chip shipping with this crap >> >> synthesised into actual silicon. >> >> >> >>> But FWIW, I did find some relevant info for the peculiar Altera EPCQ >> >>> flash here: >> >>> >> >>> https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/litera >> >>> ture/ >> >>> hb/cfg/cfg_cf52012.pdf >> >> >> >> Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just >> >> have different JEDEC >ID and are a bit more expensive. >> > >> > You can find the document at here >> > (https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literatu >> > re/ug/ug_embedded_ip.pdf) >> > >> > Chapter 42.Page 407. >> > >> > For the soft IP issue, i've requested hardware engineer to come out >> > the solution. > > That's good :) > >> > So in the mean way, our driver will NOT support Micron >> > flashes until hardware fix is completed. > > This doesn't answer my question, so let me reiterate. Is this controller > only Soft IP (as in, FPGA core) or is this controller shipping in some > chip as Hard IP (as in, piece of silicon) ? > This is new soft IP. >> > Hence, i just submitted version 5 for this driver with eliminating >> > micron device support. Hope this version will get ACKed by you. > > We'll see. > > Best regards, > Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Thursday, August 20, 2015 at 09:37:33 AM, Viet Nga Dao wrote: > Hi, Hi, > >> On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: > >>> I'm not very helpful here, so hopefully Viet can be of more use: > >> Yup :) > >> > >>> On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: > >>> > On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: > >>> > Also, I cannot find any documentation for this IP block even if I > >>> > search through Quartus/QSys, is there any proper documentation > >>> > available anywhere? > >>> > >>> I never found proper documentation, but I didn't look too hard. I've > >>> mostly been going off of Viet's comments and code. > >> > >> Me neither, and I looked through the altera stuff in fact. I'm trying to > >> learn whether this is just an Soft IP, in which case it certainly can > >> be fixed ; or if there is actually some chip shipping with this crap > >> synthesised into actual silicon. > >> > >>> But FWIW, I did find some relevant info for the peculiar Altera EPCQ > >>> flash here: > >>> > >>> https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/litera > >>> ture/ > >>> hb/cfg/cfg_cf52012.pdf > >> > >> Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just > >> have different JEDEC >ID and are a bit more expensive. > > > > You can find the document at here > > (https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literatu > > re/ug/ug_embedded_ip.pdf) > > > > Chapter 42.Page 407. > > > > For the soft IP issue, i've requested hardware engineer to come out > > the solution. That's good :) > > So in the mean way, our driver will NOT support Micron > > flashes until hardware fix is completed. This doesn't answer my question, so let me reiterate. Is this controller only Soft IP (as in, FPGA core) or is this controller shipping in some chip as Hard IP (as in, piece of silicon) ? > > Hence, i just submitted version 5 for this driver with eliminating > > micron device support. Hope this version will get ACKed by you. We'll see. Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
Hi, >> On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: >>> I'm not very helpful here, so hopefully Viet can be of more use: >> >> Yup :) >> >>> On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: >>> > On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: >>> > Also, I cannot find any documentation for this IP block even if I >>> > search through Quartus/QSys, is there any proper documentation >>> > available anywhere? >>> >>> I never found proper documentation, but I didn't look too hard. I've >>> mostly been going off of Viet's comments and code. >> >> Me neither, and I looked through the altera stuff in fact. I'm trying to >> learn whether this is just an Soft IP, in which case it certainly can be >> fixed ; or if there is actually some chip shipping with this crap >> synthesised into actual silicon. >> >>> But FWIW, I did find some relevant info for the peculiar Altera EPCQ >>> flash here: >>> >>> https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/litera >>> ture/ >>> hb/cfg/cfg_cf52012.pdf >> >> Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just have >> different JEDEC >ID and are a bit more expensive. > > You can find the document at here > (https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf) > Chapter 42.Page 407. > > For the soft IP issue, i've requested hardware engineer to come out > the solution. So in the mean way, our driver will NOT support Micron > flashes until hardware fix is completed. > > Hence, i just submitted version 5 for this driver with eliminating > micron device support. Hope this version will get ACKed by you. > > Thanks, > Viet Nga -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Tue, Aug 18, 2015 at 2:55 PM, Viet Nga Dao wrote: > > > -Original Message- > From: ma...@denx.de > Sent: Tuesday, August 18, 2015 9:33 AM > To: Brian Norris > Cc: linux-...@lists.infradead.org; Viet Nga Dao; devicet...@vger.kernel.org; > Rafa?? Mi??ecki; linux-kernel@vger.kernel.org; David Woodhouse; Graham Moore > Subject: Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver > > On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: >> I'm not very helpful here, so hopefully Viet can be of more use: > > Yup :) > >> On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: >> > On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: >> > Also, I cannot find any documentation for this IP block even if I >> > search through Quartus/QSys, is there any proper documentation >> > available anywhere? >> >> I never found proper documentation, but I didn't look too hard. I've >> mostly been going off of Viet's comments and code. > > Me neither, and I looked through the altera stuff in fact. I'm trying to > learn whether this is just an Soft IP, in which case it certainly can be > fixed ; or if there is actually some chip shipping with this crap synthesised > into actual silicon. > >> But FWIW, I did find some relevant info for the peculiar Altera EPCQ >> flash here: >> >> https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/litera >> ture/ >> hb/cfg/cfg_cf52012.pdf > > Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just have > different JEDEC >ID and are a bit more expensive. You can find the document at here (https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf) Chapter 42.Page 407. For the soft IP issue, i've requested hardware engineer to come out the solution. So in the mean way, our driver will NOT support Micron flashes until hardware fix is completed. Hence, i just submitted version 5 for this driver with eliminating micron device support. Hope this version will get ACKed by you. Thanks, Viet Nga -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Tue, Aug 18, 2015 at 2:55 PM, Viet Nga Dao vn...@altera.com wrote: -Original Message- From: ma...@denx.de Sent: Tuesday, August 18, 2015 9:33 AM To: Brian Norris Cc: linux-...@lists.infradead.org; Viet Nga Dao; devicet...@vger.kernel.org; Rafa?? Mi??ecki; linux-kernel@vger.kernel.org; David Woodhouse; Graham Moore Subject: Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: I'm not very helpful here, so hopefully Viet can be of more use: Yup :) On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: Also, I cannot find any documentation for this IP block even if I search through Quartus/QSys, is there any proper documentation available anywhere? I never found proper documentation, but I didn't look too hard. I've mostly been going off of Viet's comments and code. Me neither, and I looked through the altera stuff in fact. I'm trying to learn whether this is just an Soft IP, in which case it certainly can be fixed ; or if there is actually some chip shipping with this crap synthesised into actual silicon. But FWIW, I did find some relevant info for the peculiar Altera EPCQ flash here: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/litera ture/ hb/cfg/cfg_cf52012.pdf Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just have different JEDEC ID and are a bit more expensive. You can find the document at here (https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf) Chapter 42.Page 407. For the soft IP issue, i've requested hardware engineer to come out the solution. So in the mean way, our driver will NOT support Micron flashes until hardware fix is completed. Hence, i just submitted version 5 for this driver with eliminating micron device support. Hope this version will get ACKed by you. Thanks, Viet Nga -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Thursday, August 20, 2015 at 09:37:33 AM, Viet Nga Dao wrote: Hi, Hi, On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: I'm not very helpful here, so hopefully Viet can be of more use: Yup :) On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: Also, I cannot find any documentation for this IP block even if I search through Quartus/QSys, is there any proper documentation available anywhere? I never found proper documentation, but I didn't look too hard. I've mostly been going off of Viet's comments and code. Me neither, and I looked through the altera stuff in fact. I'm trying to learn whether this is just an Soft IP, in which case it certainly can be fixed ; or if there is actually some chip shipping with this crap synthesised into actual silicon. But FWIW, I did find some relevant info for the peculiar Altera EPCQ flash here: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/litera ture/ hb/cfg/cfg_cf52012.pdf Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just have different JEDEC ID and are a bit more expensive. You can find the document at here (https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literatu re/ug/ug_embedded_ip.pdf) Chapter 42.Page 407. For the soft IP issue, i've requested hardware engineer to come out the solution. That's good :) So in the mean way, our driver will NOT support Micron flashes until hardware fix is completed. This doesn't answer my question, so let me reiterate. Is this controller only Soft IP (as in, FPGA core) or is this controller shipping in some chip as Hard IP (as in, piece of silicon) ? Hence, i just submitted version 5 for this driver with eliminating micron device support. Hope this version will get ACKed by you. We'll see. Best regards, Marek Vasut -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
Hi, On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: I'm not very helpful here, so hopefully Viet can be of more use: Yup :) On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: Also, I cannot find any documentation for this IP block even if I search through Quartus/QSys, is there any proper documentation available anywhere? I never found proper documentation, but I didn't look too hard. I've mostly been going off of Viet's comments and code. Me neither, and I looked through the altera stuff in fact. I'm trying to learn whether this is just an Soft IP, in which case it certainly can be fixed ; or if there is actually some chip shipping with this crap synthesised into actual silicon. But FWIW, I did find some relevant info for the peculiar Altera EPCQ flash here: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/litera ture/ hb/cfg/cfg_cf52012.pdf Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just have different JEDEC ID and are a bit more expensive. You can find the document at here (https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf) Chapter 42.Page 407. For the soft IP issue, i've requested hardware engineer to come out the solution. So in the mean way, our driver will NOT support Micron flashes until hardware fix is completed. Hence, i just submitted version 5 for this driver with eliminating micron device support. Hope this version will get ACKed by you. Thanks, Viet Nga -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Thu, Aug 20, 2015 at 3:55 PM, Marek Vasut ma...@denx.de wrote: On Thursday, August 20, 2015 at 09:37:33 AM, Viet Nga Dao wrote: Hi, Hi, On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: I'm not very helpful here, so hopefully Viet can be of more use: Yup :) On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: Also, I cannot find any documentation for this IP block even if I search through Quartus/QSys, is there any proper documentation available anywhere? I never found proper documentation, but I didn't look too hard. I've mostly been going off of Viet's comments and code. Me neither, and I looked through the altera stuff in fact. I'm trying to learn whether this is just an Soft IP, in which case it certainly can be fixed ; or if there is actually some chip shipping with this crap synthesised into actual silicon. But FWIW, I did find some relevant info for the peculiar Altera EPCQ flash here: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/litera ture/ hb/cfg/cfg_cf52012.pdf Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just have different JEDEC ID and are a bit more expensive. You can find the document at here (https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literatu re/ug/ug_embedded_ip.pdf) Chapter 42.Page 407. For the soft IP issue, i've requested hardware engineer to come out the solution. That's good :) So in the mean way, our driver will NOT support Micron flashes until hardware fix is completed. This doesn't answer my question, so let me reiterate. Is this controller only Soft IP (as in, FPGA core) or is this controller shipping in some chip as Hard IP (as in, piece of silicon) ? This is new soft IP. Hence, i just submitted version 5 for this driver with eliminating micron device support. Hope this version will get ACKed by you. We'll see. Best regards, Marek Vasut -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Thursday, August 20, 2015 at 10:06:29 AM, Viet Nga Dao wrote: On Thu, Aug 20, 2015 at 3:55 PM, Marek Vasut ma...@denx.de wrote: On Thursday, August 20, 2015 at 09:37:33 AM, Viet Nga Dao wrote: Hi, Hi, On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: I'm not very helpful here, so hopefully Viet can be of more use: Yup :) On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: Also, I cannot find any documentation for this IP block even if I search through Quartus/QSys, is there any proper documentation available anywhere? I never found proper documentation, but I didn't look too hard. I've mostly been going off of Viet's comments and code. Me neither, and I looked through the altera stuff in fact. I'm trying to learn whether this is just an Soft IP, in which case it certainly can be fixed ; or if there is actually some chip shipping with this crap synthesised into actual silicon. But FWIW, I did find some relevant info for the peculiar Altera EPCQ flash here: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/lite ra ture/ hb/cfg/cfg_cf52012.pdf Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just have different JEDEC ID and are a bit more expensive. You can find the document at here (https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/liter atu re/ug/ug_embedded_ip.pdf) Chapter 42.Page 407. For the soft IP issue, i've requested hardware engineer to come out the solution. That's good :) So in the mean way, our driver will NOT support Micron flashes until hardware fix is completed. This doesn't answer my question, so let me reiterate. Is this controller only Soft IP (as in, FPGA core) or is this controller shipping in some chip as Hard IP (as in, piece of silicon) ? This is new soft IP. I see, thanks ! Best regards, Marek Vasut -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: > I'm not very helpful here, so hopefully Viet can be of more use: Yup :) > On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: > > On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: > > Also, I cannot find any documentation for this IP block even if I search > > through Quartus/QSys, is there any proper documentation available > > anywhere? > > I never found proper documentation, but I didn't look too hard. I've > mostly been going off of Viet's comments and code. Me neither, and I looked through the altera stuff in fact. I'm trying to learn whether this is just an Soft IP, in which case it certainly can be fixed ; or if there is actually some chip shipping with this crap synthesised into actual silicon. > But FWIW, I did find some relevant info for the peculiar Altera EPCQ > flash here: > > https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ > hb/cfg/cfg_cf52012.pdf Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just have different JEDEC ID and are a bit more expensive. Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
I'm not very helpful here, so hopefully Viet can be of more use: On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: > On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: > Also, I cannot find any documentation for this IP block even if I search > through > Quartus/QSys, is there any proper documentation available anywhere? I never found proper documentation, but I didn't look too hard. I've mostly been going off of Viet's comments and code. But FWIW, I did find some relevant info for the peculiar Altera EPCQ flash here: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cfg/cfg_cf52012.pdf Brian -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: Hi! [...] > > Hi Brian, > > It is really unfortunate that this controller is not able to read full > > JEDEC ID. It only can provide 1 byte ID. I did discuss with IP > > designer about this, but it is really unfortunate that they are not > > able to fix that issue. Hence it requires software to make changes. Thanks for CCing me, I assume this is a driver for that "altera_epcq_controller" which you can synthesise into your FPGA, is that correct? Is there an Hard IP variant of this controller in the public or is this purely Soft IP? Also, I cannot find any documentation for this IP block even if I search through Quartus/QSys, is there any proper documentation available anywhere? [...] Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Mon, Jul 27, 2015 at 03:10:23PM +0800, Viet Nga Dao wrote: > On Sat, Jul 25, 2015 at 2:37 AM, Brian Norris > wrote: > > On Wed, Jun 03, 2015 at 12:30:44AM -0700, vn...@altera.com wrote: > >> From: VIET NGA DAO > >> > >> Altera Quad SPI Controller is a soft IP which enables access to > >> Altera EPCS, EPCQ and Mircon flash chips. This patch adds driver > >> for these devices. > >> > >> Signed-off-by: VIET NGA DAO > >> > >> --- > >> v4: > >> - Add more flash devices support ( EPCQL and Micron) > > > > ^^ Unfortunately, I think you've added yourself another burden with this > > one. Most of the rest actually is looking pretty good, so it's sad to > > see this hold your driver back. Comments below. FWIW, this comment still stands. I cannot take your patch as-is. > >> - Remove redundant messages > >> - Change EPCQ_OPCODE_ID to NON_EPCS_OPCODE_ID > >> - Replace get_flash_name to altera_quadspi_scan > >> - Remove clk related parts > >> - Remove altera_quadspi_plat > >> - Change device tree reg name and remove opcode-id > >> > >> v3: > >> - Change altera_epcq driver name to altera_quadspi for more generic name > >> - Implement flash name searching in altera_quadspi.c instead of spi-nor > >> - Edit the altra quadspi info table in spi-nor > >> - Remove wait_til_ready in all read,write, erase, lock, unlock functions > >> - Merge .h and .c into 1 file > >> > >> v2: > >> - Change to spi_nor structure > >> - Add lock and unlock functions for spi_nor > >> - Simplify the altera_epcq_lock function > >> - Replace reg by compatible in device tree > >> --- > >> .../devicetree/bindings/mtd/altera-quadspi.txt | 49 ++ > >> drivers/mtd/spi-nor/Kconfig|8 + > >> drivers/mtd/spi-nor/Makefile |1 + > >> drivers/mtd/spi-nor/altera-quadspi.c | 568 > >> > >> drivers/mtd/spi-nor/spi-nor.c | 30 + > >> 5 files changed, 656 insertions(+), 0 deletions(-) > >> create mode 100644 > >> Documentation/devicetree/bindings/mtd/altera-quadspi.txt > >> create mode 100644 drivers/mtd/spi-nor/altera-quadspi.c > >> > >> diff --git a/Documentation/devicetree/bindings/mtd/altera-quadspi.txt > >> b/Documentation/devicetree/bindings/mtd/altera-quadspi.txt > >> new file mode 100644 > >> index 000..2873319 > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/mtd/altera-quadspi.txt > >> @@ -0,0 +1,49 @@ > >> +* MTD Altera QUADSPI driver > >> + > >> +Required properties: > >> +- compatible: Should be "altr,quadspi-1.0" > >> +- reg: Address and length of the register set for the device. It contains > >> + the information of registers in the same order as described by reg-names > >> +- reg-names: Should contain the reg names > >> + "avl_csr": Should contain the register configuration base address > >> + "avl_mem": Should contain the data base address > >> +- #address-cells: Must be <1>. > >> +- #size-cells: Must be <0>. > >> +- flash device tree subnode, there must be a node with the following > >> fields: > >> + - compatible: Should contain the flash name: > >> + 1. EPCS: epcs16, epcs64, epcs128 > >> + 2. EPCQ: epcq16, epcq32, epcq64, epcq128, epcq256, epcq512, > >> epcq1024 > >> + 3. EPCQ-L: epcql256, epcql512, epcql1024 > >> + 4. Mircon: n25q016-nonjedec, n25q032-nonjedec, n25q064-nonjedec, > >> + n25q128a13-nonjedec, n25q128a11-nonjedec, > >> n25q256a-nonjedec, > >> + n25q256a11-nonjedec, n25q512a-nonjedec, > >> n25q512ax3-nonjedec, > >> + mt25ql512-nonjedec, n25q00-nonjedec, n25q00a11-nonjedec > > > > OK, so you're adding a bunch of Micron flashes which already have > > support via standard DT bindings and spi-nor library code, except now > > you're adding "-nonjedec" to all of them. You better have a *really* > > good reason for this. Are these flash not compatible with the JEDEC READ > > ID opcode, by which every other system identifies these parts? Or are > > you adding these names because of limitations in your controller? For > > the former, I might be able to understand the need, but for the latter, > > I'm much disinclined to support this. There's got to be a better way. > > > > Hi Brian, > It is really unfortunate that this controller is not able to read full > JEDEC ID. It only can provide 1 byte ID. I did discuss with IP > designer about this, but it is really unfortunate that they are not > able to fix that issue. Hence it requires software to make changes. Wow, what a joke. (Please quote me to your IP "designer.") In any case, there's no way I'm going to support a ton of new "*-nonjedec" strings just to support your completely broken controller. These aren't actually "nonjedec" flash devices, and AFAICT, there's absolutely nothing wrong with the flash that requires this description. It's purely your controller's fault. Thus, I'm not changing the DT binding for all the flash you want to use. Instead, I
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: I'm not very helpful here, so hopefully Viet can be of more use: Yup :) On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: Also, I cannot find any documentation for this IP block even if I search through Quartus/QSys, is there any proper documentation available anywhere? I never found proper documentation, but I didn't look too hard. I've mostly been going off of Viet's comments and code. Me neither, and I looked through the altera stuff in fact. I'm trying to learn whether this is just an Soft IP, in which case it certainly can be fixed ; or if there is actually some chip shipping with this crap synthesised into actual silicon. But FWIW, I did find some relevant info for the peculiar Altera EPCQ flash here: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ hb/cfg/cfg_cf52012.pdf Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just have different JEDEC ID and are a bit more expensive. Best regards, Marek Vasut -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
I'm not very helpful here, so hopefully Viet can be of more use: On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: Also, I cannot find any documentation for this IP block even if I search through Quartus/QSys, is there any proper documentation available anywhere? I never found proper documentation, but I didn't look too hard. I've mostly been going off of Viet's comments and code. But FWIW, I did find some relevant info for the peculiar Altera EPCQ flash here: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cfg/cfg_cf52012.pdf Brian -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: Hi! [...] Hi Brian, It is really unfortunate that this controller is not able to read full JEDEC ID. It only can provide 1 byte ID. I did discuss with IP designer about this, but it is really unfortunate that they are not able to fix that issue. Hence it requires software to make changes. Thanks for CCing me, I assume this is a driver for that altera_epcq_controller which you can synthesise into your FPGA, is that correct? Is there an Hard IP variant of this controller in the public or is this purely Soft IP? Also, I cannot find any documentation for this IP block even if I search through Quartus/QSys, is there any proper documentation available anywhere? [...] Best regards, Marek Vasut -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Mon, Jul 27, 2015 at 03:10:23PM +0800, Viet Nga Dao wrote: On Sat, Jul 25, 2015 at 2:37 AM, Brian Norris computersforpe...@gmail.com wrote: On Wed, Jun 03, 2015 at 12:30:44AM -0700, vn...@altera.com wrote: From: VIET NGA DAO vn...@altera.com Altera Quad SPI Controller is a soft IP which enables access to Altera EPCS, EPCQ and Mircon flash chips. This patch adds driver for these devices. Signed-off-by: VIET NGA DAO vn...@altera.com --- v4: - Add more flash devices support ( EPCQL and Micron) ^^ Unfortunately, I think you've added yourself another burden with this one. Most of the rest actually is looking pretty good, so it's sad to see this hold your driver back. Comments below. FWIW, this comment still stands. I cannot take your patch as-is. - Remove redundant messages - Change EPCQ_OPCODE_ID to NON_EPCS_OPCODE_ID - Replace get_flash_name to altera_quadspi_scan - Remove clk related parts - Remove altera_quadspi_plat - Change device tree reg name and remove opcode-id v3: - Change altera_epcq driver name to altera_quadspi for more generic name - Implement flash name searching in altera_quadspi.c instead of spi-nor - Edit the altra quadspi info table in spi-nor - Remove wait_til_ready in all read,write, erase, lock, unlock functions - Merge .h and .c into 1 file v2: - Change to spi_nor structure - Add lock and unlock functions for spi_nor - Simplify the altera_epcq_lock function - Replace reg by compatible in device tree --- .../devicetree/bindings/mtd/altera-quadspi.txt | 49 ++ drivers/mtd/spi-nor/Kconfig|8 + drivers/mtd/spi-nor/Makefile |1 + drivers/mtd/spi-nor/altera-quadspi.c | 568 drivers/mtd/spi-nor/spi-nor.c | 30 + 5 files changed, 656 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/altera-quadspi.txt create mode 100644 drivers/mtd/spi-nor/altera-quadspi.c diff --git a/Documentation/devicetree/bindings/mtd/altera-quadspi.txt b/Documentation/devicetree/bindings/mtd/altera-quadspi.txt new file mode 100644 index 000..2873319 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/altera-quadspi.txt @@ -0,0 +1,49 @@ +* MTD Altera QUADSPI driver + +Required properties: +- compatible: Should be altr,quadspi-1.0 +- reg: Address and length of the register set for the device. It contains + the information of registers in the same order as described by reg-names +- reg-names: Should contain the reg names + avl_csr: Should contain the register configuration base address + avl_mem: Should contain the data base address +- #address-cells: Must be 1. +- #size-cells: Must be 0. +- flash device tree subnode, there must be a node with the following fields: + - compatible: Should contain the flash name: + 1. EPCS: epcs16, epcs64, epcs128 + 2. EPCQ: epcq16, epcq32, epcq64, epcq128, epcq256, epcq512, epcq1024 + 3. EPCQ-L: epcql256, epcql512, epcql1024 + 4. Mircon: n25q016-nonjedec, n25q032-nonjedec, n25q064-nonjedec, + n25q128a13-nonjedec, n25q128a11-nonjedec, n25q256a-nonjedec, + n25q256a11-nonjedec, n25q512a-nonjedec, n25q512ax3-nonjedec, + mt25ql512-nonjedec, n25q00-nonjedec, n25q00a11-nonjedec OK, so you're adding a bunch of Micron flashes which already have support via standard DT bindings and spi-nor library code, except now you're adding -nonjedec to all of them. You better have a *really* good reason for this. Are these flash not compatible with the JEDEC READ ID opcode, by which every other system identifies these parts? Or are you adding these names because of limitations in your controller? For the former, I might be able to understand the need, but for the latter, I'm much disinclined to support this. There's got to be a better way. Hi Brian, It is really unfortunate that this controller is not able to read full JEDEC ID. It only can provide 1 byte ID. I did discuss with IP designer about this, but it is really unfortunate that they are not able to fix that issue. Hence it requires software to make changes. Wow, what a joke. (Please quote me to your IP designer.) In any case, there's no way I'm going to support a ton of new *-nonjedec strings just to support your completely broken controller. These aren't actually nonjedec flash devices, and AFAICT, there's absolutely nothing wrong with the flash that requires this description. It's purely your controller's fault. Thus, I'm not changing the DT binding for all the flash you want to use. Instead, I think we need to assume that your controller is completely incapable of identifying the flash that's attached to it, and instead just rely on specifying this entirely in the device tree. Then, we need a flag for your
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
Thanks Brian for your reply!
On Sat, Jul 25, 2015 at 2:37 AM, Brian Norris
wrote:
> On Wed, Jun 03, 2015 at 12:30:44AM -0700, vn...@altera.com wrote:
>> From: VIET NGA DAO
>>
>> Altera Quad SPI Controller is a soft IP which enables access to
>> Altera EPCS, EPCQ and Mircon flash chips. This patch adds driver
>> for these devices.
>>
>> Signed-off-by: VIET NGA DAO
>>
>> ---
>> v4:
>> - Add more flash devices support ( EPCQL and Micron)
>
> ^^ Unfortunately, I think you've added yourself another burden with this
> one. Most of the rest actually is looking pretty good, so it's sad to
> see this hold your driver back. Comments below.
>
>> - Remove redundant messages
>> - Change EPCQ_OPCODE_ID to NON_EPCS_OPCODE_ID
>> - Replace get_flash_name to altera_quadspi_scan
>> - Remove clk related parts
>> - Remove altera_quadspi_plat
>> - Change device tree reg name and remove opcode-id
>>
>> v3:
>> - Change altera_epcq driver name to altera_quadspi for more generic name
>> - Implement flash name searching in altera_quadspi.c instead of spi-nor
>> - Edit the altra quadspi info table in spi-nor
>> - Remove wait_til_ready in all read,write, erase, lock, unlock functions
>> - Merge .h and .c into 1 file
>>
>> v2:
>> - Change to spi_nor structure
>> - Add lock and unlock functions for spi_nor
>> - Simplify the altera_epcq_lock function
>> - Replace reg by compatible in device tree
>> ---
>> .../devicetree/bindings/mtd/altera-quadspi.txt | 49 ++
>> drivers/mtd/spi-nor/Kconfig|8 +
>> drivers/mtd/spi-nor/Makefile |1 +
>> drivers/mtd/spi-nor/altera-quadspi.c | 568
>>
>> drivers/mtd/spi-nor/spi-nor.c | 30 +
>> 5 files changed, 656 insertions(+), 0 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/mtd/altera-quadspi.txt
>> create mode 100644 drivers/mtd/spi-nor/altera-quadspi.c
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/altera-quadspi.txt
>> b/Documentation/devicetree/bindings/mtd/altera-quadspi.txt
>> new file mode 100644
>> index 000..2873319
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mtd/altera-quadspi.txt
>> @@ -0,0 +1,49 @@
>> +* MTD Altera QUADSPI driver
>> +
>> +Required properties:
>> +- compatible: Should be "altr,quadspi-1.0"
>> +- reg: Address and length of the register set for the device. It contains
>> + the information of registers in the same order as described by reg-names
>> +- reg-names: Should contain the reg names
>> + "avl_csr": Should contain the register configuration base address
>> + "avl_mem": Should contain the data base address
>> +- #address-cells: Must be <1>.
>> +- #size-cells: Must be <0>.
>> +- flash device tree subnode, there must be a node with the following fields:
>> + - compatible: Should contain the flash name:
>> + 1. EPCS: epcs16, epcs64, epcs128
>> + 2. EPCQ: epcq16, epcq32, epcq64, epcq128, epcq256, epcq512,
>> epcq1024
>> + 3. EPCQ-L: epcql256, epcql512, epcql1024
>> + 4. Mircon: n25q016-nonjedec, n25q032-nonjedec, n25q064-nonjedec,
>> + n25q128a13-nonjedec, n25q128a11-nonjedec,
>> n25q256a-nonjedec,
>> + n25q256a11-nonjedec, n25q512a-nonjedec,
>> n25q512ax3-nonjedec,
>> + mt25ql512-nonjedec, n25q00-nonjedec, n25q00a11-nonjedec
>
> OK, so you're adding a bunch of Micron flashes which already have
> support via standard DT bindings and spi-nor library code, except now
> you're adding "-nonjedec" to all of them. You better have a *really*
> good reason for this. Are these flash not compatible with the JEDEC READ
> ID opcode, by which every other system identifies these parts? Or are
> you adding these names because of limitations in your controller? For
> the former, I might be able to understand the need, but for the latter,
> I'm much disinclined to support this. There's got to be a better way.
>
Hi Brian,
It is really unfortunate that this controller is not able to read full
JEDEC ID. It only can provide 1 byte ID. I did discuss with IP
designer about this, but it is really unfortunate that they are not
able to fix that issue. Hence it requires software to make changes.
>> + - #address-cells: please refer to /mtd/partition.txt
>> + - #size-cells: please refer to /mtd/partition.txt
>> + For partitions inside each flash, please refer to /mtd/partition.txt
>> +
>> +Example:
>> +
>> + quadspi_controller_0: quadspi@0x180014a0 {
>> + compatible = "altr,quadspi-1.0";
>> + reg = <0x180014a0 0x0020>,
>> + <0x1400 0x0400>;
>> + reg-names = "avl_csr", "avl_mem";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + flash0: epcq256@0 {
>> +
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
Thanks Brian for your reply!
On Sat, Jul 25, 2015 at 2:37 AM, Brian Norris
computersforpe...@gmail.com wrote:
On Wed, Jun 03, 2015 at 12:30:44AM -0700, vn...@altera.com wrote:
From: VIET NGA DAO vn...@altera.com
Altera Quad SPI Controller is a soft IP which enables access to
Altera EPCS, EPCQ and Mircon flash chips. This patch adds driver
for these devices.
Signed-off-by: VIET NGA DAO vn...@altera.com
---
v4:
- Add more flash devices support ( EPCQL and Micron)
^^ Unfortunately, I think you've added yourself another burden with this
one. Most of the rest actually is looking pretty good, so it's sad to
see this hold your driver back. Comments below.
- Remove redundant messages
- Change EPCQ_OPCODE_ID to NON_EPCS_OPCODE_ID
- Replace get_flash_name to altera_quadspi_scan
- Remove clk related parts
- Remove altera_quadspi_plat
- Change device tree reg name and remove opcode-id
v3:
- Change altera_epcq driver name to altera_quadspi for more generic name
- Implement flash name searching in altera_quadspi.c instead of spi-nor
- Edit the altra quadspi info table in spi-nor
- Remove wait_til_ready in all read,write, erase, lock, unlock functions
- Merge .h and .c into 1 file
v2:
- Change to spi_nor structure
- Add lock and unlock functions for spi_nor
- Simplify the altera_epcq_lock function
- Replace reg by compatible in device tree
---
.../devicetree/bindings/mtd/altera-quadspi.txt | 49 ++
drivers/mtd/spi-nor/Kconfig|8 +
drivers/mtd/spi-nor/Makefile |1 +
drivers/mtd/spi-nor/altera-quadspi.c | 568
drivers/mtd/spi-nor/spi-nor.c | 30 +
5 files changed, 656 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/altera-quadspi.txt
create mode 100644 drivers/mtd/spi-nor/altera-quadspi.c
diff --git a/Documentation/devicetree/bindings/mtd/altera-quadspi.txt
b/Documentation/devicetree/bindings/mtd/altera-quadspi.txt
new file mode 100644
index 000..2873319
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/altera-quadspi.txt
@@ -0,0 +1,49 @@
+* MTD Altera QUADSPI driver
+
+Required properties:
+- compatible: Should be altr,quadspi-1.0
+- reg: Address and length of the register set for the device. It contains
+ the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+ avl_csr: Should contain the register configuration base address
+ avl_mem: Should contain the data base address
+- #address-cells: Must be 1.
+- #size-cells: Must be 0.
+- flash device tree subnode, there must be a node with the following fields:
+ - compatible: Should contain the flash name:
+ 1. EPCS: epcs16, epcs64, epcs128
+ 2. EPCQ: epcq16, epcq32, epcq64, epcq128, epcq256, epcq512,
epcq1024
+ 3. EPCQ-L: epcql256, epcql512, epcql1024
+ 4. Mircon: n25q016-nonjedec, n25q032-nonjedec, n25q064-nonjedec,
+ n25q128a13-nonjedec, n25q128a11-nonjedec,
n25q256a-nonjedec,
+ n25q256a11-nonjedec, n25q512a-nonjedec,
n25q512ax3-nonjedec,
+ mt25ql512-nonjedec, n25q00-nonjedec, n25q00a11-nonjedec
OK, so you're adding a bunch of Micron flashes which already have
support via standard DT bindings and spi-nor library code, except now
you're adding -nonjedec to all of them. You better have a *really*
good reason for this. Are these flash not compatible with the JEDEC READ
ID opcode, by which every other system identifies these parts? Or are
you adding these names because of limitations in your controller? For
the former, I might be able to understand the need, but for the latter,
I'm much disinclined to support this. There's got to be a better way.
Hi Brian,
It is really unfortunate that this controller is not able to read full
JEDEC ID. It only can provide 1 byte ID. I did discuss with IP
designer about this, but it is really unfortunate that they are not
able to fix that issue. Hence it requires software to make changes.
+ - #address-cells: please refer to /mtd/partition.txt
+ - #size-cells: please refer to /mtd/partition.txt
+ For partitions inside each flash, please refer to /mtd/partition.txt
+
+Example:
+
+ quadspi_controller_0: quadspi@0x180014a0 {
+ compatible = altr,quadspi-1.0;
+ reg = 0x180014a0 0x0020,
+ 0x1400 0x0400;
+ reg-names = avl_csr, avl_mem;
+ #address-cells = 1;
+ #size-cells = 0;
+ flash0: epcq256@0 {
+ compatible = altr,epcq256;
+ #address-cells = 1;
+ #size-cells = 1;
+
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Wed, Jun 03, 2015 at 12:30:44AM -0700, vn...@altera.com wrote:
> From: VIET NGA DAO
>
> Altera Quad SPI Controller is a soft IP which enables access to
> Altera EPCS, EPCQ and Mircon flash chips. This patch adds driver
> for these devices.
>
> Signed-off-by: VIET NGA DAO
>
> ---
> v4:
> - Add more flash devices support ( EPCQL and Micron)
^^ Unfortunately, I think you've added yourself another burden with this
one. Most of the rest actually is looking pretty good, so it's sad to
see this hold your driver back. Comments below.
> - Remove redundant messages
> - Change EPCQ_OPCODE_ID to NON_EPCS_OPCODE_ID
> - Replace get_flash_name to altera_quadspi_scan
> - Remove clk related parts
> - Remove altera_quadspi_plat
> - Change device tree reg name and remove opcode-id
>
> v3:
> - Change altera_epcq driver name to altera_quadspi for more generic name
> - Implement flash name searching in altera_quadspi.c instead of spi-nor
> - Edit the altra quadspi info table in spi-nor
> - Remove wait_til_ready in all read,write, erase, lock, unlock functions
> - Merge .h and .c into 1 file
>
> v2:
> - Change to spi_nor structure
> - Add lock and unlock functions for spi_nor
> - Simplify the altera_epcq_lock function
> - Replace reg by compatible in device tree
> ---
> .../devicetree/bindings/mtd/altera-quadspi.txt | 49 ++
> drivers/mtd/spi-nor/Kconfig|8 +
> drivers/mtd/spi-nor/Makefile |1 +
> drivers/mtd/spi-nor/altera-quadspi.c | 568
>
> drivers/mtd/spi-nor/spi-nor.c | 30 +
> 5 files changed, 656 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mtd/altera-quadspi.txt
> create mode 100644 drivers/mtd/spi-nor/altera-quadspi.c
>
> diff --git a/Documentation/devicetree/bindings/mtd/altera-quadspi.txt
> b/Documentation/devicetree/bindings/mtd/altera-quadspi.txt
> new file mode 100644
> index 000..2873319
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/altera-quadspi.txt
> @@ -0,0 +1,49 @@
> +* MTD Altera QUADSPI driver
> +
> +Required properties:
> +- compatible: Should be "altr,quadspi-1.0"
> +- reg: Address and length of the register set for the device. It contains
> + the information of registers in the same order as described by reg-names
> +- reg-names: Should contain the reg names
> + "avl_csr": Should contain the register configuration base address
> + "avl_mem": Should contain the data base address
> +- #address-cells: Must be <1>.
> +- #size-cells: Must be <0>.
> +- flash device tree subnode, there must be a node with the following fields:
> + - compatible: Should contain the flash name:
> + 1. EPCS: epcs16, epcs64, epcs128
> + 2. EPCQ: epcq16, epcq32, epcq64, epcq128, epcq256, epcq512, epcq1024
> + 3. EPCQ-L: epcql256, epcql512, epcql1024
> + 4. Mircon: n25q016-nonjedec, n25q032-nonjedec, n25q064-nonjedec,
> + n25q128a13-nonjedec, n25q128a11-nonjedec,
> n25q256a-nonjedec,
> + n25q256a11-nonjedec, n25q512a-nonjedec,
> n25q512ax3-nonjedec,
> + mt25ql512-nonjedec, n25q00-nonjedec, n25q00a11-nonjedec
OK, so you're adding a bunch of Micron flashes which already have
support via standard DT bindings and spi-nor library code, except now
you're adding "-nonjedec" to all of them. You better have a *really*
good reason for this. Are these flash not compatible with the JEDEC READ
ID opcode, by which every other system identifies these parts? Or are
you adding these names because of limitations in your controller? For
the former, I might be able to understand the need, but for the latter,
I'm much disinclined to support this. There's got to be a better way.
> + - #address-cells: please refer to /mtd/partition.txt
> + - #size-cells: please refer to /mtd/partition.txt
> + For partitions inside each flash, please refer to /mtd/partition.txt
> +
> +Example:
> +
> + quadspi_controller_0: quadspi@0x180014a0 {
> + compatible = "altr,quadspi-1.0";
> + reg = <0x180014a0 0x0020>,
> + <0x1400 0x0400>;
> + reg-names = "avl_csr", "avl_mem";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + flash0: epcq256@0 {
> + compatible = "altr,epcq256";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + partition@0 {
> + /* 16 MB for raw data. */
> + label = "EPCQ Flash 0 raw data";
> + reg = <0x0 0x100>;
> + };
> +
Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver
On Wed, Jun 03, 2015 at 12:30:44AM -0700, vn...@altera.com wrote:
From: VIET NGA DAO vn...@altera.com
Altera Quad SPI Controller is a soft IP which enables access to
Altera EPCS, EPCQ and Mircon flash chips. This patch adds driver
for these devices.
Signed-off-by: VIET NGA DAO vn...@altera.com
---
v4:
- Add more flash devices support ( EPCQL and Micron)
^^ Unfortunately, I think you've added yourself another burden with this
one. Most of the rest actually is looking pretty good, so it's sad to
see this hold your driver back. Comments below.
- Remove redundant messages
- Change EPCQ_OPCODE_ID to NON_EPCS_OPCODE_ID
- Replace get_flash_name to altera_quadspi_scan
- Remove clk related parts
- Remove altera_quadspi_plat
- Change device tree reg name and remove opcode-id
v3:
- Change altera_epcq driver name to altera_quadspi for more generic name
- Implement flash name searching in altera_quadspi.c instead of spi-nor
- Edit the altra quadspi info table in spi-nor
- Remove wait_til_ready in all read,write, erase, lock, unlock functions
- Merge .h and .c into 1 file
v2:
- Change to spi_nor structure
- Add lock and unlock functions for spi_nor
- Simplify the altera_epcq_lock function
- Replace reg by compatible in device tree
---
.../devicetree/bindings/mtd/altera-quadspi.txt | 49 ++
drivers/mtd/spi-nor/Kconfig|8 +
drivers/mtd/spi-nor/Makefile |1 +
drivers/mtd/spi-nor/altera-quadspi.c | 568
drivers/mtd/spi-nor/spi-nor.c | 30 +
5 files changed, 656 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/altera-quadspi.txt
create mode 100644 drivers/mtd/spi-nor/altera-quadspi.c
diff --git a/Documentation/devicetree/bindings/mtd/altera-quadspi.txt
b/Documentation/devicetree/bindings/mtd/altera-quadspi.txt
new file mode 100644
index 000..2873319
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/altera-quadspi.txt
@@ -0,0 +1,49 @@
+* MTD Altera QUADSPI driver
+
+Required properties:
+- compatible: Should be altr,quadspi-1.0
+- reg: Address and length of the register set for the device. It contains
+ the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+ avl_csr: Should contain the register configuration base address
+ avl_mem: Should contain the data base address
+- #address-cells: Must be 1.
+- #size-cells: Must be 0.
+- flash device tree subnode, there must be a node with the following fields:
+ - compatible: Should contain the flash name:
+ 1. EPCS: epcs16, epcs64, epcs128
+ 2. EPCQ: epcq16, epcq32, epcq64, epcq128, epcq256, epcq512, epcq1024
+ 3. EPCQ-L: epcql256, epcql512, epcql1024
+ 4. Mircon: n25q016-nonjedec, n25q032-nonjedec, n25q064-nonjedec,
+ n25q128a13-nonjedec, n25q128a11-nonjedec,
n25q256a-nonjedec,
+ n25q256a11-nonjedec, n25q512a-nonjedec,
n25q512ax3-nonjedec,
+ mt25ql512-nonjedec, n25q00-nonjedec, n25q00a11-nonjedec
OK, so you're adding a bunch of Micron flashes which already have
support via standard DT bindings and spi-nor library code, except now
you're adding -nonjedec to all of them. You better have a *really*
good reason for this. Are these flash not compatible with the JEDEC READ
ID opcode, by which every other system identifies these parts? Or are
you adding these names because of limitations in your controller? For
the former, I might be able to understand the need, but for the latter,
I'm much disinclined to support this. There's got to be a better way.
+ - #address-cells: please refer to /mtd/partition.txt
+ - #size-cells: please refer to /mtd/partition.txt
+ For partitions inside each flash, please refer to /mtd/partition.txt
+
+Example:
+
+ quadspi_controller_0: quadspi@0x180014a0 {
+ compatible = altr,quadspi-1.0;
+ reg = 0x180014a0 0x0020,
+ 0x1400 0x0400;
+ reg-names = avl_csr, avl_mem;
+ #address-cells = 1;
+ #size-cells = 0;
+ flash0: epcq256@0 {
+ compatible = altr,epcq256;
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ /* 16 MB for raw data. */
+ label = EPCQ Flash 0 raw data;
+ reg = 0x0 0x100;
+ };
+ partition@100 {
+
