Re: [PATCH 01/31] perf, x86: Add PEBSv2 record support
On Fri, Sep 28, 2012 at 10:43:04AM +0200, Peter Zijlstra wrote:
> On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
> > + if (event->attr.precise_ip > 1 &&
> > x86_pmu.intel_cap.pebs_format < 2) {
>
> Shouldn't that be: && x86_pmu.intel_cap.pebs_trap, like most other sites
> instead? Or didn't they flip the trap capability on Haswell?
In theory you're right, but trap wouldn't work for TSX aborts. Even if PEBS
was a trap (it isn't) the trap would abort. Looking at the stack frame I
would get the wrong IP after the abort, not the abort event itself.
So to do the trap check would need to explicitely check for TSX abort
events too, which would be possible but fairly ugly.
If the flag ever changes could revisit this but I don't see it right
now. Also when available there's no good reason not to use EventingRip.
-andi
--
a...@linux.intel.com -- Speaking for myself only.
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Re: [PATCH 01/31] perf, x86: Add PEBSv2 record support
On Fri, Sep 28, 2012 at 11:28 AM, Peter Zijlstra wrote:
> On Fri, 2012-09-28 at 10:54 +0200, Stephane Eranian wrote:
>> On Fri, Sep 28, 2012 at 10:43 AM, Peter Zijlstra
>> wrote:
>> > On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
>> >> + if (event->attr.precise_ip > 1 &&
>> >> x86_pmu.intel_cap.pebs_format < 2) {
>> >
>> > Shouldn't that be: && x86_pmu.intel_cap.pebs_trap, like most other sites
>> > instead? Or didn't they flip the trap capability on Haswell?
>>
>> On Haswell, you get the event_ip which points to the sampled
>> instruction, i.e., the off-by-one
>> error can be avoided by using that value instead of pebs.rip. The nice
>> side effect is that you
>> free the LBR and minimize the overhead (no fixups). Therfore the LBR
>> filter can have any
>> setting when combined with PEBS, thus we do not need to check for
>> compatibility nor force
>> any setting for the LBR filter.
>
> Yes I got that, but what good is that trap capability flag if they don't
> use it? Them adding a second u64 to the format to report it seems to
> suggest their trap capability is pointless, but nowhere has this been
> explained.
I suspect this trap field was only meaningful for P4. Since then, the
implementation has changed and I don't think this flag is relevant anymore.
To be cautious, you could always or this (pebs_fmt > 1 || trap).
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Re: [PATCH 01/31] perf, x86: Add PEBSv2 record support
On Fri, 2012-09-28 at 10:54 +0200, Stephane Eranian wrote:
> On Fri, Sep 28, 2012 at 10:43 AM, Peter Zijlstra
> wrote:
> > On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
> >> + if (event->attr.precise_ip > 1 &&
> >> x86_pmu.intel_cap.pebs_format < 2) {
> >
> > Shouldn't that be: && x86_pmu.intel_cap.pebs_trap, like most other sites
> > instead? Or didn't they flip the trap capability on Haswell?
>
> On Haswell, you get the event_ip which points to the sampled
> instruction, i.e., the off-by-one
> error can be avoided by using that value instead of pebs.rip. The nice
> side effect is that you
> free the LBR and minimize the overhead (no fixups). Therfore the LBR
> filter can have any
> setting when combined with PEBS, thus we do not need to check for
> compatibility nor force
> any setting for the LBR filter.
Yes I got that, but what good is that trap capability flag if they don't
use it? Them adding a second u64 to the format to report it seems to
suggest their trap capability is pointless, but nowhere has this been
explained.
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 01/31] perf, x86: Add PEBSv2 record support
On Fri, Sep 28, 2012 at 10:43 AM, Peter Zijlstra wrote:
> On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
>> + if (event->attr.precise_ip > 1 &&
>> x86_pmu.intel_cap.pebs_format < 2) {
>
> Shouldn't that be: && x86_pmu.intel_cap.pebs_trap, like most other sites
> instead? Or didn't they flip the trap capability on Haswell?
On Haswell, you get the event_ip which points to the sampled
instruction, i.e., the off-by-one
error can be avoided by using that value instead of pebs.rip. The nice
side effect is that you
free the LBR and minimize the overhead (no fixups). Therfore the LBR
filter can have any
setting when combined with PEBS, thus we do not need to check for
compatibility nor force
any setting for the LBR filter.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 01/31] perf, x86: Add PEBSv2 record support
On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
> + if (event->attr.precise_ip > 1 &&
> x86_pmu.intel_cap.pebs_format < 2) {
Shouldn't that be: && x86_pmu.intel_cap.pebs_trap, like most other sites
instead? Or didn't they flip the trap capability on Haswell?
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 01/31] perf, x86: Add PEBSv2 record support
On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
+ if (event-attr.precise_ip 1
x86_pmu.intel_cap.pebs_format 2) {
Shouldn't that be: x86_pmu.intel_cap.pebs_trap, like most other sites
instead? Or didn't they flip the trap capability on Haswell?
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 01/31] perf, x86: Add PEBSv2 record support
On Fri, Sep 28, 2012 at 10:43 AM, Peter Zijlstra a.p.zijls...@chello.nl wrote:
On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
+ if (event-attr.precise_ip 1
x86_pmu.intel_cap.pebs_format 2) {
Shouldn't that be: x86_pmu.intel_cap.pebs_trap, like most other sites
instead? Or didn't they flip the trap capability on Haswell?
On Haswell, you get the event_ip which points to the sampled
instruction, i.e., the off-by-one
error can be avoided by using that value instead of pebs.rip. The nice
side effect is that you
free the LBR and minimize the overhead (no fixups). Therfore the LBR
filter can have any
setting when combined with PEBS, thus we do not need to check for
compatibility nor force
any setting for the LBR filter.
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 01/31] perf, x86: Add PEBSv2 record support
On Fri, 2012-09-28 at 10:54 +0200, Stephane Eranian wrote:
On Fri, Sep 28, 2012 at 10:43 AM, Peter Zijlstra a.p.zijls...@chello.nl
wrote:
On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
+ if (event-attr.precise_ip 1
x86_pmu.intel_cap.pebs_format 2) {
Shouldn't that be: x86_pmu.intel_cap.pebs_trap, like most other sites
instead? Or didn't they flip the trap capability on Haswell?
On Haswell, you get the event_ip which points to the sampled
instruction, i.e., the off-by-one
error can be avoided by using that value instead of pebs.rip. The nice
side effect is that you
free the LBR and minimize the overhead (no fixups). Therfore the LBR
filter can have any
setting when combined with PEBS, thus we do not need to check for
compatibility nor force
any setting for the LBR filter.
Yes I got that, but what good is that trap capability flag if they don't
use it? Them adding a second u64 to the format to report it seems to
suggest their trap capability is pointless, but nowhere has this been
explained.
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 01/31] perf, x86: Add PEBSv2 record support
On Fri, Sep 28, 2012 at 11:28 AM, Peter Zijlstra a.p.zijls...@chello.nl wrote:
On Fri, 2012-09-28 at 10:54 +0200, Stephane Eranian wrote:
On Fri, Sep 28, 2012 at 10:43 AM, Peter Zijlstra a.p.zijls...@chello.nl
wrote:
On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
+ if (event-attr.precise_ip 1
x86_pmu.intel_cap.pebs_format 2) {
Shouldn't that be: x86_pmu.intel_cap.pebs_trap, like most other sites
instead? Or didn't they flip the trap capability on Haswell?
On Haswell, you get the event_ip which points to the sampled
instruction, i.e., the off-by-one
error can be avoided by using that value instead of pebs.rip. The nice
side effect is that you
free the LBR and minimize the overhead (no fixups). Therfore the LBR
filter can have any
setting when combined with PEBS, thus we do not need to check for
compatibility nor force
any setting for the LBR filter.
Yes I got that, but what good is that trap capability flag if they don't
use it? Them adding a second u64 to the format to report it seems to
suggest their trap capability is pointless, but nowhere has this been
explained.
I suspect this trap field was only meaningful for P4. Since then, the
implementation has changed and I don't think this flag is relevant anymore.
To be cautious, you could always or this (pebs_fmt 1 || trap).
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 01/31] perf, x86: Add PEBSv2 record support
On Fri, Sep 28, 2012 at 10:43:04AM +0200, Peter Zijlstra wrote:
On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
+ if (event-attr.precise_ip 1
x86_pmu.intel_cap.pebs_format 2) {
Shouldn't that be: x86_pmu.intel_cap.pebs_trap, like most other sites
instead? Or didn't they flip the trap capability on Haswell?
In theory you're right, but trap wouldn't work for TSX aborts. Even if PEBS
was a trap (it isn't) the trap would abort. Looking at the stack frame I
would get the wrong IP after the abort, not the abort event itself.
So to do the trap check would need to explicitely check for TSX abort
events too, which would be possible but fairly ugly.
If the flag ever changes could revisit this but I don't see it right
now. Also when available there's no good reason not to use EventingRip.
-andi
--
a...@linux.intel.com -- Speaking for myself only.
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
