Re: [PATCH 1/2] mfd: cros_ec: spi: Fix end of transfer on devices with no spi-msg-delay
> cros_ec_spi makes the assumption that a 0-length message will put the
> spi chip select back to normal (non cs_toggle mode). This used to be
> the case back on kernel-3.8 on the spi-s3c64xx driver but doesn't
> appear to be true anymore. It seems like it was a pretty questionable
> assumption to begin with, so let's fix the code to be more robust. We
> know that a message with a single 0-length segment _will_ put things
> back in order. Change cros_ec_spi to handle this.
>
> This wasn't a problem on the main user of cros_ec_spi upstream (tegra)
> because it specified 'google,cros-ec-spi-msg-delay'.
>
> Signed-off-by: Doug Anderson
> ---
> drivers/mfd/cros_ec_spi.c | 18 +++---
> 1 file changed, 7 insertions(+), 11 deletions(-)
Looks fine to me and I'm sure you've tested this on your platform.
Applied, thanks.
> diff --git a/drivers/mfd/cros_ec_spi.c b/drivers/mfd/cros_ec_spi.c
> index 0b8d328..0cbc3db 100644
> --- a/drivers/mfd/cros_ec_spi.c
> +++ b/drivers/mfd/cros_ec_spi.c
> @@ -266,18 +266,14 @@ static int cros_ec_command_spi_xfer(struct
> cros_ec_device *ec_dev,
> dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
> }
>
> - /* turn off CS */
> + /*
> + * Turn off CS, possibly adding a delay to ensure the rising edge
> + * doesn't come too soon after the end of the data.
> + */
> spi_message_init();
> -
> - if (ec_spi->end_of_msg_delay) {
> - /*
> - * Add delay for last transaction, to ensure the rising edge
> - * doesn't come too soon after the end of the data.
> - */
> - memset(, 0, sizeof(trans));
> - trans.delay_usecs = ec_spi->end_of_msg_delay;
> - spi_message_add_tail(, );
> - }
> + memset(, 0, sizeof(trans));
> + trans.delay_usecs = ec_spi->end_of_msg_delay;
> + spi_message_add_tail(, );
>
> final_ret = spi_sync(ec_spi->spi, );
> ktime_get_ts();
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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Re: [PATCH 1/2] mfd: cros_ec: spi: Fix end of transfer on devices with no spi-msg-delay
cros_ec_spi makes the assumption that a 0-length message will put the
spi chip select back to normal (non cs_toggle mode). This used to be
the case back on kernel-3.8 on the spi-s3c64xx driver but doesn't
appear to be true anymore. It seems like it was a pretty questionable
assumption to begin with, so let's fix the code to be more robust. We
know that a message with a single 0-length segment _will_ put things
back in order. Change cros_ec_spi to handle this.
This wasn't a problem on the main user of cros_ec_spi upstream (tegra)
because it specified 'google,cros-ec-spi-msg-delay'.
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/mfd/cros_ec_spi.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
Looks fine to me and I'm sure you've tested this on your platform.
Applied, thanks.
diff --git a/drivers/mfd/cros_ec_spi.c b/drivers/mfd/cros_ec_spi.c
index 0b8d328..0cbc3db 100644
--- a/drivers/mfd/cros_ec_spi.c
+++ b/drivers/mfd/cros_ec_spi.c
@@ -266,18 +266,14 @@ static int cros_ec_command_spi_xfer(struct
cros_ec_device *ec_dev,
dev_err(ec_dev-dev, spi transfer failed: %d\n, ret);
}
- /* turn off CS */
+ /*
+ * Turn off CS, possibly adding a delay to ensure the rising edge
+ * doesn't come too soon after the end of the data.
+ */
spi_message_init(msg);
-
- if (ec_spi-end_of_msg_delay) {
- /*
- * Add delay for last transaction, to ensure the rising edge
- * doesn't come too soon after the end of the data.
- */
- memset(trans, 0, sizeof(trans));
- trans.delay_usecs = ec_spi-end_of_msg_delay;
- spi_message_add_tail(trans, msg);
- }
+ memset(trans, 0, sizeof(trans));
+ trans.delay_usecs = ec_spi-end_of_msg_delay;
+ spi_message_add_tail(trans, msg);
final_ret = spi_sync(ec_spi-spi, msg);
ktime_get_ts(ts);
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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Please read the FAQ at http://www.tux.org/lkml/
