Re: [PATCH 18/21] usb: chipidea: msm: Add reset controller for PHY POR bit

[Peter Chen]

On Sun, Jun 26, 2016 at 12:28:35AM -0700, Stephen Boyd wrote:
> The MSM chipidea wrapper has two bits that are used to reset the
> first or second phy. Add support for these bits via the reset
> controller framework, so that phy drivers can reset their
> hardware at the right time during initialization.
> 
> Cc: Peter Chen 
> Cc: Greg Kroah-Hartman 
> Signed-off-by: Stephen Boyd 
> ---
>  drivers/usb/chipidea/ci_hdrc_msm.c | 43 
> +-
>  1 file changed, 42 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/chipidea/ci_hdrc_msm.c 
> b/drivers/usb/chipidea/ci_hdrc_msm.c
> index fb4340f02c16..7d191928e55b 100644
> --- a/drivers/usb/chipidea/ci_hdrc_msm.c
> +++ b/drivers/usb/chipidea/ci_hdrc_msm.c
> @@ -14,14 +14,17 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  
>  #include "ci.h"
>  
>  #define HS_PHY_AHB_MODE  0x0098
> +#define HS_PHY_CTRL  0x0240
>  #define HS_PHY_SEC_CTRL  0x0278
>  # define HS_PHY_DIG_CLAMP_N  BIT(16)
> +# define HS_PHY_POR_ASSERT   BIT(0)
>  
>  #define HS_PHY_GENCONFIG 0x009c
>  # define HS_PHY_TXFIFO_IDLE_FORCE_DISBIT(4)
> @@ -38,11 +41,38 @@ struct ci_hdrc_msm {
>   struct clk *iface_clk;
>   struct extcon_dev *vbus_edev;
>   struct ci_hdrc_platform_data pdata;
> + struct reset_controller_dev rcdev;
>   bool secondary_phy;
>   bool hsic;
>   void __iomem *base;
>  };
>  
> +static int
> +ci_hdrc_msm_por_reset(struct reset_controller_dev *r, unsigned long id)
> +{
> + struct ci_hdrc_msm *ci_msm = container_of(r, struct ci_hdrc_msm, rcdev);
> + void __iomem *addr = ci_msm->base;

Like I mentioned at previous email, you can use vendor base for
0x200.

> + u32 val;
> +
> + if (id)
> + addr += HS_PHY_SEC_CTRL;
> + else
> + addr += HS_PHY_CTRL;
> +
> + val = readl_relaxed(addr);
> + val |= HS_PHY_POR_ASSERT;
> + writel_relaxed(val, addr);
> + udelay(12);
> + val &= ~HS_PHY_POR_ASSERT;
> + writel(val, addr);
> +
> + return 0;
> +}
> +
> +static const struct reset_control_ops ci_hdrc_msm_reset_ops = {
> + .reset = ci_hdrc_msm_por_reset,
> +};
> +
>  static void ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
>  {
>   struct device *dev = ci->dev->parent;
> @@ -176,13 +206,21 @@ static int ci_hdrc_msm_probe(struct platform_device 
> *pdev)
>   ci->vbus_edev = NULL;
>   }
>  
> + ci->rcdev.owner = THIS_MODULE;
> + ci->rcdev.ops = _hdrc_msm_reset_ops;
> + ci->rcdev.of_node = pdev->dev.of_node;
> + ci->rcdev.nr_resets = 2;
> + ret = reset_controller_register(>rcdev);
> + if (ret)
> + return ret;
> +
>   reset_control_assert(reset);
>   usleep_range(1, 12000);
>   reset_control_deassert(reset);
>  
>   ret = clk_prepare_enable(ci->core_clk);
>   if (ret)
> - return ret;
> + goto err_core;
>  
>   ret = clk_prepare_enable(ci->iface_clk);
>   if (ret)
> @@ -220,6 +258,8 @@ err_mux:
>   clk_disable_unprepare(ci->iface_clk);
>  err_iface:
>   clk_disable_unprepare(ci->core_clk);
> +err_core:
> + reset_controller_unregister(>rcdev);
>   return ret;
>  }
>  
> @@ -232,6 +272,7 @@ static int ci_hdrc_msm_remove(struct platform_device 
> *pdev)
>   ci_hdrc_remove_device(ci->ci);
>   clk_disable_unprepare(ci->iface_clk);
>   clk_disable_unprepare(ci->core_clk);
> + reset_controller_unregister(>rcdev);
>  
>   return 0;
>  }
> -- 
> 2.9.0.rc2.8.ga28705d
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 

Best Regards,
Peter Chen

Re: [PATCH 18/21] usb: chipidea: msm: Add reset controller for PHY POR bit

[Peter Chen]

On Sun, Jun 26, 2016 at 12:28:35AM -0700, Stephen Boyd wrote:
> The MSM chipidea wrapper has two bits that are used to reset the
> first or second phy. Add support for these bits via the reset
> controller framework, so that phy drivers can reset their
> hardware at the right time during initialization.
> 
> Cc: Peter Chen 
> Cc: Greg Kroah-Hartman 
> Signed-off-by: Stephen Boyd 
> ---
>  drivers/usb/chipidea/ci_hdrc_msm.c | 43 
> +-
>  1 file changed, 42 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/chipidea/ci_hdrc_msm.c 
> b/drivers/usb/chipidea/ci_hdrc_msm.c
> index fb4340f02c16..7d191928e55b 100644
> --- a/drivers/usb/chipidea/ci_hdrc_msm.c
> +++ b/drivers/usb/chipidea/ci_hdrc_msm.c
> @@ -14,14 +14,17 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  
>  #include "ci.h"
>  
>  #define HS_PHY_AHB_MODE  0x0098
> +#define HS_PHY_CTRL  0x0240
>  #define HS_PHY_SEC_CTRL  0x0278
>  # define HS_PHY_DIG_CLAMP_N  BIT(16)
> +# define HS_PHY_POR_ASSERT   BIT(0)
>  
>  #define HS_PHY_GENCONFIG 0x009c
>  # define HS_PHY_TXFIFO_IDLE_FORCE_DISBIT(4)
> @@ -38,11 +41,38 @@ struct ci_hdrc_msm {
>   struct clk *iface_clk;
>   struct extcon_dev *vbus_edev;
>   struct ci_hdrc_platform_data pdata;
> + struct reset_controller_dev rcdev;
>   bool secondary_phy;
>   bool hsic;
>   void __iomem *base;
>  };
>  
> +static int
> +ci_hdrc_msm_por_reset(struct reset_controller_dev *r, unsigned long id)
> +{
> + struct ci_hdrc_msm *ci_msm = container_of(r, struct ci_hdrc_msm, rcdev);
> + void __iomem *addr = ci_msm->base;

Like I mentioned at previous email, you can use vendor base for
0x200.

> + u32 val;
> +
> + if (id)
> + addr += HS_PHY_SEC_CTRL;
> + else
> + addr += HS_PHY_CTRL;
> +
> + val = readl_relaxed(addr);
> + val |= HS_PHY_POR_ASSERT;
> + writel_relaxed(val, addr);
> + udelay(12);
> + val &= ~HS_PHY_POR_ASSERT;
> + writel(val, addr);
> +
> + return 0;
> +}
> +
> +static const struct reset_control_ops ci_hdrc_msm_reset_ops = {
> + .reset = ci_hdrc_msm_por_reset,
> +};
> +
>  static void ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
>  {
>   struct device *dev = ci->dev->parent;
> @@ -176,13 +206,21 @@ static int ci_hdrc_msm_probe(struct platform_device 
> *pdev)
>   ci->vbus_edev = NULL;
>   }
>  
> + ci->rcdev.owner = THIS_MODULE;
> + ci->rcdev.ops = _hdrc_msm_reset_ops;
> + ci->rcdev.of_node = pdev->dev.of_node;
> + ci->rcdev.nr_resets = 2;
> + ret = reset_controller_register(>rcdev);
> + if (ret)
> + return ret;
> +
>   reset_control_assert(reset);
>   usleep_range(1, 12000);
>   reset_control_deassert(reset);
>  
>   ret = clk_prepare_enable(ci->core_clk);
>   if (ret)
> - return ret;
> + goto err_core;
>  
>   ret = clk_prepare_enable(ci->iface_clk);
>   if (ret)
> @@ -220,6 +258,8 @@ err_mux:
>   clk_disable_unprepare(ci->iface_clk);
>  err_iface:
>   clk_disable_unprepare(ci->core_clk);
> +err_core:
> + reset_controller_unregister(>rcdev);
>   return ret;
>  }
>  
> @@ -232,6 +272,7 @@ static int ci_hdrc_msm_remove(struct platform_device 
> *pdev)
>   ci_hdrc_remove_device(ci->ci);
>   clk_disable_unprepare(ci->iface_clk);
>   clk_disable_unprepare(ci->core_clk);
> + reset_controller_unregister(>rcdev);
>  
>   return 0;
>  }
> -- 
> 2.9.0.rc2.8.ga28705d
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 

Best Regards,
Peter Chen

Re: [PATCH 18/21] usb: chipidea: msm: Add reset controller for PHY POR bit

[kbuild test robot]

Hi,

[auto build test ERROR on peter.chen-usb/ci-for-usb-next]
[also build test ERROR on v4.7-rc5 next-20160624]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Stephen-Boyd/Support-qcom-s-HSIC-USB-and-rewrite-USB2-HS-phy-support/20160627-102637
base:   https://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/usb 
ci-for-usb-next
config: x86_64-randconfig-s5-06271251 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-1) 6.1.1 20160430
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All errors (new ones prefixed by >>):

>> ERROR: "reset_controller_unregister" [drivers/usb/chipidea/ci_hdrc_msm.ko] 
>> undefined!

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: Binary data

Re: [PATCH 18/21] usb: chipidea: msm: Add reset controller for PHY POR bit

[kbuild test robot]

Hi,

[auto build test ERROR on peter.chen-usb/ci-for-usb-next]
[also build test ERROR on v4.7-rc5 next-20160624]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Stephen-Boyd/Support-qcom-s-HSIC-USB-and-rewrite-USB2-HS-phy-support/20160627-102637
base:   https://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/usb 
ci-for-usb-next
config: x86_64-randconfig-s5-06271251 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-1) 6.1.1 20160430
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All errors (new ones prefixed by >>):

>> ERROR: "reset_controller_unregister" [drivers/usb/chipidea/ci_hdrc_msm.ko] 
>> undefined!

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: Binary data

Re: [PATCH 18/21] usb: chipidea: msm: Add reset controller for PHY POR bit

[kbuild test robot]

Hi,

[auto build test ERROR on peter.chen-usb/ci-for-usb-next]
[also build test ERROR on v4.7-rc5 next-20160624]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Stephen-Boyd/Support-qcom-s-HSIC-USB-and-rewrite-USB2-HS-phy-support/20160627-102637
base:   https://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/usb 
ci-for-usb-next
config: arm-multi_v5_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.3.1-8) 5.3.1 20160205
reproduce:
wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm 

All errors (new ones prefixed by >>):

   drivers/built-in.o: In function `ci_hdrc_msm_remove':
>> drivers/usb/chipidea/ci_hdrc_msm.c:275: undefined reference to 
>> `reset_controller_unregister'

vim +275 drivers/usb/chipidea/ci_hdrc_msm.c

   269  
   270  pm_runtime_put(>dev);
   271  pm_runtime_disable(>dev);
   272  ci_hdrc_remove_device(ci->ci);
   273  clk_disable_unprepare(ci->iface_clk);
   274  clk_disable_unprepare(ci->core_clk);
 > 275  reset_controller_unregister(>rcdev);
   276  
   277  return 0;
   278  }

---
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.config.gz
Description: Binary data

Re: [PATCH 18/21] usb: chipidea: msm: Add reset controller for PHY POR bit

[kbuild test robot]

Hi,

[auto build test ERROR on peter.chen-usb/ci-for-usb-next]
[also build test ERROR on v4.7-rc5 next-20160624]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Stephen-Boyd/Support-qcom-s-HSIC-USB-and-rewrite-USB2-HS-phy-support/20160627-102637
base:   https://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/usb 
ci-for-usb-next
config: arm-multi_v5_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.3.1-8) 5.3.1 20160205
reproduce:
wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm 

All errors (new ones prefixed by >>):

   drivers/built-in.o: In function `ci_hdrc_msm_remove':
>> drivers/usb/chipidea/ci_hdrc_msm.c:275: undefined reference to 
>> `reset_controller_unregister'

vim +275 drivers/usb/chipidea/ci_hdrc_msm.c

   269  
   270  pm_runtime_put(>dev);
   271  pm_runtime_disable(>dev);
   272  ci_hdrc_remove_device(ci->ci);
   273  clk_disable_unprepare(ci->iface_clk);
   274  clk_disable_unprepare(ci->core_clk);
 > 275  reset_controller_unregister(>rcdev);
   276  
   277  return 0;
   278  }

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: Binary data

Re: [PATCH 18/21] usb: chipidea: msm: Add reset controller for PHY POR bit

[kbuild test robot]

Hi,

[auto build test ERROR on peter.chen-usb/ci-for-usb-next]
[also build test ERROR on v4.7-rc5 next-20160624]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Stephen-Boyd/Support-qcom-s-HSIC-USB-and-rewrite-USB2-HS-phy-support/20160627-102637
base:   https://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/usb 
ci-for-usb-next
config: x86_64-acpi-redef (attached as .config)
compiler: gcc-6 (Debian 6.1.1-1) 6.1.1 20160430
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/built-in.o: In function `ci_hdrc_msm_remove':
>> ci_hdrc_msm.c:(.text+0x4fffd2): undefined reference to 
>> `reset_controller_unregister'

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: Binary data

Re: [PATCH 18/21] usb: chipidea: msm: Add reset controller for PHY POR bit

[kbuild test robot]

Hi,

[auto build test ERROR on peter.chen-usb/ci-for-usb-next]
[also build test ERROR on v4.7-rc5 next-20160624]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Stephen-Boyd/Support-qcom-s-HSIC-USB-and-rewrite-USB2-HS-phy-support/20160627-102637
base:   https://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/usb 
ci-for-usb-next
config: x86_64-acpi-redef (attached as .config)
compiler: gcc-6 (Debian 6.1.1-1) 6.1.1 20160430
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/built-in.o: In function `ci_hdrc_msm_remove':
>> ci_hdrc_msm.c:(.text+0x4fffd2): undefined reference to 
>> `reset_controller_unregister'

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: Binary data