Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access v2
On Tue, Apr 25, 2017 at 12:22 PM, Christian König
wrote:
> Am 25.04.2017 um 17:14 schrieb Alex Deucher:
>>
>> On Tue, Apr 25, 2017 at 11:09 AM, Christian König
>> wrote:
>>>
>>> Am 25.04.2017 um 16:34 schrieb Alex Deucher:
On Tue, Apr 25, 2017 at 9:19 AM, Christian König
wrote:
>
> From: Christian König
>
> Try to resize BAR0 to let CPU access all of VRAM.
>
> v2: rebased, style cleanups, disable mem decode before resize,
> handle gmc_v9 as well, round size up to power of two.
>
> Signed-off-by: Christian König
> ---
>drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
>drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 37
> ++
>drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 ---
>drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 ---
>drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10
>5 files changed, 54 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 4a16e3c..9484062 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1879,6 +1879,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct
> amdgpu_device *adev, struct ttm_tt *ttm,
>struct ttm_mem_reg *mem);
>void amdgpu_vram_location(struct amdgpu_device *adev, struct
> amdgpu_mc
> *mc, u64 base);
>void amdgpu_gtt_location(struct amdgpu_device *adev, struct
> amdgpu_mc
> *mc);
> +void amdgpu_resize_bar0(struct amdgpu_device *adev);
>void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64
> size);
>int amdgpu_ttm_init(struct amdgpu_device *adev);
>void amdgpu_ttm_fini(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index a09ad3cf..d5ca77a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -695,6 +695,43 @@ void amdgpu_gtt_location(struct amdgpu_device
> *adev,
> struct amdgpu_mc *mc)
> mc->gtt_size >> 20, mc->gtt_start,
> mc->gtt_end);
>}
>
> +/**
> + * amdgpu_resize_bar0 - try to resize BAR0
> + *
> + * @adev: amdgpu_device pointer
> + *
> + * Try to resize BAR0 to make all VRAM CPU accessible.
> + */
> +void amdgpu_resize_bar0(struct amdgpu_device *adev)
I'd suggest renaming this to amdgpu_device_resize_bar() to try and
impose some consistency in this file, but not a big deal either way.
> +{
> + u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size);
> + u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) -1;
> + u16 cmd;
> + int r;
> +
> + /* Free the doorbell mapping, it most likely needs to move as
> well */
> + amdgpu_doorbell_fini(adev);
> + pci_release_resource(adev->pdev, 2);
This should check for if (adev->asic_type >= CHIP_BONAIRE) since SI
didn't have doorbells.
> +
> + /* Disable memory decoding while we change the BAR addresses
> and
> size */
> + pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
> + pci_write_config_word(adev->pdev, PCI_COMMAND,
> + cmd & ~PCI_COMMAND_MEMORY);
> +
> + r = pci_resize_resource(adev->pdev, 0, rbar_size);
> + if (r == -ENOSPC)
> + DRM_INFO("Not enough PCI address space for a large
> BAR.");
> + else if (r && r != -ENOTSUPP)
> + DRM_ERROR("Problem resizing BAR0 (%d).", r);
> +
> + pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
> +
> + /* When the doorbell BAR isn't available we have no chance of
> +* using the device.
> +*/
> + BUG_ON(amdgpu_doorbell_init(adev));
Same here.
> +}
> +
>/*
> * GPU helpers function.
> */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index a9083a1..ae71524 100644
What about SI (gmc_v6_0.c)?
>>>
>>>
>>> As far as I know there is no SI hardware with resizeable BAR support.
>>>
>>> The all VI generation can do this, but I'm not 100% sure if there aren't
>>> any
>>> Bonaires out there which can handle it as well that's why I added gmc_v7
>>> support.
>>>
>>> Still need to double check that.
>>
>> I think NI or even evergreen supported resizeable bars in theory,
>> although I'm not sure if any boards were fused to expose it.
>
>
> In theory yes, in practice no.
>
> Their PCIE config space defines the necessary registers, but I haven't found
> any board from
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access v2
Am 25.04.2017 um 17:14 schrieb Alex Deucher:
On Tue, Apr 25, 2017 at 11:09 AM, Christian König
wrote:
Am 25.04.2017 um 16:34 schrieb Alex Deucher:
On Tue, Apr 25, 2017 at 9:19 AM, Christian König
wrote:
From: Christian König
Try to resize BAR0 to let CPU access all of VRAM.
v2: rebased, style cleanups, disable mem decode before resize,
handle gmc_v9 as well, round size up to power of two.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 37
++
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 ---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 ---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10
5 files changed, 54 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4a16e3c..9484062 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1879,6 +1879,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct
amdgpu_device *adev, struct ttm_tt *ttm,
struct ttm_mem_reg *mem);
void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc
*mc, u64 base);
void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc
*mc);
+void amdgpu_resize_bar0(struct amdgpu_device *adev);
void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64
size);
int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a09ad3cf..d5ca77a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -695,6 +695,43 @@ void amdgpu_gtt_location(struct amdgpu_device *adev,
struct amdgpu_mc *mc)
mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
}
+/**
+ * amdgpu_resize_bar0 - try to resize BAR0
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Try to resize BAR0 to make all VRAM CPU accessible.
+ */
+void amdgpu_resize_bar0(struct amdgpu_device *adev)
I'd suggest renaming this to amdgpu_device_resize_bar() to try and
impose some consistency in this file, but not a big deal either way.
+{
+ u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size);
+ u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) -1;
+ u16 cmd;
+ int r;
+
+ /* Free the doorbell mapping, it most likely needs to move as
well */
+ amdgpu_doorbell_fini(adev);
+ pci_release_resource(adev->pdev, 2);
This should check for if (adev->asic_type >= CHIP_BONAIRE) since SI
didn't have doorbells.
+
+ /* Disable memory decoding while we change the BAR addresses and
size */
+ pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
+ pci_write_config_word(adev->pdev, PCI_COMMAND,
+ cmd & ~PCI_COMMAND_MEMORY);
+
+ r = pci_resize_resource(adev->pdev, 0, rbar_size);
+ if (r == -ENOSPC)
+ DRM_INFO("Not enough PCI address space for a large
BAR.");
+ else if (r && r != -ENOTSUPP)
+ DRM_ERROR("Problem resizing BAR0 (%d).", r);
+
+ pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
+
+ /* When the doorbell BAR isn't available we have no chance of
+* using the device.
+*/
+ BUG_ON(amdgpu_doorbell_init(adev));
Same here.
+}
+
/*
* GPU helpers function.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index a9083a1..ae71524 100644
What about SI (gmc_v6_0.c)?
As far as I know there is no SI hardware with resizeable BAR support.
The all VI generation can do this, but I'm not 100% sure if there aren't any
Bonaires out there which can handle it as well that's why I added gmc_v7
support.
Still need to double check that.
I think NI or even evergreen supported resizeable bars in theory,
although I'm not sure if any boards were fused to expose it.
In theory yes, in practice no.
Their PCIE config space defines the necessary registers, but I haven't
found any board from Evergreen, NI, SI or CIK generation where that is
actually validated.
Tonga is the first one I'm 100% sure that it is supported and I have
hardware to test it.
I would rather drop Bonaire support as well and wait for somebody with
the hardware to complain so that we can test and enable it.
Christian.
Alex
Christian.
Alex
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -372,13 +372,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device
*adev)
}
adev->mc.vram_width = numchan * chansize;
}
- /* Could aper size report 0 ? */
- adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->mc.aper_size = pci_resource_len(adev->pdev,
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access v2
Am 25.04.2017 um 16:34 schrieb Alex Deucher:
On Tue, Apr 25, 2017 at 9:19 AM, Christian König
wrote:
From: Christian König
Try to resize BAR0 to let CPU access all of VRAM.
v2: rebased, style cleanups, disable mem decode before resize,
handle gmc_v9 as well, round size up to power of two.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 37 ++
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 ---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 ---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10
5 files changed, 54 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4a16e3c..9484062 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1879,6 +1879,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev, struct ttm_tt *ttm,
struct ttm_mem_reg *mem);
void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc,
u64 base);
void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
+void amdgpu_resize_bar0(struct amdgpu_device *adev);
void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a09ad3cf..d5ca77a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -695,6 +695,43 @@ void amdgpu_gtt_location(struct amdgpu_device *adev,
struct amdgpu_mc *mc)
mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
}
+/**
+ * amdgpu_resize_bar0 - try to resize BAR0
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Try to resize BAR0 to make all VRAM CPU accessible.
+ */
+void amdgpu_resize_bar0(struct amdgpu_device *adev)
I'd suggest renaming this to amdgpu_device_resize_bar() to try and
impose some consistency in this file, but not a big deal either way.
+{
+ u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size);
+ u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) -1;
+ u16 cmd;
+ int r;
+
+ /* Free the doorbell mapping, it most likely needs to move as well */
+ amdgpu_doorbell_fini(adev);
+ pci_release_resource(adev->pdev, 2);
This should check for if (adev->asic_type >= CHIP_BONAIRE) since SI
didn't have doorbells.
+
+ /* Disable memory decoding while we change the BAR addresses and size */
+ pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
+ pci_write_config_word(adev->pdev, PCI_COMMAND,
+ cmd & ~PCI_COMMAND_MEMORY);
+
+ r = pci_resize_resource(adev->pdev, 0, rbar_size);
+ if (r == -ENOSPC)
+ DRM_INFO("Not enough PCI address space for a large BAR.");
+ else if (r && r != -ENOTSUPP)
+ DRM_ERROR("Problem resizing BAR0 (%d).", r);
+
+ pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
+
+ /* When the doorbell BAR isn't available we have no chance of
+* using the device.
+*/
+ BUG_ON(amdgpu_doorbell_init(adev));
Same here.
+}
+
/*
* GPU helpers function.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index a9083a1..ae71524 100644
What about SI (gmc_v6_0.c)?
As far as I know there is no SI hardware with resizeable BAR support.
The all VI generation can do this, but I'm not 100% sure if there aren't
any Bonaires out there which can handle it as well that's why I added
gmc_v7 support.
Still need to double check that.
Christian.
Alex
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -372,13 +372,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
}
adev->mc.vram_width = numchan * chansize;
}
- /* Could aper size report 0 ? */
- adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
/* size in MB on si */
adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
+ if (!(adev->flags & AMD_IS_APU))
+ amdgpu_resize_bar0(adev);
+ adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
+ adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
+
#ifdef CONFIG_X86_64
if (adev->flags & AMD_IS_APU) {
adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 4ac9978..1655de2 100644
--- a/drivers/gpu/drm
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access v2
On Tue, Apr 25, 2017 at 11:09 AM, Christian König
wrote:
> Am 25.04.2017 um 16:34 schrieb Alex Deucher:
>>
>> On Tue, Apr 25, 2017 at 9:19 AM, Christian König
>> wrote:
>>>
>>> From: Christian König
>>>
>>> Try to resize BAR0 to let CPU access all of VRAM.
>>>
>>> v2: rebased, style cleanups, disable mem decode before resize,
>>> handle gmc_v9 as well, round size up to power of two.
>>>
>>> Signed-off-by: Christian König
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 37
>>> ++
>>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 ---
>>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 ---
>>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10
>>> 5 files changed, 54 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index 4a16e3c..9484062 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -1879,6 +1879,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct
>>> amdgpu_device *adev, struct ttm_tt *ttm,
>>> struct ttm_mem_reg *mem);
>>> void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc
>>> *mc, u64 base);
>>> void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc
>>> *mc);
>>> +void amdgpu_resize_bar0(struct amdgpu_device *adev);
>>> void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64
>>> size);
>>> int amdgpu_ttm_init(struct amdgpu_device *adev);
>>> void amdgpu_ttm_fini(struct amdgpu_device *adev);
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> index a09ad3cf..d5ca77a 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> @@ -695,6 +695,43 @@ void amdgpu_gtt_location(struct amdgpu_device *adev,
>>> struct amdgpu_mc *mc)
>>> mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
>>> }
>>>
>>> +/**
>>> + * amdgpu_resize_bar0 - try to resize BAR0
>>> + *
>>> + * @adev: amdgpu_device pointer
>>> + *
>>> + * Try to resize BAR0 to make all VRAM CPU accessible.
>>> + */
>>> +void amdgpu_resize_bar0(struct amdgpu_device *adev)
>>
>> I'd suggest renaming this to amdgpu_device_resize_bar() to try and
>> impose some consistency in this file, but not a big deal either way.
>>
>>> +{
>>> + u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size);
>>> + u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) -1;
>>> + u16 cmd;
>>> + int r;
>>> +
>>> + /* Free the doorbell mapping, it most likely needs to move as
>>> well */
>>> + amdgpu_doorbell_fini(adev);
>>> + pci_release_resource(adev->pdev, 2);
>>
>> This should check for if (adev->asic_type >= CHIP_BONAIRE) since SI
>> didn't have doorbells.
>>
>>> +
>>> + /* Disable memory decoding while we change the BAR addresses and
>>> size */
>>> + pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
>>> + pci_write_config_word(adev->pdev, PCI_COMMAND,
>>> + cmd & ~PCI_COMMAND_MEMORY);
>>> +
>>> + r = pci_resize_resource(adev->pdev, 0, rbar_size);
>>> + if (r == -ENOSPC)
>>> + DRM_INFO("Not enough PCI address space for a large
>>> BAR.");
>>> + else if (r && r != -ENOTSUPP)
>>> + DRM_ERROR("Problem resizing BAR0 (%d).", r);
>>> +
>>> + pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
>>> +
>>> + /* When the doorbell BAR isn't available we have no chance of
>>> +* using the device.
>>> +*/
>>> + BUG_ON(amdgpu_doorbell_init(adev));
>>
>> Same here.
>>
>>> +}
>>> +
>>> /*
>>>* GPU helpers function.
>>>*/
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> index a9083a1..ae71524 100644
>>
>> What about SI (gmc_v6_0.c)?
>
>
> As far as I know there is no SI hardware with resizeable BAR support.
>
> The all VI generation can do this, but I'm not 100% sure if there aren't any
> Bonaires out there which can handle it as well that's why I added gmc_v7
> support.
>
> Still need to double check that.
I think NI or even evergreen supported resizeable bars in theory,
although I'm not sure if any boards were fused to expose it.
Alex
>
> Christian.
>
>
>>
>> Alex
>>
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> @@ -372,13 +372,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device
>>> *adev)
>>> }
>>> adev->mc.vram_width = numchan * chansize;
>>> }
>>> - /* Could aper size report 0 ? */
>>> - adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
>>> - adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
>>> /* size in MB on si */
>>>
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access v2
On Tue, Apr 25, 2017 at 9:19 AM, Christian König
wrote:
> From: Christian König
>
> Try to resize BAR0 to let CPU access all of VRAM.
>
> v2: rebased, style cleanups, disable mem decode before resize,
> handle gmc_v9 as well, round size up to power of two.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 37
> ++
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 ---
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 ---
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10
> 5 files changed, 54 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 4a16e3c..9484062 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1879,6 +1879,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
> *adev, struct ttm_tt *ttm,
> struct ttm_mem_reg *mem);
> void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc,
> u64 base);
> void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
> +void amdgpu_resize_bar0(struct amdgpu_device *adev);
> void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
> int amdgpu_ttm_init(struct amdgpu_device *adev);
> void amdgpu_ttm_fini(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index a09ad3cf..d5ca77a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -695,6 +695,43 @@ void amdgpu_gtt_location(struct amdgpu_device *adev,
> struct amdgpu_mc *mc)
> mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
> }
>
> +/**
> + * amdgpu_resize_bar0 - try to resize BAR0
> + *
> + * @adev: amdgpu_device pointer
> + *
> + * Try to resize BAR0 to make all VRAM CPU accessible.
> + */
> +void amdgpu_resize_bar0(struct amdgpu_device *adev)
I'd suggest renaming this to amdgpu_device_resize_bar() to try and
impose some consistency in this file, but not a big deal either way.
> +{
> + u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size);
> + u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) -1;
> + u16 cmd;
> + int r;
> +
> + /* Free the doorbell mapping, it most likely needs to move as well */
> + amdgpu_doorbell_fini(adev);
> + pci_release_resource(adev->pdev, 2);
This should check for if (adev->asic_type >= CHIP_BONAIRE) since SI
didn't have doorbells.
> +
> + /* Disable memory decoding while we change the BAR addresses and size
> */
> + pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
> + pci_write_config_word(adev->pdev, PCI_COMMAND,
> + cmd & ~PCI_COMMAND_MEMORY);
> +
> + r = pci_resize_resource(adev->pdev, 0, rbar_size);
> + if (r == -ENOSPC)
> + DRM_INFO("Not enough PCI address space for a large BAR.");
> + else if (r && r != -ENOTSUPP)
> + DRM_ERROR("Problem resizing BAR0 (%d).", r);
> +
> + pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
> +
> + /* When the doorbell BAR isn't available we have no chance of
> +* using the device.
> +*/
> + BUG_ON(amdgpu_doorbell_init(adev));
Same here.
> +}
> +
> /*
> * GPU helpers function.
> */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index a9083a1..ae71524 100644
What about SI (gmc_v6_0.c)?
Alex
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -372,13 +372,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
> }
> adev->mc.vram_width = numchan * chansize;
> }
> - /* Could aper size report 0 ? */
> - adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
> - adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
> /* size in MB on si */
> adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
> adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL *
> 1024ULL;
>
> + if (!(adev->flags & AMD_IS_APU))
> + amdgpu_resize_bar0(adev);
> + adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
> + adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
> +
> #ifdef CONFIG_X86_64
> if (adev->flags & AMD_IS_APU) {
> adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 4ac9978..1655de2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -534,13 +534,15 @@ static int gmc_v8_0_mc_init(struct amdgpu_device
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
On Mon, Mar 13, 2017 at 01:41:36PM +0100, Christian König wrote:
> From: Christian König
>
> Try to resize BAR0 to let CPU access all of VRAM.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 +
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +---
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +---
> 4 files changed, 40 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 3b81ded..905ded9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
> *adev, struct ttm_tt *ttm,
>struct ttm_mem_reg *mem);
> void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc,
> u64 base);
> void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
> +void amdgpu_resize_bar0(struct amdgpu_device *adev);
> void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
> int amdgpu_ttm_init(struct amdgpu_device *adev);
> void amdgpu_ttm_fini(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 118f4e6..92955fe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -692,6 +692,35 @@ void amdgpu_gtt_location(struct amdgpu_device *adev,
> struct amdgpu_mc *mc)
> mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
> }
>
> +/**
> + * amdgpu_resize_bar0 - try to resize BAR0
> + *
> + * @adev: amdgpu_device pointer
> + *
> + * Try to resize BAR0 to make all VRAM CPU accessible.
> + */
> +void amdgpu_resize_bar0(struct amdgpu_device *adev)
> +{
> + u32 size = max(ilog2(adev->mc.real_vram_size - 1) + 1, 20) - 20;
> + int r;
> +
> + r = pci_resize_resource(adev->pdev, 0, size);
> +
> + if (r == -ENOTSUPP) {
> + /* The hardware don't support the extension. */
> + return;
> +
> + } else if (r == -ENOSPC) {
> + DRM_INFO("Not enoigh PCI address space for a large BAR.");
s/enoigh/enough/
> + } else if (r) {
> + DRM_ERROR("Problem resizing BAR0 (%d).", r);
> + }
> +
> + /* Reinit the doorbell mapping, it is most likely moved as well */
I think you should assume all BARs moved (I don't know how many you have;
maybe this already covers all of them).
> + amdgpu_doorbell_fini(adev);
> + BUG_ON(amdgpu_doorbell_init(adev));
I think things inside BUG_ON() tend to get overlooked, so I avoid things
that have side-effects. But that's just my personal preference.
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
- Are we going to support resizing BAR when kernel modesetting is not enabled and we are running in console under VBIOS control (VESA/VGA)? No, initial I've tried to resize the PCI BAR during probing without the help of the driver at all. But the VESA/EFI/VBIOS don't seem to be able to handle addresses above 4GB for some reason. So the approach is to let the driver kick the VESA/EFI drivers out and then resize when we know that nobody is accessing the BAR. That's the only approach I've found without either blacklisting VESA/EFI drivers or crashing the system during the resize. - Should we restore PCI configuration if amdgpu will be unloaded? Yeah, thought about the as well. I'm just not sure how to do it. There is a lot of stuff we need to save and reset when the driver unloads for not much gain. - In function amdgpu_resize_bar0(): If resizing for "max" size failed should we try other sizes? What do you think? Probably not worth it. If we get the BAR moved to a 64bit address we should have enough address space in almost all cases, so setting it to the maximum should succeed. But I think we could add another parameter to allow limiting the resized size for all corner cases and for testing. Regards, Christian. Am 23.03.2017 um 15:30 schrieb Sagalovitch, Serguei: Christian, - Are we going to support resizing BAR when kernel modesetting is not enabled and we are running in console under VBIOS control (VESA/VGA)? - Should we restore PCI configuration if amdgpu will be unloaded? - In function amdgpu_resize_bar0(): If resizing for "max" size failed should we try other sizes? What do you think? Sincerely yours, Serguei Sagalovitch From: amd-gfx on behalf of Zhang, Jerry Sent: March 15, 2017 10:41 PM To: Alex Deucher Cc: Zhou, David(ChunMing); Ayyappa Ch; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; dri-de...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; Christian König; helg...@kernel.org; amd-...@lists.freedesktop.org Subject: RE: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access Thanks for your info. I see. Regards, Jerry (Junwei Zhang) Linux Base Graphics SRDC Software Development _ -Original Message- From: Alex Deucher [mailto:alexdeuc...@gmail.com] Sent: Thursday, March 16, 2017 10:25 To: Zhang, Jerry Cc: Christian König; Zhou, David(ChunMing); Ayyappa Ch; linux- p...@vger.kernel.org; linux-kernel@vger.kernel.org; dri- de...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; helg...@kernel.org; amd-...@lists.freedesktop.org Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access On Wed, Mar 15, 2017 at 10:19 PM, Zhang, Jerry wrote: -Original Message- From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of Christian K?nig Sent: Wednesday, March 15, 2017 17:29 To: Zhou, David(ChunMing); Ayyappa Ch Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; amd- g...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; helg...@kernel.org; dri-de...@lists.freedesktop.org Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access Yes, exactly that. (I'm not familiar with PCI too much.) Is there any restrict for PCI device? I'm concerning if any PCI couldn't support it on some motherboard. It depends on the PCI root bridge. This patch set only implements support for AMD root bridges. Intel and other vendors would need similar code. Alex Christian. Am 15.03.2017 um 09:25 schrieb Zhou, David(ChunMing): Does that means we don't need invisible vram later? David -Original Message- From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of Christian K?nig Sent: Wednesday, March 15, 2017 3:38 PM To: Ayyappa Ch Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; amd-...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; helg...@kernel.org; dri-de...@lists.freedesktop.org Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access Carizzo is an APU and resizing BARs isn't needed nor supported there. The CPU can access the full stolen VRAM directly on that hardware. As far as I know ASICs with support for this are Tonga, Fiji and all Polaris variants. Christian. Am 15.03.2017 um 08:23 schrieb Ayyappa Ch: Is it possible on Carrizo asics? Or only supports on newer asics? On Mon, Mar 13, 2017 at 6:11 PM, Christian König wrote: From: Christian König Try to resize BAR0 to let CPU access all of VRAM. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 + drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +--- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +--- 4 files changed, 40 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/a
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
Christian, - Are we going to support resizing BAR when kernel modesetting is not enabled and we are running in console under VBIOS control (VESA/VGA)? - Should we restore PCI configuration if amdgpu will be unloaded? - In function amdgpu_resize_bar0(): If resizing for "max" size failed should we try other sizes? What do you think? Sincerely yours, Serguei Sagalovitch From: amd-gfx on behalf of Zhang, Jerry Sent: March 15, 2017 10:41 PM To: Alex Deucher Cc: Zhou, David(ChunMing); Ayyappa Ch; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; dri-de...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; Christian König; helg...@kernel.org; amd-...@lists.freedesktop.org Subject: RE: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access Thanks for your info. I see. Regards, Jerry (Junwei Zhang) Linux Base Graphics SRDC Software Development _ > -Original Message- > From: Alex Deucher [mailto:alexdeuc...@gmail.com] > Sent: Thursday, March 16, 2017 10:25 > To: Zhang, Jerry > Cc: Christian König; Zhou, David(ChunMing); Ayyappa Ch; linux- > p...@vger.kernel.org; linux-kernel@vger.kernel.org; dri- > de...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; > helg...@kernel.org; amd-...@lists.freedesktop.org > Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access > > On Wed, Mar 15, 2017 at 10:19 PM, Zhang, Jerry wrote: > >> -Original Message- > >> From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On > >> Behalf Of Christian K?nig > >> Sent: Wednesday, March 15, 2017 17:29 > >> To: Zhou, David(ChunMing); Ayyappa Ch > >> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; amd- > >> g...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; > >> helg...@kernel.org; dri-de...@lists.freedesktop.org > >> Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access > >> > >> Yes, exactly that. > > > > (I'm not familiar with PCI too much.) > > Is there any restrict for PCI device? > > I'm concerning if any PCI couldn't support it on some motherboard. > > It depends on the PCI root bridge. This patch set only implements support for > AMD root bridges. Intel and other vendors would need similar code. > > Alex > > > > >> > >> Christian. > >> > >> Am 15.03.2017 um 09:25 schrieb Zhou, David(ChunMing): > >> > Does that means we don't need invisible vram later? > >> > > >> > David > >> > > >> > -Original Message- > >> > From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On > >> > Behalf Of Christian K?nig > >> > Sent: Wednesday, March 15, 2017 3:38 PM > >> > To: Ayyappa Ch > >> > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > >> > amd-...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; > >> > helg...@kernel.org; dri-de...@lists.freedesktop.org > >> > Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access > >> > > >> > Carizzo is an APU and resizing BARs isn't needed nor supported there. > >> > The CPU can access the full stolen VRAM directly on that hardware. > >> > > >> > As far as I know ASICs with support for this are Tonga, Fiji and all > >> > Polaris > variants. > >> > > >> > Christian. > >> > > >> > Am 15.03.2017 um 08:23 schrieb Ayyappa Ch: > >> >> Is it possible on Carrizo asics? Or only supports on newer asics? > >> >> > >> >> On Mon, Mar 13, 2017 at 6:11 PM, Christian König > >> >> wrote: > >> >>> From: Christian König > >> >>> > >> >>> Try to resize BAR0 to let CPU access all of VRAM. > >> >>> > >> >>> Signed-off-by: Christian König > >> >>> --- > >> >>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + > >> >>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 > >> + > >> >>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +--- > >> >>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +--- > >> >>> 4 files changed, 40 insertions(+), 6 deletions(-) > >> >>> > >> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> index 3b81ded..905ded9
RE: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
Thanks for your info. I see. Regards, Jerry (Junwei Zhang) Linux Base Graphics SRDC Software Development _ > -Original Message- > From: Alex Deucher [mailto:alexdeuc...@gmail.com] > Sent: Thursday, March 16, 2017 10:25 > To: Zhang, Jerry > Cc: Christian König; Zhou, David(ChunMing); Ayyappa Ch; linux- > p...@vger.kernel.org; linux-kernel@vger.kernel.org; dri- > de...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; > helg...@kernel.org; amd-...@lists.freedesktop.org > Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access > > On Wed, Mar 15, 2017 at 10:19 PM, Zhang, Jerry wrote: > >> -Original Message- > >> From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On > >> Behalf Of Christian K?nig > >> Sent: Wednesday, March 15, 2017 17:29 > >> To: Zhou, David(ChunMing); Ayyappa Ch > >> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; amd- > >> g...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; > >> helg...@kernel.org; dri-de...@lists.freedesktop.org > >> Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access > >> > >> Yes, exactly that. > > > > (I'm not familiar with PCI too much.) > > Is there any restrict for PCI device? > > I'm concerning if any PCI couldn't support it on some motherboard. > > It depends on the PCI root bridge. This patch set only implements support for > AMD root bridges. Intel and other vendors would need similar code. > > Alex > > > > >> > >> Christian. > >> > >> Am 15.03.2017 um 09:25 schrieb Zhou, David(ChunMing): > >> > Does that means we don't need invisible vram later? > >> > > >> > David > >> > > >> > -Original Message- > >> > From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On > >> > Behalf Of Christian K?nig > >> > Sent: Wednesday, March 15, 2017 3:38 PM > >> > To: Ayyappa Ch > >> > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > >> > amd-...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; > >> > helg...@kernel.org; dri-de...@lists.freedesktop.org > >> > Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access > >> > > >> > Carizzo is an APU and resizing BARs isn't needed nor supported there. > >> > The CPU can access the full stolen VRAM directly on that hardware. > >> > > >> > As far as I know ASICs with support for this are Tonga, Fiji and all > >> > Polaris > variants. > >> > > >> > Christian. > >> > > >> > Am 15.03.2017 um 08:23 schrieb Ayyappa Ch: > >> >> Is it possible on Carrizo asics? Or only supports on newer asics? > >> >> > >> >> On Mon, Mar 13, 2017 at 6:11 PM, Christian König > >> >> wrote: > >> >>> From: Christian König > >> >>> > >> >>> Try to resize BAR0 to let CPU access all of VRAM. > >> >>> > >> >>> Signed-off-by: Christian König > >> >>> --- > >> >>>drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 + > >> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 > >> + > >> >>>drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +--- > >> >>>drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +--- > >> >>>4 files changed, 40 insertions(+), 6 deletions(-) > >> >>> > >> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> index 3b81ded..905ded9 100644 > >> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> @@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct > >> amdgpu_device *adev, struct ttm_tt *ttm, > >> >>>struct ttm_mem_reg *mem); > >> >>>void amdgpu_vram_location(struct amdgpu_device *adev, struct > >> amdgpu_mc *mc, u64 base); > >> >>>void amdgpu_gtt_location(struct amdgpu_device *adev, struct > >> >>> amdgpu_mc *mc); > >> >>> +void amdgpu_resize_bar0(struct amdgpu_device *adev); > >> >>>void amdgpu_ttm_set_active_vram_size
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
On Wed, Mar 15, 2017 at 10:19 PM, Zhang, Jerry wrote: >> -Original Message- >> From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of >> Christian K?nig >> Sent: Wednesday, March 15, 2017 17:29 >> To: Zhou, David(ChunMing); Ayyappa Ch >> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; amd- >> g...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; >> helg...@kernel.org; dri-de...@lists.freedesktop.org >> Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access >> >> Yes, exactly that. > > (I'm not familiar with PCI too much.) > Is there any restrict for PCI device? > I'm concerning if any PCI couldn't support it on some motherboard. It depends on the PCI root bridge. This patch set only implements support for AMD root bridges. Intel and other vendors would need similar code. Alex > >> >> Christian. >> >> Am 15.03.2017 um 09:25 schrieb Zhou, David(ChunMing): >> > Does that means we don't need invisible vram later? >> > >> > David >> > >> > -Original Message- >> > From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On >> > Behalf Of Christian K?nig >> > Sent: Wednesday, March 15, 2017 3:38 PM >> > To: Ayyappa Ch >> > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; >> > amd-...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; >> > helg...@kernel.org; dri-de...@lists.freedesktop.org >> > Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access >> > >> > Carizzo is an APU and resizing BARs isn't needed nor supported there. >> > The CPU can access the full stolen VRAM directly on that hardware. >> > >> > As far as I know ASICs with support for this are Tonga, Fiji and all >> > Polaris variants. >> > >> > Christian. >> > >> > Am 15.03.2017 um 08:23 schrieb Ayyappa Ch: >> >> Is it possible on Carrizo asics? Or only supports on newer asics? >> >> >> >> On Mon, Mar 13, 2017 at 6:11 PM, Christian König >> >> wrote: >> >>> From: Christian König >> >>> >> >>> Try to resize BAR0 to let CPU access all of VRAM. >> >>> >> >>> Signed-off-by: Christian König >> >>> --- >> >>>drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 + >> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 >> + >> >>>drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +--- >> >>>drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +--- >> >>>4 files changed, 40 insertions(+), 6 deletions(-) >> >>> >> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> >>> index 3b81ded..905ded9 100644 >> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> >>> @@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct >> amdgpu_device *adev, struct ttm_tt *ttm, >> >>>struct ttm_mem_reg *mem); >> >>>void amdgpu_vram_location(struct amdgpu_device *adev, struct >> amdgpu_mc *mc, u64 base); >> >>>void amdgpu_gtt_location(struct amdgpu_device *adev, struct >> >>> amdgpu_mc *mc); >> >>> +void amdgpu_resize_bar0(struct amdgpu_device *adev); >> >>>void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, >> u64 size); >> >>>int amdgpu_ttm_init(struct amdgpu_device *adev); >> >>>void amdgpu_ttm_fini(struct amdgpu_device *adev); diff --git >> >>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> >>> index 118f4e6..92955fe 100644 >> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> >>> @@ -692,6 +692,35 @@ void amdgpu_gtt_location(struct amdgpu_device >> *adev, struct amdgpu_mc *mc) >> >>> mc->gtt_size >> 20, mc->gtt_start, >> >>> mc->gtt_end); >> >>>} >> >>> >> >>> +/** >> >>> + * amdgpu_resize_bar0 - try to resize BAR0 >> >>> + * >> >>> + * @adev: amdgpu_device pointer >> >>> + *
RE: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
> -Original Message-
> From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
> Christian K?nig
> Sent: Wednesday, March 15, 2017 17:29
> To: Zhou, David(ChunMing); Ayyappa Ch
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; amd-
> g...@lists.freedesktop.org; platform-driver-...@vger.kernel.org;
> helg...@kernel.org; dri-de...@lists.freedesktop.org
> Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
>
> Yes, exactly that.
(I'm not familiar with PCI too much.)
Is there any restrict for PCI device?
I'm concerning if any PCI couldn't support it on some motherboard.
>
> Christian.
>
> Am 15.03.2017 um 09:25 schrieb Zhou, David(ChunMing):
> > Does that means we don't need invisible vram later?
> >
> > David
> >
> > -Original Message-
> > From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On
> > Behalf Of Christian K?nig
> > Sent: Wednesday, March 15, 2017 3:38 PM
> > To: Ayyappa Ch
> > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> > amd-...@lists.freedesktop.org; platform-driver-...@vger.kernel.org;
> > helg...@kernel.org; dri-de...@lists.freedesktop.org
> > Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
> >
> > Carizzo is an APU and resizing BARs isn't needed nor supported there.
> > The CPU can access the full stolen VRAM directly on that hardware.
> >
> > As far as I know ASICs with support for this are Tonga, Fiji and all
> > Polaris variants.
> >
> > Christian.
> >
> > Am 15.03.2017 um 08:23 schrieb Ayyappa Ch:
> >> Is it possible on Carrizo asics? Or only supports on newer asics?
> >>
> >> On Mon, Mar 13, 2017 at 6:11 PM, Christian König
> >> wrote:
> >>> From: Christian König
> >>>
> >>> Try to resize BAR0 to let CPU access all of VRAM.
> >>>
> >>> Signed-off-by: Christian König
> >>> ---
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29
> +
> >>>drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +---
> >>>drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +---
> >>>4 files changed, 40 insertions(+), 6 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> index 3b81ded..905ded9 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> @@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct
> amdgpu_device *adev, struct ttm_tt *ttm,
> >>>struct ttm_mem_reg *mem);
> >>>void amdgpu_vram_location(struct amdgpu_device *adev, struct
> amdgpu_mc *mc, u64 base);
> >>>void amdgpu_gtt_location(struct amdgpu_device *adev, struct
> >>> amdgpu_mc *mc);
> >>> +void amdgpu_resize_bar0(struct amdgpu_device *adev);
> >>>void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev,
> u64 size);
> >>>int amdgpu_ttm_init(struct amdgpu_device *adev);
> >>>void amdgpu_ttm_fini(struct amdgpu_device *adev); diff --git
> >>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >>> index 118f4e6..92955fe 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >>> @@ -692,6 +692,35 @@ void amdgpu_gtt_location(struct amdgpu_device
> *adev, struct amdgpu_mc *mc)
> >>> mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
> >>>}
> >>>
> >>> +/**
> >>> + * amdgpu_resize_bar0 - try to resize BAR0
> >>> + *
> >>> + * @adev: amdgpu_device pointer
> >>> + *
> >>> + * Try to resize BAR0 to make all VRAM CPU accessible.
> >>> + */
> >>> +void amdgpu_resize_bar0(struct amdgpu_device *adev) {
> >>> + u32 size = max(ilog2(adev->mc.real_vram_size - 1) + 1, 20) - 20;
> >>> + int r;
> >>> +
> >>> + r = pci_resize_resource(adev->pdev, 0, size);
> >>> +
> >>> + if (r == -ENOTSUPP) {
> >>> + /* The hardware don't support the extension. */
> >>> + return;
> >>
RE: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Wednesday, March 15, 2017 3:38 AM
> To: Ayyappa Ch
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; amd-
> g...@lists.freedesktop.org; platform-driver-...@vger.kernel.org;
> helg...@kernel.org; dri-de...@lists.freedesktop.org
> Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
>
> Carizzo is an APU and resizing BARs isn't needed nor supported there.
> The CPU can access the full stolen VRAM directly on that hardware.
>
> As far as I know ASICs with support for this are Tonga, Fiji and all
> Polaris variants.
I think resizable BARs are supported as far back as evergreen or NI.
Alex
>
> Christian.
>
> Am 15.03.2017 um 08:23 schrieb Ayyappa Ch:
> > Is it possible on Carrizo asics? Or only supports on newer asics?
> >
> > On Mon, Mar 13, 2017 at 6:11 PM, Christian König
> > wrote:
> >> From: Christian König
> >>
> >> Try to resize BAR0 to let CPU access all of VRAM.
> >>
> >> Signed-off-by: Christian König
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29
> +
> >> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +---
> >> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +---
> >> 4 files changed, 40 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> index 3b81ded..905ded9 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> @@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct
> amdgpu_device *adev, struct ttm_tt *ttm,
> >> struct ttm_mem_reg *mem);
> >> void amdgpu_vram_location(struct amdgpu_device *adev, struct
> amdgpu_mc *mc, u64 base);
> >> void amdgpu_gtt_location(struct amdgpu_device *adev, struct
> amdgpu_mc *mc);
> >> +void amdgpu_resize_bar0(struct amdgpu_device *adev);
> >> void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev,
> u64 size);
> >> int amdgpu_ttm_init(struct amdgpu_device *adev);
> >> void amdgpu_ttm_fini(struct amdgpu_device *adev);
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> index 118f4e6..92955fe 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> @@ -692,6 +692,35 @@ void amdgpu_gtt_location(struct amdgpu_device
> *adev, struct amdgpu_mc *mc)
> >> mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
> >> }
> >>
> >> +/**
> >> + * amdgpu_resize_bar0 - try to resize BAR0
> >> + *
> >> + * @adev: amdgpu_device pointer
> >> + *
> >> + * Try to resize BAR0 to make all VRAM CPU accessible.
> >> + */
> >> +void amdgpu_resize_bar0(struct amdgpu_device *adev)
> >> +{
> >> + u32 size = max(ilog2(adev->mc.real_vram_size - 1) + 1, 20) - 20;
> >> + int r;
> >> +
> >> + r = pci_resize_resource(adev->pdev, 0, size);
> >> +
> >> + if (r == -ENOTSUPP) {
> >> + /* The hardware don't support the extension. */
> >> + return;
> >> +
> >> + } else if (r == -ENOSPC) {
> >> + DRM_INFO("Not enoigh PCI address space for a large BAR.");
> >> + } else if (r) {
> >> + DRM_ERROR("Problem resizing BAR0 (%d).", r);
> >> + }
> >> +
> >> + /* Reinit the doorbell mapping, it is most likely moved as well */
> >> + amdgpu_doorbell_fini(adev);
> >> + BUG_ON(amdgpu_doorbell_init(adev));
> >> +}
> >> +
> >> /*
> >>* GPU helpers function.
> >>*/
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> >> index dc9b6d6..36a7aa5 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> >> @@ -367,13 +367,15 @@ static int gmc_v7_0_mc_init(struct
> amdgpu_device *adev)
> >> break;
> >> }
> >> adev->mc.vram_width = numchan * chansize;
> >>
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
No, we resize the BAR on the fly during driver load without help from
the BIOS or VBIOS.
Christian.
Am 15.03.2017 um 11:42 schrieb Ayyappa Ch:
It also needs any support from VBIOS side ? I mean PCIe large bar support?
Thanks,
Ayyappa.
On Wed, Mar 15, 2017 at 1:07 PM, Christian König
wrote:
Carizzo is an APU and resizing BARs isn't needed nor supported there. The
CPU can access the full stolen VRAM directly on that hardware.
As far as I know ASICs with support for this are Tonga, Fiji and all Polaris
variants.
Christian.
Am 15.03.2017 um 08:23 schrieb Ayyappa Ch:
Is it possible on Carrizo asics? Or only supports on newer asics?
On Mon, Mar 13, 2017 at 6:11 PM, Christian König
wrote:
From: Christian König
Try to resize BAR0 to let CPU access all of VRAM.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29
+
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +---
4 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3b81ded..905ded9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct
amdgpu_device *adev, struct ttm_tt *ttm,
struct ttm_mem_reg *mem);
void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc
*mc, u64 base);
void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc
*mc);
+void amdgpu_resize_bar0(struct amdgpu_device *adev);
void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64
size);
int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 118f4e6..92955fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -692,6 +692,35 @@ void amdgpu_gtt_location(struct amdgpu_device *adev,
struct amdgpu_mc *mc)
mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
}
+/**
+ * amdgpu_resize_bar0 - try to resize BAR0
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Try to resize BAR0 to make all VRAM CPU accessible.
+ */
+void amdgpu_resize_bar0(struct amdgpu_device *adev)
+{
+ u32 size = max(ilog2(adev->mc.real_vram_size - 1) + 1, 20) - 20;
+ int r;
+
+ r = pci_resize_resource(adev->pdev, 0, size);
+
+ if (r == -ENOTSUPP) {
+ /* The hardware don't support the extension. */
+ return;
+
+ } else if (r == -ENOSPC) {
+ DRM_INFO("Not enoigh PCI address space for a large
BAR.");
+ } else if (r) {
+ DRM_ERROR("Problem resizing BAR0 (%d).", r);
+ }
+
+ /* Reinit the doorbell mapping, it is most likely moved as well
*/
+ amdgpu_doorbell_fini(adev);
+ BUG_ON(amdgpu_doorbell_init(adev));
+}
+
/*
* GPU helpers function.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index dc9b6d6..36a7aa5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -367,13 +367,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device
*adev)
break;
}
adev->mc.vram_width = numchan * chansize;
- /* Could aper size report 0 ? */
- adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
/* size in MB on si */
adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL *
1024ULL;
adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL *
1024ULL;
+ if (!(adev->flags & AMD_IS_APU))
+ amdgpu_resize_bar0(adev);
+ adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
+ adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
+
#ifdef CONFIG_X86_64
if (adev->flags & AMD_IS_APU) {
adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) <<
22;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index c087b00..7761ad3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -459,13 +459,15 @@ static int gmc_v8_0_mc_init(struct amdgpu_device
*adev)
break;
}
adev->mc.vram_width = numchan * chansize;
- /* Could aper size report 0 ? */
- adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
/* size in MB on si */
adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL *
1024ULL;
adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) *
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
It also needs any support from VBIOS side ? I mean PCIe large bar support?
Thanks,
Ayyappa.
On Wed, Mar 15, 2017 at 1:07 PM, Christian König
wrote:
> Carizzo is an APU and resizing BARs isn't needed nor supported there. The
> CPU can access the full stolen VRAM directly on that hardware.
>
> As far as I know ASICs with support for this are Tonga, Fiji and all Polaris
> variants.
>
> Christian.
>
>
> Am 15.03.2017 um 08:23 schrieb Ayyappa Ch:
>>
>> Is it possible on Carrizo asics? Or only supports on newer asics?
>>
>> On Mon, Mar 13, 2017 at 6:11 PM, Christian König
>> wrote:
>>>
>>> From: Christian König
>>>
>>> Try to resize BAR0 to let CPU access all of VRAM.
>>>
>>> Signed-off-by: Christian König
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29
>>> +
>>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +---
>>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +---
>>> 4 files changed, 40 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index 3b81ded..905ded9 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct
>>> amdgpu_device *adev, struct ttm_tt *ttm,
>>> struct ttm_mem_reg *mem);
>>> void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc
>>> *mc, u64 base);
>>> void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc
>>> *mc);
>>> +void amdgpu_resize_bar0(struct amdgpu_device *adev);
>>> void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64
>>> size);
>>> int amdgpu_ttm_init(struct amdgpu_device *adev);
>>> void amdgpu_ttm_fini(struct amdgpu_device *adev);
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> index 118f4e6..92955fe 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> @@ -692,6 +692,35 @@ void amdgpu_gtt_location(struct amdgpu_device *adev,
>>> struct amdgpu_mc *mc)
>>> mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
>>> }
>>>
>>> +/**
>>> + * amdgpu_resize_bar0 - try to resize BAR0
>>> + *
>>> + * @adev: amdgpu_device pointer
>>> + *
>>> + * Try to resize BAR0 to make all VRAM CPU accessible.
>>> + */
>>> +void amdgpu_resize_bar0(struct amdgpu_device *adev)
>>> +{
>>> + u32 size = max(ilog2(adev->mc.real_vram_size - 1) + 1, 20) - 20;
>>> + int r;
>>> +
>>> + r = pci_resize_resource(adev->pdev, 0, size);
>>> +
>>> + if (r == -ENOTSUPP) {
>>> + /* The hardware don't support the extension. */
>>> + return;
>>> +
>>> + } else if (r == -ENOSPC) {
>>> + DRM_INFO("Not enoigh PCI address space for a large
>>> BAR.");
>>> + } else if (r) {
>>> + DRM_ERROR("Problem resizing BAR0 (%d).", r);
>>> + }
>>> +
>>> + /* Reinit the doorbell mapping, it is most likely moved as well
>>> */
>>> + amdgpu_doorbell_fini(adev);
>>> + BUG_ON(amdgpu_doorbell_init(adev));
>>> +}
>>> +
>>> /*
>>>* GPU helpers function.
>>>*/
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> index dc9b6d6..36a7aa5 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> @@ -367,13 +367,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device
>>> *adev)
>>> break;
>>> }
>>> adev->mc.vram_width = numchan * chansize;
>>> - /* Could aper size report 0 ? */
>>> - adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
>>> - adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
>>> /* size in MB on si */
>>> adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL *
>>> 1024ULL;
>>> adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL *
>>> 1024ULL;
>>>
>>> + if (!(adev->flags & AMD_IS_APU))
>>> + amdgpu_resize_bar0(adev);
>>> + adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
>>> + adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
>>> +
>>> #ifdef CONFIG_X86_64
>>> if (adev->flags & AMD_IS_APU) {
>>> adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) <<
>>> 22;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>>> index c087b00..7761ad3 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>>> @@ -459,13 +459,15 @@ static int gmc_v8_0_mc_init(struct amdgpu_device
>>> *adev)
>>> break;
>>> }
>>> adev->mc.vram_width = numchan * chansize;
>>> - /* Could aper size report 0 ? */
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
Yes, exactly that.
Christian.
Am 15.03.2017 um 09:25 schrieb Zhou, David(ChunMing):
Does that means we don't need invisible vram later?
David
-Original Message-
From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
Christian K?nig
Sent: Wednesday, March 15, 2017 3:38 PM
To: Ayyappa Ch
Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
amd-...@lists.freedesktop.org; platform-driver-...@vger.kernel.org;
helg...@kernel.org; dri-de...@lists.freedesktop.org
Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
Carizzo is an APU and resizing BARs isn't needed nor supported there.
The CPU can access the full stolen VRAM directly on that hardware.
As far as I know ASICs with support for this are Tonga, Fiji and all Polaris
variants.
Christian.
Am 15.03.2017 um 08:23 schrieb Ayyappa Ch:
Is it possible on Carrizo asics? Or only supports on newer asics?
On Mon, Mar 13, 2017 at 6:11 PM, Christian König
wrote:
From: Christian König
Try to resize BAR0 to let CPU access all of VRAM.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 +
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +---
4 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3b81ded..905ded9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev, struct ttm_tt *ttm,
struct ttm_mem_reg *mem);
void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc,
u64 base);
void amdgpu_gtt_location(struct amdgpu_device *adev, struct
amdgpu_mc *mc);
+void amdgpu_resize_bar0(struct amdgpu_device *adev);
void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev); diff --git
a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 118f4e6..92955fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -692,6 +692,35 @@ void amdgpu_gtt_location(struct amdgpu_device *adev,
struct amdgpu_mc *mc)
mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
}
+/**
+ * amdgpu_resize_bar0 - try to resize BAR0
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Try to resize BAR0 to make all VRAM CPU accessible.
+ */
+void amdgpu_resize_bar0(struct amdgpu_device *adev) {
+ u32 size = max(ilog2(adev->mc.real_vram_size - 1) + 1, 20) - 20;
+ int r;
+
+ r = pci_resize_resource(adev->pdev, 0, size);
+
+ if (r == -ENOTSUPP) {
+ /* The hardware don't support the extension. */
+ return;
+
+ } else if (r == -ENOSPC) {
+ DRM_INFO("Not enoigh PCI address space for a large BAR.");
+ } else if (r) {
+ DRM_ERROR("Problem resizing BAR0 (%d).", r);
+ }
+
+ /* Reinit the doorbell mapping, it is most likely moved as well */
+ amdgpu_doorbell_fini(adev);
+ BUG_ON(amdgpu_doorbell_init(adev));
+}
+
/*
* GPU helpers function.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index dc9b6d6..36a7aa5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -367,13 +367,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
break;
}
adev->mc.vram_width = numchan * chansize;
- /* Could aper size report 0 ? */
- adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
/* size in MB on si */
adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL
* 1024ULL;
+ if (!(adev->flags & AMD_IS_APU))
+ amdgpu_resize_bar0(adev);
+ adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
+ adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
+
#ifdef CONFIG_X86_64
if (adev->flags & AMD_IS_APU) {
adev->mc.aper_base =
((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; diff --git
a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index c087b00..7761ad3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -459,13 +459,15 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
break;
RE: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
Does that means we don't need invisible vram later?
David
-Original Message-
From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
Christian K?nig
Sent: Wednesday, March 15, 2017 3:38 PM
To: Ayyappa Ch
Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
amd-...@lists.freedesktop.org; platform-driver-...@vger.kernel.org;
helg...@kernel.org; dri-de...@lists.freedesktop.org
Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
Carizzo is an APU and resizing BARs isn't needed nor supported there.
The CPU can access the full stolen VRAM directly on that hardware.
As far as I know ASICs with support for this are Tonga, Fiji and all Polaris
variants.
Christian.
Am 15.03.2017 um 08:23 schrieb Ayyappa Ch:
> Is it possible on Carrizo asics? Or only supports on newer asics?
>
> On Mon, Mar 13, 2017 at 6:11 PM, Christian König
> wrote:
>> From: Christian König
>>
>> Try to resize BAR0 to let CPU access all of VRAM.
>>
>> Signed-off-by: Christian König
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29
>> +
>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +---
>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +---
>> 4 files changed, 40 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 3b81ded..905ded9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
>> *adev, struct ttm_tt *ttm,
>> struct ttm_mem_reg *mem);
>> void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc
>> *mc, u64 base);
>> void amdgpu_gtt_location(struct amdgpu_device *adev, struct
>> amdgpu_mc *mc);
>> +void amdgpu_resize_bar0(struct amdgpu_device *adev);
>> void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
>> int amdgpu_ttm_init(struct amdgpu_device *adev);
>> void amdgpu_ttm_fini(struct amdgpu_device *adev); diff --git
>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index 118f4e6..92955fe 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -692,6 +692,35 @@ void amdgpu_gtt_location(struct amdgpu_device *adev,
>> struct amdgpu_mc *mc)
>> mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
>> }
>>
>> +/**
>> + * amdgpu_resize_bar0 - try to resize BAR0
>> + *
>> + * @adev: amdgpu_device pointer
>> + *
>> + * Try to resize BAR0 to make all VRAM CPU accessible.
>> + */
>> +void amdgpu_resize_bar0(struct amdgpu_device *adev) {
>> + u32 size = max(ilog2(adev->mc.real_vram_size - 1) + 1, 20) - 20;
>> + int r;
>> +
>> + r = pci_resize_resource(adev->pdev, 0, size);
>> +
>> + if (r == -ENOTSUPP) {
>> + /* The hardware don't support the extension. */
>> + return;
>> +
>> + } else if (r == -ENOSPC) {
>> + DRM_INFO("Not enoigh PCI address space for a large BAR.");
>> + } else if (r) {
>> + DRM_ERROR("Problem resizing BAR0 (%d).", r);
>> + }
>> +
>> + /* Reinit the doorbell mapping, it is most likely moved as well */
>> + amdgpu_doorbell_fini(adev);
>> + BUG_ON(amdgpu_doorbell_init(adev));
>> +}
>> +
>> /*
>>* GPU helpers function.
>>*/
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> index dc9b6d6..36a7aa5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> @@ -367,13 +367,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
>> break;
>> }
>> adev->mc.vram_width = numchan * chansize;
>> - /* Could aper size report 0 ? */
>> - adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
>> - adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
>> /* size in MB on si */
>> adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL *
>> 1024ULL;
>> adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL
>> * 1024ULL;
>>
>> +
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
Carizzo is an APU and resizing BARs isn't needed nor supported there.
The CPU can access the full stolen VRAM directly on that hardware.
As far as I know ASICs with support for this are Tonga, Fiji and all
Polaris variants.
Christian.
Am 15.03.2017 um 08:23 schrieb Ayyappa Ch:
Is it possible on Carrizo asics? Or only supports on newer asics?
On Mon, Mar 13, 2017 at 6:11 PM, Christian König
wrote:
From: Christian König
Try to resize BAR0 to let CPU access all of VRAM.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 +
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +---
4 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3b81ded..905ded9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev, struct ttm_tt *ttm,
struct ttm_mem_reg *mem);
void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc,
u64 base);
void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
+void amdgpu_resize_bar0(struct amdgpu_device *adev);
void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 118f4e6..92955fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -692,6 +692,35 @@ void amdgpu_gtt_location(struct amdgpu_device *adev,
struct amdgpu_mc *mc)
mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
}
+/**
+ * amdgpu_resize_bar0 - try to resize BAR0
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Try to resize BAR0 to make all VRAM CPU accessible.
+ */
+void amdgpu_resize_bar0(struct amdgpu_device *adev)
+{
+ u32 size = max(ilog2(adev->mc.real_vram_size - 1) + 1, 20) - 20;
+ int r;
+
+ r = pci_resize_resource(adev->pdev, 0, size);
+
+ if (r == -ENOTSUPP) {
+ /* The hardware don't support the extension. */
+ return;
+
+ } else if (r == -ENOSPC) {
+ DRM_INFO("Not enoigh PCI address space for a large BAR.");
+ } else if (r) {
+ DRM_ERROR("Problem resizing BAR0 (%d).", r);
+ }
+
+ /* Reinit the doorbell mapping, it is most likely moved as well */
+ amdgpu_doorbell_fini(adev);
+ BUG_ON(amdgpu_doorbell_init(adev));
+}
+
/*
* GPU helpers function.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index dc9b6d6..36a7aa5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -367,13 +367,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
break;
}
adev->mc.vram_width = numchan * chansize;
- /* Could aper size report 0 ? */
- adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
/* size in MB on si */
adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
+ if (!(adev->flags & AMD_IS_APU))
+ amdgpu_resize_bar0(adev);
+ adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
+ adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
+
#ifdef CONFIG_X86_64
if (adev->flags & AMD_IS_APU) {
adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index c087b00..7761ad3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -459,13 +459,15 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
break;
}
adev->mc.vram_width = numchan * chansize;
- /* Could aper size report 0 ? */
- adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
/* size in MB on si */
adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
+ if (!(adev->flags & AMD_IS_APU))
+ amdgpu_resize_bar0(adev);
+ adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
+ adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
+
#ifdef CONFIG_X86_64
if (adev->flags & AMD_IS_APU) {
adev->mc
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
Is it possible on Carrizo asics? Or only supports on newer asics?
On Mon, Mar 13, 2017 at 6:11 PM, Christian König
wrote:
> From: Christian König
>
> Try to resize BAR0 to let CPU access all of VRAM.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 +
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +---
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +---
> 4 files changed, 40 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 3b81ded..905ded9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
> *adev, struct ttm_tt *ttm,
> struct ttm_mem_reg *mem);
> void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc,
> u64 base);
> void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
> +void amdgpu_resize_bar0(struct amdgpu_device *adev);
> void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
> int amdgpu_ttm_init(struct amdgpu_device *adev);
> void amdgpu_ttm_fini(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 118f4e6..92955fe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -692,6 +692,35 @@ void amdgpu_gtt_location(struct amdgpu_device *adev,
> struct amdgpu_mc *mc)
> mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
> }
>
> +/**
> + * amdgpu_resize_bar0 - try to resize BAR0
> + *
> + * @adev: amdgpu_device pointer
> + *
> + * Try to resize BAR0 to make all VRAM CPU accessible.
> + */
> +void amdgpu_resize_bar0(struct amdgpu_device *adev)
> +{
> + u32 size = max(ilog2(adev->mc.real_vram_size - 1) + 1, 20) - 20;
> + int r;
> +
> + r = pci_resize_resource(adev->pdev, 0, size);
> +
> + if (r == -ENOTSUPP) {
> + /* The hardware don't support the extension. */
> + return;
> +
> + } else if (r == -ENOSPC) {
> + DRM_INFO("Not enoigh PCI address space for a large BAR.");
> + } else if (r) {
> + DRM_ERROR("Problem resizing BAR0 (%d).", r);
> + }
> +
> + /* Reinit the doorbell mapping, it is most likely moved as well */
> + amdgpu_doorbell_fini(adev);
> + BUG_ON(amdgpu_doorbell_init(adev));
> +}
> +
> /*
> * GPU helpers function.
> */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index dc9b6d6..36a7aa5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -367,13 +367,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
> break;
> }
> adev->mc.vram_width = numchan * chansize;
> - /* Could aper size report 0 ? */
> - adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
> - adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
> /* size in MB on si */
> adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
> adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL *
> 1024ULL;
>
> + if (!(adev->flags & AMD_IS_APU))
> + amdgpu_resize_bar0(adev);
> + adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
> + adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
> +
> #ifdef CONFIG_X86_64
> if (adev->flags & AMD_IS_APU) {
> adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index c087b00..7761ad3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -459,13 +459,15 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
> break;
> }
> adev->mc.vram_width = numchan * chansize;
> - /* Could aper size report 0 ? */
> - adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
> - adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
> /* size in MB on si */
> adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
> adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL *
> 1024ULL;
>
> + if (!(adev->flags & AMD_IS_APU))
> + amdgpu_resize_bar0(adev);
> + adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
> + adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
> +
> #ifdef CONFIG_X86_64
> if (adev->flags & AMD_IS_APU) {
> adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
> --
> 2.7.4
>
> _
Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
On Mon, Mar 13, 2017 at 2:41 PM, Christian König
wrote:
> From: Christian König
>
> Try to resize BAR0 to let CPU access all of VRAM.
> +void amdgpu_resize_bar0(struct amdgpu_device *adev)
> +{
> + u32 size = max(ilog2(adev->mc.real_vram_size - 1) + 1, 20) - 20;
> + int r;
> +
> + r = pci_resize_resource(adev->pdev, 0, size);
> +
Redundant.
> + if (r == -ENOTSUPP) {
> + /* The hardware don't support the extension. */
> + return;
> +
Ditto.
> + } else if (r == -ENOSPC) {
Useless use of else. And thus of curly braces.
> + DRM_INFO("Not enoigh PCI address space for a large BAR.");
> + } else if (r) {
> + DRM_ERROR("Problem resizing BAR0 (%d).", r);
> + }
> +
> + /* Reinit the doorbell mapping, it is most likely moved as well */
> + amdgpu_doorbell_fini(adev);
> + BUG_ON(amdgpu_doorbell_init(adev));
Comment why it's used here.
--
With Best Regards,
Andy Shevchenko
