Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset
* Andi Kleen wrote: > On Tue, Feb 12, 2013 at 09:43:46AM +0100, Ingo Molnar wrote: > > Was this stress-tested on all affected main CPU types, or only > > on Haswell? > > I tested it on Haswell and Ivy Bridge. I can also try Westmere > and a Saltwell(Atom), but for the majority of other family 6 > systems I'll need to rely on the community. The systems you tested should be OK. > White listing is somewhat difficult because it affects the > architectural mode too. Yeah, I'd rather avoid that. > I don't really expect problems from this change, we should > probably have always done it like this. I expect potential problems: the ordering of the operations in the NMI handler was always very fragile, resulting in hard to debug hangs - which sometimes needed hours long very intense PMU stress-testing to trigger. That is why I asked how heavily you've tested this. Once the series passes review I'll keep this patch last to make it easy to revert/zap if it causes problems. Thanks, Ingo -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset
* Andi Kleen a...@firstfloor.org wrote: On Tue, Feb 12, 2013 at 09:43:46AM +0100, Ingo Molnar wrote: Was this stress-tested on all affected main CPU types, or only on Haswell? I tested it on Haswell and Ivy Bridge. I can also try Westmere and a Saltwell(Atom), but for the majority of other family 6 systems I'll need to rely on the community. The systems you tested should be OK. White listing is somewhat difficult because it affects the architectural mode too. Yeah, I'd rather avoid that. I don't really expect problems from this change, we should probably have always done it like this. I expect potential problems: the ordering of the operations in the NMI handler was always very fragile, resulting in hard to debug hangs - which sometimes needed hours long very intense PMU stress-testing to trigger. That is why I asked how heavily you've tested this. Once the series passes review I'll keep this patch last to make it easy to revert/zap if it causes problems. Thanks, Ingo -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset
On Tue, Feb 12, 2013 at 09:43:46AM +0100, Ingo Molnar wrote: > Was this stress-tested on all affected main CPU types, or only > on Haswell? I tested it on Haswell and Ivy Bridge. I can also try Westmere and a Saltwell(Atom), but for the majority of other family 6 systems I'll need to rely on the community. White listing is somewhat difficult because it affects the architectural mode too. I don't really expect problems from this change, we should probably have always done it like this. -Andi -- a...@linux.intel.com -- Speaking for myself only. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset
* Andi Kleen wrote: > From: Andi Kleen > > This avoids some problems with spurious PMIs on Haswell. > Haswell seems to behave more like P4 in this regard. Do > the same thing as the P4 perf handler by unmasking > the NMI only at the end. Shouldn't make any difference > for earlier non P4 cores. Was this stress-tested on all affected main CPU types, or only on Haswell? Thanks, Ingo -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset
* Andi Kleen a...@firstfloor.org wrote: From: Andi Kleen a...@linux.intel.com This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any difference for earlier non P4 cores. Was this stress-tested on all affected main CPU types, or only on Haswell? Thanks, Ingo -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset
On Tue, Feb 12, 2013 at 09:43:46AM +0100, Ingo Molnar wrote: Was this stress-tested on all affected main CPU types, or only on Haswell? I tested it on Haswell and Ivy Bridge. I can also try Westmere and a Saltwell(Atom), but for the majority of other family 6 systems I'll need to rely on the community. White listing is somewhat difficult because it affects the architectural mode too. I don't really expect problems from this change, we should probably have always done it like this. -Andi -- a...@linux.intel.com -- Speaking for myself only. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
