Re: [PATCH 5/5] phy: tegra: xusb: Add Tegra186 support
On Thu, Feb 07, 2019 at 05:17:59PM +0530, Kishon Vijay Abraham I wrote: > Hi, > > On 25/01/19 4:55 PM, Thierry Reding wrote: > > From: JC Kuo > > > > Add support for the XUSB pad controller found on Tegra186 SoCs. It is > > mostly similar to the same IP found on earlier chips, but the number of > > pads exposed differs, as do the programming sequences. > > > > Note that the DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL power > > supplies of the XUSB pad controller require strict power sequencing and > > are therefore controlled by the PMIC on Tegra186. > > > > Signed-off-by: JC Kuo > > Signed-off-by: Thierry Reding > > --- > > MAINTAINERS | 5 + > > drivers/phy/tegra/Makefile| 1 + > > drivers/phy/tegra/xusb-tegra186.c | 908 ++ > > drivers/phy/tegra/xusb.c | 6 + > > drivers/phy/tegra/xusb.h | 27 + > > 5 files changed, 947 insertions(+) > > create mode 100644 drivers/phy/tegra/xusb-tegra186.c > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index ddcdc29dfe1f..754f7e757361 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -15099,6 +15099,11 @@ M: Laxman Dewangan > > S: Supported > > F: drivers/spi/spi-tegra* > > > > +TEGRA XUSB PADCTL DRIVER > > +M: JC Kuo > > +S: Supported > > +F: drivers/phy/tegra/xusb* > > + > > TEHUTI ETHERNET DRIVER > > M: Andy Gospodarek > > L: net...@vger.kernel.org > > diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile > > index 898589238fd9..a93cd9a499b2 100644 > > --- a/drivers/phy/tegra/Makefile > > +++ b/drivers/phy/tegra/Makefile > > @@ -4,3 +4,4 @@ phy-tegra-xusb-y += xusb.o > > phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o > > phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o > > phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o > > +phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o > > diff --git a/drivers/phy/tegra/xusb-tegra186.c > > b/drivers/phy/tegra/xusb-tegra186.c > > new file mode 100644 > > index ..0dbcaddade90 > > --- /dev/null > > +++ b/drivers/phy/tegra/xusb-tegra186.c > > @@ -0,0 +1,908 @@ > > +/* > > + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. > > + * > > + * This program is free software; you can redistribute it and/or modify it > > + * under the terms and conditions of the GNU General Public License, > > + * version 2, as published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope it will be useful, but WITHOUT > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > > for > > + * more details. > > + */ > > please use SPDX license format. Done. > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > + > > +#include "xusb.h" > > + > > +/* FUSE USB_CALIB registers */ > > +#define HS_CURR_LEVEL_PADX_SHIFT(x)((x) ? (11 + (x - 1) * 6) : 0) > > +#define HS_CURR_LEVEL_PAD_MASK 0x3f > > +#define HS_TERM_RANGE_ADJ_SHIFT7 > > +#define HS_TERM_RANGE_ADJ_MASK 0xf > > +#define HS_SQUELCH_SHIFT 29 > > +#define HS_SQUELCH_MASK0x7 > > + > > +#define RPD_CTRL_SHIFT 0 > > +#define RPD_CTRL_MASK 0x1f > > + > > +/* XUSB PADCTL registers */ > > +#define XUSB_PADCTL_USB2_PAD_MUX 0x4 > > +#define USB2_PORT_SHIFT(x)((x) * 2) > > +#define USB2_PORT_MASK0x3 > > +#define PORT_XUSB1 > > +#define HSIC_PORT_SHIFT(x)((x) + 20) > > +#define HSIC_PORT_MASK0x1 > > +#define PORT_HSIC0 > > + > > +#define XUSB_PADCTL_USB2_PORT_CAP 0x8 > > +#define XUSB_PADCTL_SS_PORT_CAP0xc > > +#define PORTX_CAP_SHIFT(x)((x) * 4) > > +#define PORT_CAP_MASK 0x3 > > +#define PORT_CAP_DISABLED0x0 > > +#define PORT_CAP_HOST0x1 > > +#define PORT_CAP_DEVICE 0x2 > > +#define PORT_CAP_OTG 0x3 > > + > > +#define XUSB_PADCTL_ELPG_PROGRAM 0x20 > > +#define USB2_PORT_WAKE_INTERRUPT_ENABLE(x)(1 << (x)) > > Use BIT() macros here and below Done. > > +#define USB2_PORT_WAKEUP_EVENT(x) ( 1 << ((x) + 7)) > > +#define SS_PORT_WAKE_INTERRUPT_ENABLE(x) (1 << ((x) + 14)) > > +#define SS_PORT_WAKEUP_EVENT(x) (1 << ((x) + 21)) > > +#define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) (1 << ((x) + 28)) > > +#define USB2_HSIC_PORT_WAKEUP_EVENT(x)(1 << ((x) + > > 30)) > > +#define ALL_WAKE_EVENTS \ > > + (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) |
Re: [PATCH 5/5] phy: tegra: xusb: Add Tegra186 support
Hi, On 25/01/19 4:55 PM, Thierry Reding wrote: > From: JC Kuo > > Add support for the XUSB pad controller found on Tegra186 SoCs. It is > mostly similar to the same IP found on earlier chips, but the number of > pads exposed differs, as do the programming sequences. > > Note that the DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL power > supplies of the XUSB pad controller require strict power sequencing and > are therefore controlled by the PMIC on Tegra186. > > Signed-off-by: JC Kuo > Signed-off-by: Thierry Reding > --- > MAINTAINERS | 5 + > drivers/phy/tegra/Makefile| 1 + > drivers/phy/tegra/xusb-tegra186.c | 908 ++ > drivers/phy/tegra/xusb.c | 6 + > drivers/phy/tegra/xusb.h | 27 + > 5 files changed, 947 insertions(+) > create mode 100644 drivers/phy/tegra/xusb-tegra186.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index ddcdc29dfe1f..754f7e757361 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -15099,6 +15099,11 @@ M: Laxman Dewangan > S: Supported > F: drivers/spi/spi-tegra* > > +TEGRA XUSB PADCTL DRIVER > +M: JC Kuo > +S: Supported > +F: drivers/phy/tegra/xusb* > + > TEHUTI ETHERNET DRIVER > M: Andy Gospodarek > L: net...@vger.kernel.org > diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile > index 898589238fd9..a93cd9a499b2 100644 > --- a/drivers/phy/tegra/Makefile > +++ b/drivers/phy/tegra/Makefile > @@ -4,3 +4,4 @@ phy-tegra-xusb-y += xusb.o > phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o > phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o > phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o > +phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o > diff --git a/drivers/phy/tegra/xusb-tegra186.c > b/drivers/phy/tegra/xusb-tegra186.c > new file mode 100644 > index ..0dbcaddade90 > --- /dev/null > +++ b/drivers/phy/tegra/xusb-tegra186.c > @@ -0,0 +1,908 @@ > +/* > + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + */ please use SPDX license format. > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include "xusb.h" > + > +/* FUSE USB_CALIB registers */ > +#define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0) > +#define HS_CURR_LEVEL_PAD_MASK 0x3f > +#define HS_TERM_RANGE_ADJ_SHIFT 7 > +#define HS_TERM_RANGE_ADJ_MASK 0xf > +#define HS_SQUELCH_SHIFT 29 > +#define HS_SQUELCH_MASK 0x7 > + > +#define RPD_CTRL_SHIFT 0 > +#define RPD_CTRL_MASK0x1f > + > +/* XUSB PADCTL registers */ > +#define XUSB_PADCTL_USB2_PAD_MUX 0x4 > +#define USB2_PORT_SHIFT(x) ((x) * 2) > +#define USB2_PORT_MASK 0x3 > +#define PORT_XUSB 1 > +#define HSIC_PORT_SHIFT(x) ((x) + 20) > +#define HSIC_PORT_MASK 0x1 > +#define PORT_HSIC 0 > + > +#define XUSB_PADCTL_USB2_PORT_CAP0x8 > +#define XUSB_PADCTL_SS_PORT_CAP 0xc > +#define PORTX_CAP_SHIFT(x) ((x) * 4) > +#define PORT_CAP_MASK 0x3 > +#define PORT_CAP_DISABLED 0x0 > +#define PORT_CAP_HOST 0x1 > +#define PORT_CAP_DEVICE0x2 > +#define PORT_CAP_OTG 0x3 > + > +#define XUSB_PADCTL_ELPG_PROGRAM 0x20 > +#define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) (1 << (x)) Use BIT() macros here and below > +#define USB2_PORT_WAKEUP_EVENT(x) ( 1 << ((x) + 7)) > +#define SS_PORT_WAKE_INTERRUPT_ENABLE(x)(1 << ((x) + 14)) > +#define SS_PORT_WAKEUP_EVENT(x) (1 << ((x) + 21)) > +#define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) (1 << ((x) + 28)) > +#define USB2_HSIC_PORT_WAKEUP_EVENT(x) (1 << ((x) + > 30)) > +#define ALL_WAKE_EVENTS \ > + (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) |\ > + USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \ > + SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \ > + USB2_HSIC_PORT_WAKEUP_EVENT(0)) > + > +#define XUSB_PADCTL_ELPG_PROGRAM_1 0x24 > +#define SSPX_ELPG_CLAMP_EN(x) (1 << (0 + (x) * 3))
Re: [PATCH 5/5] phy: tegra: xusb: Add Tegra186 support
Reviewed-by: JC Kuo On 1/25/19 7:25 PM, Thierry Reding wrote: From: JC Kuo Add support for the XUSB pad controller found on Tegra186 SoCs. It is mostly similar to the same IP found on earlier chips, but the number of pads exposed differs, as do the programming sequences. Note that the DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL power supplies of the XUSB pad controller require strict power sequencing and are therefore controlled by the PMIC on Tegra186. Signed-off-by: JC Kuo Signed-off-by: Thierry Reding --- MAINTAINERS | 5 + drivers/phy/tegra/Makefile| 1 + drivers/phy/tegra/xusb-tegra186.c | 908 ++ drivers/phy/tegra/xusb.c | 6 + drivers/phy/tegra/xusb.h | 27 + 5 files changed, 947 insertions(+) create mode 100644 drivers/phy/tegra/xusb-tegra186.c diff --git a/MAINTAINERS b/MAINTAINERS index ddcdc29dfe1f..754f7e757361 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15099,6 +15099,11 @@ M: Laxman Dewangan S:Supported F:drivers/spi/spi-tegra* +TEGRA XUSB PADCTL DRIVER +M: JC Kuo +S: Supported +F: drivers/phy/tegra/xusb* + TEHUTI ETHERNET DRIVER M:Andy Gospodarek L:net...@vger.kernel.org diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile index 898589238fd9..a93cd9a499b2 100644 --- a/drivers/phy/tegra/Makefile +++ b/drivers/phy/tegra/Makefile @@ -4,3 +4,4 @@ phy-tegra-xusb-y += xusb.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o +phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c new file mode 100644 index ..0dbcaddade90 --- /dev/null +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -0,0 +1,908 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "xusb.h" + +/* FUSE USB_CALIB registers */ +#define HS_CURR_LEVEL_PADX_SHIFT(x)((x) ? (11 + (x - 1) * 6) : 0) +#define HS_CURR_LEVEL_PAD_MASK 0x3f +#define HS_TERM_RANGE_ADJ_SHIFT7 +#define HS_TERM_RANGE_ADJ_MASK 0xf +#define HS_SQUELCH_SHIFT 29 +#define HS_SQUELCH_MASK0x7 + +#define RPD_CTRL_SHIFT 0 +#define RPD_CTRL_MASK 0x1f + +/* XUSB PADCTL registers */ +#define XUSB_PADCTL_USB2_PAD_MUX 0x4 +#define USB2_PORT_SHIFT(x)((x) * 2) +#define USB2_PORT_MASK0x3 +#define PORT_XUSB1 +#define HSIC_PORT_SHIFT(x)((x) + 20) +#define HSIC_PORT_MASK0x1 +#define PORT_HSIC0 + +#define XUSB_PADCTL_USB2_PORT_CAP 0x8 +#define XUSB_PADCTL_SS_PORT_CAP0xc +#define PORTX_CAP_SHIFT(x)((x) * 4) +#define PORT_CAP_MASK 0x3 +#define PORT_CAP_DISABLED0x0 +#define PORT_CAP_HOST0x1 +#define PORT_CAP_DEVICE 0x2 +#define PORT_CAP_OTG 0x3 + +#define XUSB_PADCTL_ELPG_PROGRAM 0x20 +#define USB2_PORT_WAKE_INTERRUPT_ENABLE(x)(1 << (x)) +#define USB2_PORT_WAKEUP_EVENT(x) ( 1 << ((x) + 7)) +#define SS_PORT_WAKE_INTERRUPT_ENABLE(x) (1 << ((x) + 14)) +#define SS_PORT_WAKEUP_EVENT(x) (1 << ((x) + 21)) +#define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) (1 << ((x) + 28)) +#define USB2_HSIC_PORT_WAKEUP_EVENT(x)(1 << ((x) + 30)) +#define ALL_WAKE_EVENTS \ + (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) |\ + USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \ + SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \ + USB2_HSIC_PORT_WAKEUP_EVENT(0)) + +#define XUSB_PADCTL_ELPG_PROGRAM_1 0x24 +#define SSPX_ELPG_CLAMP_EN(x) (1 << (0 + (x) * 3)) +#define SSPX_ELPG_CLAMP_EN_EARLY(x) (1 << (1 + (x) * 3)) +#define SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3)) + +#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40) +#define HS_CURR_LEVEL(x)
