Re: [PATCH V3 0/5] Updates to EDAC and AMD MCE driver
On 3/3/16 12:45 PM, Borislav Petkov wrote: Applied, minor stuff corrected and pushed out to http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git/log/?h=tip-ras so that the 0day bot can chew on them a little. Thanks! -Aravind.
Re: [PATCH V3 0/5] Updates to EDAC and AMD MCE driver
On 3/3/16 12:45 PM, Borislav Petkov wrote: Applied, minor stuff corrected and pushed out to http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git/log/?h=tip-ras so that the 0day bot can chew on them a little. Thanks! -Aravind.
Re: [PATCH V3 0/5] Updates to EDAC and AMD MCE driver
On Thu, Mar 03, 2016 at 10:10:53AM -0600, Aravind Gopalakrishnan wrote: > This patchset mainly provides necessary EDAC bits to decode errors > occuring on Scalable MCA enabled processors and also updates AMD MCE > driver to program the correct MCx_MISC register address for upcoming > processors. > > Patches 1, 2 and 3 are for upcoming processor. > > Patches 4 and 5 are either fixing or adding comments to help in > understanding the code and do not introduce any functional changes. > > Patch 1: Move MSR definition to mce.h > Patch 2: Updates to EDAC driver to decode the new error signatures > Patch 3: Fix logic to obtain correct block address > Patch 4: Fix deferred error comment > Patch 5: Add comments to amd_nb.h to describe threshold_block structure > > Note 1: Introduced new patch for moving MCx_CONFIG MSR to mce.h > Note 2: The enums, amd_hwids[], and string arrays amd_core_mcablock_names[], > amd_df_mcablock_names[] are placed in arch/x86 as there are > follow-up patches which use them here. > > Changes from V1: (per Boris suggestions) > - Simplify error decoding routines > - Move headers to mce.h > - Rename enumerations and struct members (to be more descriptive) > - Drop gerund usage > - Remove comments that are spelling out the code > > Changes from V2: (per Boris suggestions) > - Incorporated all changes as suggested by Boris from here- > - http://marc.info/?l=linux-kernel=145691594921586=2 > - http://marc.info/?l=linux-kernel=145691606221610=2 > - http://marc.info/?l=linux-kernel=145691610421627=2 > - No functional change is introduced > > Aravind Gopalakrishnan (5): > x86/mce: Move MCx_CONFIG MSR definition > EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors > x86/mce/AMD: Fix logic to obtain block address > x86/mce: Clarify comments regarding deferred error > x86/mce/AMD: Add comments for easier understanding > > arch/x86/include/asm/amd_nb.h| 18 +- > arch/x86/include/asm/mce.h | 69 +++- > arch/x86/include/asm/msr-index.h | 4 - > arch/x86/kernel/cpu/mcheck/mce_amd.c | 127 + > drivers/edac/mce_amd.c | 334 > ++- > 5 files changed, 501 insertions(+), 51 deletions(-) Applied, minor stuff corrected and pushed out to http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git/log/?h=tip-ras so that the 0day bot can chew on them a little. Thanks. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply.
Re: [PATCH V3 0/5] Updates to EDAC and AMD MCE driver
On Thu, Mar 03, 2016 at 10:10:53AM -0600, Aravind Gopalakrishnan wrote: > This patchset mainly provides necessary EDAC bits to decode errors > occuring on Scalable MCA enabled processors and also updates AMD MCE > driver to program the correct MCx_MISC register address for upcoming > processors. > > Patches 1, 2 and 3 are for upcoming processor. > > Patches 4 and 5 are either fixing or adding comments to help in > understanding the code and do not introduce any functional changes. > > Patch 1: Move MSR definition to mce.h > Patch 2: Updates to EDAC driver to decode the new error signatures > Patch 3: Fix logic to obtain correct block address > Patch 4: Fix deferred error comment > Patch 5: Add comments to amd_nb.h to describe threshold_block structure > > Note 1: Introduced new patch for moving MCx_CONFIG MSR to mce.h > Note 2: The enums, amd_hwids[], and string arrays amd_core_mcablock_names[], > amd_df_mcablock_names[] are placed in arch/x86 as there are > follow-up patches which use them here. > > Changes from V1: (per Boris suggestions) > - Simplify error decoding routines > - Move headers to mce.h > - Rename enumerations and struct members (to be more descriptive) > - Drop gerund usage > - Remove comments that are spelling out the code > > Changes from V2: (per Boris suggestions) > - Incorporated all changes as suggested by Boris from here- > - http://marc.info/?l=linux-kernel=145691594921586=2 > - http://marc.info/?l=linux-kernel=145691606221610=2 > - http://marc.info/?l=linux-kernel=145691610421627=2 > - No functional change is introduced > > Aravind Gopalakrishnan (5): > x86/mce: Move MCx_CONFIG MSR definition > EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors > x86/mce/AMD: Fix logic to obtain block address > x86/mce: Clarify comments regarding deferred error > x86/mce/AMD: Add comments for easier understanding > > arch/x86/include/asm/amd_nb.h| 18 +- > arch/x86/include/asm/mce.h | 69 +++- > arch/x86/include/asm/msr-index.h | 4 - > arch/x86/kernel/cpu/mcheck/mce_amd.c | 127 + > drivers/edac/mce_amd.c | 334 > ++- > 5 files changed, 501 insertions(+), 51 deletions(-) Applied, minor stuff corrected and pushed out to http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git/log/?h=tip-ras so that the 0day bot can chew on them a little. Thanks. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply.
