Re: [PATCH v1 2/3] nvmem: Add the Broadcom OTP controller driver

[Florian Fainelli]

On 10/31/2016 12:55 PM, Scott Branden wrote:
> Florian,
> 
> On 16-10-31 07:23 AM, Srinivas Kandagatla wrote:
>>
>> On 24/10/16 20:12, Jonathan Richardson wrote:
>>> From: Jonathan Richardson 
>>>
>>> Add support for 32 and 64-bit versions of Broadcom's On-Chip OTP
>>> controller. These controllers are used on SoC's such as Cygnus and
>>> Stingray.
>>>
>>> Reviewed-by: Ray Jui 
>>> Tested-by: Jonathan Richardson 
>>> Signed-off-by: Scott Branden 
>>> Signed-off-by: Oza Pawandeep 
>>> Signed-off-by: Jonathan Richardson 
>>> ---
>>>  drivers/nvmem/Kconfig |  12 ++
>>>  drivers/nvmem/Makefile|   2 +
>>>  drivers/nvmem/bcm-ocotp.c | 335
>>> ++
>>>  3 files changed, 349 insertions(+)
>>>  create mode 100644 drivers/nvmem/bcm-ocotp.c
>>
>>
>> I can pick this patch along with dt bindings document, but dts patch has
>> to go via arm-soc tree.
> 
> Can you pick up [PATCH v1 3/3] ARM: dts: Add node from Broadcom OTP
> controller driver?

As soon as we get Rob's acked-by for Patch 1, sure.
-- 
Florian

Re: [PATCH v1 2/3] nvmem: Add the Broadcom OTP controller driver

[Florian Fainelli]

On 10/31/2016 12:55 PM, Scott Branden wrote:
> Florian,
> 
> On 16-10-31 07:23 AM, Srinivas Kandagatla wrote:
>>
>> On 24/10/16 20:12, Jonathan Richardson wrote:
>>> From: Jonathan Richardson 
>>>
>>> Add support for 32 and 64-bit versions of Broadcom's On-Chip OTP
>>> controller. These controllers are used on SoC's such as Cygnus and
>>> Stingray.
>>>
>>> Reviewed-by: Ray Jui 
>>> Tested-by: Jonathan Richardson 
>>> Signed-off-by: Scott Branden 
>>> Signed-off-by: Oza Pawandeep 
>>> Signed-off-by: Jonathan Richardson 
>>> ---
>>>  drivers/nvmem/Kconfig |  12 ++
>>>  drivers/nvmem/Makefile|   2 +
>>>  drivers/nvmem/bcm-ocotp.c | 335
>>> ++
>>>  3 files changed, 349 insertions(+)
>>>  create mode 100644 drivers/nvmem/bcm-ocotp.c
>>
>>
>> I can pick this patch along with dt bindings document, but dts patch has
>> to go via arm-soc tree.
> 
> Can you pick up [PATCH v1 3/3] ARM: dts: Add node from Broadcom OTP
> controller driver?

As soon as we get Rob's acked-by for Patch 1, sure.
-- 
Florian

Re: [PATCH v1 2/3] nvmem: Add the Broadcom OTP controller driver

[Scott Branden]

Florian,

On 16-10-31 07:23 AM, Srinivas Kandagatla wrote:


On 24/10/16 20:12, Jonathan Richardson wrote:

From: Jonathan Richardson 

Add support for 32 and 64-bit versions of Broadcom's On-Chip OTP
controller. These controllers are used on SoC's such as Cygnus and
Stingray.

Reviewed-by: Ray Jui 
Tested-by: Jonathan Richardson 
Signed-off-by: Scott Branden 
Signed-off-by: Oza Pawandeep 
Signed-off-by: Jonathan Richardson 
---
 drivers/nvmem/Kconfig |  12 ++
 drivers/nvmem/Makefile|   2 +
 drivers/nvmem/bcm-ocotp.c | 335
++
 3 files changed, 349 insertions(+)
 create mode 100644 drivers/nvmem/bcm-ocotp.c



I can pick this patch along with dt bindings document, but dts patch has
to go via arm-soc tree.


Can you pick up [PATCH v1 3/3] ARM: dts: Add node from Broadcom OTP 
controller driver?




Thanks,
srini



Thanks,
 Scott

Re: [PATCH v1 2/3] nvmem: Add the Broadcom OTP controller driver

[Scott Branden]

Florian,

On 16-10-31 07:23 AM, Srinivas Kandagatla wrote:


On 24/10/16 20:12, Jonathan Richardson wrote:

From: Jonathan Richardson 

Add support for 32 and 64-bit versions of Broadcom's On-Chip OTP
controller. These controllers are used on SoC's such as Cygnus and
Stingray.

Reviewed-by: Ray Jui 
Tested-by: Jonathan Richardson 
Signed-off-by: Scott Branden 
Signed-off-by: Oza Pawandeep 
Signed-off-by: Jonathan Richardson 
---
 drivers/nvmem/Kconfig |  12 ++
 drivers/nvmem/Makefile|   2 +
 drivers/nvmem/bcm-ocotp.c | 335
++
 3 files changed, 349 insertions(+)
 create mode 100644 drivers/nvmem/bcm-ocotp.c



I can pick this patch along with dt bindings document, but dts patch has
to go via arm-soc tree.


Can you pick up [PATCH v1 3/3] ARM: dts: Add node from Broadcom OTP 
controller driver?




Thanks,
srini



Thanks,
 Scott

Re: [PATCH v1 2/3] nvmem: Add the Broadcom OTP controller driver

[Srinivas Kandagatla]

On 24/10/16 20:12, Jonathan Richardson wrote:

From: Jonathan Richardson 

Add support for 32 and 64-bit versions of Broadcom's On-Chip OTP
controller. These controllers are used on SoC's such as Cygnus and
Stingray.

Reviewed-by: Ray Jui 
Tested-by: Jonathan Richardson 
Signed-off-by: Scott Branden 
Signed-off-by: Oza Pawandeep 
Signed-off-by: Jonathan Richardson 
---
 drivers/nvmem/Kconfig |  12 ++
 drivers/nvmem/Makefile|   2 +
 drivers/nvmem/bcm-ocotp.c | 335 ++
 3 files changed, 349 insertions(+)
 create mode 100644 drivers/nvmem/bcm-ocotp.c



I can pick this patch along with dt bindings document, but dts patch has 
to go via arm-soc tree.


Thanks,
srini




diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index ba140ea..06935a7 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -80,6 +80,18 @@ config ROCKCHIP_EFUSE
  This driver can also be built as a module. If so, the module
  will be called nvmem_rockchip_efuse.

+config NVMEM_BCM_OCOTP
+   tristate "Broadcom On-Chip OTP Controller support"
+   depends on ARCH_BCM_IPROC || COMPILE_TEST
+   depends on HAS_IOMEM
+   default ARCH_BCM_IPROC

?

+   help
+ Say y here to enable read/write access to the Broadcom OTP
+ controller.
+
+ This driver can also be built as a module. If so, the module
+ will be called nvmem-bcm-ocotp.
+
 config NVMEM_SUNXI_SID
tristate "Allwinner SoCs SID support"
depends on ARCH_SUNXI
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 8f942a0..71781ca 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -6,6 +6,8 @@ obj-$(CONFIG_NVMEM) += nvmem_core.o
 nvmem_core-y   := core.o

 # Devices
+obj-$(CONFIG_NVMEM_BCM_OCOTP)  += nvmem-bcm-ocotp.o
+nvmem-bcm-ocotp-y  := bcm-ocotp.o
 obj-$(CONFIG_NVMEM_IMX_OCOTP)  += nvmem-imx-ocotp.o
 nvmem-imx-ocotp-y  := imx-ocotp.o
 obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o
diff --git a/drivers/nvmem/bcm-ocotp.c b/drivers/nvmem/bcm-ocotp.c
new file mode 100644
index 000..646cadb
--- /dev/null
+++ b/drivers/nvmem/bcm-ocotp.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (C) 2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * # of tries for OTP Status. The time to execute a command varies. The slowest
+ * commands are writes which also vary based on the # of bits turned on. 
Writing
+ * 0x takes ~3800 us.
+ */
+#define OTPC_RETRIES 5000
+
+/* Sequence to enable OTP program */
+#define OTPC_PROG_EN_SEQ { 0xf, 0x4, 0x8, 0xd }
+
+/* OTPC Commands */
+#define OTPC_CMD_READ0x0
+#define OTPC_CMD_OTP_PROG_ENABLE 0x2
+#define OTPC_CMD_OTP_PROG_DISABLE0x3
+#define OTPC_CMD_PROGRAM 0xA
+
+/* OTPC Status Bits */
+#define OTPC_STAT_CMD_DONE   BIT(1)
+#define OTPC_STAT_PROG_OKBIT(2)
+
+/* OTPC register definition */
+#define OTPC_MODE_REG_OFFSET 0x0
+#define OTPC_MODE_REG_OTPC_MODE  0
+#define OTPC_COMMAND_OFFSET  0x4
+#define OTPC_COMMAND_COMMAND_WIDTH   6
+#define OTPC_CMD_START_OFFSET0x8
+#define OTPC_CMD_START_START 0
+#define OTPC_CPU_STATUS_OFFSET   0xc
+#define OTPC_CPUADDR_REG_OFFSET  0x28
+#define OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH 16
+#define OTPC_CPU_WRITE_REG_OFFSET0x2c
+
+#define OTPC_CMD_MASK  (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1)
+#define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1)
+
+
+struct otpc_map {
+   /* in words. */
+   u32 otpc_row_size;
+   /* 128 bit row / 4 words support. */
+   u16 data_r_offset[4];
+   /* 128 bit row / 4 words support. */
+   u16 data_w_offset[4];
+};
+
+static struct otpc_map otp_map = {
+   .otpc_row_size = 1,
+   .data_r_offset = {0x10},
+   .data_w_offset = {0x2c},
+};
+
+static struct otpc_map otp_map_v2 = {
+   .otpc_row_size = 2,
+   .data_r_offset = {0x10, 0x5c},
+   .data_w_offset = {0x2c, 0x64},
+};
+
+struct otpc_priv {
+   struct device   *dev;
+   void __iomem*base;
+   struct otpc_map *map;
+   struct nvmem_config *config;
+};
+
+static inline void set_command(void __iomem *base, 

Re: [PATCH v1 2/3] nvmem: Add the Broadcom OTP controller driver

[Srinivas Kandagatla]

On 24/10/16 20:12, Jonathan Richardson wrote:

From: Jonathan Richardson 

Add support for 32 and 64-bit versions of Broadcom's On-Chip OTP
controller. These controllers are used on SoC's such as Cygnus and
Stingray.

Reviewed-by: Ray Jui 
Tested-by: Jonathan Richardson 
Signed-off-by: Scott Branden 
Signed-off-by: Oza Pawandeep 
Signed-off-by: Jonathan Richardson 
---
 drivers/nvmem/Kconfig |  12 ++
 drivers/nvmem/Makefile|   2 +
 drivers/nvmem/bcm-ocotp.c | 335 ++
 3 files changed, 349 insertions(+)
 create mode 100644 drivers/nvmem/bcm-ocotp.c



I can pick this patch along with dt bindings document, but dts patch has 
to go via arm-soc tree.


Thanks,
srini




diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index ba140ea..06935a7 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -80,6 +80,18 @@ config ROCKCHIP_EFUSE
  This driver can also be built as a module. If so, the module
  will be called nvmem_rockchip_efuse.

+config NVMEM_BCM_OCOTP
+   tristate "Broadcom On-Chip OTP Controller support"
+   depends on ARCH_BCM_IPROC || COMPILE_TEST
+   depends on HAS_IOMEM
+   default ARCH_BCM_IPROC

?

+   help
+ Say y here to enable read/write access to the Broadcom OTP
+ controller.
+
+ This driver can also be built as a module. If so, the module
+ will be called nvmem-bcm-ocotp.
+
 config NVMEM_SUNXI_SID
tristate "Allwinner SoCs SID support"
depends on ARCH_SUNXI
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 8f942a0..71781ca 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -6,6 +6,8 @@ obj-$(CONFIG_NVMEM) += nvmem_core.o
 nvmem_core-y   := core.o

 # Devices
+obj-$(CONFIG_NVMEM_BCM_OCOTP)  += nvmem-bcm-ocotp.o
+nvmem-bcm-ocotp-y  := bcm-ocotp.o
 obj-$(CONFIG_NVMEM_IMX_OCOTP)  += nvmem-imx-ocotp.o
 nvmem-imx-ocotp-y  := imx-ocotp.o
 obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o
diff --git a/drivers/nvmem/bcm-ocotp.c b/drivers/nvmem/bcm-ocotp.c
new file mode 100644
index 000..646cadb
--- /dev/null
+++ b/drivers/nvmem/bcm-ocotp.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (C) 2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * # of tries for OTP Status. The time to execute a command varies. The slowest
+ * commands are writes which also vary based on the # of bits turned on. 
Writing
+ * 0x takes ~3800 us.
+ */
+#define OTPC_RETRIES 5000
+
+/* Sequence to enable OTP program */
+#define OTPC_PROG_EN_SEQ { 0xf, 0x4, 0x8, 0xd }
+
+/* OTPC Commands */
+#define OTPC_CMD_READ0x0
+#define OTPC_CMD_OTP_PROG_ENABLE 0x2
+#define OTPC_CMD_OTP_PROG_DISABLE0x3
+#define OTPC_CMD_PROGRAM 0xA
+
+/* OTPC Status Bits */
+#define OTPC_STAT_CMD_DONE   BIT(1)
+#define OTPC_STAT_PROG_OKBIT(2)
+
+/* OTPC register definition */
+#define OTPC_MODE_REG_OFFSET 0x0
+#define OTPC_MODE_REG_OTPC_MODE  0
+#define OTPC_COMMAND_OFFSET  0x4
+#define OTPC_COMMAND_COMMAND_WIDTH   6
+#define OTPC_CMD_START_OFFSET0x8
+#define OTPC_CMD_START_START 0
+#define OTPC_CPU_STATUS_OFFSET   0xc
+#define OTPC_CPUADDR_REG_OFFSET  0x28
+#define OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH 16
+#define OTPC_CPU_WRITE_REG_OFFSET0x2c
+
+#define OTPC_CMD_MASK  (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1)
+#define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1)
+
+
+struct otpc_map {
+   /* in words. */
+   u32 otpc_row_size;
+   /* 128 bit row / 4 words support. */
+   u16 data_r_offset[4];
+   /* 128 bit row / 4 words support. */
+   u16 data_w_offset[4];
+};
+
+static struct otpc_map otp_map = {
+   .otpc_row_size = 1,
+   .data_r_offset = {0x10},
+   .data_w_offset = {0x2c},
+};
+
+static struct otpc_map otp_map_v2 = {
+   .otpc_row_size = 2,
+   .data_r_offset = {0x10, 0x5c},
+   .data_w_offset = {0x2c, 0x64},
+};
+
+struct otpc_priv {
+   struct device   *dev;
+   void __iomem*base;
+   struct otpc_map *map;
+   struct nvmem_config *config;
+};
+
+static inline void set_command(void __iomem *base, u32 command)
+{
+   writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET);
+}
+
+static inline void set_cpu_address(void __iomem *base, u32 addr)
+{
+