Re: [PATCH v10 3/3] arm64: dts: mediatek: add xHCI & usb phy for mt8173

[chunfeng yun]

On Sun, 2015-10-18 at 14:01 +0300, Sergei Shtylyov wrote:
> Hello.
> 
> On 10/18/2015 6:51 AM, Chunfeng Yun wrote:
> 
> > add xHCI and phy drivers for MT8173-EVB
> >
> > Signed-off-by: Chunfeng Yun 
> 
> [...]
> 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index d18ee42..46f5f50 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> [...]
> > @@ -487,6 +488,47 @@
> > clock-names = "source", "hclk";
> > status = "disabled";
> > };
> > +
> > +   usb30: usb@1127 {
> > +   compatible = "mediatek,mt8173-xhci";
> > +   reg = <0 0x1127 0 0x1000>,
> > + <0 0x11280700 0 0x0100>;
> > +   interrupts = ;
> > +   power-domains = < MT8173_POWER_DOMAIN_USB>;
> > +   clocks = < CLK_TOP_USB30_SEL>,
> > +< CLK_PERI_USB0>,
> > +< CLK_PERI_USB1>;
> > +   clock-names = "sys_ck",
> > + "wakeup_deb_p0",
> > + "wakeup_deb_p1";
> > +   phys = <_port0 PHY_TYPE_USB3>,
> > +  <_port1 PHY_TYPE_USB2>;
> > +   mediatek,syscon-wakeup = <>;
> > +   status = "okay";
> > +   };
> > +
> > +   u3phy: usb-phy@1129 {
> > +   compatible = "mediatek,mt8173-u3phy";
> > +   reg = <0 0x1129 0 0x800>;
> > +   clocks = < CLK_APMIXED_REF2USB_TX>;
> > +   clock-names = "u3phya_ref";
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +   ranges;
> > +   status = "okay";
> 
> Don't you need the "power-domains" prop here as well?
No, the power-domains of MAC and PHY are separated, but PHY's can't be
operated by software.

Thanks.
> 
> > +
> > +   phy_port0: port@11290800 {
> > +   reg = <0 0x11290800 0 0x800>;
> > +   #phy-cells = <1>;
> > +   status = "okay";
> > +   };
> > +
> > +   phy_port1: port@11291000 {
> > +   reg = <0 0x11291000 0 0x800>;
> > +   #phy-cells = <1>;
> > +   status = "okay";
> > +   };
> > +   };
> > };
> >   };
> >
> 
> MBR, Sergei
> 


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Re: [PATCH v10 3/3] arm64: dts: mediatek: add xHCI & usb phy for mt8173

[Sergei Shtylyov]

Hello.

On 10/18/2015 6:51 AM, Chunfeng Yun wrote:


add xHCI and phy drivers for MT8173-EVB

Signed-off-by: Chunfeng Yun 


[...]


diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index d18ee42..46f5f50 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi

[...]

@@ -487,6 +488,47 @@
clock-names = "source", "hclk";
status = "disabled";
};
+
+   usb30: usb@1127 {
+   compatible = "mediatek,mt8173-xhci";
+   reg = <0 0x1127 0 0x1000>,
+ <0 0x11280700 0 0x0100>;
+   interrupts = ;
+   power-domains = < MT8173_POWER_DOMAIN_USB>;
+   clocks = < CLK_TOP_USB30_SEL>,
+< CLK_PERI_USB0>,
+< CLK_PERI_USB1>;
+   clock-names = "sys_ck",
+ "wakeup_deb_p0",
+ "wakeup_deb_p1";
+   phys = <_port0 PHY_TYPE_USB3>,
+  <_port1 PHY_TYPE_USB2>;
+   mediatek,syscon-wakeup = <>;
+   status = "okay";
+   };
+
+   u3phy: usb-phy@1129 {
+   compatible = "mediatek,mt8173-u3phy";
+   reg = <0 0x1129 0 0x800>;
+   clocks = < CLK_APMIXED_REF2USB_TX>;
+   clock-names = "u3phya_ref";
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+   status = "okay";


   Don't you need the "power-domains" prop here as well?


+
+   phy_port0: port@11290800 {
+   reg = <0 0x11290800 0 0x800>;
+   #phy-cells = <1>;
+   status = "okay";
+   };
+
+   phy_port1: port@11291000 {
+   reg = <0 0x11291000 0 0x800>;
+   #phy-cells = <1>;
+   status = "okay";
+   };
+   };
};
  };



MBR, Sergei

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Re: [PATCH v10 3/3] arm64: dts: mediatek: add xHCI & usb phy for mt8173

[chunfeng yun]

On Sun, 2015-10-18 at 14:01 +0300, Sergei Shtylyov wrote:
> Hello.
> 
> On 10/18/2015 6:51 AM, Chunfeng Yun wrote:
> 
> > add xHCI and phy drivers for MT8173-EVB
> >
> > Signed-off-by: Chunfeng Yun 
> 
> [...]
> 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index d18ee42..46f5f50 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> [...]
> > @@ -487,6 +488,47 @@
> > clock-names = "source", "hclk";
> > status = "disabled";
> > };
> > +
> > +   usb30: usb@1127 {
> > +   compatible = "mediatek,mt8173-xhci";
> > +   reg = <0 0x1127 0 0x1000>,
> > + <0 0x11280700 0 0x0100>;
> > +   interrupts = ;
> > +   power-domains = < MT8173_POWER_DOMAIN_USB>;
> > +   clocks = < CLK_TOP_USB30_SEL>,
> > +< CLK_PERI_USB0>,
> > +< CLK_PERI_USB1>;
> > +   clock-names = "sys_ck",
> > + "wakeup_deb_p0",
> > + "wakeup_deb_p1";
> > +   phys = <_port0 PHY_TYPE_USB3>,
> > +  <_port1 PHY_TYPE_USB2>;
> > +   mediatek,syscon-wakeup = <>;
> > +   status = "okay";
> > +   };
> > +
> > +   u3phy: usb-phy@1129 {
> > +   compatible = "mediatek,mt8173-u3phy";
> > +   reg = <0 0x1129 0 0x800>;
> > +   clocks = < CLK_APMIXED_REF2USB_TX>;
> > +   clock-names = "u3phya_ref";
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +   ranges;
> > +   status = "okay";
> 
> Don't you need the "power-domains" prop here as well?
No, the power-domains of MAC and PHY are separated, but PHY's can't be
operated by software.

Thanks.
> 
> > +
> > +   phy_port0: port@11290800 {
> > +   reg = <0 0x11290800 0 0x800>;
> > +   #phy-cells = <1>;
> > +   status = "okay";
> > +   };
> > +
> > +   phy_port1: port@11291000 {
> > +   reg = <0 0x11291000 0 0x800>;
> > +   #phy-cells = <1>;
> > +   status = "okay";
> > +   };
> > +   };
> > };
> >   };
> >
> 
> MBR, Sergei
> 


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Re: [PATCH v10 3/3] arm64: dts: mediatek: add xHCI & usb phy for mt8173

[Sergei Shtylyov]

Hello.

On 10/18/2015 6:51 AM, Chunfeng Yun wrote:


add xHCI and phy drivers for MT8173-EVB

Signed-off-by: Chunfeng Yun 


[...]


diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index d18ee42..46f5f50 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi

[...]

@@ -487,6 +488,47 @@
clock-names = "source", "hclk";
status = "disabled";
};
+
+   usb30: usb@1127 {
+   compatible = "mediatek,mt8173-xhci";
+   reg = <0 0x1127 0 0x1000>,
+ <0 0x11280700 0 0x0100>;
+   interrupts = ;
+   power-domains = < MT8173_POWER_DOMAIN_USB>;
+   clocks = < CLK_TOP_USB30_SEL>,
+< CLK_PERI_USB0>,
+< CLK_PERI_USB1>;
+   clock-names = "sys_ck",
+ "wakeup_deb_p0",
+ "wakeup_deb_p1";
+   phys = <_port0 PHY_TYPE_USB3>,
+  <_port1 PHY_TYPE_USB2>;
+   mediatek,syscon-wakeup = <>;
+   status = "okay";
+   };
+
+   u3phy: usb-phy@1129 {
+   compatible = "mediatek,mt8173-u3phy";
+   reg = <0 0x1129 0 0x800>;
+   clocks = < CLK_APMIXED_REF2USB_TX>;
+   clock-names = "u3phya_ref";
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+   status = "okay";


   Don't you need the "power-domains" prop here as well?


+
+   phy_port0: port@11290800 {
+   reg = <0 0x11290800 0 0x800>;
+   #phy-cells = <1>;
+   status = "okay";
+   };
+
+   phy_port1: port@11291000 {
+   reg = <0 0x11291000 0 0x800>;
+   #phy-cells = <1>;
+   status = "okay";
+   };
+   };
};
  };



MBR, Sergei

--
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the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/