Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Linus Walleij]

On Sat, May 20, 2017 at 7:54 AM, Bjorn Andersson
 wrote:
> On Thu 18 May 01:39 PDT 2017, Varadarajan Narayanan wrote:

>> There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
>> controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for
>> NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3
>> groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
>>
>
> If you consider that you are defining the available functions for this
> pinmuxer and then define the sets of pins exposing these available
> functions it does make sense to just name it "qpic".
>
> I think that naming them _common, _lcd and _nand is just adding
> confusion when it comes to writing the dts files.
>
> @Linus, do you have a different preference here?

No I pretty much trust the driver maintainer to know this best.

Yours,
Linus Walleij

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Linus Walleij]

On Sat, May 20, 2017 at 7:54 AM, Bjorn Andersson
 wrote:
> On Thu 18 May 01:39 PDT 2017, Varadarajan Narayanan wrote:

>> There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
>> controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for
>> NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3
>> groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
>>
>
> If you consider that you are defining the available functions for this
> pinmuxer and then define the sets of pins exposing these available
> functions it does make sense to just name it "qpic".
>
> I think that naming them _common, _lcd and _nand is just adding
> confusion when it comes to writing the dts files.
>
> @Linus, do you have a different preference here?

No I pretty much trust the driver maintainer to know this best.

Yours,
Linus Walleij

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Bjorn Andersson]

On Thu 18 May 01:39 PDT 2017, Varadarajan Narayanan wrote:

> 
> 
> On 5/18/2017 1:03 AM, Bjorn Andersson wrote:
> > On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:
> > 
> > > On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > > > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > > > 
> > > > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> > [..]
> > > > > > > + msm_mux_qpic_pad4,
> > > > > > 
> > > > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different 
> > > > > > functions,
> > > > > > alternative muxings...?
> > > > > 
> > > > > This is for the NAND and LCD display. The pins listed are the 9 data 
> > > > > pins.
> > > > > 
> > > > 
> > > > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > > > possible to reference a partial group in the DTS, if that's necessary)
> > > 
> > > There are two sets of 9 pins, either of which can go to NAND or LCD.
> > > Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> > > Is that ok?
> > > 
> > 
> > So you have NAND and LCD hardware muxed to either "a" or "b" and then
> > you mux either "a" or "b" out onto actual pins?
> > 
> > How is this first mux configured?
> > 
> > I think the a/b scheme sounds reasonable, if above is how it works.
> 
> Sorry, I was wrong. I had misread the documentation.
> 
> There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
> controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for
> NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3
> groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
> 

If you consider that you are defining the available functions for this
pinmuxer and then define the sets of pins exposing these available
functions it does make sense to just name it "qpic".

I think that naming them _common, _lcd and _nand is just adding
confusion when it comes to writing the dts files.


@Linus, do you have a different preference here?

Regards,
Bjorn

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Bjorn Andersson]

On Thu 18 May 01:39 PDT 2017, Varadarajan Narayanan wrote:

> 
> 
> On 5/18/2017 1:03 AM, Bjorn Andersson wrote:
> > On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:
> > 
> > > On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > > > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > > > 
> > > > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> > [..]
> > > > > > > + msm_mux_qpic_pad4,
> > > > > > 
> > > > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different 
> > > > > > functions,
> > > > > > alternative muxings...?
> > > > > 
> > > > > This is for the NAND and LCD display. The pins listed are the 9 data 
> > > > > pins.
> > > > > 
> > > > 
> > > > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > > > possible to reference a partial group in the DTS, if that's necessary)
> > > 
> > > There are two sets of 9 pins, either of which can go to NAND or LCD.
> > > Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> > > Is that ok?
> > > 
> > 
> > So you have NAND and LCD hardware muxed to either "a" or "b" and then
> > you mux either "a" or "b" out onto actual pins?
> > 
> > How is this first mux configured?
> > 
> > I think the a/b scheme sounds reasonable, if above is how it works.
> 
> Sorry, I was wrong. I had misread the documentation.
> 
> There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
> controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for
> NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3
> groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
> 

If you consider that you are defining the available functions for this
pinmuxer and then define the sets of pins exposing these available
functions it does make sense to just name it "qpic".

I think that naming them _common, _lcd and _nand is just adding
confusion when it comes to writing the dts files.


@Linus, do you have a different preference here?

Regards,
Bjorn

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Varadarajan Narayanan]

On 5/18/2017 1:03 AM, Bjorn Andersson wrote:

On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:


On 5/14/2017 9:53 AM, Bjorn Andersson wrote:

On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:


On 5/11/2017 4:13 AM, Bjorn Andersson wrote:

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:

[..]

+   msm_mux_qpic_pad4,


What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
alternative muxings...?


This is for the NAND and LCD display. The pins listed are the 9 data pins.



Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
possible to reference a partial group in the DTS, if that's necessary)


There are two sets of 9 pins, either of which can go to NAND or LCD.
Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
Is that ok?



So you have NAND and LCD hardware muxed to either "a" or "b" and then
you mux either "a" or "b" out onto actual pins?

How is this first mux configured?

I think the a/b scheme sounds reasonable, if above is how it works.


Sorry, I was wrong. I had misread the documentation.

There are 18 pins. 15 pins are common between LCD and NAND. The QPIC 
controller arbitrates between LCD and NAND. Of the remaining 4, 2 are 
for NAND and 2 are for LCD exclusively. We plan to group the qpic pins 
into 3 groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?


Thanks
Varada



Regards,
Bjorn

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--
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Forum, a Linux Foundation Collaborative Project

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Varadarajan Narayanan]

On 5/18/2017 1:03 AM, Bjorn Andersson wrote:

On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:


On 5/14/2017 9:53 AM, Bjorn Andersson wrote:

On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:


On 5/11/2017 4:13 AM, Bjorn Andersson wrote:

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:

[..]

+   msm_mux_qpic_pad4,


What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
alternative muxings...?


This is for the NAND and LCD display. The pins listed are the 9 data pins.



Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
possible to reference a partial group in the DTS, if that's necessary)


There are two sets of 9 pins, either of which can go to NAND or LCD.
Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
Is that ok?



So you have NAND and LCD hardware muxed to either "a" or "b" and then
you mux either "a" or "b" out onto actual pins?

How is this first mux configured?

I think the a/b scheme sounds reasonable, if above is how it works.


Sorry, I was wrong. I had misread the documentation.

There are 18 pins. 15 pins are common between LCD and NAND. The QPIC 
controller arbitrates between LCD and NAND. Of the remaining 4, 2 are 
for NAND and 2 are for LCD exclusively. We plan to group the qpic pins 
into 3 groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?


Thanks
Varada



Regards,
Bjorn

___
linux-arm-kernel mailing list
linux-arm-ker...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum, a Linux Foundation Collaborative Project

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Varadarajan Narayanan]

On 5/18/2017 1:17 AM, Bjorn Andersson wrote:

On Mon 15 May 04:24 PDT 2017, Varadarajan Narayanan wrote:




On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:

On 5/14/2017 9:53 AM, Bjorn Andersson wrote:

On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:


On 5/11/2017 4:13 AM, Bjorn Andersson wrote:

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:


[..]

+enum ipq8074_functions {


Please keep these sorted alphabetically.


Ok


+msm_mux_gpio,
+msm_mux_qpic_pad,
+msm_mux_blsp5_i2c,
+msm_mux_blsp5_spi,
+msm_mux_wci20,


What does "20" mean here?


This is for Wireless Coex Interface. The same functionality can
be muxed on
to different GPIOs. WCI2, is the 2nd edition of the WCI standard
and 0, 1
are for the muxing to different GPIOs (alternate muxes).



In other Qualcomm platforms the alternative muxes are denoted by letters
(a,b,c...). Would you mind picking up this naming scheme, or do you see
any problems with that? (E.g. wci2a in this case)


Ok


Btw, do you need any additional configuration for selecting alternative
muxing or is that automagical these days?


No additional configuration is needed.


+msm_mux_blsp3_spi3,
+msm_mux_burn0,
+msm_mux_pcm_zsi0,
+msm_mux_blsp5_uart,
+msm_mux_mac12,


What does "12" mean here?


The SoC has three MAC cores. Each core has two pins for the
smart antenna
feature. macXY indicates the function select for MAC no. X and
smart antenna
no. Y.



Ok


+msm_mux_blsp3_spi0,
+msm_mux_burn1,
+msm_mux_mac01,
+msm_mux_qdss_cti_trig_out_b0,
+msm_mux_qdss_cti_trig_in_b0,
+msm_mux_qpic_pad4,


What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
alternative muxings...?


This is for the NAND and LCD display. The pins listed are the 9
data pins.



Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
possible to reference a partial group in the DTS, if that's necessary)


There are two sets of 9 pins, either of which can go to NAND or LCD.
Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
Is that ok?


+msm_mux_blsp4_uart0,
+msm_mux_blsp4_i2c0,
+msm_mux_blsp4_spi0,
+msm_mux_mac21,
+msm_mux_qdss_cti_trig_out_b1,
+msm_mux_qpic_pad5,
+msm_mux_qdss_cti_trig_in_b1,
+msm_mux_qpic_pad6,
+msm_mux_qpic_pad7,
+msm_mux_cxc0,
+msm_mux_mac13,
+msm_mux_qdss_cti_trig_in_a1,
+msm_mux_qdss_cti_trig_out_a1,
+msm_mux_wci22,
+msm_mux_qdss_cti_trig_in_a0,
+msm_mux_qpic_pad1,
+msm_mux_qdss_cti_trig_out_a0,
+msm_mux_qpic_pad2,
+msm_mux_qpic_pad3,
+msm_mux_qdss_traceclk_b,
+msm_mux_qpic_pad0,
+msm_mux_qdss_tracectl_b,
+msm_mux_qpic_pad8,
+msm_mux_pcm_zsi1,
+msm_mux_qdss_tracedata_b,
+msm_mux_led0,
+msm_mux_pwm04,


What does "04" mean here?


There are 4 Pulse Width Modulation channels, pwmXY is pwm
channel X and pin
Y.


So Y is alternative mux? Can we use letters for this as well?


Ok


Sorry, actually they are not alternative muxes. There are 4 different PWM
instances. Each PWM instance can handle 'n' different GPIOs (for example,
that can be connected to LED etc.).



So we have 4 PWMs and the output from a single PWM can muxed to drive
the output of 4 pins?

Then skip the last digit and just go pwm0, ... pwm3 and include all four
pins that can be part of each instance. As the pingroup configuration is
per pin in the TLMM it's possible to configure subsets of the pins in a
group.


Ok

Thanks
Varada


Regards,
Bjorn



--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum, a Linux Foundation Collaborative Project

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Varadarajan Narayanan]

On 5/18/2017 1:17 AM, Bjorn Andersson wrote:

On Mon 15 May 04:24 PDT 2017, Varadarajan Narayanan wrote:




On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:

On 5/14/2017 9:53 AM, Bjorn Andersson wrote:

On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:


On 5/11/2017 4:13 AM, Bjorn Andersson wrote:

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:


[..]

+enum ipq8074_functions {


Please keep these sorted alphabetically.


Ok


+msm_mux_gpio,
+msm_mux_qpic_pad,
+msm_mux_blsp5_i2c,
+msm_mux_blsp5_spi,
+msm_mux_wci20,


What does "20" mean here?


This is for Wireless Coex Interface. The same functionality can
be muxed on
to different GPIOs. WCI2, is the 2nd edition of the WCI standard
and 0, 1
are for the muxing to different GPIOs (alternate muxes).



In other Qualcomm platforms the alternative muxes are denoted by letters
(a,b,c...). Would you mind picking up this naming scheme, or do you see
any problems with that? (E.g. wci2a in this case)


Ok


Btw, do you need any additional configuration for selecting alternative
muxing or is that automagical these days?


No additional configuration is needed.


+msm_mux_blsp3_spi3,
+msm_mux_burn0,
+msm_mux_pcm_zsi0,
+msm_mux_blsp5_uart,
+msm_mux_mac12,


What does "12" mean here?


The SoC has three MAC cores. Each core has two pins for the
smart antenna
feature. macXY indicates the function select for MAC no. X and
smart antenna
no. Y.



Ok


+msm_mux_blsp3_spi0,
+msm_mux_burn1,
+msm_mux_mac01,
+msm_mux_qdss_cti_trig_out_b0,
+msm_mux_qdss_cti_trig_in_b0,
+msm_mux_qpic_pad4,


What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
alternative muxings...?


This is for the NAND and LCD display. The pins listed are the 9
data pins.



Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
possible to reference a partial group in the DTS, if that's necessary)


There are two sets of 9 pins, either of which can go to NAND or LCD.
Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
Is that ok?


+msm_mux_blsp4_uart0,
+msm_mux_blsp4_i2c0,
+msm_mux_blsp4_spi0,
+msm_mux_mac21,
+msm_mux_qdss_cti_trig_out_b1,
+msm_mux_qpic_pad5,
+msm_mux_qdss_cti_trig_in_b1,
+msm_mux_qpic_pad6,
+msm_mux_qpic_pad7,
+msm_mux_cxc0,
+msm_mux_mac13,
+msm_mux_qdss_cti_trig_in_a1,
+msm_mux_qdss_cti_trig_out_a1,
+msm_mux_wci22,
+msm_mux_qdss_cti_trig_in_a0,
+msm_mux_qpic_pad1,
+msm_mux_qdss_cti_trig_out_a0,
+msm_mux_qpic_pad2,
+msm_mux_qpic_pad3,
+msm_mux_qdss_traceclk_b,
+msm_mux_qpic_pad0,
+msm_mux_qdss_tracectl_b,
+msm_mux_qpic_pad8,
+msm_mux_pcm_zsi1,
+msm_mux_qdss_tracedata_b,
+msm_mux_led0,
+msm_mux_pwm04,


What does "04" mean here?


There are 4 Pulse Width Modulation channels, pwmXY is pwm
channel X and pin
Y.


So Y is alternative mux? Can we use letters for this as well?


Ok


Sorry, actually they are not alternative muxes. There are 4 different PWM
instances. Each PWM instance can handle 'n' different GPIOs (for example,
that can be connected to LED etc.).



So we have 4 PWMs and the output from a single PWM can muxed to drive
the output of 4 pins?

Then skip the last digit and just go pwm0, ... pwm3 and include all four
pins that can be part of each instance. As the pingroup configuration is
per pin in the TLMM it's possible to configure subsets of the pins in a
group.


Ok

Thanks
Varada


Regards,
Bjorn



--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum, a Linux Foundation Collaborative Project

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Bjorn Andersson]

On Mon 15 May 04:24 PDT 2017, Varadarajan Narayanan wrote:

> 
> 
> On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
> > On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > > 
> > > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> > > > > 
> > > [..]
> > > > > > +enum ipq8074_functions {
> > > > > 
> > > > > Please keep these sorted alphabetically.
> > > > 
> > > > Ok
> > > > 
> > > > > > +msm_mux_gpio,
> > > > > > +msm_mux_qpic_pad,
> > > > > > +msm_mux_blsp5_i2c,
> > > > > > +msm_mux_blsp5_spi,
> > > > > > +msm_mux_wci20,
> > > > > 
> > > > > What does "20" mean here?
> > > > 
> > > > This is for Wireless Coex Interface. The same functionality can
> > > > be muxed on
> > > > to different GPIOs. WCI2, is the 2nd edition of the WCI standard
> > > > and 0, 1
> > > > are for the muxing to different GPIOs (alternate muxes).
> > > > 
> > > 
> > > In other Qualcomm platforms the alternative muxes are denoted by letters
> > > (a,b,c...). Would you mind picking up this naming scheme, or do you see
> > > any problems with that? (E.g. wci2a in this case)
> > 
> > Ok
> > 
> > > Btw, do you need any additional configuration for selecting alternative
> > > muxing or is that automagical these days?
> > 
> > No additional configuration is needed.
> > 
> > > > > > +msm_mux_blsp3_spi3,
> > > > > > +msm_mux_burn0,
> > > > > > +msm_mux_pcm_zsi0,
> > > > > > +msm_mux_blsp5_uart,
> > > > > > +msm_mux_mac12,
> > > > > 
> > > > > What does "12" mean here?
> > > > 
> > > > The SoC has three MAC cores. Each core has two pins for the
> > > > smart antenna
> > > > feature. macXY indicates the function select for MAC no. X and
> > > > smart antenna
> > > > no. Y.
> > > > 
> > > 
> > > Ok
> > > 
> > > > > > +msm_mux_blsp3_spi0,
> > > > > > +msm_mux_burn1,
> > > > > > +msm_mux_mac01,
> > > > > > +msm_mux_qdss_cti_trig_out_b0,
> > > > > > +msm_mux_qdss_cti_trig_in_b0,
> > > > > > +msm_mux_qpic_pad4,
> > > > > 
> > > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different 
> > > > > functions,
> > > > > alternative muxings...?
> > > > 
> > > > This is for the NAND and LCD display. The pins listed are the 9
> > > > data pins.
> > > > 
> > > 
> > > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > > possible to reference a partial group in the DTS, if that's necessary)
> > 
> > There are two sets of 9 pins, either of which can go to NAND or LCD.
> > Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> > Is that ok?
> > 
> > > > > > +msm_mux_blsp4_uart0,
> > > > > > +msm_mux_blsp4_i2c0,
> > > > > > +msm_mux_blsp4_spi0,
> > > > > > +msm_mux_mac21,
> > > > > > +msm_mux_qdss_cti_trig_out_b1,
> > > > > > +msm_mux_qpic_pad5,
> > > > > > +msm_mux_qdss_cti_trig_in_b1,
> > > > > > +msm_mux_qpic_pad6,
> > > > > > +msm_mux_qpic_pad7,
> > > > > > +msm_mux_cxc0,
> > > > > > +msm_mux_mac13,
> > > > > > +msm_mux_qdss_cti_trig_in_a1,
> > > > > > +msm_mux_qdss_cti_trig_out_a1,
> > > > > > +msm_mux_wci22,
> > > > > > +msm_mux_qdss_cti_trig_in_a0,
> > > > > > +msm_mux_qpic_pad1,
> > > > > > +msm_mux_qdss_cti_trig_out_a0,
> > > > > > +msm_mux_qpic_pad2,
> > > > > > +msm_mux_qpic_pad3,
> > > > > > +msm_mux_qdss_traceclk_b,
> > > > > > +msm_mux_qpic_pad0,
> > > > > > +msm_mux_qdss_tracectl_b,
> > > > > > +msm_mux_qpic_pad8,
> > > > > > +msm_mux_pcm_zsi1,
> > > > > > +msm_mux_qdss_tracedata_b,
> > > > > > +msm_mux_led0,
> > > > > > +msm_mux_pwm04,
> > > > > 
> > > > > What does "04" mean here?
> > > > 
> > > > There are 4 Pulse Width Modulation channels, pwmXY is pwm
> > > > channel X and pin
> > > > Y.
> > > 
> > > So Y is alternative mux? Can we use letters for this as well?
> > 
> > Ok
> 
> Sorry, actually they are not alternative muxes. There are 4 different PWM
> instances. Each PWM instance can handle 'n' different GPIOs (for example,
> that can be connected to LED etc.).
> 

So we have 4 PWMs and the output from a single PWM can muxed to drive
the output of 4 pins?

Then skip the last digit and just go pwm0, ... pwm3 and include all four
pins that can be part of each instance. As the pingroup configuration is
per pin in the TLMM it's possible to configure subsets of the pins in a
group.

Regards,
Bjorn

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Bjorn Andersson]

On Mon 15 May 04:24 PDT 2017, Varadarajan Narayanan wrote:

> 
> 
> On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
> > On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > > 
> > > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> > > > > 
> > > [..]
> > > > > > +enum ipq8074_functions {
> > > > > 
> > > > > Please keep these sorted alphabetically.
> > > > 
> > > > Ok
> > > > 
> > > > > > +msm_mux_gpio,
> > > > > > +msm_mux_qpic_pad,
> > > > > > +msm_mux_blsp5_i2c,
> > > > > > +msm_mux_blsp5_spi,
> > > > > > +msm_mux_wci20,
> > > > > 
> > > > > What does "20" mean here?
> > > > 
> > > > This is for Wireless Coex Interface. The same functionality can
> > > > be muxed on
> > > > to different GPIOs. WCI2, is the 2nd edition of the WCI standard
> > > > and 0, 1
> > > > are for the muxing to different GPIOs (alternate muxes).
> > > > 
> > > 
> > > In other Qualcomm platforms the alternative muxes are denoted by letters
> > > (a,b,c...). Would you mind picking up this naming scheme, or do you see
> > > any problems with that? (E.g. wci2a in this case)
> > 
> > Ok
> > 
> > > Btw, do you need any additional configuration for selecting alternative
> > > muxing or is that automagical these days?
> > 
> > No additional configuration is needed.
> > 
> > > > > > +msm_mux_blsp3_spi3,
> > > > > > +msm_mux_burn0,
> > > > > > +msm_mux_pcm_zsi0,
> > > > > > +msm_mux_blsp5_uart,
> > > > > > +msm_mux_mac12,
> > > > > 
> > > > > What does "12" mean here?
> > > > 
> > > > The SoC has three MAC cores. Each core has two pins for the
> > > > smart antenna
> > > > feature. macXY indicates the function select for MAC no. X and
> > > > smart antenna
> > > > no. Y.
> > > > 
> > > 
> > > Ok
> > > 
> > > > > > +msm_mux_blsp3_spi0,
> > > > > > +msm_mux_burn1,
> > > > > > +msm_mux_mac01,
> > > > > > +msm_mux_qdss_cti_trig_out_b0,
> > > > > > +msm_mux_qdss_cti_trig_in_b0,
> > > > > > +msm_mux_qpic_pad4,
> > > > > 
> > > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different 
> > > > > functions,
> > > > > alternative muxings...?
> > > > 
> > > > This is for the NAND and LCD display. The pins listed are the 9
> > > > data pins.
> > > > 
> > > 
> > > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > > possible to reference a partial group in the DTS, if that's necessary)
> > 
> > There are two sets of 9 pins, either of which can go to NAND or LCD.
> > Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> > Is that ok?
> > 
> > > > > > +msm_mux_blsp4_uart0,
> > > > > > +msm_mux_blsp4_i2c0,
> > > > > > +msm_mux_blsp4_spi0,
> > > > > > +msm_mux_mac21,
> > > > > > +msm_mux_qdss_cti_trig_out_b1,
> > > > > > +msm_mux_qpic_pad5,
> > > > > > +msm_mux_qdss_cti_trig_in_b1,
> > > > > > +msm_mux_qpic_pad6,
> > > > > > +msm_mux_qpic_pad7,
> > > > > > +msm_mux_cxc0,
> > > > > > +msm_mux_mac13,
> > > > > > +msm_mux_qdss_cti_trig_in_a1,
> > > > > > +msm_mux_qdss_cti_trig_out_a1,
> > > > > > +msm_mux_wci22,
> > > > > > +msm_mux_qdss_cti_trig_in_a0,
> > > > > > +msm_mux_qpic_pad1,
> > > > > > +msm_mux_qdss_cti_trig_out_a0,
> > > > > > +msm_mux_qpic_pad2,
> > > > > > +msm_mux_qpic_pad3,
> > > > > > +msm_mux_qdss_traceclk_b,
> > > > > > +msm_mux_qpic_pad0,
> > > > > > +msm_mux_qdss_tracectl_b,
> > > > > > +msm_mux_qpic_pad8,
> > > > > > +msm_mux_pcm_zsi1,
> > > > > > +msm_mux_qdss_tracedata_b,
> > > > > > +msm_mux_led0,
> > > > > > +msm_mux_pwm04,
> > > > > 
> > > > > What does "04" mean here?
> > > > 
> > > > There are 4 Pulse Width Modulation channels, pwmXY is pwm
> > > > channel X and pin
> > > > Y.
> > > 
> > > So Y is alternative mux? Can we use letters for this as well?
> > 
> > Ok
> 
> Sorry, actually they are not alternative muxes. There are 4 different PWM
> instances. Each PWM instance can handle 'n' different GPIOs (for example,
> that can be connected to LED etc.).
> 

So we have 4 PWMs and the output from a single PWM can muxed to drive
the output of 4 pins?

Then skip the last digit and just go pwm0, ... pwm3 and include all four
pins that can be part of each instance. As the pingroup configuration is
per pin in the TLMM it's possible to configure subsets of the pins in a
group.

Regards,
Bjorn

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Bjorn Andersson]

On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:

> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > 
> > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
[..]
> > > > > + msm_mux_qpic_pad4,
> > > > 
> > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > > > alternative muxings...?
> > > 
> > > This is for the NAND and LCD display. The pins listed are the 9 data pins.
> > > 
> > 
> > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > possible to reference a partial group in the DTS, if that's necessary)
> 
> There are two sets of 9 pins, either of which can go to NAND or LCD.
> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> Is that ok?
> 

So you have NAND and LCD hardware muxed to either "a" or "b" and then
you mux either "a" or "b" out onto actual pins?

How is this first mux configured?


I think the a/b scheme sounds reasonable, if above is how it works.

Regards,
Bjorn

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Bjorn Andersson]

On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:

> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > 
> > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
[..]
> > > > > + msm_mux_qpic_pad4,
> > > > 
> > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > > > alternative muxings...?
> > > 
> > > This is for the NAND and LCD display. The pins listed are the 9 data pins.
> > > 
> > 
> > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > possible to reference a partial group in the DTS, if that's necessary)
> 
> There are two sets of 9 pins, either of which can go to NAND or LCD.
> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> Is that ok?
> 

So you have NAND and LCD hardware muxed to either "a" or "b" and then
you mux either "a" or "b" out onto actual pins?

How is this first mux configured?


I think the a/b scheme sounds reasonable, if above is how it works.

Regards,
Bjorn

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Varadarajan Narayanan]

On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:

On 5/14/2017 9:53 AM, Bjorn Andersson wrote:

On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:


On 5/11/2017 4:13 AM, Bjorn Andersson wrote:

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:


[..]

+enum ipq8074_functions {


Please keep these sorted alphabetically.


Ok


+msm_mux_gpio,
+msm_mux_qpic_pad,
+msm_mux_blsp5_i2c,
+msm_mux_blsp5_spi,
+msm_mux_wci20,


What does "20" mean here?


This is for Wireless Coex Interface. The same functionality can be 
muxed on
to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 
0, 1

are for the muxing to different GPIOs (alternate muxes).



In other Qualcomm platforms the alternative muxes are denoted by letters
(a,b,c...). Would you mind picking up this naming scheme, or do you see
any problems with that? (E.g. wci2a in this case)


Ok


Btw, do you need any additional configuration for selecting alternative
muxing or is that automagical these days?


No additional configuration is needed.


+msm_mux_blsp3_spi3,
+msm_mux_burn0,
+msm_mux_pcm_zsi0,
+msm_mux_blsp5_uart,
+msm_mux_mac12,


What does "12" mean here?


The SoC has three MAC cores. Each core has two pins for the smart 
antenna
feature. macXY indicates the function select for MAC no. X and smart 
antenna

no. Y.



Ok


+msm_mux_blsp3_spi0,
+msm_mux_burn1,
+msm_mux_mac01,
+msm_mux_qdss_cti_trig_out_b0,
+msm_mux_qdss_cti_trig_in_b0,
+msm_mux_qpic_pad4,


What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
alternative muxings...?


This is for the NAND and LCD display. The pins listed are the 9 data 
pins.




Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
possible to reference a partial group in the DTS, if that's necessary)


There are two sets of 9 pins, either of which can go to NAND or LCD.
Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
Is that ok?


+msm_mux_blsp4_uart0,
+msm_mux_blsp4_i2c0,
+msm_mux_blsp4_spi0,
+msm_mux_mac21,
+msm_mux_qdss_cti_trig_out_b1,
+msm_mux_qpic_pad5,
+msm_mux_qdss_cti_trig_in_b1,
+msm_mux_qpic_pad6,
+msm_mux_qpic_pad7,
+msm_mux_cxc0,
+msm_mux_mac13,
+msm_mux_qdss_cti_trig_in_a1,
+msm_mux_qdss_cti_trig_out_a1,
+msm_mux_wci22,
+msm_mux_qdss_cti_trig_in_a0,
+msm_mux_qpic_pad1,
+msm_mux_qdss_cti_trig_out_a0,
+msm_mux_qpic_pad2,
+msm_mux_qpic_pad3,
+msm_mux_qdss_traceclk_b,
+msm_mux_qpic_pad0,
+msm_mux_qdss_tracectl_b,
+msm_mux_qpic_pad8,
+msm_mux_pcm_zsi1,
+msm_mux_qdss_tracedata_b,
+msm_mux_led0,
+msm_mux_pwm04,


What does "04" mean here?


There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X 
and pin

Y.


So Y is alternative mux? Can we use letters for this as well?


Ok


Sorry, actually they are not alternative muxes. There are 4 different 
PWM instances. Each PWM instance can handle 'n' different GPIOs (for 
example, that can be connected to LED etc.).


Thanks
Varada


+msm_mux_led1,
+msm_mux_pwm14,
+msm_mux_led2,
+msm_mux_pwm24,
+msm_mux_pwm00,
+msm_mux_blsp4_uart1,


Are uart0 vs uart1 alternative muxes?


These are two different uarts available at two independent pins.



Ok, then I'm happy with the naming of this :)

Thanks,
Bjorn



Thanks
Varada


--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum, a Linux Foundation Collaborative Project

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Varadarajan Narayanan]

On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:

On 5/14/2017 9:53 AM, Bjorn Andersson wrote:

On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:


On 5/11/2017 4:13 AM, Bjorn Andersson wrote:

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:


[..]

+enum ipq8074_functions {


Please keep these sorted alphabetically.


Ok


+msm_mux_gpio,
+msm_mux_qpic_pad,
+msm_mux_blsp5_i2c,
+msm_mux_blsp5_spi,
+msm_mux_wci20,


What does "20" mean here?


This is for Wireless Coex Interface. The same functionality can be 
muxed on
to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 
0, 1

are for the muxing to different GPIOs (alternate muxes).



In other Qualcomm platforms the alternative muxes are denoted by letters
(a,b,c...). Would you mind picking up this naming scheme, or do you see
any problems with that? (E.g. wci2a in this case)


Ok


Btw, do you need any additional configuration for selecting alternative
muxing or is that automagical these days?


No additional configuration is needed.


+msm_mux_blsp3_spi3,
+msm_mux_burn0,
+msm_mux_pcm_zsi0,
+msm_mux_blsp5_uart,
+msm_mux_mac12,


What does "12" mean here?


The SoC has three MAC cores. Each core has two pins for the smart 
antenna
feature. macXY indicates the function select for MAC no. X and smart 
antenna

no. Y.



Ok


+msm_mux_blsp3_spi0,
+msm_mux_burn1,
+msm_mux_mac01,
+msm_mux_qdss_cti_trig_out_b0,
+msm_mux_qdss_cti_trig_in_b0,
+msm_mux_qpic_pad4,


What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
alternative muxings...?


This is for the NAND and LCD display. The pins listed are the 9 data 
pins.




Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
possible to reference a partial group in the DTS, if that's necessary)


There are two sets of 9 pins, either of which can go to NAND or LCD.
Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
Is that ok?


+msm_mux_blsp4_uart0,
+msm_mux_blsp4_i2c0,
+msm_mux_blsp4_spi0,
+msm_mux_mac21,
+msm_mux_qdss_cti_trig_out_b1,
+msm_mux_qpic_pad5,
+msm_mux_qdss_cti_trig_in_b1,
+msm_mux_qpic_pad6,
+msm_mux_qpic_pad7,
+msm_mux_cxc0,
+msm_mux_mac13,
+msm_mux_qdss_cti_trig_in_a1,
+msm_mux_qdss_cti_trig_out_a1,
+msm_mux_wci22,
+msm_mux_qdss_cti_trig_in_a0,
+msm_mux_qpic_pad1,
+msm_mux_qdss_cti_trig_out_a0,
+msm_mux_qpic_pad2,
+msm_mux_qpic_pad3,
+msm_mux_qdss_traceclk_b,
+msm_mux_qpic_pad0,
+msm_mux_qdss_tracectl_b,
+msm_mux_qpic_pad8,
+msm_mux_pcm_zsi1,
+msm_mux_qdss_tracedata_b,
+msm_mux_led0,
+msm_mux_pwm04,


What does "04" mean here?


There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X 
and pin

Y.


So Y is alternative mux? Can we use letters for this as well?


Ok


Sorry, actually they are not alternative muxes. There are 4 different 
PWM instances. Each PWM instance can handle 'n' different GPIOs (for 
example, that can be connected to LED etc.).


Thanks
Varada


+msm_mux_led1,
+msm_mux_pwm14,
+msm_mux_led2,
+msm_mux_pwm24,
+msm_mux_pwm00,
+msm_mux_blsp4_uart1,


Are uart0 vs uart1 alternative muxes?


These are two different uarts available at two independent pins.



Ok, then I'm happy with the naming of this :)

Thanks,
Bjorn



Thanks
Varada


--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum, a Linux Foundation Collaborative Project

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Varadarajan Narayanan]

On 5/14/2017 9:53 AM, Bjorn Andersson wrote:

On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:


On 5/11/2017 4:13 AM, Bjorn Andersson wrote:

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:


[..]

+enum ipq8074_functions {


Please keep these sorted alphabetically.


Ok


+   msm_mux_gpio,
+   msm_mux_qpic_pad,
+   msm_mux_blsp5_i2c,
+   msm_mux_blsp5_spi,
+   msm_mux_wci20,


What does "20" mean here?


This is for Wireless Coex Interface. The same functionality can be muxed on
to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1
are for the muxing to different GPIOs (alternate muxes).



In other Qualcomm platforms the alternative muxes are denoted by letters
(a,b,c...). Would you mind picking up this naming scheme, or do you see
any problems with that? (E.g. wci2a in this case)


Ok


Btw, do you need any additional configuration for selecting alternative
muxing or is that automagical these days?


No additional configuration is needed.


+   msm_mux_blsp3_spi3,
+   msm_mux_burn0,
+   msm_mux_pcm_zsi0,
+   msm_mux_blsp5_uart,
+   msm_mux_mac12,


What does "12" mean here?


The SoC has three MAC cores. Each core has two pins for the smart antenna
feature. macXY indicates the function select for MAC no. X and smart antenna
no. Y.



Ok


+   msm_mux_blsp3_spi0,
+   msm_mux_burn1,
+   msm_mux_mac01,
+   msm_mux_qdss_cti_trig_out_b0,
+   msm_mux_qdss_cti_trig_in_b0,
+   msm_mux_qpic_pad4,


What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
alternative muxings...?


This is for the NAND and LCD display. The pins listed are the 9 data pins.



Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
possible to reference a partial group in the DTS, if that's necessary)


There are two sets of 9 pins, either of which can go to NAND or LCD.
Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
Is that ok?


+   msm_mux_blsp4_uart0,
+   msm_mux_blsp4_i2c0,
+   msm_mux_blsp4_spi0,
+   msm_mux_mac21,
+   msm_mux_qdss_cti_trig_out_b1,
+   msm_mux_qpic_pad5,
+   msm_mux_qdss_cti_trig_in_b1,
+   msm_mux_qpic_pad6,
+   msm_mux_qpic_pad7,
+   msm_mux_cxc0,
+   msm_mux_mac13,
+   msm_mux_qdss_cti_trig_in_a1,
+   msm_mux_qdss_cti_trig_out_a1,
+   msm_mux_wci22,
+   msm_mux_qdss_cti_trig_in_a0,
+   msm_mux_qpic_pad1,
+   msm_mux_qdss_cti_trig_out_a0,
+   msm_mux_qpic_pad2,
+   msm_mux_qpic_pad3,
+   msm_mux_qdss_traceclk_b,
+   msm_mux_qpic_pad0,
+   msm_mux_qdss_tracectl_b,
+   msm_mux_qpic_pad8,
+   msm_mux_pcm_zsi1,
+   msm_mux_qdss_tracedata_b,
+   msm_mux_led0,
+   msm_mux_pwm04,


What does "04" mean here?


There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin
Y.


So Y is alternative mux? Can we use letters for this as well?


Ok


+   msm_mux_led1,
+   msm_mux_pwm14,
+   msm_mux_led2,
+   msm_mux_pwm24,
+   msm_mux_pwm00,
+   msm_mux_blsp4_uart1,


Are uart0 vs uart1 alternative muxes?


These are two different uarts available at two independent pins.



Ok, then I'm happy with the naming of this :)

Thanks,
Bjorn



Thanks
Varada
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum, a Linux Foundation Collaborative Project

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Varadarajan Narayanan]

On 5/14/2017 9:53 AM, Bjorn Andersson wrote:

On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:


On 5/11/2017 4:13 AM, Bjorn Andersson wrote:

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:


[..]

+enum ipq8074_functions {


Please keep these sorted alphabetically.


Ok


+   msm_mux_gpio,
+   msm_mux_qpic_pad,
+   msm_mux_blsp5_i2c,
+   msm_mux_blsp5_spi,
+   msm_mux_wci20,


What does "20" mean here?


This is for Wireless Coex Interface. The same functionality can be muxed on
to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1
are for the muxing to different GPIOs (alternate muxes).



In other Qualcomm platforms the alternative muxes are denoted by letters
(a,b,c...). Would you mind picking up this naming scheme, or do you see
any problems with that? (E.g. wci2a in this case)


Ok


Btw, do you need any additional configuration for selecting alternative
muxing or is that automagical these days?


No additional configuration is needed.


+   msm_mux_blsp3_spi3,
+   msm_mux_burn0,
+   msm_mux_pcm_zsi0,
+   msm_mux_blsp5_uart,
+   msm_mux_mac12,


What does "12" mean here?


The SoC has three MAC cores. Each core has two pins for the smart antenna
feature. macXY indicates the function select for MAC no. X and smart antenna
no. Y.



Ok


+   msm_mux_blsp3_spi0,
+   msm_mux_burn1,
+   msm_mux_mac01,
+   msm_mux_qdss_cti_trig_out_b0,
+   msm_mux_qdss_cti_trig_in_b0,
+   msm_mux_qpic_pad4,


What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
alternative muxings...?


This is for the NAND and LCD display. The pins listed are the 9 data pins.



Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
possible to reference a partial group in the DTS, if that's necessary)


There are two sets of 9 pins, either of which can go to NAND or LCD.
Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
Is that ok?


+   msm_mux_blsp4_uart0,
+   msm_mux_blsp4_i2c0,
+   msm_mux_blsp4_spi0,
+   msm_mux_mac21,
+   msm_mux_qdss_cti_trig_out_b1,
+   msm_mux_qpic_pad5,
+   msm_mux_qdss_cti_trig_in_b1,
+   msm_mux_qpic_pad6,
+   msm_mux_qpic_pad7,
+   msm_mux_cxc0,
+   msm_mux_mac13,
+   msm_mux_qdss_cti_trig_in_a1,
+   msm_mux_qdss_cti_trig_out_a1,
+   msm_mux_wci22,
+   msm_mux_qdss_cti_trig_in_a0,
+   msm_mux_qpic_pad1,
+   msm_mux_qdss_cti_trig_out_a0,
+   msm_mux_qpic_pad2,
+   msm_mux_qpic_pad3,
+   msm_mux_qdss_traceclk_b,
+   msm_mux_qpic_pad0,
+   msm_mux_qdss_tracectl_b,
+   msm_mux_qpic_pad8,
+   msm_mux_pcm_zsi1,
+   msm_mux_qdss_tracedata_b,
+   msm_mux_led0,
+   msm_mux_pwm04,


What does "04" mean here?


There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin
Y.


So Y is alternative mux? Can we use letters for this as well?


Ok


+   msm_mux_led1,
+   msm_mux_pwm14,
+   msm_mux_led2,
+   msm_mux_pwm24,
+   msm_mux_pwm00,
+   msm_mux_blsp4_uart1,


Are uart0 vs uart1 alternative muxes?


These are two different uarts available at two independent pins.



Ok, then I'm happy with the naming of this :)

Thanks,
Bjorn



Thanks
Varada
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum, a Linux Foundation Collaborative Project

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Bjorn Andersson]

On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:

> 
> 
> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> > 
[..]
> > > +enum ipq8074_functions {
> > 
> > Please keep these sorted alphabetically.
> 
> Ok
> 
> > > + msm_mux_gpio,
> > > + msm_mux_qpic_pad,
> > > + msm_mux_blsp5_i2c,
> > > + msm_mux_blsp5_spi,
> > > + msm_mux_wci20,
> > 
> > What does "20" mean here?
> 
> This is for Wireless Coex Interface. The same functionality can be muxed on
> to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1
> are for the muxing to different GPIOs (alternate muxes).
> 

In other Qualcomm platforms the alternative muxes are denoted by letters
(a,b,c...). Would you mind picking up this naming scheme, or do you see
any problems with that? (E.g. wci2a in this case)


Btw, do you need any additional configuration for selecting alternative
muxing or is that automagical these days?

> > > + msm_mux_blsp3_spi3,
> > > + msm_mux_burn0,
> > > + msm_mux_pcm_zsi0,
> > > + msm_mux_blsp5_uart,
> > > + msm_mux_mac12,
> > 
> > What does "12" mean here?
> 
> The SoC has three MAC cores. Each core has two pins for the smart antenna
> feature. macXY indicates the function select for MAC no. X and smart antenna
> no. Y.
> 

Ok

> > > + msm_mux_blsp3_spi0,
> > > + msm_mux_burn1,
> > > + msm_mux_mac01,
> > > + msm_mux_qdss_cti_trig_out_b0,
> > > + msm_mux_qdss_cti_trig_in_b0,
> > > + msm_mux_qpic_pad4,
> > 
> > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > alternative muxings...?
> 
> This is for the NAND and LCD display. The pins listed are the 9 data pins.
> 

Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
possible to reference a partial group in the DTS, if that's necessary)

> > > + msm_mux_blsp4_uart0,
> > > + msm_mux_blsp4_i2c0,
> > > + msm_mux_blsp4_spi0,
> > > + msm_mux_mac21,
> > > + msm_mux_qdss_cti_trig_out_b1,
> > > + msm_mux_qpic_pad5,
> > > + msm_mux_qdss_cti_trig_in_b1,
> > > + msm_mux_qpic_pad6,
> > > + msm_mux_qpic_pad7,
> > > + msm_mux_cxc0,
> > > + msm_mux_mac13,
> > > + msm_mux_qdss_cti_trig_in_a1,
> > > + msm_mux_qdss_cti_trig_out_a1,
> > > + msm_mux_wci22,
> > > + msm_mux_qdss_cti_trig_in_a0,
> > > + msm_mux_qpic_pad1,
> > > + msm_mux_qdss_cti_trig_out_a0,
> > > + msm_mux_qpic_pad2,
> > > + msm_mux_qpic_pad3,
> > > + msm_mux_qdss_traceclk_b,
> > > + msm_mux_qpic_pad0,
> > > + msm_mux_qdss_tracectl_b,
> > > + msm_mux_qpic_pad8,
> > > + msm_mux_pcm_zsi1,
> > > + msm_mux_qdss_tracedata_b,
> > > + msm_mux_led0,
> > > + msm_mux_pwm04,
> > 
> > What does "04" mean here?
> 
> There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin
> Y.

So Y is alternative mux? Can we use letters for this as well?

> > 
> > > + msm_mux_led1,
> > > + msm_mux_pwm14,
> > > + msm_mux_led2,
> > > + msm_mux_pwm24,
> > > + msm_mux_pwm00,
> > > + msm_mux_blsp4_uart1,
> > 
> > Are uart0 vs uart1 alternative muxes?
> 
> These are two different uarts available at two independent pins.
> 

Ok, then I'm happy with the naming of this :)

Thanks,
Bjorn

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Bjorn Andersson]

On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:

> 
> 
> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> > 
[..]
> > > +enum ipq8074_functions {
> > 
> > Please keep these sorted alphabetically.
> 
> Ok
> 
> > > + msm_mux_gpio,
> > > + msm_mux_qpic_pad,
> > > + msm_mux_blsp5_i2c,
> > > + msm_mux_blsp5_spi,
> > > + msm_mux_wci20,
> > 
> > What does "20" mean here?
> 
> This is for Wireless Coex Interface. The same functionality can be muxed on
> to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1
> are for the muxing to different GPIOs (alternate muxes).
> 

In other Qualcomm platforms the alternative muxes are denoted by letters
(a,b,c...). Would you mind picking up this naming scheme, or do you see
any problems with that? (E.g. wci2a in this case)


Btw, do you need any additional configuration for selecting alternative
muxing or is that automagical these days?

> > > + msm_mux_blsp3_spi3,
> > > + msm_mux_burn0,
> > > + msm_mux_pcm_zsi0,
> > > + msm_mux_blsp5_uart,
> > > + msm_mux_mac12,
> > 
> > What does "12" mean here?
> 
> The SoC has three MAC cores. Each core has two pins for the smart antenna
> feature. macXY indicates the function select for MAC no. X and smart antenna
> no. Y.
> 

Ok

> > > + msm_mux_blsp3_spi0,
> > > + msm_mux_burn1,
> > > + msm_mux_mac01,
> > > + msm_mux_qdss_cti_trig_out_b0,
> > > + msm_mux_qdss_cti_trig_in_b0,
> > > + msm_mux_qpic_pad4,
> > 
> > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > alternative muxings...?
> 
> This is for the NAND and LCD display. The pins listed are the 9 data pins.
> 

Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
possible to reference a partial group in the DTS, if that's necessary)

> > > + msm_mux_blsp4_uart0,
> > > + msm_mux_blsp4_i2c0,
> > > + msm_mux_blsp4_spi0,
> > > + msm_mux_mac21,
> > > + msm_mux_qdss_cti_trig_out_b1,
> > > + msm_mux_qpic_pad5,
> > > + msm_mux_qdss_cti_trig_in_b1,
> > > + msm_mux_qpic_pad6,
> > > + msm_mux_qpic_pad7,
> > > + msm_mux_cxc0,
> > > + msm_mux_mac13,
> > > + msm_mux_qdss_cti_trig_in_a1,
> > > + msm_mux_qdss_cti_trig_out_a1,
> > > + msm_mux_wci22,
> > > + msm_mux_qdss_cti_trig_in_a0,
> > > + msm_mux_qpic_pad1,
> > > + msm_mux_qdss_cti_trig_out_a0,
> > > + msm_mux_qpic_pad2,
> > > + msm_mux_qpic_pad3,
> > > + msm_mux_qdss_traceclk_b,
> > > + msm_mux_qpic_pad0,
> > > + msm_mux_qdss_tracectl_b,
> > > + msm_mux_qpic_pad8,
> > > + msm_mux_pcm_zsi1,
> > > + msm_mux_qdss_tracedata_b,
> > > + msm_mux_led0,
> > > + msm_mux_pwm04,
> > 
> > What does "04" mean here?
> 
> There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin
> Y.

So Y is alternative mux? Can we use letters for this as well?

> > 
> > > + msm_mux_led1,
> > > + msm_mux_pwm14,
> > > + msm_mux_led2,
> > > + msm_mux_pwm24,
> > > + msm_mux_pwm00,
> > > + msm_mux_blsp4_uart1,
> > 
> > Are uart0 vs uart1 alternative muxes?
> 
> These are two different uarts available at two independent pins.
> 

Ok, then I'm happy with the naming of this :)

Thanks,
Bjorn

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Varadarajan Narayanan]

On 5/11/2017 4:13 AM, Bjorn Andersson wrote:

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:


Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq8074.

Signed-off-by: Manoharan Vijaya Raghavan 
Signed-off-by: Varadarajan Narayanan 
---
  .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt  |  187 +++
  drivers/pinctrl/qcom/Kconfig   |   10 +
  drivers/pinctrl/qcom/Makefile  |1 +
  drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 
  4 files changed, 1415 insertions(+)
  create mode 100644 
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
  create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt

[..]

+- pins:
+   Usage: required
+   Value type: 
+   Definition: List of gpio pins affected by the properties specified in
+   this subnode.  Valid pins are:
+   gpio0-gpio121,
+   sdc1_clk,
+   sdc1_cmd,
+   sdc1_data
+   sdc2_clk,
+   sdc2_cmd,
+   sdc2_data,
+   qdsd_cmd,
+   qdsd_data0,
+   qdsd_data1,
+   qdsd_data2,
+   qdsd_data3


These doesn't match the implementation.


Will remove them.


+
+- function:
+   Usage: required
+   Value type: 
+   Definition: Specify the alternative function to be configured for the
+   specified pins. Functions are only valid for gpio pins.
+   Valid values are:
+   gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
+   burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
+   qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
+   blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+   qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
+   qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
+   qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
+   qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
+   qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
+   qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
+   pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+   blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
+   audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
+   audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
+   atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
+   pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
+   mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
+   qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
+   blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
+   blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,
+   cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
+   cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
+   pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
+   gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
+   gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
+   tsens_max, mdc, mdio, NA


Please indent these to the same level as the description.


Ok


+

[..]

+
+- output-high:
+   Usage: optional
+   Value type: 
+   Definition: The specified pins are configured in output mode, driven
+   high.
+   Not valid for sdc pins.


If you don't have any sdc pins, drop this.


Ok


+
+- output-low:
+   Usage: optional
+   Value type: 
+   Definition: The specified pins are configured in output mode, driven
+   low.
+   Not valid for sdc pins.


If you don't have any sdc pins, drop this.


Ok


+
+- drive-strength:
+   Usage: optional
+   Value type: 
+   Definition: Selects the drive strength for the specified pins, in mA.
+   Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+

[..]

diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c 
b/drivers/pinctrl/qcom/pinctrl-ipq8074.c

[..]

+
+enum ipq8074_functions {


Please keep these sorted alphabetically.


Ok


+   msm_mux_gpio,
+   msm_mux_qpic_pad,
+   msm_mux_blsp5_i2c,
+   msm_mux_blsp5_spi,
+   msm_mux_wci20,


What does "20" mean here?


This is for Wireless Coex Interface. The same functionality can be muxed 
on to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 
0, 1 are for the muxing to different GPIOs (alternate muxes).



+   msm_mux_blsp3_spi3,
+   msm_mux_burn0,
+   msm_mux_pcm_zsi0,
+   msm_mux_blsp5_uart,
+   msm_mux_mac12,


What does "12" mean here?

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Varadarajan Narayanan]

On 5/11/2017 4:13 AM, Bjorn Andersson wrote:

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:


Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq8074.

Signed-off-by: Manoharan Vijaya Raghavan 
Signed-off-by: Varadarajan Narayanan 
---
  .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt  |  187 +++
  drivers/pinctrl/qcom/Kconfig   |   10 +
  drivers/pinctrl/qcom/Makefile  |1 +
  drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 
  4 files changed, 1415 insertions(+)
  create mode 100644 
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
  create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt

[..]

+- pins:
+   Usage: required
+   Value type: 
+   Definition: List of gpio pins affected by the properties specified in
+   this subnode.  Valid pins are:
+   gpio0-gpio121,
+   sdc1_clk,
+   sdc1_cmd,
+   sdc1_data
+   sdc2_clk,
+   sdc2_cmd,
+   sdc2_data,
+   qdsd_cmd,
+   qdsd_data0,
+   qdsd_data1,
+   qdsd_data2,
+   qdsd_data3


These doesn't match the implementation.


Will remove them.


+
+- function:
+   Usage: required
+   Value type: 
+   Definition: Specify the alternative function to be configured for the
+   specified pins. Functions are only valid for gpio pins.
+   Valid values are:
+   gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
+   burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
+   qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
+   blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+   qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
+   qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
+   qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
+   qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
+   qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
+   qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
+   pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+   blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
+   audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
+   audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
+   atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
+   pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
+   mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
+   qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
+   blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
+   blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,
+   cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
+   cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
+   pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
+   gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
+   gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
+   tsens_max, mdc, mdio, NA


Please indent these to the same level as the description.


Ok


+

[..]

+
+- output-high:
+   Usage: optional
+   Value type: 
+   Definition: The specified pins are configured in output mode, driven
+   high.
+   Not valid for sdc pins.


If you don't have any sdc pins, drop this.


Ok


+
+- output-low:
+   Usage: optional
+   Value type: 
+   Definition: The specified pins are configured in output mode, driven
+   low.
+   Not valid for sdc pins.


If you don't have any sdc pins, drop this.


Ok


+
+- drive-strength:
+   Usage: optional
+   Value type: 
+   Definition: Selects the drive strength for the specified pins, in mA.
+   Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+

[..]

diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c 
b/drivers/pinctrl/qcom/pinctrl-ipq8074.c

[..]

+
+enum ipq8074_functions {


Please keep these sorted alphabetically.


Ok


+   msm_mux_gpio,
+   msm_mux_qpic_pad,
+   msm_mux_blsp5_i2c,
+   msm_mux_blsp5_spi,
+   msm_mux_wci20,


What does "20" mean here?


This is for Wireless Coex Interface. The same functionality can be muxed 
on to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 
0, 1 are for the muxing to different GPIOs (alternate muxes).



+   msm_mux_blsp3_spi3,
+   msm_mux_burn0,
+   msm_mux_pcm_zsi0,
+   msm_mux_blsp5_uart,
+   msm_mux_mac12,


What does "12" mean here?


The SoC has three MAC cores. Each core has two 

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Bjorn Andersson]

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:

> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for ipq8074.
> 
> Signed-off-by: Manoharan Vijaya Raghavan 
> Signed-off-by: Varadarajan Narayanan 
> ---
>  .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt  |  187 +++
>  drivers/pinctrl/qcom/Kconfig   |   10 +
>  drivers/pinctrl/qcom/Makefile  |1 +
>  drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 
> 
>  4 files changed, 1415 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
>  create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
> 
> diff --git 
> a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt 
> b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
[..]
> +- pins:
> + Usage: required
> + Value type: 
> + Definition: List of gpio pins affected by the properties specified in
> + this subnode.  Valid pins are:
> + gpio0-gpio121,
> + sdc1_clk,
> + sdc1_cmd,
> + sdc1_data
> + sdc2_clk,
> + sdc2_cmd,
> + sdc2_data,
> + qdsd_cmd,
> + qdsd_data0,
> + qdsd_data1,
> + qdsd_data2,
> + qdsd_data3

These doesn't match the implementation.

> +
> +- function:
> + Usage: required
> + Value type: 
> + Definition: Specify the alternative function to be configured for the
> + specified pins. Functions are only valid for gpio pins.
> + Valid values are:
> + gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
> + burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
> + qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
> + blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
> + qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
> + qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
> + qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
> + qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
> + qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
> + qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
> + pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
> + blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
> + audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
> + audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
> + atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
> + pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
> + mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
> + qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
> + blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
> + blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,
> + cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
> + cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
> + pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
> + gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
> + gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
> + tsens_max, mdc, mdio, NA

Please indent these to the same level as the description.

> +
[..]
> +
> +- output-high:
> + Usage: optional
> + Value type: 
> + Definition: The specified pins are configured in output mode, driven
> + high.
> + Not valid for sdc pins.

If you don't have any sdc pins, drop this.

> +
> +- output-low:
> + Usage: optional
> + Value type: 
> + Definition: The specified pins are configured in output mode, driven
> + low.
> + Not valid for sdc pins.

If you don't have any sdc pins, drop this.

> +
> +- drive-strength:
> + Usage: optional
> + Value type: 
> + Definition: Selects the drive strength for the specified pins, in mA.
> + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
> +
[..]
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c 
> b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
[..]
> +
> +enum ipq8074_functions {

Please keep these sorted alphabetically.

> + msm_mux_gpio,
> + msm_mux_qpic_pad,
> + msm_mux_blsp5_i2c,
> + msm_mux_blsp5_spi,
> + msm_mux_wci20,

What does "20" mean here?

> + msm_mux_blsp3_spi3,
> + msm_mux_burn0,
> + msm_mux_pcm_zsi0,
> + msm_mux_blsp5_uart,
> + msm_mux_mac12,

What does "12" mean here?

> + msm_mux_blsp3_spi0,
> + msm_mux_burn1,
> + msm_mux_mac01,
> + msm_mux_qdss_cti_trig_out_b0,
> + msm_mux_qdss_cti_trig_in_b0,
> + msm_mux_qpic_pad4,

What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
alternative 

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Bjorn Andersson]

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:

> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for ipq8074.
> 
> Signed-off-by: Manoharan Vijaya Raghavan 
> Signed-off-by: Varadarajan Narayanan 
> ---
>  .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt  |  187 +++
>  drivers/pinctrl/qcom/Kconfig   |   10 +
>  drivers/pinctrl/qcom/Makefile  |1 +
>  drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 
> 
>  4 files changed, 1415 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
>  create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c
> 
> diff --git 
> a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt 
> b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
[..]
> +- pins:
> + Usage: required
> + Value type: 
> + Definition: List of gpio pins affected by the properties specified in
> + this subnode.  Valid pins are:
> + gpio0-gpio121,
> + sdc1_clk,
> + sdc1_cmd,
> + sdc1_data
> + sdc2_clk,
> + sdc2_cmd,
> + sdc2_data,
> + qdsd_cmd,
> + qdsd_data0,
> + qdsd_data1,
> + qdsd_data2,
> + qdsd_data3

These doesn't match the implementation.

> +
> +- function:
> + Usage: required
> + Value type: 
> + Definition: Specify the alternative function to be configured for the
> + specified pins. Functions are only valid for gpio pins.
> + Valid values are:
> + gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
> + burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
> + qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
> + blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
> + qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
> + qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
> + qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
> + qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
> + qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
> + qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
> + pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
> + blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
> + audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
> + audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
> + atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
> + pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
> + mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
> + qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
> + blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
> + blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,
> + cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
> + cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
> + pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
> + gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
> + gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
> + tsens_max, mdc, mdio, NA

Please indent these to the same level as the description.

> +
[..]
> +
> +- output-high:
> + Usage: optional
> + Value type: 
> + Definition: The specified pins are configured in output mode, driven
> + high.
> + Not valid for sdc pins.

If you don't have any sdc pins, drop this.

> +
> +- output-low:
> + Usage: optional
> + Value type: 
> + Definition: The specified pins are configured in output mode, driven
> + low.
> + Not valid for sdc pins.

If you don't have any sdc pins, drop this.

> +
> +- drive-strength:
> + Usage: optional
> + Value type: 
> + Definition: Selects the drive strength for the specified pins, in mA.
> + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
> +
[..]
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c 
> b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
[..]
> +
> +enum ipq8074_functions {

Please keep these sorted alphabetically.

> + msm_mux_gpio,
> + msm_mux_qpic_pad,
> + msm_mux_blsp5_i2c,
> + msm_mux_blsp5_spi,
> + msm_mux_wci20,

What does "20" mean here?

> + msm_mux_blsp3_spi3,
> + msm_mux_burn0,
> + msm_mux_pcm_zsi0,
> + msm_mux_blsp5_uart,
> + msm_mux_mac12,

What does "12" mean here?

> + msm_mux_blsp3_spi0,
> + msm_mux_burn1,
> + msm_mux_mac01,
> + msm_mux_qdss_cti_trig_out_b0,
> + msm_mux_qdss_cti_trig_in_b0,
> + msm_mux_qpic_pad4,

What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
alternative muxings...?

> + msm_mux_blsp4_uart0,
> + 

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Rob Herring]

On Thu, May 04, 2017 at 05:23:57PM +0530, Varadarajan Narayanan wrote:
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for ipq8074.
> 
> Signed-off-by: Manoharan Vijaya Raghavan 
> Signed-off-by: Varadarajan Narayanan 
> ---
>  .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt  |  187 +++

Acked-by: Rob Herring 

>  drivers/pinctrl/qcom/Kconfig   |   10 +
>  drivers/pinctrl/qcom/Makefile  |1 +
>  drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 
> 
>  4 files changed, 1415 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
>  create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Rob Herring]

On Thu, May 04, 2017 at 05:23:57PM +0530, Varadarajan Narayanan wrote:
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for ipq8074.
> 
> Signed-off-by: Manoharan Vijaya Raghavan 
> Signed-off-by: Varadarajan Narayanan 
> ---
>  .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt  |  187 +++

Acked-by: Rob Herring 

>  drivers/pinctrl/qcom/Kconfig   |   10 +
>  drivers/pinctrl/qcom/Makefile  |1 +
>  drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 
> 
>  4 files changed, 1415 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
>  create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Varadarajan Narayanan]

+ Bjorn Andersson

On 5/4/2017 5:23 PM, Varadarajan Narayanan wrote:

Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq8074.

Signed-off-by: Manoharan Vijaya Raghavan 
Signed-off-by: Varadarajan Narayanan 
---
  .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt  |  187 +++
  drivers/pinctrl/qcom/Kconfig   |   10 +
  drivers/pinctrl/qcom/Makefile  |1 +
  drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 
  4 files changed, 1415 insertions(+)
  create mode 100644 
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
  create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
new file mode 100644
index 000..7765bca
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
@@ -0,0 +1,187 @@
+Qualcomm Technologies, Inc. IPQ8074 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+IPQ8074 platform.
+
+- compatible:
+   Usage: required
+   Value type: 
+   Definition: must be "qcom,ipq8074-pinctrl"
+
+- reg:
+   Usage: required
+   Value type: 
+   Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+   Usage: required
+   Value type: 
+   Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+   Usage: required
+   Value type: 
+   Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+   Usage: required
+   Value type: 
+   Definition: must be 2. Specifying the pin number and flags, as defined
+   in 
+
+- gpio-controller:
+   Usage: required
+   Value type: 
+   Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+   Usage: required
+   Value type: 
+   Definition: must be 2. Specifying the pin number and flags, as defined
+   in 
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+   Usage: required
+   Value type: 
+   Definition: List of gpio pins affected by the properties specified in
+   this subnode.  Valid pins are:
+   gpio0-gpio121,
+   sdc1_clk,
+   sdc1_cmd,
+   sdc1_data
+   sdc2_clk,
+   sdc2_cmd,
+   sdc2_data,
+   qdsd_cmd,
+   qdsd_data0,
+   qdsd_data1,
+   qdsd_data2,
+   qdsd_data3
+
+- function:
+   Usage: required
+   Value type: 
+   Definition: Specify the alternative function to be configured for the
+   specified pins. Functions are only valid for gpio pins.
+   Valid values are:
+   gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
+   burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
+   qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
+   blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+   qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
+   qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
+   qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
+   qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
+   qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
+   qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
+   pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+   

Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

[Varadarajan Narayanan]

+ Bjorn Andersson

On 5/4/2017 5:23 PM, Varadarajan Narayanan wrote:

Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq8074.

Signed-off-by: Manoharan Vijaya Raghavan 
Signed-off-by: Varadarajan Narayanan 
---
  .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt  |  187 +++
  drivers/pinctrl/qcom/Kconfig   |   10 +
  drivers/pinctrl/qcom/Makefile  |1 +
  drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1217 
  4 files changed, 1415 insertions(+)
  create mode 100644 
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
  create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
new file mode 100644
index 000..7765bca
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
@@ -0,0 +1,187 @@
+Qualcomm Technologies, Inc. IPQ8074 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+IPQ8074 platform.
+
+- compatible:
+   Usage: required
+   Value type: 
+   Definition: must be "qcom,ipq8074-pinctrl"
+
+- reg:
+   Usage: required
+   Value type: 
+   Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+   Usage: required
+   Value type: 
+   Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+   Usage: required
+   Value type: 
+   Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+   Usage: required
+   Value type: 
+   Definition: must be 2. Specifying the pin number and flags, as defined
+   in 
+
+- gpio-controller:
+   Usage: required
+   Value type: 
+   Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+   Usage: required
+   Value type: 
+   Definition: must be 2. Specifying the pin number and flags, as defined
+   in 
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+   Usage: required
+   Value type: 
+   Definition: List of gpio pins affected by the properties specified in
+   this subnode.  Valid pins are:
+   gpio0-gpio121,
+   sdc1_clk,
+   sdc1_cmd,
+   sdc1_data
+   sdc2_clk,
+   sdc2_cmd,
+   sdc2_data,
+   qdsd_cmd,
+   qdsd_data0,
+   qdsd_data1,
+   qdsd_data2,
+   qdsd_data3
+
+- function:
+   Usage: required
+   Value type: 
+   Definition: Specify the alternative function to be configured for the
+   specified pins. Functions are only valid for gpio pins.
+   Valid values are:
+   gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
+   burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
+   qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
+   blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+   qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
+   qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
+   qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
+   qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
+   qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
+   qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
+   pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+   blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk,