Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
On 8/28/2018 2:34 AM, Stephen Boyd wrote: Quoting Stephen Boyd (2018-08-23 11:25:41) Quoting Taniya Das (2018-08-22 03:28:31) H. Ok. That won't work then. recalc_rate() better not try to populate the frequency table then or it will not work. So I suppose it needs to fallback to reading the registers and assuming the parent_rate coming in is the actual frequency of it's parent until the frequency table pointer is non-NULL. Would that work? Yes that would work. Ok. BTW, does DFS switch parents without software knowing about it? DFS would not switch until a HW request is sent, but SW would be unware of the switch except the current_perf_state being updated with the requested level. What happens in that case? Does the QUP driver make sure that the new parent of this RCG is properly enabled so that it can switch to it when needed? I am not sure if they poll for any of their QUP HW state to make sure the switch is complete. I'm still trying to understand this whole design. Who takes care of the voltage requirements in this case? The QUP driver as well? When the QUP driver requires to switch to new performance level, the first request would be to set_rate()(QUP driver would get the list of supported frequencies using the clk_round_rate()) which in QCOM clock driver would take care of setting the required voltage for the new parent switch. It would also make sure that the new parent is enabled if the QUP clk is enabled. That's another concern. Does the PLL turn on automatically when the RCG switches to it? Then the QUP driver would request the HW for a new perf switch which would result to a DFS switch for the QUP clocks. It sounds like the QUP driver does half of the work via the clk APIs and then the other half through the DFS register. Maybe the QUP driver should be registering a clk as well for its DFS register so it can all be clk API calls here. Something to consider. Anyway, that's not important to this patch so here's the updated patch. I've squashed this in and applied the patches. Thanks Stephen. -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
On 8/28/2018 2:34 AM, Stephen Boyd wrote: Quoting Stephen Boyd (2018-08-23 11:25:41) Quoting Taniya Das (2018-08-22 03:28:31) H. Ok. That won't work then. recalc_rate() better not try to populate the frequency table then or it will not work. So I suppose it needs to fallback to reading the registers and assuming the parent_rate coming in is the actual frequency of it's parent until the frequency table pointer is non-NULL. Would that work? Yes that would work. Ok. BTW, does DFS switch parents without software knowing about it? DFS would not switch until a HW request is sent, but SW would be unware of the switch except the current_perf_state being updated with the requested level. What happens in that case? Does the QUP driver make sure that the new parent of this RCG is properly enabled so that it can switch to it when needed? I am not sure if they poll for any of their QUP HW state to make sure the switch is complete. I'm still trying to understand this whole design. Who takes care of the voltage requirements in this case? The QUP driver as well? When the QUP driver requires to switch to new performance level, the first request would be to set_rate()(QUP driver would get the list of supported frequencies using the clk_round_rate()) which in QCOM clock driver would take care of setting the required voltage for the new parent switch. It would also make sure that the new parent is enabled if the QUP clk is enabled. That's another concern. Does the PLL turn on automatically when the RCG switches to it? Then the QUP driver would request the HW for a new perf switch which would result to a DFS switch for the QUP clocks. It sounds like the QUP driver does half of the work via the clk APIs and then the other half through the DFS register. Maybe the QUP driver should be registering a clk as well for its DFS register so it can all be clk API calls here. Something to consider. Anyway, that's not important to this patch so here's the updated patch. I've squashed this in and applied the patches. Thanks Stephen. -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
Quoting Stephen Boyd (2018-08-23 11:25:41) > Quoting Taniya Das (2018-08-22 03:28:31) > > > > > > > > H. Ok. That won't work then. recalc_rate() better not try to > > > populate the frequency table then or it will not work. So I suppose it > > > needs to fallback to reading the registers and assuming the parent_rate > > > coming in is the actual frequency of it's parent until the frequency > > > table pointer is non-NULL. Would that work? > > > > > Yes that would work. > > Ok. > > > > > > BTW, does DFS switch parents without software knowing about it? > > DFS would not switch until a HW request is sent, but SW would be unware > > of the switch except the current_perf_state being updated with the > > requested level. > > > > What > > > happens in that case? Does the QUP driver make sure that the new parent > > > of this RCG is properly enabled so that it can switch to it when needed? > > > > I am not sure if they poll for any of their QUP HW state to make sure > > the switch is complete. > > > > > I'm still trying to understand this whole design. Who takes care of the > > > voltage requirements in this case? The QUP driver as well? > > > > > > > When the QUP driver requires to switch to new performance level, the > > first request would be to set_rate()(QUP driver would get the list of > > supported frequencies using the clk_round_rate()) which in QCOM clock > > driver would take care of setting the required voltage for the new > > parent switch. > > It would also make sure that the new parent is enabled if the QUP clk is > enabled. That's another concern. Does the PLL turn on automatically when > the RCG switches to it? > > > Then the QUP driver would request the HW for a new perf switch which > > would result to a DFS switch for the QUP clocks. > > It sounds like the QUP driver does half of the work via the clk APIs and > then the other half through the DFS register. Maybe the QUP driver > should be registering a clk as well for its DFS register so it can all > be clk API calls here. Something to consider. Anyway, that's not > important to this patch so here's the updated patch. I've squashed this in and applied the patches.
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
Quoting Stephen Boyd (2018-08-23 11:25:41) > Quoting Taniya Das (2018-08-22 03:28:31) > > > > > > > > H. Ok. That won't work then. recalc_rate() better not try to > > > populate the frequency table then or it will not work. So I suppose it > > > needs to fallback to reading the registers and assuming the parent_rate > > > coming in is the actual frequency of it's parent until the frequency > > > table pointer is non-NULL. Would that work? > > > > > Yes that would work. > > Ok. > > > > > > BTW, does DFS switch parents without software knowing about it? > > DFS would not switch until a HW request is sent, but SW would be unware > > of the switch except the current_perf_state being updated with the > > requested level. > > > > What > > > happens in that case? Does the QUP driver make sure that the new parent > > > of this RCG is properly enabled so that it can switch to it when needed? > > > > I am not sure if they poll for any of their QUP HW state to make sure > > the switch is complete. > > > > > I'm still trying to understand this whole design. Who takes care of the > > > voltage requirements in this case? The QUP driver as well? > > > > > > > When the QUP driver requires to switch to new performance level, the > > first request would be to set_rate()(QUP driver would get the list of > > supported frequencies using the clk_round_rate()) which in QCOM clock > > driver would take care of setting the required voltage for the new > > parent switch. > > It would also make sure that the new parent is enabled if the QUP clk is > enabled. That's another concern. Does the PLL turn on automatically when > the RCG switches to it? > > > Then the QUP driver would request the HW for a new perf switch which > > would result to a DFS switch for the QUP clocks. > > It sounds like the QUP driver does half of the work via the clk APIs and > then the other half through the DFS register. Maybe the QUP driver > should be registering a clk as well for its DFS register so it can all > be clk API calls here. Something to consider. Anyway, that's not > important to this patch so here's the updated patch. I've squashed this in and applied the patches.
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
Quoting Taniya Das (2018-08-22 03:28:31)
>
> >
> > H. Ok. That won't work then. recalc_rate() better not try to
> > populate the frequency table then or it will not work. So I suppose it
> > needs to fallback to reading the registers and assuming the parent_rate
> > coming in is the actual frequency of it's parent until the frequency
> > table pointer is non-NULL. Would that work?
> >
> Yes that would work.
Ok.
>
> > BTW, does DFS switch parents without software knowing about it?
> DFS would not switch until a HW request is sent, but SW would be unware
> of the switch except the current_perf_state being updated with the
> requested level.
>
> What
> > happens in that case? Does the QUP driver make sure that the new parent
> > of this RCG is properly enabled so that it can switch to it when needed?
>
> I am not sure if they poll for any of their QUP HW state to make sure
> the switch is complete.
>
> > I'm still trying to understand this whole design. Who takes care of the
> > voltage requirements in this case? The QUP driver as well?
> >
>
> When the QUP driver requires to switch to new performance level, the
> first request would be to set_rate()(QUP driver would get the list of
> supported frequencies using the clk_round_rate()) which in QCOM clock
> driver would take care of setting the required voltage for the new
> parent switch.
It would also make sure that the new parent is enabled if the QUP clk is
enabled. That's another concern. Does the PLL turn on automatically when
the RCG switches to it?
> Then the QUP driver would request the HW for a new perf switch which
> would result to a DFS switch for the QUP clocks.
It sounds like the QUP driver does half of the work via the clk APIs and
then the other half through the DFS register. Maybe the QUP driver
should be registering a clk as well for its DFS register so it can all
be clk API calls here. Something to consider. Anyway, that's not
important to this patch so here's the updated patch.
---8<
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index e6300e05d5df..e5eca8a1abe4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -163,6 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
extern const struct clk_ops clk_gfx3d_ops;
extern const struct clk_ops clk_rcg2_shared_ops;
+struct clk_rcg_dfs_data {
+ struct clk_rcg2 *rcg;
+ struct clk_init_data *init;
+};
+
+#define DEFINE_RCG_DFS(r) \
+ { .rcg = ##_src, .init = ##_init }
+
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
-struct clk_rcg2 **rcgs, int num_clks);
+ const struct clk_rcg_dfs_data *rcgs,
+ size_t len);
#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 55a5b58cbb15..d5d77f9ad170 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -940,25 +940,21 @@ const struct clk_ops clk_rcg2_shared_ops = {
EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
/* Common APIs to be used for DFS based RCGR */
-static unsigned long clk_rcg2_calculate_freq(struct clk_hw *hw,
- int level, struct freq_tbl *f)
+static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
+ struct freq_tbl *f)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
struct clk_hw *p;
unsigned long prate = 0;
- u32 val, mask, cfg, m_off, n_off, offset, mode;
- int i, ret, num_parents;
+ u32 val, mask, cfg, mode;
+ int i, num_parents;
- offset = SE_PERF_DFSR(level);
- ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + offset, );
- if (ret)
- return ret;
+ regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), );
mask = BIT(rcg->hid_width) - 1;
- f->pre_div = cfg & mask ? (cfg & mask) : 1;
-
- mode = cfg & CFG_MODE_MASK;
- mode >>= CFG_MODE_SHIFT;
+ f->pre_div = 1;
+ if (cfg & mask)
+ f->pre_div = cfg & mask;
cfg &= CFG_SRC_SEL_MASK;
cfg >>= CFG_SRC_SEL_SHIFT;
@@ -972,60 +968,39 @@ static unsigned long clk_rcg2_calculate_freq(struct
clk_hw *hw,
}
}
+ mode = cfg & CFG_MODE_MASK;
+ mode >>= CFG_MODE_SHIFT;
if (mode) {
- /* Calculate M & N values */
- m_off = SE_PERF_M_DFSR(level);
- n_off = SE_PERF_N_DFSR(level);
-
mask = BIT(rcg->mnd_width) - 1;
- ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + m_off,
- );
- if (ret) {
- pr_err("Failed to read M offset register\n");
- return ret;
- }
+ regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),
+ );
val &= mask;
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
Quoting Taniya Das (2018-08-22 03:28:31)
>
> >
> > H. Ok. That won't work then. recalc_rate() better not try to
> > populate the frequency table then or it will not work. So I suppose it
> > needs to fallback to reading the registers and assuming the parent_rate
> > coming in is the actual frequency of it's parent until the frequency
> > table pointer is non-NULL. Would that work?
> >
> Yes that would work.
Ok.
>
> > BTW, does DFS switch parents without software knowing about it?
> DFS would not switch until a HW request is sent, but SW would be unware
> of the switch except the current_perf_state being updated with the
> requested level.
>
> What
> > happens in that case? Does the QUP driver make sure that the new parent
> > of this RCG is properly enabled so that it can switch to it when needed?
>
> I am not sure if they poll for any of their QUP HW state to make sure
> the switch is complete.
>
> > I'm still trying to understand this whole design. Who takes care of the
> > voltage requirements in this case? The QUP driver as well?
> >
>
> When the QUP driver requires to switch to new performance level, the
> first request would be to set_rate()(QUP driver would get the list of
> supported frequencies using the clk_round_rate()) which in QCOM clock
> driver would take care of setting the required voltage for the new
> parent switch.
It would also make sure that the new parent is enabled if the QUP clk is
enabled. That's another concern. Does the PLL turn on automatically when
the RCG switches to it?
> Then the QUP driver would request the HW for a new perf switch which
> would result to a DFS switch for the QUP clocks.
It sounds like the QUP driver does half of the work via the clk APIs and
then the other half through the DFS register. Maybe the QUP driver
should be registering a clk as well for its DFS register so it can all
be clk API calls here. Something to consider. Anyway, that's not
important to this patch so here's the updated patch.
---8<
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index e6300e05d5df..e5eca8a1abe4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -163,6 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
extern const struct clk_ops clk_gfx3d_ops;
extern const struct clk_ops clk_rcg2_shared_ops;
+struct clk_rcg_dfs_data {
+ struct clk_rcg2 *rcg;
+ struct clk_init_data *init;
+};
+
+#define DEFINE_RCG_DFS(r) \
+ { .rcg = ##_src, .init = ##_init }
+
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
-struct clk_rcg2 **rcgs, int num_clks);
+ const struct clk_rcg_dfs_data *rcgs,
+ size_t len);
#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 55a5b58cbb15..d5d77f9ad170 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -940,25 +940,21 @@ const struct clk_ops clk_rcg2_shared_ops = {
EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
/* Common APIs to be used for DFS based RCGR */
-static unsigned long clk_rcg2_calculate_freq(struct clk_hw *hw,
- int level, struct freq_tbl *f)
+static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
+ struct freq_tbl *f)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
struct clk_hw *p;
unsigned long prate = 0;
- u32 val, mask, cfg, m_off, n_off, offset, mode;
- int i, ret, num_parents;
+ u32 val, mask, cfg, mode;
+ int i, num_parents;
- offset = SE_PERF_DFSR(level);
- ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + offset, );
- if (ret)
- return ret;
+ regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), );
mask = BIT(rcg->hid_width) - 1;
- f->pre_div = cfg & mask ? (cfg & mask) : 1;
-
- mode = cfg & CFG_MODE_MASK;
- mode >>= CFG_MODE_SHIFT;
+ f->pre_div = 1;
+ if (cfg & mask)
+ f->pre_div = cfg & mask;
cfg &= CFG_SRC_SEL_MASK;
cfg >>= CFG_SRC_SEL_SHIFT;
@@ -972,60 +968,39 @@ static unsigned long clk_rcg2_calculate_freq(struct
clk_hw *hw,
}
}
+ mode = cfg & CFG_MODE_MASK;
+ mode >>= CFG_MODE_SHIFT;
if (mode) {
- /* Calculate M & N values */
- m_off = SE_PERF_M_DFSR(level);
- n_off = SE_PERF_N_DFSR(level);
-
mask = BIT(rcg->mnd_width) - 1;
- ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + m_off,
- );
- if (ret) {
- pr_err("Failed to read M offset register\n");
- return ret;
- }
+ regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),
+ );
val &= mask;
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
On 8/21/2018 9:00 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-21 04:36:20)
On 8/18/2018 11:31 PM, Taniya Das wrote:
Hello Stephen,
I will test these changes and get back.
On 8/18/2018 7:42 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-10 18:53:54)
[v4]
* Add recalc_clk_ops to calculate the clock frequency reading the
current
perf state, also add CLK_GET_RATE_NOCACHE flag.
* Cleanup 'goto' during mode check in 'clk_rcg2_calculate_freq'.
* cleanup return from function 'com_cc_register_rcg_dfs'.
I want to squash this in. I have only compile tested it. Let me know
what you think.
8<---
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index e6300e05d5df..e5eca8a1abe4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -163,6 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
extern const struct clk_ops clk_gfx3d_ops;
extern const struct clk_ops clk_rcg2_shared_ops;
+struct clk_rcg_dfs_data {
+ struct clk_rcg2 *rcg;
+ struct clk_init_data *init;
+};
+
+#define DEFINE_RCG_DFS(r) \
+ { .rcg = ##_src, .init = ##_init }
+
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
- struct clk_rcg2 **rcgs, int num_clks);
+ const struct clk_rcg_dfs_data *rcgs,
+ size_t len);
#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 55a5b58cbb15..bbe2a1916296 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -1051,48 +1051,24 @@ static unsigned long
clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
- u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask, level;
- int num_parents, i;
- unsigned long prate;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_CMD_DFSR_OFFSET, );
- level = (GENMASK(4, 1) & cfg) >> 1;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_DFSR(level), );
- if (rcg->mnd_width) {
- mask = BIT(rcg->mnd_width) - 1;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_M_DFSR(level), );
- m &= mask;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_N_DFSR(level), );
- n = ~n;
- n &= mask;
- n += m;
- mode = cfg & CFG_MODE_MASK;
- mode >>= CFG_MODE_SHIFT;
- }
+ int ret;
+ u32 level;
- mask = BIT(rcg->hid_width) - 1;
- hid_div = cfg >> CFG_SRC_DIV_SHIFT;
- hid_div &= mask;
- cfg &= CFG_SRC_SEL_MASK;
- cfg >>= CFG_SRC_SEL_SHIFT;
+ regmap_read(rcg->clkr.regmap,
+ rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, );
+ level &= GENMASK(4, 1);
+ level >>= 1;
- num_parents = clk_hw_get_num_parents(hw);
- for (i = 0; i < num_parents; i++) {
- if (cfg == rcg->parent_map[i].cfg) {
- prate = clk_hw_get_rate(
- clk_hw_get_parent_by_index(>clkr.hw, i));
- if (parent_rate != prate)
- parent_rate = prate;
+ if (!rcg->freq_tbl) {
+ ret = clk_rcg2_dfs_populate_freq_table(rcg);
This function would retrieve the parent_rate and if the parent_rate is
not ready then it would fail to boot up.
So we have to make sure the parents are registered before these RCGs.
That also was one reason for me to not populate the frequency table at
recalc.
We would need this patch to make this work.
H. Ok. That won't work then. recalc_rate() better not try to
populate the frequency table then or it will not work. So I suppose it
needs to fallback to reading the registers and assuming the parent_rate
coming in is the actual frequency of it's parent until the frequency
table pointer is non-NULL. Would that work?
Yes that would work.
BTW, does DFS switch parents without software knowing about it?
DFS would not switch until a HW request is sent, but SW would be unware
of the switch except the current_perf_state being updated with the
requested level.
What
happens in that case? Does the QUP driver make sure that the new parent
of this RCG is properly enabled so that it can switch to it when needed?
I am not sure if they poll for any of their QUP HW state to make sure
the switch is complete.
I'm still trying to understand this whole design. Who takes care of the
voltage requirements in this case? The QUP driver as well?
When the QUP driver requires to switch to new performance level, the
first request would be to set_rate()(QUP driver would get the list of
supported frequencies using the clk_round_rate()) which in QCOM clock
driver would take care of setting the required voltage for the new
parent switch.
Then the QUP driver would request the HW for a new perf switch which
would result to a DFS switch for the QUP clocks.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
On 8/21/2018 9:00 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-21 04:36:20)
On 8/18/2018 11:31 PM, Taniya Das wrote:
Hello Stephen,
I will test these changes and get back.
On 8/18/2018 7:42 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-10 18:53:54)
[v4]
* Add recalc_clk_ops to calculate the clock frequency reading the
current
perf state, also add CLK_GET_RATE_NOCACHE flag.
* Cleanup 'goto' during mode check in 'clk_rcg2_calculate_freq'.
* cleanup return from function 'com_cc_register_rcg_dfs'.
I want to squash this in. I have only compile tested it. Let me know
what you think.
8<---
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index e6300e05d5df..e5eca8a1abe4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -163,6 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
extern const struct clk_ops clk_gfx3d_ops;
extern const struct clk_ops clk_rcg2_shared_ops;
+struct clk_rcg_dfs_data {
+ struct clk_rcg2 *rcg;
+ struct clk_init_data *init;
+};
+
+#define DEFINE_RCG_DFS(r) \
+ { .rcg = ##_src, .init = ##_init }
+
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
- struct clk_rcg2 **rcgs, int num_clks);
+ const struct clk_rcg_dfs_data *rcgs,
+ size_t len);
#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 55a5b58cbb15..bbe2a1916296 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -1051,48 +1051,24 @@ static unsigned long
clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
- u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask, level;
- int num_parents, i;
- unsigned long prate;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_CMD_DFSR_OFFSET, );
- level = (GENMASK(4, 1) & cfg) >> 1;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_DFSR(level), );
- if (rcg->mnd_width) {
- mask = BIT(rcg->mnd_width) - 1;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_M_DFSR(level), );
- m &= mask;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_N_DFSR(level), );
- n = ~n;
- n &= mask;
- n += m;
- mode = cfg & CFG_MODE_MASK;
- mode >>= CFG_MODE_SHIFT;
- }
+ int ret;
+ u32 level;
- mask = BIT(rcg->hid_width) - 1;
- hid_div = cfg >> CFG_SRC_DIV_SHIFT;
- hid_div &= mask;
- cfg &= CFG_SRC_SEL_MASK;
- cfg >>= CFG_SRC_SEL_SHIFT;
+ regmap_read(rcg->clkr.regmap,
+ rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, );
+ level &= GENMASK(4, 1);
+ level >>= 1;
- num_parents = clk_hw_get_num_parents(hw);
- for (i = 0; i < num_parents; i++) {
- if (cfg == rcg->parent_map[i].cfg) {
- prate = clk_hw_get_rate(
- clk_hw_get_parent_by_index(>clkr.hw, i));
- if (parent_rate != prate)
- parent_rate = prate;
+ if (!rcg->freq_tbl) {
+ ret = clk_rcg2_dfs_populate_freq_table(rcg);
This function would retrieve the parent_rate and if the parent_rate is
not ready then it would fail to boot up.
So we have to make sure the parents are registered before these RCGs.
That also was one reason for me to not populate the frequency table at
recalc.
We would need this patch to make this work.
H. Ok. That won't work then. recalc_rate() better not try to
populate the frequency table then or it will not work. So I suppose it
needs to fallback to reading the registers and assuming the parent_rate
coming in is the actual frequency of it's parent until the frequency
table pointer is non-NULL. Would that work?
Yes that would work.
BTW, does DFS switch parents without software knowing about it?
DFS would not switch until a HW request is sent, but SW would be unware
of the switch except the current_perf_state being updated with the
requested level.
What
happens in that case? Does the QUP driver make sure that the new parent
of this RCG is properly enabled so that it can switch to it when needed?
I am not sure if they poll for any of their QUP HW state to make sure
the switch is complete.
I'm still trying to understand this whole design. Who takes care of the
voltage requirements in this case? The QUP driver as well?
When the QUP driver requires to switch to new performance level, the
first request would be to set_rate()(QUP driver would get the list of
supported frequencies using the clk_round_rate()) which in QCOM clock
driver would take care of setting the required voltage for the new
parent switch.
Then the QUP driver would request the HW for a new perf switch which
would result to a DFS switch for the QUP clocks.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
Quoting Taniya Das (2018-08-21 04:36:20)
> On 8/18/2018 11:31 PM, Taniya Das wrote:
> > Hello Stephen,
> >
> > I will test these changes and get back.
> >
> > On 8/18/2018 7:42 AM, Stephen Boyd wrote:
> >> Quoting Taniya Das (2018-08-10 18:53:54)
> >>> [v4]
> >>> * Add recalc_clk_ops to calculate the clock frequency reading the
> >>> current
> >>> perf state, also add CLK_GET_RATE_NOCACHE flag.
> >>> * Cleanup 'goto' during mode check in 'clk_rcg2_calculate_freq'.
> >>> * cleanup return from function 'com_cc_register_rcg_dfs'.
> >>
> >> I want to squash this in. I have only compile tested it. Let me know
> >> what you think.
> >>
> >> 8<---
> >> diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
> >> index e6300e05d5df..e5eca8a1abe4 100644
> >> --- a/drivers/clk/qcom/clk-rcg.h
> >> +++ b/drivers/clk/qcom/clk-rcg.h
> >> @@ -163,6 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
> >> extern const struct clk_ops clk_gfx3d_ops;
> >> extern const struct clk_ops clk_rcg2_shared_ops;
> >> +struct clk_rcg_dfs_data {
> >> + struct clk_rcg2 *rcg;
> >> + struct clk_init_data *init;
> >> +};
> >> +
> >> +#define DEFINE_RCG_DFS(r) \
> >> + { .rcg = ##_src, .init = ##_init }
> >> +
> >> extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
> >> - struct clk_rcg2 **rcgs, int num_clks);
> >> + const struct clk_rcg_dfs_data *rcgs,
> >> + size_t len);
> >> #endif
> >> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
> >> index 55a5b58cbb15..bbe2a1916296 100644
> >> --- a/drivers/clk/qcom/clk-rcg2.c
> >> +++ b/drivers/clk/qcom/clk-rcg2.c
> >> @@ -1051,48 +1051,24 @@ static unsigned long
> >> clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> >> {
> >> struct clk_rcg2 *rcg = to_clk_rcg2(hw);
> >> - u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask, level;
> >> - int num_parents, i;
> >> - unsigned long prate;
> >> -
> >> - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
> >> - SE_CMD_DFSR_OFFSET, );
> >> - level = (GENMASK(4, 1) & cfg) >> 1;
> >> -
> >> - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
> >> - SE_PERF_DFSR(level), );
> >> - if (rcg->mnd_width) {
> >> - mask = BIT(rcg->mnd_width) - 1;
> >> - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
> >> - SE_PERF_M_DFSR(level), );
> >> - m &= mask;
> >> - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
> >> - SE_PERF_N_DFSR(level), );
> >> - n = ~n;
> >> - n &= mask;
> >> - n += m;
> >> - mode = cfg & CFG_MODE_MASK;
> >> - mode >>= CFG_MODE_SHIFT;
> >> - }
> >> + int ret;
> >> + u32 level;
> >> - mask = BIT(rcg->hid_width) - 1;
> >> - hid_div = cfg >> CFG_SRC_DIV_SHIFT;
> >> - hid_div &= mask;
> >> - cfg &= CFG_SRC_SEL_MASK;
> >> - cfg >>= CFG_SRC_SEL_SHIFT;
> >> + regmap_read(rcg->clkr.regmap,
> >> + rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, );
> >> + level &= GENMASK(4, 1);
> >> + level >>= 1;
> >> - num_parents = clk_hw_get_num_parents(hw);
> >> - for (i = 0; i < num_parents; i++) {
> >> - if (cfg == rcg->parent_map[i].cfg) {
> >> - prate = clk_hw_get_rate(
> >> - clk_hw_get_parent_by_index(>clkr.hw, i));
> >> - if (parent_rate != prate)
> >> - parent_rate = prate;
> >> + if (!rcg->freq_tbl) {
> >> + ret = clk_rcg2_dfs_populate_freq_table(rcg);
>
> This function would retrieve the parent_rate and if the parent_rate is
> not ready then it would fail to boot up.
>
> So we have to make sure the parents are registered before these RCGs.
> That also was one reason for me to not populate the frequency table at
> recalc.
>
> We would need this patch to make this work.
H. Ok. That won't work then. recalc_rate() better not try to
populate the frequency table then or it will not work. So I suppose it
needs to fallback to reading the registers and assuming the parent_rate
coming in is the actual frequency of it's parent until the frequency
table pointer is non-NULL. Would that work?
BTW, does DFS switch parents without software knowing about it? What
happens in that case? Does the QUP driver make sure that the new parent
of this RCG is properly enabled so that it can switch to it when needed?
I'm still trying to understand this whole design. Who takes care of the
voltage requirements in this case? The QUP driver as well?
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
Quoting Taniya Das (2018-08-21 04:36:20)
> On 8/18/2018 11:31 PM, Taniya Das wrote:
> > Hello Stephen,
> >
> > I will test these changes and get back.
> >
> > On 8/18/2018 7:42 AM, Stephen Boyd wrote:
> >> Quoting Taniya Das (2018-08-10 18:53:54)
> >>> [v4]
> >>> * Add recalc_clk_ops to calculate the clock frequency reading the
> >>> current
> >>> perf state, also add CLK_GET_RATE_NOCACHE flag.
> >>> * Cleanup 'goto' during mode check in 'clk_rcg2_calculate_freq'.
> >>> * cleanup return from function 'com_cc_register_rcg_dfs'.
> >>
> >> I want to squash this in. I have only compile tested it. Let me know
> >> what you think.
> >>
> >> 8<---
> >> diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
> >> index e6300e05d5df..e5eca8a1abe4 100644
> >> --- a/drivers/clk/qcom/clk-rcg.h
> >> +++ b/drivers/clk/qcom/clk-rcg.h
> >> @@ -163,6 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
> >> extern const struct clk_ops clk_gfx3d_ops;
> >> extern const struct clk_ops clk_rcg2_shared_ops;
> >> +struct clk_rcg_dfs_data {
> >> + struct clk_rcg2 *rcg;
> >> + struct clk_init_data *init;
> >> +};
> >> +
> >> +#define DEFINE_RCG_DFS(r) \
> >> + { .rcg = ##_src, .init = ##_init }
> >> +
> >> extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
> >> - struct clk_rcg2 **rcgs, int num_clks);
> >> + const struct clk_rcg_dfs_data *rcgs,
> >> + size_t len);
> >> #endif
> >> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
> >> index 55a5b58cbb15..bbe2a1916296 100644
> >> --- a/drivers/clk/qcom/clk-rcg2.c
> >> +++ b/drivers/clk/qcom/clk-rcg2.c
> >> @@ -1051,48 +1051,24 @@ static unsigned long
> >> clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> >> {
> >> struct clk_rcg2 *rcg = to_clk_rcg2(hw);
> >> - u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask, level;
> >> - int num_parents, i;
> >> - unsigned long prate;
> >> -
> >> - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
> >> - SE_CMD_DFSR_OFFSET, );
> >> - level = (GENMASK(4, 1) & cfg) >> 1;
> >> -
> >> - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
> >> - SE_PERF_DFSR(level), );
> >> - if (rcg->mnd_width) {
> >> - mask = BIT(rcg->mnd_width) - 1;
> >> - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
> >> - SE_PERF_M_DFSR(level), );
> >> - m &= mask;
> >> - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
> >> - SE_PERF_N_DFSR(level), );
> >> - n = ~n;
> >> - n &= mask;
> >> - n += m;
> >> - mode = cfg & CFG_MODE_MASK;
> >> - mode >>= CFG_MODE_SHIFT;
> >> - }
> >> + int ret;
> >> + u32 level;
> >> - mask = BIT(rcg->hid_width) - 1;
> >> - hid_div = cfg >> CFG_SRC_DIV_SHIFT;
> >> - hid_div &= mask;
> >> - cfg &= CFG_SRC_SEL_MASK;
> >> - cfg >>= CFG_SRC_SEL_SHIFT;
> >> + regmap_read(rcg->clkr.regmap,
> >> + rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, );
> >> + level &= GENMASK(4, 1);
> >> + level >>= 1;
> >> - num_parents = clk_hw_get_num_parents(hw);
> >> - for (i = 0; i < num_parents; i++) {
> >> - if (cfg == rcg->parent_map[i].cfg) {
> >> - prate = clk_hw_get_rate(
> >> - clk_hw_get_parent_by_index(>clkr.hw, i));
> >> - if (parent_rate != prate)
> >> - parent_rate = prate;
> >> + if (!rcg->freq_tbl) {
> >> + ret = clk_rcg2_dfs_populate_freq_table(rcg);
>
> This function would retrieve the parent_rate and if the parent_rate is
> not ready then it would fail to boot up.
>
> So we have to make sure the parents are registered before these RCGs.
> That also was one reason for me to not populate the frequency table at
> recalc.
>
> We would need this patch to make this work.
H. Ok. That won't work then. recalc_rate() better not try to
populate the frequency table then or it will not work. So I suppose it
needs to fallback to reading the registers and assuming the parent_rate
coming in is the actual frequency of it's parent until the frequency
table pointer is non-NULL. Would that work?
BTW, does DFS switch parents without software knowing about it? What
happens in that case? Does the QUP driver make sure that the new parent
of this RCG is properly enabled so that it can switch to it when needed?
I'm still trying to understand this whole design. Who takes care of the
voltage requirements in this case? The QUP driver as well?
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
Hello Stephen,
Thanks for the changes, I have tested the changes and would require the
change mentioned below for this to work.
On 8/18/2018 11:31 PM, Taniya Das wrote:
Hello Stephen,
I will test these changes and get back.
On 8/18/2018 7:42 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-10 18:53:54)
[v4]
* Add recalc_clk_ops to calculate the clock frequency reading the
current
perf state, also add CLK_GET_RATE_NOCACHE flag.
* Cleanup 'goto' during mode check in 'clk_rcg2_calculate_freq'.
* cleanup return from function 'com_cc_register_rcg_dfs'.
I want to squash this in. I have only compile tested it. Let me know
what you think.
8<---
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index e6300e05d5df..e5eca8a1abe4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -163,6 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
extern const struct clk_ops clk_gfx3d_ops;
extern const struct clk_ops clk_rcg2_shared_ops;
+struct clk_rcg_dfs_data {
+ struct clk_rcg2 *rcg;
+ struct clk_init_data *init;
+};
+
+#define DEFINE_RCG_DFS(r) \
+ { .rcg = ##_src, .init = ##_init }
+
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
- struct clk_rcg2 **rcgs, int num_clks);
+ const struct clk_rcg_dfs_data *rcgs,
+ size_t len);
#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 55a5b58cbb15..bbe2a1916296 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -1051,48 +1051,24 @@ static unsigned long
clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
- u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask, level;
- int num_parents, i;
- unsigned long prate;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_CMD_DFSR_OFFSET, );
- level = (GENMASK(4, 1) & cfg) >> 1;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_DFSR(level), );
- if (rcg->mnd_width) {
- mask = BIT(rcg->mnd_width) - 1;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_M_DFSR(level), );
- m &= mask;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_N_DFSR(level), );
- n = ~n;
- n &= mask;
- n += m;
- mode = cfg & CFG_MODE_MASK;
- mode >>= CFG_MODE_SHIFT;
- }
+ int ret;
+ u32 level;
- mask = BIT(rcg->hid_width) - 1;
- hid_div = cfg >> CFG_SRC_DIV_SHIFT;
- hid_div &= mask;
- cfg &= CFG_SRC_SEL_MASK;
- cfg >>= CFG_SRC_SEL_SHIFT;
+ regmap_read(rcg->clkr.regmap,
+ rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, );
+ level &= GENMASK(4, 1);
+ level >>= 1;
- num_parents = clk_hw_get_num_parents(hw);
- for (i = 0; i < num_parents; i++) {
- if (cfg == rcg->parent_map[i].cfg) {
- prate = clk_hw_get_rate(
- clk_hw_get_parent_by_index(>clkr.hw, i));
- if (parent_rate != prate)
- parent_rate = prate;
+ if (!rcg->freq_tbl) {
+ ret = clk_rcg2_dfs_populate_freq_table(rcg);
This function would retrieve the parent_rate and if the parent_rate is
not ready then it would fail to boot up.
So we have to make sure the parents are registered before these RCGs.
That also was one reason for me to not populate the frequency table at
recalc.
We would need this patch to make this work.
/* GCC clock registers */
-#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
-#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
-#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
-#define GCC_AGGRE_USB3_PRIM_AXI_CLK3
+#define GPLL0 0
+#define GPLL0_OUT_EVEN 1
+#define GPLL0_OUT_MAIN 2
+#define GPLL4 3
#define GCC_AGGRE_USB3_SEC_AXI_CLK 4
#define GCC_BOOT_ROM_AHB_CLK 5
#define GCC_CAMERA_AHB_CLK 6
@@ -172,9 +172,9 @@
#define GCC_VIDEO_AHB_CLK 162
#define GCC_VIDEO_AXI_CLK 163
#define GCC_VIDEO_XO_CLK 164
-#define GPLL0 165
-#define GPLL0_OUT_EVEN 166
-#define GPLL0_OUT_MAIN 167
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK 165
+#define GCC_AGGRE_UFS_CARD_AXI_CLK 166
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 167
#define GCC_GPU_IREF_CLK 168
#define
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
Hello Stephen,
Thanks for the changes, I have tested the changes and would require the
change mentioned below for this to work.
On 8/18/2018 11:31 PM, Taniya Das wrote:
Hello Stephen,
I will test these changes and get back.
On 8/18/2018 7:42 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-10 18:53:54)
[v4]
* Add recalc_clk_ops to calculate the clock frequency reading the
current
perf state, also add CLK_GET_RATE_NOCACHE flag.
* Cleanup 'goto' during mode check in 'clk_rcg2_calculate_freq'.
* cleanup return from function 'com_cc_register_rcg_dfs'.
I want to squash this in. I have only compile tested it. Let me know
what you think.
8<---
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index e6300e05d5df..e5eca8a1abe4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -163,6 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
extern const struct clk_ops clk_gfx3d_ops;
extern const struct clk_ops clk_rcg2_shared_ops;
+struct clk_rcg_dfs_data {
+ struct clk_rcg2 *rcg;
+ struct clk_init_data *init;
+};
+
+#define DEFINE_RCG_DFS(r) \
+ { .rcg = ##_src, .init = ##_init }
+
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
- struct clk_rcg2 **rcgs, int num_clks);
+ const struct clk_rcg_dfs_data *rcgs,
+ size_t len);
#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 55a5b58cbb15..bbe2a1916296 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -1051,48 +1051,24 @@ static unsigned long
clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
- u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask, level;
- int num_parents, i;
- unsigned long prate;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_CMD_DFSR_OFFSET, );
- level = (GENMASK(4, 1) & cfg) >> 1;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_DFSR(level), );
- if (rcg->mnd_width) {
- mask = BIT(rcg->mnd_width) - 1;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_M_DFSR(level), );
- m &= mask;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_N_DFSR(level), );
- n = ~n;
- n &= mask;
- n += m;
- mode = cfg & CFG_MODE_MASK;
- mode >>= CFG_MODE_SHIFT;
- }
+ int ret;
+ u32 level;
- mask = BIT(rcg->hid_width) - 1;
- hid_div = cfg >> CFG_SRC_DIV_SHIFT;
- hid_div &= mask;
- cfg &= CFG_SRC_SEL_MASK;
- cfg >>= CFG_SRC_SEL_SHIFT;
+ regmap_read(rcg->clkr.regmap,
+ rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, );
+ level &= GENMASK(4, 1);
+ level >>= 1;
- num_parents = clk_hw_get_num_parents(hw);
- for (i = 0; i < num_parents; i++) {
- if (cfg == rcg->parent_map[i].cfg) {
- prate = clk_hw_get_rate(
- clk_hw_get_parent_by_index(>clkr.hw, i));
- if (parent_rate != prate)
- parent_rate = prate;
+ if (!rcg->freq_tbl) {
+ ret = clk_rcg2_dfs_populate_freq_table(rcg);
This function would retrieve the parent_rate and if the parent_rate is
not ready then it would fail to boot up.
So we have to make sure the parents are registered before these RCGs.
That also was one reason for me to not populate the frequency table at
recalc.
We would need this patch to make this work.
/* GCC clock registers */
-#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
-#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
-#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
-#define GCC_AGGRE_USB3_PRIM_AXI_CLK3
+#define GPLL0 0
+#define GPLL0_OUT_EVEN 1
+#define GPLL0_OUT_MAIN 2
+#define GPLL4 3
#define GCC_AGGRE_USB3_SEC_AXI_CLK 4
#define GCC_BOOT_ROM_AHB_CLK 5
#define GCC_CAMERA_AHB_CLK 6
@@ -172,9 +172,9 @@
#define GCC_VIDEO_AHB_CLK 162
#define GCC_VIDEO_AXI_CLK 163
#define GCC_VIDEO_XO_CLK 164
-#define GPLL0 165
-#define GPLL0_OUT_EVEN 166
-#define GPLL0_OUT_MAIN 167
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK 165
+#define GCC_AGGRE_UFS_CARD_AXI_CLK 166
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 167
#define GCC_GPU_IREF_CLK 168
#define
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
Hello Stephen,
I will test these changes and get back.
On 8/18/2018 7:42 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-10 18:53:54)
[v4]
* Add recalc_clk_ops to calculate the clock frequency reading the current
perf state, also add CLK_GET_RATE_NOCACHE flag.
* Cleanup 'goto' during mode check in 'clk_rcg2_calculate_freq'.
* cleanup return from function 'com_cc_register_rcg_dfs'.
I want to squash this in. I have only compile tested it. Let me know
what you think.
8<---
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index e6300e05d5df..e5eca8a1abe4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -163,6 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
extern const struct clk_ops clk_gfx3d_ops;
extern const struct clk_ops clk_rcg2_shared_ops;
+struct clk_rcg_dfs_data {
+ struct clk_rcg2 *rcg;
+ struct clk_init_data *init;
+};
+
+#define DEFINE_RCG_DFS(r) \
+ { .rcg = ##_src, .init = ##_init }
+
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
-struct clk_rcg2 **rcgs, int num_clks);
+ const struct clk_rcg_dfs_data *rcgs,
+ size_t len);
#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 55a5b58cbb15..bbe2a1916296 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -1051,48 +1051,24 @@ static unsigned long
clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
- u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask, level;
- int num_parents, i;
- unsigned long prate;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_CMD_DFSR_OFFSET, );
- level = (GENMASK(4, 1) & cfg) >> 1;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_DFSR(level), );
- if (rcg->mnd_width) {
- mask = BIT(rcg->mnd_width) - 1;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_M_DFSR(level), );
- m &= mask;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_N_DFSR(level), );
- n = ~n;
- n &= mask;
- n += m;
- mode = cfg & CFG_MODE_MASK;
- mode >>= CFG_MODE_SHIFT;
- }
+ int ret;
+ u32 level;
- mask = BIT(rcg->hid_width) - 1;
- hid_div = cfg >> CFG_SRC_DIV_SHIFT;
- hid_div &= mask;
- cfg &= CFG_SRC_SEL_MASK;
- cfg >>= CFG_SRC_SEL_SHIFT;
+ regmap_read(rcg->clkr.regmap,
+ rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, );
+ level &= GENMASK(4, 1);
+ level >>= 1;
- num_parents = clk_hw_get_num_parents(hw);
- for (i = 0; i < num_parents; i++) {
- if (cfg == rcg->parent_map[i].cfg) {
- prate = clk_hw_get_rate(
- clk_hw_get_parent_by_index(>clkr.hw, i));
- if (parent_rate != prate)
- parent_rate = prate;
+ if (!rcg->freq_tbl) {
+ ret = clk_rcg2_dfs_populate_freq_table(rcg);
+ if (ret) {
+ pr_err("Failed to update DFS tables for %s\n",
+ clk_hw_get_name(hw));
+ return ret;
}
}
-
- return calc_rate(parent_rate, m, n, mode, hid_div);
+ return rcg->freq_tbl[level].freq;
}
static const struct clk_ops clk_rcg2_dfs_ops = {
@@ -1102,9 +1078,11 @@ static const struct clk_ops clk_rcg2_dfs_ops = {
.recalc_rate = clk_rcg2_dfs_recalc_rate,
};
-static int clk_rcg2_enable_dfs(struct clk_rcg2 *rcg, struct regmap *regmap)
+static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
+ struct regmap *regmap)
{
- struct clk_init_data *init;
+ struct clk_rcg2 *rcg = data->rcg;
+ struct clk_init_data *init = data->init;
u32 val;
int ret;
@@ -1116,18 +1094,13 @@ static int clk_rcg2_enable_dfs(struct clk_rcg2 *rcg, struct regmap *regmap)
if (!(val & SE_CMD_DFS_EN))
return 0;
- init = kzalloc(sizeof(*init), GFP_KERNEL);
- if (!init)
- return -ENOMEM;
-
- init->name = rcg->clkr.hw.init->name;
- init->flags = rcg->clkr.hw.init->flags;
- init->parent_names = rcg->clkr.hw.init->parent_names;
- init->num_parents = rcg->clkr.hw.init->num_parents;
- init->flags = CLK_GET_RATE_NOCACHE;
+ /*
+* Rate changes with consumer writing a register in
+* their own I/O region
+*/
+ init->flags |= CLK_GET_RATE_NOCACHE;
init->ops = _rcg2_dfs_ops;
- rcg->clkr.hw.init = init;
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
Hello Stephen,
I will test these changes and get back.
On 8/18/2018 7:42 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-10 18:53:54)
[v4]
* Add recalc_clk_ops to calculate the clock frequency reading the current
perf state, also add CLK_GET_RATE_NOCACHE flag.
* Cleanup 'goto' during mode check in 'clk_rcg2_calculate_freq'.
* cleanup return from function 'com_cc_register_rcg_dfs'.
I want to squash this in. I have only compile tested it. Let me know
what you think.
8<---
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index e6300e05d5df..e5eca8a1abe4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -163,6 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
extern const struct clk_ops clk_gfx3d_ops;
extern const struct clk_ops clk_rcg2_shared_ops;
+struct clk_rcg_dfs_data {
+ struct clk_rcg2 *rcg;
+ struct clk_init_data *init;
+};
+
+#define DEFINE_RCG_DFS(r) \
+ { .rcg = ##_src, .init = ##_init }
+
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
-struct clk_rcg2 **rcgs, int num_clks);
+ const struct clk_rcg_dfs_data *rcgs,
+ size_t len);
#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 55a5b58cbb15..bbe2a1916296 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -1051,48 +1051,24 @@ static unsigned long
clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
- u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask, level;
- int num_parents, i;
- unsigned long prate;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_CMD_DFSR_OFFSET, );
- level = (GENMASK(4, 1) & cfg) >> 1;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_DFSR(level), );
- if (rcg->mnd_width) {
- mask = BIT(rcg->mnd_width) - 1;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_M_DFSR(level), );
- m &= mask;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_N_DFSR(level), );
- n = ~n;
- n &= mask;
- n += m;
- mode = cfg & CFG_MODE_MASK;
- mode >>= CFG_MODE_SHIFT;
- }
+ int ret;
+ u32 level;
- mask = BIT(rcg->hid_width) - 1;
- hid_div = cfg >> CFG_SRC_DIV_SHIFT;
- hid_div &= mask;
- cfg &= CFG_SRC_SEL_MASK;
- cfg >>= CFG_SRC_SEL_SHIFT;
+ regmap_read(rcg->clkr.regmap,
+ rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, );
+ level &= GENMASK(4, 1);
+ level >>= 1;
- num_parents = clk_hw_get_num_parents(hw);
- for (i = 0; i < num_parents; i++) {
- if (cfg == rcg->parent_map[i].cfg) {
- prate = clk_hw_get_rate(
- clk_hw_get_parent_by_index(>clkr.hw, i));
- if (parent_rate != prate)
- parent_rate = prate;
+ if (!rcg->freq_tbl) {
+ ret = clk_rcg2_dfs_populate_freq_table(rcg);
+ if (ret) {
+ pr_err("Failed to update DFS tables for %s\n",
+ clk_hw_get_name(hw));
+ return ret;
}
}
-
- return calc_rate(parent_rate, m, n, mode, hid_div);
+ return rcg->freq_tbl[level].freq;
}
static const struct clk_ops clk_rcg2_dfs_ops = {
@@ -1102,9 +1078,11 @@ static const struct clk_ops clk_rcg2_dfs_ops = {
.recalc_rate = clk_rcg2_dfs_recalc_rate,
};
-static int clk_rcg2_enable_dfs(struct clk_rcg2 *rcg, struct regmap *regmap)
+static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
+ struct regmap *regmap)
{
- struct clk_init_data *init;
+ struct clk_rcg2 *rcg = data->rcg;
+ struct clk_init_data *init = data->init;
u32 val;
int ret;
@@ -1116,18 +1094,13 @@ static int clk_rcg2_enable_dfs(struct clk_rcg2 *rcg, struct regmap *regmap)
if (!(val & SE_CMD_DFS_EN))
return 0;
- init = kzalloc(sizeof(*init), GFP_KERNEL);
- if (!init)
- return -ENOMEM;
-
- init->name = rcg->clkr.hw.init->name;
- init->flags = rcg->clkr.hw.init->flags;
- init->parent_names = rcg->clkr.hw.init->parent_names;
- init->num_parents = rcg->clkr.hw.init->num_parents;
- init->flags = CLK_GET_RATE_NOCACHE;
+ /*
+* Rate changes with consumer writing a register in
+* their own I/O region
+*/
+ init->flags |= CLK_GET_RATE_NOCACHE;
init->ops = _rcg2_dfs_ops;
- rcg->clkr.hw.init = init;
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
Quoting Taniya Das (2018-08-10 18:53:54)
> [v4]
> * Add recalc_clk_ops to calculate the clock frequency reading the current
> perf state, also add CLK_GET_RATE_NOCACHE flag.
> * Cleanup 'goto' during mode check in 'clk_rcg2_calculate_freq'.
> * cleanup return from function 'com_cc_register_rcg_dfs'.
I want to squash this in. I have only compile tested it. Let me know
what you think.
8<---
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index e6300e05d5df..e5eca8a1abe4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -163,6 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
extern const struct clk_ops clk_gfx3d_ops;
extern const struct clk_ops clk_rcg2_shared_ops;
+struct clk_rcg_dfs_data {
+ struct clk_rcg2 *rcg;
+ struct clk_init_data *init;
+};
+
+#define DEFINE_RCG_DFS(r) \
+ { .rcg = ##_src, .init = ##_init }
+
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
-struct clk_rcg2 **rcgs, int num_clks);
+ const struct clk_rcg_dfs_data *rcgs,
+ size_t len);
#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 55a5b58cbb15..bbe2a1916296 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -1051,48 +1051,24 @@ static unsigned long
clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
- u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask, level;
- int num_parents, i;
- unsigned long prate;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_CMD_DFSR_OFFSET, );
- level = (GENMASK(4, 1) & cfg) >> 1;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_DFSR(level), );
- if (rcg->mnd_width) {
- mask = BIT(rcg->mnd_width) - 1;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_M_DFSR(level), );
- m &= mask;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_N_DFSR(level), );
- n = ~n;
- n &= mask;
- n += m;
- mode = cfg & CFG_MODE_MASK;
- mode >>= CFG_MODE_SHIFT;
- }
+ int ret;
+ u32 level;
- mask = BIT(rcg->hid_width) - 1;
- hid_div = cfg >> CFG_SRC_DIV_SHIFT;
- hid_div &= mask;
- cfg &= CFG_SRC_SEL_MASK;
- cfg >>= CFG_SRC_SEL_SHIFT;
+ regmap_read(rcg->clkr.regmap,
+ rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, );
+ level &= GENMASK(4, 1);
+ level >>= 1;
- num_parents = clk_hw_get_num_parents(hw);
- for (i = 0; i < num_parents; i++) {
- if (cfg == rcg->parent_map[i].cfg) {
- prate = clk_hw_get_rate(
- clk_hw_get_parent_by_index(>clkr.hw, i));
- if (parent_rate != prate)
- parent_rate = prate;
+ if (!rcg->freq_tbl) {
+ ret = clk_rcg2_dfs_populate_freq_table(rcg);
+ if (ret) {
+ pr_err("Failed to update DFS tables for %s\n",
+ clk_hw_get_name(hw));
+ return ret;
}
}
-
- return calc_rate(parent_rate, m, n, mode, hid_div);
+ return rcg->freq_tbl[level].freq;
}
static const struct clk_ops clk_rcg2_dfs_ops = {
@@ -1102,9 +1078,11 @@ static const struct clk_ops clk_rcg2_dfs_ops = {
.recalc_rate = clk_rcg2_dfs_recalc_rate,
};
-static int clk_rcg2_enable_dfs(struct clk_rcg2 *rcg, struct regmap *regmap)
+static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
+ struct regmap *regmap)
{
- struct clk_init_data *init;
+ struct clk_rcg2 *rcg = data->rcg;
+ struct clk_init_data *init = data->init;
u32 val;
int ret;
@@ -1116,18 +1094,13 @@ static int clk_rcg2_enable_dfs(struct clk_rcg2 *rcg,
struct regmap *regmap)
if (!(val & SE_CMD_DFS_EN))
return 0;
- init = kzalloc(sizeof(*init), GFP_KERNEL);
- if (!init)
- return -ENOMEM;
-
- init->name = rcg->clkr.hw.init->name;
- init->flags = rcg->clkr.hw.init->flags;
- init->parent_names = rcg->clkr.hw.init->parent_names;
- init->num_parents = rcg->clkr.hw.init->num_parents;
- init->flags = CLK_GET_RATE_NOCACHE;
+ /*
+* Rate changes with consumer writing a register in
+* their own I/O region
+*/
+ init->flags |= CLK_GET_RATE_NOCACHE;
init->ops = _rcg2_dfs_ops;
- rcg->clkr.hw.init = init;
rcg->freq_tbl = NULL;
pr_debug("DFS registered for clk %s\n", init->name);
@@ -1136,14
Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS
Quoting Taniya Das (2018-08-10 18:53:54)
> [v4]
> * Add recalc_clk_ops to calculate the clock frequency reading the current
> perf state, also add CLK_GET_RATE_NOCACHE flag.
> * Cleanup 'goto' during mode check in 'clk_rcg2_calculate_freq'.
> * cleanup return from function 'com_cc_register_rcg_dfs'.
I want to squash this in. I have only compile tested it. Let me know
what you think.
8<---
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index e6300e05d5df..e5eca8a1abe4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -163,6 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
extern const struct clk_ops clk_gfx3d_ops;
extern const struct clk_ops clk_rcg2_shared_ops;
+struct clk_rcg_dfs_data {
+ struct clk_rcg2 *rcg;
+ struct clk_init_data *init;
+};
+
+#define DEFINE_RCG_DFS(r) \
+ { .rcg = ##_src, .init = ##_init }
+
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
-struct clk_rcg2 **rcgs, int num_clks);
+ const struct clk_rcg_dfs_data *rcgs,
+ size_t len);
#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 55a5b58cbb15..bbe2a1916296 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -1051,48 +1051,24 @@ static unsigned long
clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
- u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask, level;
- int num_parents, i;
- unsigned long prate;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_CMD_DFSR_OFFSET, );
- level = (GENMASK(4, 1) & cfg) >> 1;
-
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_DFSR(level), );
- if (rcg->mnd_width) {
- mask = BIT(rcg->mnd_width) - 1;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_M_DFSR(level), );
- m &= mask;
- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
- SE_PERF_N_DFSR(level), );
- n = ~n;
- n &= mask;
- n += m;
- mode = cfg & CFG_MODE_MASK;
- mode >>= CFG_MODE_SHIFT;
- }
+ int ret;
+ u32 level;
- mask = BIT(rcg->hid_width) - 1;
- hid_div = cfg >> CFG_SRC_DIV_SHIFT;
- hid_div &= mask;
- cfg &= CFG_SRC_SEL_MASK;
- cfg >>= CFG_SRC_SEL_SHIFT;
+ regmap_read(rcg->clkr.regmap,
+ rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, );
+ level &= GENMASK(4, 1);
+ level >>= 1;
- num_parents = clk_hw_get_num_parents(hw);
- for (i = 0; i < num_parents; i++) {
- if (cfg == rcg->parent_map[i].cfg) {
- prate = clk_hw_get_rate(
- clk_hw_get_parent_by_index(>clkr.hw, i));
- if (parent_rate != prate)
- parent_rate = prate;
+ if (!rcg->freq_tbl) {
+ ret = clk_rcg2_dfs_populate_freq_table(rcg);
+ if (ret) {
+ pr_err("Failed to update DFS tables for %s\n",
+ clk_hw_get_name(hw));
+ return ret;
}
}
-
- return calc_rate(parent_rate, m, n, mode, hid_div);
+ return rcg->freq_tbl[level].freq;
}
static const struct clk_ops clk_rcg2_dfs_ops = {
@@ -1102,9 +1078,11 @@ static const struct clk_ops clk_rcg2_dfs_ops = {
.recalc_rate = clk_rcg2_dfs_recalc_rate,
};
-static int clk_rcg2_enable_dfs(struct clk_rcg2 *rcg, struct regmap *regmap)
+static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
+ struct regmap *regmap)
{
- struct clk_init_data *init;
+ struct clk_rcg2 *rcg = data->rcg;
+ struct clk_init_data *init = data->init;
u32 val;
int ret;
@@ -1116,18 +1094,13 @@ static int clk_rcg2_enable_dfs(struct clk_rcg2 *rcg,
struct regmap *regmap)
if (!(val & SE_CMD_DFS_EN))
return 0;
- init = kzalloc(sizeof(*init), GFP_KERNEL);
- if (!init)
- return -ENOMEM;
-
- init->name = rcg->clkr.hw.init->name;
- init->flags = rcg->clkr.hw.init->flags;
- init->parent_names = rcg->clkr.hw.init->parent_names;
- init->num_parents = rcg->clkr.hw.init->num_parents;
- init->flags = CLK_GET_RATE_NOCACHE;
+ /*
+* Rate changes with consumer writing a register in
+* their own I/O region
+*/
+ init->flags |= CLK_GET_RATE_NOCACHE;
init->ops = _rcg2_dfs_ops;
- rcg->clkr.hw.init = init;
rcg->freq_tbl = NULL;
pr_debug("DFS registered for clk %s\n", init->name);
@@ -1136,14
