Re: [PATCH v4 2/5] irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts
On Wed, 29 Jul 2020 at 20:43, David Lechner wrote: > > On 7/28/20 4:18 AM, Grzegorz Jaszczyk wrote: > > The Programmable Real-Time Unit Subsystem (PRUSS) contains a local > > interrupt controller (INTC) that can handle various system input events > > and post interrupts back to the device-level initiators. The INTC can > > support upto 64 input events with individual control configuration and > > hardware prioritization. These events are mapped onto 10 output interrupt > > lines through two levels of many-to-one mapping support. Different > > interrupt lines are routed to the individual PRU cores or to the host > > CPU, or to other devices on the SoC. Some of these events are sourced > > from peripherals or other sub-modules within that PRUSS, while a few > > others are sourced from SoC-level peripherals/devices. > > > > The PRUSS INTC platform driver manages this PRUSS interrupt controller > > and implements an irqchip driver to provide a Linux standard way for > > the PRU client users to enable/disable/ack/re-trigger a PRUSS system > > event. The system events to interrupt channels and output interrupts > > relies on the mapping configuration provided either through the PRU > > firmware blob (for interrupts routed to PRU cores) or via the PRU > > application's device tree node (for interrupt routed to the main CPU). > > In the first case the mappings will be programmed on PRU remoteproc > > driver demand (via irq_create_fwspec_mapping) during the boot of a PRU > > core and cleaned up after the PRU core is stopped. > > > > Reference counting is used to allow multiple system events to share a > > single channel and to allow multiple channels to share a single host > > event. > > > > The PRUSS INTC module is reference counted during the interrupt > > setup phase through the irqchip's irq_request_resources() and > > irq_release_resources() ops. This restricts the module from being > > removed as long as there are active interrupt users. > > > > The driver currently supports and can be built for OMAP architecture > > based AM335x, AM437x and AM57xx SoCs; Keystone2 architecture based > > 66AK2G SoCs and Davinci architecture based OMAP-L13x/AM18x/DA850 SoCs. > > All of these SoCs support 64 system events, 10 interrupt channels and > > 10 output interrupt lines per PRUSS INTC with a few SoC integration > > differences. > > > > NOTE: > > Each PRU-ICSS's INTC on AM57xx SoCs is preceded by a Crossbar that > > enables multiple external events to be routed to a specific number > > of input interrupt events. Any non-default external interrupt event > > directed towards PRUSS needs this crossbar to be setup properly. > > > > Signed-off-by: Suman Anna > > Signed-off-by: Andrew F. Davis > > Signed-off-by: Roger Quadros > > Signed-off-by: Grzegorz Jaszczyk > > --- > > It looks like this patch also includes code that I wrote [1] so: > > Signed-off-by: David Lechner Sure, and thank you for suggestions from mentioned discussion in v2. I've credited you with suggested-by in v3 of this patchest but it got lost after squashing patch #6 with patch #2 in this patch-set. I will add your sign-off in the next version. > > > [1]: > https://lore.kernel.org/lkml/124b03b8-f8e7-682b-8767-13a739329...@lechnology.com/ > > > > diff --git a/drivers/irqchip/irq-pruss-intc.c > > b/drivers/irqchip/irq-pruss-intc.c > > new file mode 100644 > > index 000..45b966a > > --- /dev/null > > +++ b/drivers/irqchip/irq-pruss-intc.c > > @@ -0,0 +1,591 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > +/* > > + * PRU-ICSS INTC IRQChip driver for various TI SoCs > > + * > > + * Copyright (C) 2016-2020 Texas Instruments Incorporated - > > http://www.ti.com/ > > + * Andrew F. Davis > > + * Suman Anna > > Please add: > > + * Copyright (C) 2019 David Lechner Yes, as above. > > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* > > + * Number of host interrupts reaching the main MPU sub-system. Note that > > this > > + * is not the same as the total number of host interrupts supported by the > > PRUSS > > + * INTC instance > > + */ > > +#define MAX_NUM_HOST_IRQS8 > > + > > +/* minimum starting host interrupt number for MPU */ > > +#define MIN_PRU_HOST_INT 2 > > nit: "First" might be a better word choice than "minimum" Ok. > > > + > > +/* PRU_ICSS_INTC registers */ > > +#define PRU_INTC_REVID 0x > > +#define PRU_INTC_CR 0x0004 > > +#define PRU_INTC_GER 0x0010 > > +#define PRU_INTC_GNLR0x001c > > +#define PRU_INTC_SISR0x0020 > > +#define PRU_INTC_SICR0x0024 > > +#define PRU_INTC_EISR0x0028 > > +#define PRU_INTC_EICR0x002c > > +#define PRU_INTC_HIEISR 0x0034 > > +#define PRU_INTC_HIDISR 0x0038 > > +#define PRU_INTC_GPIR0x0080 > > +#define PRU_INTC_SRSR(x) (0x0200 + (x) * 4) > > +#define PRU_INTC_SECR(x)
Re: [PATCH v4 2/5] irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts
On 7/28/20 4:18 AM, Grzegorz Jaszczyk wrote: The Programmable Real-Time Unit Subsystem (PRUSS) contains a local interrupt controller (INTC) that can handle various system input events and post interrupts back to the device-level initiators. The INTC can support upto 64 input events with individual control configuration and hardware prioritization. These events are mapped onto 10 output interrupt lines through two levels of many-to-one mapping support. Different interrupt lines are routed to the individual PRU cores or to the host CPU, or to other devices on the SoC. Some of these events are sourced from peripherals or other sub-modules within that PRUSS, while a few others are sourced from SoC-level peripherals/devices. The PRUSS INTC platform driver manages this PRUSS interrupt controller and implements an irqchip driver to provide a Linux standard way for the PRU client users to enable/disable/ack/re-trigger a PRUSS system event. The system events to interrupt channels and output interrupts relies on the mapping configuration provided either through the PRU firmware blob (for interrupts routed to PRU cores) or via the PRU application's device tree node (for interrupt routed to the main CPU). In the first case the mappings will be programmed on PRU remoteproc driver demand (via irq_create_fwspec_mapping) during the boot of a PRU core and cleaned up after the PRU core is stopped. Reference counting is used to allow multiple system events to share a single channel and to allow multiple channels to share a single host event. The PRUSS INTC module is reference counted during the interrupt setup phase through the irqchip's irq_request_resources() and irq_release_resources() ops. This restricts the module from being removed as long as there are active interrupt users. The driver currently supports and can be built for OMAP architecture based AM335x, AM437x and AM57xx SoCs; Keystone2 architecture based 66AK2G SoCs and Davinci architecture based OMAP-L13x/AM18x/DA850 SoCs. All of these SoCs support 64 system events, 10 interrupt channels and 10 output interrupt lines per PRUSS INTC with a few SoC integration differences. NOTE: Each PRU-ICSS's INTC on AM57xx SoCs is preceded by a Crossbar that enables multiple external events to be routed to a specific number of input interrupt events. Any non-default external interrupt event directed towards PRUSS needs this crossbar to be setup properly. Signed-off-by: Suman Anna Signed-off-by: Andrew F. Davis Signed-off-by: Roger Quadros Signed-off-by: Grzegorz Jaszczyk --- It looks like this patch also includes code that I wrote [1] so: Signed-off-by: David Lechner [1]: https://lore.kernel.org/lkml/124b03b8-f8e7-682b-8767-13a739329...@lechnology.com/ diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c new file mode 100644 index 000..45b966a --- /dev/null +++ b/drivers/irqchip/irq-pruss-intc.c @@ -0,0 +1,591 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PRU-ICSS INTC IRQChip driver for various TI SoCs + * + * Copyright (C) 2016-2020 Texas Instruments Incorporated - http://www.ti.com/ + * Andrew F. Davis + * Suman Anna Please add: + * Copyright (C) 2019 David Lechner + */ + +#include +#include +#include +#include +#include +#include + +/* + * Number of host interrupts reaching the main MPU sub-system. Note that this + * is not the same as the total number of host interrupts supported by the PRUSS + * INTC instance + */ +#define MAX_NUM_HOST_IRQS 8 + +/* minimum starting host interrupt number for MPU */ +#define MIN_PRU_HOST_INT 2 nit: "First" might be a better word choice than "minimum" + +/* PRU_ICSS_INTC registers */ +#define PRU_INTC_REVID 0x +#define PRU_INTC_CR0x0004 +#define PRU_INTC_GER 0x0010 +#define PRU_INTC_GNLR 0x001c +#define PRU_INTC_SISR 0x0020 +#define PRU_INTC_SICR 0x0024 +#define PRU_INTC_EISR 0x0028 +#define PRU_INTC_EICR 0x002c +#define PRU_INTC_HIEISR0x0034 +#define PRU_INTC_HIDISR0x0038 +#define PRU_INTC_GPIR 0x0080 +#define PRU_INTC_SRSR(x) (0x0200 + (x) * 4) +#define PRU_INTC_SECR(x) (0x0280 + (x) * 4) +#define PRU_INTC_ESR(x)(0x0300 + (x) * 4) +#define PRU_INTC_ECR(x)(0x0380 + (x) * 4) +#define PRU_INTC_CMR(x)(0x0400 + (x) * 4) +#define PRU_INTC_HMR(x)(0x0800 + (x) * 4) +#define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4) +#define PRU_INTC_SIPR(x) (0x0d00 + (x) * 4) +#define PRU_INTC_SITR(x) (0x0d80 + (x) * 4) +#define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) +#define PRU_INTC_HIER 0x1500 + +/* CMR register bit-field macros */ +#define CMR_EVT_MAP_MASK 0xf +#define CMR_EVT_MAP_BITS 8 +#define CMR_EVT_PER_REG4 + +/* HMR register bit-field macros */ +#define HMR_CH_MAP_MASK0xf +#define HMR_CH_MAP_BITS
