Re: [PATCH v7 4/9] clk: mediatek: Add MT2701 clock support
Hi Stephen,
On Mon, 2016-05-09 at 15:29 -0700, Stephen Boyd wrote:
> On 05/09, James Liao wrote:
> > On Fri, 2016-05-06 at 16:11 -0700, Stephen Boyd wrote:
> > > On 04/14, James Liao wrote:
> > > > diff --git a/drivers/clk/mediatek/clk-mt2701.c
> > > > b/drivers/clk/mediatek/clk-mt2701.c
> > > > new file mode 100644
> > > > index 000..b4db141
> > > > --- /dev/null
> > > > +++ b/drivers/clk/mediatek/clk-mt2701.c
> > > > +static void __init mtk_infrasys_init(struct device_node *node)
> > > > +{
> > > > + struct clk_onecell_data *clk_data;
> > > > + int r;
> > > > +
> > > > + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
> > > > +
> > > > + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
> > > > + clk_data);
> > > > + mtk_clk_register_factors(infra_fixed_divs,
> > > > ARRAY_SIZE(infra_fixed_divs),
> > > > + clk_data);
> > > > +
> > > > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > > > + if (r)
> > > > + pr_err("%s(): could not register clock provider: %d\n",
> > > > + __func__, r);
> > > > +}
> > > > +CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt2701-infracfg",
> > > > mtk_infrasys_init);
> > >
> > > I'm still lost on the usage of CLK_OF_DECLARE here. What part of
> > > these clk controllers needs to be registered to make the timer
> > > work?
> >
> > GPT (mtk-timer.c) may need infracfg and topckgen clocks. MT8173 for
> > example:
> >
> > timer: timer@10008000 {
> > [...]
> > clocks = <&infracfg CLK_INFRA_CLK_13M>,
> > <&topckgen CLK_TOP_RTC_SEL>;
> > };
>
> Ok. It should be possible to only register the clk tree for these
> clks in CLK_OF_DECLARE() and then register the other clks that
> the clk provider provides with a regular driver probe routine.
> That way we can get the advantage of the device framework, etc.
> but still register the clks we need to make the timer work early
> on.
I'll study a new way to separate clock registration of a subsystem into
CLK_OF_DECLARE() and device probe().
> >
> > > > + GATE_DISP1(CLK_MM_DPI_DIGL, "mm_dpi_digl", "dpi0_sel", 2),
> > > > + GATE_DISP1(CLK_MM_DPI_ENGINE, "mm_dpi_eng", "mm_sel", 3),
> > > > + GATE_DISP1(CLK_MM_DPI1_DIGL, "mm_dpi1_digl", "dpi1_sel", 4),
> > > > + GATE_DISP1(CLK_MM_DPI1_ENGINE, "mm_dpi1_eng", "mm_sel", 5),
> > > > + GATE_DISP1(CLK_MM_TVE_OUTPUT, "mm_tve_output", "tve_sel", 6),
> > > > + GATE_DISP1(CLK_MM_TVE_INPUT, "mm_tve_input", "dpi0_sel", 7),
> > > > + GATE_DISP1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 8),
> > > > + GATE_DISP1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmi_sel", 9),
> > > > + GATE_DISP1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll_sel", 10),
> > > > + GATE_DISP1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll_sel", 11),
> > > > + GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14),
> > > > +};
> > >
> > > I also don't understand why we don't have different files and
> > > drivers for all these different clock controllers? They all have
> > > a similar probe structure, sure, but otherwise these are
> > > different devices with different clks for them. The whole #ifdef
> > > thing in the later patch would go away too.
> >
> > Yes, you are right. So you prefer to support subsystem clocks in
> > separated files such as clk-mt2701-mm.c, clk-mt2701-bdp.c and so on,
> > right?
> >
> > But even if we implement subsystem clock in separated files, we still
> > need a way to make them optional. So the config options and #ifdef may
> > not be removed.
>
> Presumably different files could just not be compiled if the
> config is disabled, thus removing any need for #ifdef.
OK. I'll try to implement these subsystem clocks into separated files in
next patch.
> >
> > > > + GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),
> > > > + GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),
> > > > + GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),
> > > > + GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),
> > > > + GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16),
> > > > +};
> > > > +
> > > > +static void __init mtk_bdpsys_init(struct device_node *node)
> > >
> > > Shouldn't be __init because it's driver probe path.
> >
> > I use builtin_platform_driver_probe(clk_drv, clk_probe) to register this
> > driver, and it looks can be __init.
>
> Ok, but that doesn't work with deferred probe right? It may be
> better to avoid it then.
It may be a concern. I'll investigate a proper way to implement the init
functions.
Best regards,
James
Re: [PATCH v7 4/9] clk: mediatek: Add MT2701 clock support
On 05/09, James Liao wrote:
> Hi Stephen,
>
> On Fri, 2016-05-06 at 16:11 -0700, Stephen Boyd wrote:
> > On 04/14, James Liao wrote:
> > > diff --git a/drivers/clk/mediatek/clk-mt2701.c
> > > b/drivers/clk/mediatek/clk-mt2701.c
> > > new file mode 100644
> > > index 000..b4db141
> > > --- /dev/null
> > > +++ b/drivers/clk/mediatek/clk-mt2701.c
> > > +static void __init mtk_infrasys_init(struct device_node *node)
> > > +{
> > > + struct clk_onecell_data *clk_data;
> > > + int r;
> > > +
> > > + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
> > > +
> > > + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
> > > + clk_data);
> > > + mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
> > > + clk_data);
> > > +
> > > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > > + if (r)
> > > + pr_err("%s(): could not register clock provider: %d\n",
> > > + __func__, r);
> > > +}
> > > +CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt2701-infracfg",
> > > mtk_infrasys_init);
> >
> > I'm still lost on the usage of CLK_OF_DECLARE here. What part of
> > these clk controllers needs to be registered to make the timer
> > work?
>
> GPT (mtk-timer.c) may need infracfg and topckgen clocks. MT8173 for
> example:
>
> timer: timer@10008000 {
> [...]
> clocks = <&infracfg CLK_INFRA_CLK_13M>,
><&topckgen CLK_TOP_RTC_SEL>;
> };
Ok. It should be possible to only register the clk tree for these
clks in CLK_OF_DECLARE() and then register the other clks that
the clk provider provides with a regular driver probe routine.
That way we can get the advantage of the device framework, etc.
but still register the clks we need to make the timer work early
on.
>
> > > + GATE_DISP1(CLK_MM_DPI_DIGL, "mm_dpi_digl", "dpi0_sel", 2),
> > > + GATE_DISP1(CLK_MM_DPI_ENGINE, "mm_dpi_eng", "mm_sel", 3),
> > > + GATE_DISP1(CLK_MM_DPI1_DIGL, "mm_dpi1_digl", "dpi1_sel", 4),
> > > + GATE_DISP1(CLK_MM_DPI1_ENGINE, "mm_dpi1_eng", "mm_sel", 5),
> > > + GATE_DISP1(CLK_MM_TVE_OUTPUT, "mm_tve_output", "tve_sel", 6),
> > > + GATE_DISP1(CLK_MM_TVE_INPUT, "mm_tve_input", "dpi0_sel", 7),
> > > + GATE_DISP1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 8),
> > > + GATE_DISP1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmi_sel", 9),
> > > + GATE_DISP1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll_sel", 10),
> > > + GATE_DISP1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll_sel", 11),
> > > + GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14),
> > > +};
> >
> > I also don't understand why we don't have different files and
> > drivers for all these different clock controllers? They all have
> > a similar probe structure, sure, but otherwise these are
> > different devices with different clks for them. The whole #ifdef
> > thing in the later patch would go away too.
>
> Yes, you are right. So you prefer to support subsystem clocks in
> separated files such as clk-mt2701-mm.c, clk-mt2701-bdp.c and so on,
> right?
>
> But even if we implement subsystem clock in separated files, we still
> need a way to make them optional. So the config options and #ifdef may
> not be removed.
Presumably different files could just not be compiled if the
config is disabled, thus removing any need for #ifdef.
>
> > > + GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),
> > > + GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),
> > > + GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),
> > > + GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),
> > > + GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16),
> > > +};
> > > +
> > > +static void __init mtk_bdpsys_init(struct device_node *node)
> >
> > Shouldn't be __init because it's driver probe path.
>
> I use builtin_platform_driver_probe(clk_drv, clk_probe) to register this
> driver, and it looks can be __init.
Ok, but that doesn't work with deferred probe right? It may be
better to avoid it then.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
Re: [PATCH v7 4/9] clk: mediatek: Add MT2701 clock support
Hi Stephen,
On Fri, 2016-05-06 at 16:11 -0700, Stephen Boyd wrote:
> On 04/14, James Liao wrote:
> > diff --git a/drivers/clk/mediatek/clk-mt2701.c
> > b/drivers/clk/mediatek/clk-mt2701.c
> > new file mode 100644
> > index 000..b4db141
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt2701.c
> > +static void __init mtk_infrasys_init(struct device_node *node)
> > +{
> > + struct clk_onecell_data *clk_data;
> > + int r;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
> > +
> > + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
> > + clk_data);
> > + mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
> > + clk_data);
> > +
> > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > + if (r)
> > + pr_err("%s(): could not register clock provider: %d\n",
> > + __func__, r);
> > +}
> > +CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt2701-infracfg",
> > mtk_infrasys_init);
>
> I'm still lost on the usage of CLK_OF_DECLARE here. What part of
> these clk controllers needs to be registered to make the timer
> work?
GPT (mtk-timer.c) may need infracfg and topckgen clocks. MT8173 for
example:
timer: timer@10008000 {
[...]
clocks = <&infracfg CLK_INFRA_CLK_13M>,
<&topckgen CLK_TOP_RTC_SEL>;
};
> > + GATE_DISP1(CLK_MM_DPI_DIGL, "mm_dpi_digl", "dpi0_sel", 2),
> > + GATE_DISP1(CLK_MM_DPI_ENGINE, "mm_dpi_eng", "mm_sel", 3),
> > + GATE_DISP1(CLK_MM_DPI1_DIGL, "mm_dpi1_digl", "dpi1_sel", 4),
> > + GATE_DISP1(CLK_MM_DPI1_ENGINE, "mm_dpi1_eng", "mm_sel", 5),
> > + GATE_DISP1(CLK_MM_TVE_OUTPUT, "mm_tve_output", "tve_sel", 6),
> > + GATE_DISP1(CLK_MM_TVE_INPUT, "mm_tve_input", "dpi0_sel", 7),
> > + GATE_DISP1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 8),
> > + GATE_DISP1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmi_sel", 9),
> > + GATE_DISP1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll_sel", 10),
> > + GATE_DISP1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll_sel", 11),
> > + GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14),
> > +};
>
> I also don't understand why we don't have different files and
> drivers for all these different clock controllers? They all have
> a similar probe structure, sure, but otherwise these are
> different devices with different clks for them. The whole #ifdef
> thing in the later patch would go away too.
Yes, you are right. So you prefer to support subsystem clocks in
separated files such as clk-mt2701-mm.c, clk-mt2701-bdp.c and so on,
right?
But even if we implement subsystem clock in separated files, we still
need a way to make them optional. So the config options and #ifdef may
not be removed.
> > + GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),
> > + GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),
> > + GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),
> > + GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),
> > + GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16),
> > +};
> > +
> > +static void __init mtk_bdpsys_init(struct device_node *node)
>
> Shouldn't be __init because it's driver probe path.
I use builtin_platform_driver_probe(clk_drv, clk_probe) to register this
driver, and it looks can be __init.
> > +{
> > + struct clk_onecell_data *clk_data;
> > + int r;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
> > +
> > + mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
> > + clk_data);
> > +
> > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > + if (r)
> > + pr_err("%s(): could not register clock provider: %d\n",
> > + __func__, r);
> > +}
> [...]
> > +
> > +static int __init clk_probe(struct platform_device *pdev)
> > +{
> > + void (*clk_init)(struct device_node *);
> > + const struct of_device_id *of_id;
> > +
> > + of_id = of_match_node(of_clk_match_tbl, pdev->dev.of_node);
> > + if (!of_id || !of_id->data)
> > + return -EINVAL;
> > +
> > + clk_init = of_id->data;
> > + clk_init(pdev->dev.of_node);
> > +
> > + return 0;
> > +}
> > +
> > +static struct platform_driver clk_drv = {
>
> Please add some mtk here, 'clk_drv' is too generic.
OK. I'll add it in next patch.
> > + .driver = {
> > + .name = "mtk-clk",
> > + .owner = THIS_MODULE,
>
> This is unnecessary.
I'll remove it.
> > + .of_match_table = of_match_ptr(of_clk_match_tbl),
>
> Just drop of_match_ptr() because it's not helping. Also
> of_clk_match_tbl is too generic.
I'll change it.
> > + },
> > +};
> > +
> > +builtin_platform_driver_probe(clk_drv, clk_probe);
> > +}
> > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> > index 32d2e45..8796acc 100644
> > --- a/drivers/clk
Re: [PATCH v7 4/9] clk: mediatek: Add MT2701 clock support
On 04/14, James Liao wrote:
> diff --git a/drivers/clk/mediatek/clk-mt2701.c
> b/drivers/clk/mediatek/clk-mt2701.c
> new file mode 100644
> index 000..b4db141
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt2701.c
> +static void __init mtk_infrasys_init(struct device_node *node)
> +{
> + struct clk_onecell_data *clk_data;
> + int r;
> +
> + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
> +
> + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
> + clk_data);
> + mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
> + clk_data);
> +
> + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> + if (r)
> + pr_err("%s(): could not register clock provider: %d\n",
> + __func__, r);
> +}
> +CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt2701-infracfg", mtk_infrasys_init);
I'm still lost on the usage of CLK_OF_DECLARE here. What part of
these clk controllers needs to be registered to make the timer
work?
> + GATE_DISP1(CLK_MM_DPI_DIGL, "mm_dpi_digl", "dpi0_sel", 2),
> + GATE_DISP1(CLK_MM_DPI_ENGINE, "mm_dpi_eng", "mm_sel", 3),
> + GATE_DISP1(CLK_MM_DPI1_DIGL, "mm_dpi1_digl", "dpi1_sel", 4),
> + GATE_DISP1(CLK_MM_DPI1_ENGINE, "mm_dpi1_eng", "mm_sel", 5),
> + GATE_DISP1(CLK_MM_TVE_OUTPUT, "mm_tve_output", "tve_sel", 6),
> + GATE_DISP1(CLK_MM_TVE_INPUT, "mm_tve_input", "dpi0_sel", 7),
> + GATE_DISP1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 8),
> + GATE_DISP1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmi_sel", 9),
> + GATE_DISP1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll_sel", 10),
> + GATE_DISP1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll_sel", 11),
> + GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14),
> +};
I also don't understand why we don't have different files and
drivers for all these different clock controllers? They all have
a similar probe structure, sure, but otherwise these are
different devices with different clks for them. The whole #ifdef
thing in the later patch would go away too.
> + GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),
> + GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),
> + GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),
> + GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),
> + GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16),
> +};
> +
> +static void __init mtk_bdpsys_init(struct device_node *node)
Shouldn't be __init because it's driver probe path.
> +{
> + struct clk_onecell_data *clk_data;
> + int r;
> +
> + clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
> +
> + mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
> + clk_data);
> +
> + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> + if (r)
> + pr_err("%s(): could not register clock provider: %d\n",
> + __func__, r);
> +}
[...]
> +
> +static int __init clk_probe(struct platform_device *pdev)
> +{
> + void (*clk_init)(struct device_node *);
> + const struct of_device_id *of_id;
> +
> + of_id = of_match_node(of_clk_match_tbl, pdev->dev.of_node);
> + if (!of_id || !of_id->data)
> + return -EINVAL;
> +
> + clk_init = of_id->data;
> + clk_init(pdev->dev.of_node);
> +
> + return 0;
> +}
> +
> +static struct platform_driver clk_drv = {
Please add some mtk here, 'clk_drv' is too generic.
> + .driver = {
> + .name = "mtk-clk",
> + .owner = THIS_MODULE,
This is unnecessary.
> + .of_match_table = of_match_ptr(of_clk_match_tbl),
Just drop of_match_ptr() because it's not helping. Also
of_clk_match_tbl is too generic.
> + },
> +};
> +
> +builtin_platform_driver_probe(clk_drv, clk_probe);
> +}
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 32d2e45..8796acc 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -145,8 +146,35 @@ struct mtk_gate {
[...]
> +struct mtk_clk_divider {
> + int id;
> + const char *name;
> + const char *parent_name;
> + unsigned long flags;
> +
> + uint32_t div_reg;
u32 is shorter
> + unsigned char div_shift;
> + unsigned char div_width;
> + unsigned char clk_divider_flags;
> + const struct clk_div_table *clk_div_table;
> +};
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
Re: [PATCH v7 4/9] clk: mediatek: Add MT2701 clock support
On 14/04/16 10:11, James Liao wrote:
From: Shunli Wang
Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.
Signed-off-by: Shunli Wang
Signed-off-by: James Liao
Tested-by: John Crispin
Reviewed-by: Matthias Brugger
---
drivers/clk/mediatek/Kconfig |8 +
drivers/clk/mediatek/Makefile |1 +
drivers/clk/mediatek/clk-gate.c | 52 ++
drivers/clk/mediatek/clk-gate.h |2 +
drivers/clk/mediatek/clk-mt2701.c | 1356 +
drivers/clk/mediatek/clk-mtk.c| 25 +
drivers/clk/mediatek/clk-mtk.h| 34 +-
7 files changed, 1475 insertions(+), 3 deletions(-)
create mode 100644 drivers/clk/mediatek/clk-mt2701.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index dc224e6..1e56000 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -6,6 +6,14 @@ config COMMON_CLK_MEDIATEK
---help---
Mediatek SoCs' clock support.
+config COMMON_CLK_MT2701
+ bool "Clock driver for Mediatek MT2701"
+ depends on COMMON_CLK
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ ---help---
+ This driver supports Mediatek MT2701 clocks.
+
config COMMON_CLK_MT8135
bool "Clock driver for Mediatek MT8135"
depends on COMMON_CLK
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 32e7222..5b2b91b 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o
clk-apmixed.o
obj-$(CONFIG_RESET_CONTROLLER) += reset.o
+obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 2a76901..65ad4ca 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -61,6 +61,22 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
}
+static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ u32 cgbit = BIT(cg->bit);
+
+ regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, cgbit);
+}
+
+static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
+{
+ struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+ u32 cgbit = BIT(cg->bit);
+
+ regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, 0);
+}
+
static int mtk_cg_enable(struct clk_hw *hw)
{
mtk_cg_clr_bit(hw);
@@ -85,6 +101,30 @@ static void mtk_cg_disable_inv(struct clk_hw *hw)
mtk_cg_clr_bit(hw);
}
+static int mtk_cg_enable_no_setclr(struct clk_hw *hw)
+{
+ mtk_cg_clr_bit_no_setclr(hw);
+
+ return 0;
+}
+
+static void mtk_cg_disable_no_setclr(struct clk_hw *hw)
+{
+ mtk_cg_set_bit_no_setclr(hw);
+}
+
+static int mtk_cg_enable_inv_no_setclr(struct clk_hw *hw)
+{
+ mtk_cg_set_bit_no_setclr(hw);
+
+ return 0;
+}
+
+static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw)
+{
+ mtk_cg_clr_bit_no_setclr(hw);
+}
+
const struct clk_ops mtk_clk_gate_ops_setclr = {
.is_enabled = mtk_cg_bit_is_cleared,
.enable = mtk_cg_enable,
@@ -97,6 +137,18 @@ const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
.disable= mtk_cg_disable_inv,
};
+const struct clk_ops mtk_clk_gate_ops_no_setclr = {
+ .is_enabled = mtk_cg_bit_is_cleared,
+ .enable = mtk_cg_enable_no_setclr,
+ .disable= mtk_cg_disable_no_setclr,
+};
+
+const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
+ .is_enabled = mtk_cg_bit_is_set,
+ .enable = mtk_cg_enable_inv_no_setclr,
+ .disable= mtk_cg_disable_inv_no_setclr,
+};
+
struct clk * __init mtk_clk_register_gate(
const char *name,
const char *parent_name,
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index b182160..72ef89b 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -36,6 +36,8 @@ static inline struct mtk_clk_gate *to_mtk_clk_gate(struct
clk_hw *hw)
extern const struct clk_ops mtk_clk_gate_ops_setclr;
extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
+extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
+extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
struct clk *mtk_clk_register_gate(
const char *name,
diff --git a/drivers/clk/mediatek/clk-mt2701.c
b/drivers/clk/mediatek/clk-mt2701.c
new file mode 100644
index 000..b4db141
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -0,0 +1,1356 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Shunli Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of t
