On 18/06/2020 19:09, Jan Kiszka wrote:
On 12.03.20 10:58, Tero Kristo wrote:
TI K3 SoCs contain an RTI (Real Time Interrupt) module which can be
used to implement a windowed watchdog functionality. Windowed watchdog
will generate an error if it is petted outside the time window, either
too early or too late.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Tero Kristo
---
v4:
* changed license to dual
* added documentation for missing properties
* added ref to watchdog.yaml
* renamed main_rti0 to watchdog0 in example
.../bindings/watchdog/ti,rti-wdt.yaml | 65 +++
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml
diff --git a/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml
b/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml
new file mode 100644
index ..e83026fef2e9
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/ti,rti-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 SoC Watchdog Timer
+
+maintainers:
+ - Tero Kristo
+
+description:
+ The TI K3 SoC watchdog timer is implemented via the RTI (Real Time
+ Interrupt) IP module. This timer adds a support for windowed watchdog
+ mode, which will signal an error if it is pinged outside the watchdog
+ time window, meaning either too early or too late. The error signal
+ generated can be routed to either interrupt a safety controller or
+ to directly reset the SoC.
+
+allOf:
+ - $ref: "watchdog.yaml#"
+
+properties:
+ compatible:
+enum:
+ - ti,j7-rti-wdt
+
+ reg:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+ power-domains:
+maxItems: 1
+
+ assigned-clocks:
+maxItems: 1
+
+ assigned-clocks-parents:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+
+examples:
+ - |
+/*
+ * RTI WDT in main domain on J721e SoC. Assigned clocks are used to
+ * select the source clock for the watchdog, forcing it to tick with
+ * a 32kHz clock in this case.
+ */
+#include
+
+watchdog0: rti@220 {
+compatible = "ti,rti-wdt";
At some stage, you changed the compatible string to something
J721e-specific. This one wasn't updated.
Hmm nice catch, this should be fixed. I wonder why the DT test tools did
not catch this when I changed the compatible...
+reg = <0x0 0x220 0x0 0x100>;
+clocks = <_clks 252 1>;
+power-domains = <_pds 252 TI_SCI_PD_EXCLUSIVE>;
+assigned-clocks = <_clks 252 1>;
+assigned-clock-parents = <_clks 252 5>;
+};
And where is the binding for the AM65x? I know that PG1 has nice
erratum, but I would expect PG2 to be fine and register-wise compatible, no?
ti,am65-rti-wdt should be added as a new compatible to this binding once
we have a board where we can actually support this. Right now TI AM65x
boards depend on firmware for the ESM side support; there has been some
internal discussion about how to get this done and I believe you are
aware of that.
-Tero
--
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