Re: [RFC 2/2] PCI: imx6: Add support for i.MX8QM/QXP PCIe
On Thu, Mar 14, 2019 at 11:05 PM Richard Zhu wrote:
> > > > > + imx6_pcie->pcie_inbound_axi =
> > > > devm_clk_get(>dev,
> > > > > + "pcie_inbound_axi");
> > > > > + if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
> > > > > + dev_err(>dev,
> > > > > + "pcie clock source missing or
> > > > invalid\n");
> > > > > + return
> > > > PTR_ERR(imx6_pcie->pcie_inbound_axi);
> > > > > + }
> > > >
> > > > On i.MX8MQ "pcie_bus" clock in vendor tree wasn't actually pointing
> > > > to actual PCIE bus clock, so it might be worth checking if that's
> > > > the case for i.MX8QM/X and you actually need one more clock.
> > > [Richard Zhu] Regarding to my understanding, iMX PCIe module is
> > connected to AXI bus.
> > > Thus, the AXI related clock can be treated as bus clock. Correct me if my
> > understand is wrong.
> > > So, I use the pcie_bus clock for i.MX8QM/QXP PCIe in the dts binding.
> > > Otherwise, I can use another new clock in codes to support i.MX8QM/QXP
> > PCIes.
> > >
> >
> > So, "pcie_bus" is supposed to be the clock driving PCIE bus itself. In this
> > case
> > the clock that is controlled by CLKREQ_B. On i.MX8MQ EVK that was an
> > external 100 Mhz oscillator, so the final patch has "pcie_bus" pointing to a
> > dedicated "fixed-clock":
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ke
> > rnel.org%2Flkml%2F20190220015857.7136-6-andrew.smirnov%40gmail.com
> > %2FT%2F%23udata=02%7C01%7Chongxing.zhu%40nxp.com%7Cb745
> > 5fe59e384723f44208d6a8ec835a%7C686ea1d3bc2b4c6fa92cd99c5c301635
> > %7C0%7C0%7C636882131105162138sdata=s7438xBSNxnWwTMxZXkj
> > LhgdPiS6puCRdrgr9suZpPQ%3Dreserved=0
> >
> > Originally vendor tree was using "pcie_bus" to point at
> > IMX8MQ_CLK_PCIE1_AUX. If the situation on i.MX8QM/QXP is similar, then,
> > yeah, I think it should be moved out into a separate clock.
> >
> [Richard Zhu] The clocks of the i.MX8QM/QXP PCIe are different to the iMX8MQ
> PCIe's.
> Five clocks MASTER_AXI, SLAVE_AXI, DBI_AXI, PIPE_CLK and PER_CLK are
> mandatory required.
> Currently, They are named "pcie", "pcie_bus", "pcie_inbound_axi", "pcie_phy",
> "pcie_per" in the vendor tree.
> PIPE_CLK is output to PHY, so "pcie_phy" clock name is used by it.
> I'm not sure that the names of the xxx_AXI clocks are proper or not.
> What're your suggests about the names of xxx_AXI clocks?
> Did new clock names for all or part of these three xxx_AXI clocks shall be
> added in to the codes?
> Thanks in advanced.
>
I am hardly an authority on how those clocks should be named, so don't
put too much value in my suggestion. However if I had to do, I'd
probably use "pcie" for MASTER_AXI and add "pcie_slave" or maybe
"pcie2" to control SLAVE_AXI.
Lucas, if you don't mind, could you please comment on clock naming
situation here?
Thanks,
Andrey Smirnov
RE: [RFC 2/2] PCI: imx6: Add support for i.MX8QM/QXP PCIe
Hi Andrey:
> -Original Message-
> From: Andrey Smirnov [mailto:andrew.smir...@gmail.com]
> Sent: 2019年3月15日 10:18
> To: Richard Zhu
> Cc: bhelg...@google.com; lorenzo.pieral...@arm.com;
> l.st...@pengutronix.de; linux-...@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: Re: [RFC 2/2] PCI: imx6: Add support for i.MX8QM/QXP PCIe
>
> On Thu, Mar 14, 2019 at 2:18 AM Richard Zhu
> wrote:
> >
> > Hi Andrey:
> > Thanks a lot for your review comments.
> >
> > Best Regards
> > Richard Zhu
> > Office: 86-21-28937189
> > Mobile: 86-13386059786
> >
> >
> > > -Original Message-
> > > From: Andrey Smirnov [mailto:andrew.smir...@gmail.com]
> > > Sent: 2019年3月14日 4:20
> > > To: Richard Zhu
> > > Cc: bhelg...@google.com; lorenzo.pieral...@arm.com;
> > > l.st...@pengutronix.de; linux-...@vger.kernel.org;
> > > linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org
> > > Subject: Re: [RFC 2/2] PCI: imx6: Add support for i.MX8QM/QXP PCIe
> > >
> > > On Wed, Mar 13, 2019 at 2:15 AM Richard Zhu
> > > wrote:
> > > >
> > > > Add codes needed to support i.MX8QM/QXP PCIe.
> > > > - HSIO(High Speed IO) subsystem is new defined on i.MX8QM/QXP.
> > > > The PCIe and SATA modules are contained in the HSIO subsystem.
> There
> > > > are two PCIe, one SATA controllers and three mixed lane PHYs on
> > > > i.MX8QM. There are three use cases of the HSIO subsystem on
> > > i.MX8QM.
> > > > 1. PCIea 2 lanes and one SATA AHCI port.
> > > > 2. PCIea 1 lane, PCIeb 1 lane and one SATA AHCI port.
> > > > 3. PCIea 2 lanes, PCIeb 1 lane.
> > > > i.MX8QXP only has PCIeb controller and one lane PHY.
> > > > - The HSIO address map as viewed from system level is as shown below.
> > > > address [31:24]Local addressTargetAddress Size
> > > > 5F 0HSIO 16MB
> > > > 60-6F 40-4FHSIO 256MB
> > > > 70-7F 80-8FHSIO 256MB
> > > > So, the cpu_addr_fixup is required to enable i.MX8QM/QXP PCIe.
> > > > - Both external OSC and internal PLL can be used as PCIe reference
> > > > clock.
> > > > - clock request GPIO for controlling the PCI reference clock request
> > > > signal. And should be configure OD when L1SS maybe enabled later.
> > > > - One more power domain HSIO_GPIO and clock PCIE_PER are required
> by
> > > > i.MX8QM/QXP PCIe.
> > > >
> > > > Signed-off-by: Richard Zhu
> > > > ---
> > > > drivers/pci/controller/dwc/pci-imx6.c | 392
> > > > +-
> > > > 1 file changed, 387 insertions(+), 5 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > > > b/drivers/pci/controller/dwc/pci-imx6.c
> > > > index aaa9489..aacefb6 100644
> > > > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > > > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > > > @@ -39,6 +39,7 @@
> > > > #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
> > > > #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE
> GENMASK(11,
> > > 8)
> > > > #define IMX8MQ_PCIE2_BASE_ADDR
> 0x33c0
> > > > +#define IMX8_HSIO_PCIEB_BASE_ADDR 0x5f01
> > > >
> > > > #define to_imx6_pcie(x)dev_get_drvdata((x)->dev)
> > > >
> > > > @@ -48,10 +49,13 @@ enum imx6_pcie_variants {
> > > > IMX6QP,
> > > > IMX7D,
> > > > IMX8MQ,
> > > > + IMX8QM,
> > > > + IMX8QXP,
> > > > };
> > > >
> > > > #define IMX6_PCIE_FLAG_IMX6_PHY
> BIT(0)
> > > > #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
> > > > +#define IMX6_PCIE_FLAG_IMX6_CPU_ADDR_FIXUP BIT(2)
> > >
> > > This is an IMX8Q* specific flag, so it probably should be called
> > > something like IMX6_PCIE_FLAG_IMX8Qx_CPU_ADD_FIXUP.
> > [Richard Zhu] Okay, would change it later.
> > >
> > > >
> > > > struct imx6_pcie_drvdata {
> > > > enum imx6_pcie_variants variant; @@ -60,10 +64,12 @@
> > > > struct imx6_pcie_drvdata {
> > > >
> > > > struct imx6_pcie {
> >
Re: [RFC 2/2] PCI: imx6: Add support for i.MX8QM/QXP PCIe
On Thu, Mar 14, 2019 at 2:18 AM Richard Zhu wrote:
>
> Hi Andrey:
> Thanks a lot for your review comments.
>
> Best Regards
> Richard Zhu
> Office: 86-21-28937189
> Mobile: 86-13386059786
>
>
> > -Original Message-
> > From: Andrey Smirnov [mailto:andrew.smir...@gmail.com]
> > Sent: 2019年3月14日 4:20
> > To: Richard Zhu
> > Cc: bhelg...@google.com; lorenzo.pieral...@arm.com;
> > l.st...@pengutronix.de; linux-...@vger.kernel.org;
> > linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org
> > Subject: Re: [RFC 2/2] PCI: imx6: Add support for i.MX8QM/QXP PCIe
> >
> > On Wed, Mar 13, 2019 at 2:15 AM Richard Zhu
> > wrote:
> > >
> > > Add codes needed to support i.MX8QM/QXP PCIe.
> > > - HSIO(High Speed IO) subsystem is new defined on i.MX8QM/QXP.
> > > The PCIe and SATA modules are contained in the HSIO subsystem. There
> > > are two PCIe, one SATA controllers and three mixed lane PHYs on
> > > i.MX8QM. There are three use cases of the HSIO subsystem on
> > i.MX8QM.
> > > 1. PCIea 2 lanes and one SATA AHCI port.
> > > 2. PCIea 1 lane, PCIeb 1 lane and one SATA AHCI port.
> > > 3. PCIea 2 lanes, PCIeb 1 lane.
> > > i.MX8QXP only has PCIeb controller and one lane PHY.
> > > - The HSIO address map as viewed from system level is as shown below.
> > > address [31:24]Local addressTargetAddress Size
> > > 5F 0HSIO 16MB
> > > 60-6F 40-4FHSIO 256MB
> > > 70-7F 80-8FHSIO 256MB
> > > So, the cpu_addr_fixup is required to enable i.MX8QM/QXP PCIe.
> > > - Both external OSC and internal PLL can be used as PCIe reference
> > > clock.
> > > - clock request GPIO for controlling the PCI reference clock request
> > > signal. And should be configure OD when L1SS maybe enabled later.
> > > - One more power domain HSIO_GPIO and clock PCIE_PER are required by
> > > i.MX8QM/QXP PCIe.
> > >
> > > Signed-off-by: Richard Zhu
> > > ---
> > > drivers/pci/controller/dwc/pci-imx6.c | 392
> > > +-
> > > 1 file changed, 387 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > > b/drivers/pci/controller/dwc/pci-imx6.c
> > > index aaa9489..aacefb6 100644
> > > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > > @@ -39,6 +39,7 @@
> > > #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
> > > #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPEGENMASK(11,
> > 8)
> > > #define IMX8MQ_PCIE2_BASE_ADDR 0x33c0
> > > +#define IMX8_HSIO_PCIEB_BASE_ADDR 0x5f01
> > >
> > > #define to_imx6_pcie(x)dev_get_drvdata((x)->dev)
> > >
> > > @@ -48,10 +49,13 @@ enum imx6_pcie_variants {
> > > IMX6QP,
> > > IMX7D,
> > > IMX8MQ,
> > > + IMX8QM,
> > > + IMX8QXP,
> > > };
> > >
> > > #define IMX6_PCIE_FLAG_IMX6_PHYBIT(0)
> > > #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
> > > +#define IMX6_PCIE_FLAG_IMX6_CPU_ADDR_FIXUP BIT(2)
> >
> > This is an IMX8Q* specific flag, so it probably should be called something
> > like
> > IMX6_PCIE_FLAG_IMX8Qx_CPU_ADD_FIXUP.
> [Richard Zhu] Okay, would change it later.
> >
> > >
> > > struct imx6_pcie_drvdata {
> > > enum imx6_pcie_variants variant; @@ -60,10 +64,12 @@ struct
> > > imx6_pcie_drvdata {
> > >
> > > struct imx6_pcie {
> > > struct dw_pcie *pci;
> > > + int clkreq_gpio;
> >
> > Is this really necessary? On i.MX8MQ vendor tree for some unknown reason
> > would reconfigure a dedicated CLKREQ_B signal as a GPIO and then use it as
> > CLKREQ signal that way instead of controlling it via dedicated bits in
> > register
> > file, so I am wondering if that is the case with QM and QXP.
> [Richard Zhu] There is a same mechanism of the CLKREQ on iMX8QM/QXP/MQ.
> Up to now, this pin is configured as GPIO, because that this pin would be
> pull up when OD is set
> and the EP device doesn't support the L1SS at all.
> Thus, the external CLK would be turned off in this scenario.
> This pin would be used in OD(Open Drain) mode when L1SS is enabled
RE: [RFC 2/2] PCI: imx6: Add support for i.MX8QM/QXP PCIe
Hi Andrey:
Thanks a lot for your review comments.
Best Regards
Richard Zhu
Office: 86-21-28937189
Mobile: 86-13386059786
> -Original Message-
> From: Andrey Smirnov [mailto:andrew.smir...@gmail.com]
> Sent: 2019年3月14日 4:20
> To: Richard Zhu
> Cc: bhelg...@google.com; lorenzo.pieral...@arm.com;
> l.st...@pengutronix.de; linux-...@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: Re: [RFC 2/2] PCI: imx6: Add support for i.MX8QM/QXP PCIe
>
> On Wed, Mar 13, 2019 at 2:15 AM Richard Zhu
> wrote:
> >
> > Add codes needed to support i.MX8QM/QXP PCIe.
> > - HSIO(High Speed IO) subsystem is new defined on i.MX8QM/QXP.
> > The PCIe and SATA modules are contained in the HSIO subsystem. There
> > are two PCIe, one SATA controllers and three mixed lane PHYs on
> > i.MX8QM. There are three use cases of the HSIO subsystem on
> i.MX8QM.
> > 1. PCIea 2 lanes and one SATA AHCI port.
> > 2. PCIea 1 lane, PCIeb 1 lane and one SATA AHCI port.
> > 3. PCIea 2 lanes, PCIeb 1 lane.
> > i.MX8QXP only has PCIeb controller and one lane PHY.
> > - The HSIO address map as viewed from system level is as shown below.
> > address [31:24]Local addressTargetAddress Size
> > 5F 0HSIO 16MB
> > 60-6F 40-4FHSIO 256MB
> > 70-7F 80-8FHSIO 256MB
> > So, the cpu_addr_fixup is required to enable i.MX8QM/QXP PCIe.
> > - Both external OSC and internal PLL can be used as PCIe reference
> > clock.
> > - clock request GPIO for controlling the PCI reference clock request
> > signal. And should be configure OD when L1SS maybe enabled later.
> > - One more power domain HSIO_GPIO and clock PCIE_PER are required by
> > i.MX8QM/QXP PCIe.
> >
> > Signed-off-by: Richard Zhu
> > ---
> > drivers/pci/controller/dwc/pci-imx6.c | 392
> > +-
> > 1 file changed, 387 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index aaa9489..aacefb6 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -39,6 +39,7 @@
> > #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
> > #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPEGENMASK(11,
> 8)
> > #define IMX8MQ_PCIE2_BASE_ADDR 0x33c0
> > +#define IMX8_HSIO_PCIEB_BASE_ADDR 0x5f01
> >
> > #define to_imx6_pcie(x)dev_get_drvdata((x)->dev)
> >
> > @@ -48,10 +49,13 @@ enum imx6_pcie_variants {
> > IMX6QP,
> > IMX7D,
> > IMX8MQ,
> > + IMX8QM,
> > + IMX8QXP,
> > };
> >
> > #define IMX6_PCIE_FLAG_IMX6_PHYBIT(0)
> > #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
> > +#define IMX6_PCIE_FLAG_IMX6_CPU_ADDR_FIXUP BIT(2)
>
> This is an IMX8Q* specific flag, so it probably should be called something
> like
> IMX6_PCIE_FLAG_IMX8Qx_CPU_ADD_FIXUP.
[Richard Zhu] Okay, would change it later.
>
> >
> > struct imx6_pcie_drvdata {
> > enum imx6_pcie_variants variant; @@ -60,10 +64,12 @@ struct
> > imx6_pcie_drvdata {
> >
> > struct imx6_pcie {
> > struct dw_pcie *pci;
> > + int clkreq_gpio;
>
> Is this really necessary? On i.MX8MQ vendor tree for some unknown reason
> would reconfigure a dedicated CLKREQ_B signal as a GPIO and then use it as
> CLKREQ signal that way instead of controlling it via dedicated bits in
> register
> file, so I am wondering if that is the case with QM and QXP.
[Richard Zhu] There is a same mechanism of the CLKREQ on iMX8QM/QXP/MQ.
Up to now, this pin is configured as GPIO, because that this pin would be pull
up when OD is set
and the EP device doesn't support the L1SS at all.
Thus, the external CLK would be turned off in this scenario.
This pin would be used in OD(Open Drain) mode when L1SS is enabled.
The L1SS has been verified on iMX8MQ. But I don't have a dynamic method to
turn the L1SS feature on at RC side yet when the L1SS is supported by EP.
Configure CLK_REQ as GPIO here currently, and hope to figure out one solution
in future.
>
> > int reset_gpio;
> > boolgpio_active_high;
> > struct clk *pcie_bus;
> > struct clk *pcie_phy;
> > + struct clk *pcie_per;
> > struc
Re: [RFC 2/2] PCI: imx6: Add support for i.MX8QM/QXP PCIe
On Wed, Mar 13, 2019 at 2:15 AM Richard Zhu wrote:
>
> Add codes needed to support i.MX8QM/QXP PCIe.
> - HSIO(High Speed IO) subsystem is new defined on i.MX8QM/QXP.
> The PCIe and SATA modules are contained in the HSIO subsystem. There
> are two PCIe, one SATA controllers and three mixed lane PHYs on
> i.MX8QM. There are three use cases of the HSIO subsystem on i.MX8QM.
> 1. PCIea 2 lanes and one SATA AHCI port.
> 2. PCIea 1 lane, PCIeb 1 lane and one SATA AHCI port.
> 3. PCIea 2 lanes, PCIeb 1 lane.
> i.MX8QXP only has PCIeb controller and one lane PHY.
> - The HSIO address map as viewed from system level is as shown below.
> address [31:24]Local addressTargetAddress Size
> 5F 0HSIO 16MB
> 60-6F 40-4FHSIO 256MB
> 70-7F 80-8FHSIO 256MB
> So, the cpu_addr_fixup is required to enable i.MX8QM/QXP PCIe.
> - Both external OSC and internal PLL can be used as PCIe reference
> clock.
> - clock request GPIO for controlling the PCI reference clock request
> signal. And should be configure OD when L1SS maybe enabled later.
> - One more power domain HSIO_GPIO and clock PCIE_PER are required by
> i.MX8QM/QXP PCIe.
>
> Signed-off-by: Richard Zhu
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 392
> +-
> 1 file changed, 387 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> b/drivers/pci/controller/dwc/pci-imx6.c
> index aaa9489..aacefb6 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -39,6 +39,7 @@
> #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
> #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPEGENMASK(11, 8)
> #define IMX8MQ_PCIE2_BASE_ADDR 0x33c0
> +#define IMX8_HSIO_PCIEB_BASE_ADDR 0x5f01
>
> #define to_imx6_pcie(x)dev_get_drvdata((x)->dev)
>
> @@ -48,10 +49,13 @@ enum imx6_pcie_variants {
> IMX6QP,
> IMX7D,
> IMX8MQ,
> + IMX8QM,
> + IMX8QXP,
> };
>
> #define IMX6_PCIE_FLAG_IMX6_PHYBIT(0)
> #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
> +#define IMX6_PCIE_FLAG_IMX6_CPU_ADDR_FIXUP BIT(2)
This is an IMX8Q* specific flag, so it probably should be called
something like IMX6_PCIE_FLAG_IMX8Qx_CPU_ADD_FIXUP.
>
> struct imx6_pcie_drvdata {
> enum imx6_pcie_variants variant;
> @@ -60,10 +64,12 @@ struct imx6_pcie_drvdata {
>
> struct imx6_pcie {
> struct dw_pcie *pci;
> + int clkreq_gpio;
Is this really necessary? On i.MX8MQ vendor tree for some unknown
reason would reconfigure a dedicated CLKREQ_B signal as a GPIO and
then use it as CLKREQ signal that way instead of controlling it via
dedicated bits in register file, so I am wondering if that is the case
with QM and QXP.
> int reset_gpio;
> boolgpio_active_high;
> struct clk *pcie_bus;
> struct clk *pcie_phy;
> + struct clk *pcie_per;
> struct clk *pcie_inbound_axi;
> struct clk *pcie;
> struct clk *pcie_aux;
> @@ -77,6 +83,9 @@ struct imx6_pcie {
> u32 tx_deemph_gen2_6db;
> u32 tx_swing_full;
> u32 tx_swing_low;
> + u32 hsio_cfg;
> + u32 ext_osc;
> + u32 local_addr;
> int link_gen;
> struct regulator*vpcie;
> void __iomem*phy_base;
> @@ -85,6 +94,8 @@ struct imx6_pcie {
> struct device *pd_pcie;
> /* power domain for pcie phy */
> struct device *pd_pcie_phy;
> + /* power domain for hsio gpio used by pcie */
> + struct device *pd_hsio_gpio;
> const struct imx6_pcie_drvdata *drvdata;
> };
>
> @@ -92,6 +103,7 @@ struct imx6_pcie {
> #define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000
> #define PHY_PLL_LOCK_WAIT_USLEEP_MIN 50
> #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
> +#define L2_ENTRY_WAIT_MAX_RETRIES 1
>
> /* PCIe Root Complex registers (memory-mapped) */
> #define PCIE_RC_IMX6_MSI_CAP 0x50
> @@ -157,6 +169,43 @@ struct imx6_pcie {
> #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
> #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
>
> +/* iMX8 HSIO registers */
> +#define IMX8QM_CSR_PHYX2_OFFSET0x0
> +#define IMX8QM_CSR_PHYX1_OFFSET0x1
> +#define IMX8QM_CSR_PHYX_STTS0_OFFSET 0x4
> +#define IMX8QM_CSR_PCIEA_OFFSET0x2
> +#define IMX8QM_CSR_PCIEB_OFFSET0x3
> +#define IMX8QM_CSR_PCIE_CTRL1_OFFSET 0x4
