subject:"Re\: \[RFC PATCH 6\/7\] soc\: mediatek\: add MT8183 dvfsrc support"

Re: [RFC PATCH 6/7] soc: mediatek: add MT8183 dvfsrc support

2019-01-03 Thread Nicolas Boichat

On Thu, Jan 3, 2019 at 10:16 PM Henry Chen  wrote:
>
> On Thu, 2019-01-03 at 10:16 +0800, Nicolas Boichat wrote:
> > On Wed, Jan 2, 2019 at 10:01 PM Henry Chen  wrote:
> > >
> > > Add dvfsrc driver for MT8183
> > >
> > > Signed-off-by: Henry Chen 
> > > ---
> > >  drivers/soc/mediatek/Kconfig  |  15 ++
> > >  drivers/soc/mediatek/Makefile |   1 +
> > >  drivers/soc/mediatek/mtk-dvfsrc.c | 473 
> > > ++
> > >  3 files changed, 489 insertions(+)
> > >  create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
> > >
> > > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> > > index a7d0667..f956f03 100644
> > > --- a/drivers/soc/mediatek/Kconfig
> > > +++ b/drivers/soc/mediatek/Kconfig
> > > @@ -12,6 +12,21 @@ config MTK_INFRACFG
> > >   INFRACFG controller contains various infrastructure registers 
> > > not
> > >   directly associated to any device.
> > >
> > > +config MTK_DVFSRC
> > > +   bool "MediaTek DVFSRC Support"
> > > +   depends on ARCH_MEDIATEK
> > > +   default ARCH_MEDIATEK
> > > +   select REGMAP
> > > +   select MTK_INFRACFG
> > > +   select PM_GENERIC_DOMAINS if PM
> > > +   depends on MTK_SCPSYS
> > > +   help
> > > + Say yes here to add support for the MediaTek DVFSRC found
> > > + on different MediaTek SoCs. The DVFSRC is a proprietary
> > > + hardware which is used to collect all the requests from
> > > + system and turn into the decision of minimum Vcore voltage
> > > + and minimum DRAM frequency to fulfill those requests.
> > > +
> > >  config MTK_PMIC_WRAP
> > > tristate "MediaTek PMIC Wrapper Support"
> > > depends on RESET_CONTROLLER
> > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> > > index 9dc6670..5c010b9 100644
> > > --- a/drivers/soc/mediatek/Makefile
> > > +++ b/drivers/soc/mediatek/Makefile
> > > @@ -1,3 +1,4 @@
> > > +obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
> > >  obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
> > >  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> > >  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> > > diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c 
> > > b/drivers/soc/mediatek/mtk-dvfsrc.c
> > > new file mode 100644
> > > index 000..af462a3
> > > --- /dev/null
> > > +++ b/drivers/soc/mediatek/mtk-dvfsrc.c
> > > @@ -0,0 +1,473 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Copyright (C) 2018 MediaTek Inc.
> > > + */
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> >
> > Alphabetical order.
> I will fix it.
> >
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include "mtk-scpsys.h"
> > > +
> > > +#define DVFSRC_IDLE0x00
> > > +#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x)
> > > +#define DVFSRC_GET_CURRENT_LEVEL(x)(((x) >> 16) & 0x)
> > > +
> > > +/* macro for irq */
> > > +#define DVFSRC_IRQ_TIMEOUT_EN  BIT(1)
> > > +
> > > +struct dvfsrc_opp {
> > > +   int vcore_opp;
> > > +   int dram_opp;
> > > +};
> > > +
> > > +struct dvfsrc_domain {
> > > +   int id;
> > > +   int state;
> > > +};
> > > +
> > > +struct mtk_dvfsrc;
> > > +struct dvfsrc_soc_data {
> > > +   const int *regs;
> > > +   int num_opp;
> > > +   int num_domains;
> > > +   int dram_sft;
> > > +   int vcore_sft;
> > > +   const struct dvfsrc_opp **opps;
> > > +   struct dvfsrc_domain *domains;
> > > +   void (*init_soc)(struct mtk_dvfsrc *dvfsrc);
> > > +   int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
> > > +   int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
> > > +};
> > > +
> > > +struct mtk_dvfsrc {
> > > +   struct device *dev;
> > > +   struct clk *clk_dvfsrc;
> > > +   const struct dvfsrc_soc_data *dvd;
> > > +   int dram_type;
> > > +   int irq;
> > > +   void __iomem *regs;
> > > +   struct mutex lock;  /* generic mutex for dvfsrc driver */
> > > +
> > > +   struct notifier_block qos_notifier;
> > > +   struct notifier_block scpsys_notifier;
> > > +};
> > > +
> > > +static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
> > > +{
> > > +   return readl(dvfs->regs + dvfs->dvd->regs[offset]);
> > > +}
> > > +
> > > +static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
> > > +{
> > > +   writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
> > > +}
> > > +
> > > +enum dvfsrc_regs {
> > > +   DVFSRC_BASIC_CONTROL,
> > > +   DVFSRC_SW_REQ,
> > > +   DVFSRC_SW_REQ2,
> > > +   DVFSRC_EMI_REQUEST,
> > > +   DVFSRC_EMI_REQUEST2,
> > > +   DVFSRC_EMI_REQUEST3,
> > > +   DVFSRC_EMI_QOS0,
> > > +   DVFSRC_EMI_QOS1,
> > > +   DVFSRC_EMI_QOS2,
> > > +

Re: [RFC PATCH 6/7] soc: mediatek: add MT8183 dvfsrc support

2019-01-03 Thread Henry Chen

On Thu, 2019-01-03 at 10:16 +0800, Nicolas Boichat wrote:
> On Wed, Jan 2, 2019 at 10:01 PM Henry Chen  wrote:
> >
> > Add dvfsrc driver for MT8183
> >
> > Signed-off-by: Henry Chen 
> > ---
> >  drivers/soc/mediatek/Kconfig  |  15 ++
> >  drivers/soc/mediatek/Makefile |   1 +
> >  drivers/soc/mediatek/mtk-dvfsrc.c | 473 
> > ++
> >  3 files changed, 489 insertions(+)
> >  create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
> >
> > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> > index a7d0667..f956f03 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -12,6 +12,21 @@ config MTK_INFRACFG
> >   INFRACFG controller contains various infrastructure registers not
> >   directly associated to any device.
> >
> > +config MTK_DVFSRC
> > +   bool "MediaTek DVFSRC Support"
> > +   depends on ARCH_MEDIATEK
> > +   default ARCH_MEDIATEK
> > +   select REGMAP
> > +   select MTK_INFRACFG
> > +   select PM_GENERIC_DOMAINS if PM
> > +   depends on MTK_SCPSYS
> > +   help
> > + Say yes here to add support for the MediaTek DVFSRC found
> > + on different MediaTek SoCs. The DVFSRC is a proprietary
> > + hardware which is used to collect all the requests from
> > + system and turn into the decision of minimum Vcore voltage
> > + and minimum DRAM frequency to fulfill those requests.
> > +
> >  config MTK_PMIC_WRAP
> > tristate "MediaTek PMIC Wrapper Support"
> > depends on RESET_CONTROLLER
> > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> > index 9dc6670..5c010b9 100644
> > --- a/drivers/soc/mediatek/Makefile
> > +++ b/drivers/soc/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
> >  obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
> >  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> >  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> > diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c 
> > b/drivers/soc/mediatek/mtk-dvfsrc.c
> > new file mode 100644
> > index 000..af462a3
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mtk-dvfsrc.c
> > @@ -0,0 +1,473 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2018 MediaTek Inc.
> > + */
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> 
> Alphabetical order.
I will fix it.
> 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include "mtk-scpsys.h"
> > +
> > +#define DVFSRC_IDLE0x00
> > +#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x)
> > +#define DVFSRC_GET_CURRENT_LEVEL(x)(((x) >> 16) & 0x)
> > +
> > +/* macro for irq */
> > +#define DVFSRC_IRQ_TIMEOUT_EN  BIT(1)
> > +
> > +struct dvfsrc_opp {
> > +   int vcore_opp;
> > +   int dram_opp;
> > +};
> > +
> > +struct dvfsrc_domain {
> > +   int id;
> > +   int state;
> > +};
> > +
> > +struct mtk_dvfsrc;
> > +struct dvfsrc_soc_data {
> > +   const int *regs;
> > +   int num_opp;
> > +   int num_domains;
> > +   int dram_sft;
> > +   int vcore_sft;
> > +   const struct dvfsrc_opp **opps;
> > +   struct dvfsrc_domain *domains;
> > +   void (*init_soc)(struct mtk_dvfsrc *dvfsrc);
> > +   int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
> > +   int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
> > +};
> > +
> > +struct mtk_dvfsrc {
> > +   struct device *dev;
> > +   struct clk *clk_dvfsrc;
> > +   const struct dvfsrc_soc_data *dvd;
> > +   int dram_type;
> > +   int irq;
> > +   void __iomem *regs;
> > +   struct mutex lock;  /* generic mutex for dvfsrc driver */
> > +
> > +   struct notifier_block qos_notifier;
> > +   struct notifier_block scpsys_notifier;
> > +};
> > +
> > +static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
> > +{
> > +   return readl(dvfs->regs + dvfs->dvd->regs[offset]);
> > +}
> > +
> > +static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
> > +{
> > +   writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
> > +}
> > +
> > +enum dvfsrc_regs {
> > +   DVFSRC_BASIC_CONTROL,
> > +   DVFSRC_SW_REQ,
> > +   DVFSRC_SW_REQ2,
> > +   DVFSRC_EMI_REQUEST,
> > +   DVFSRC_EMI_REQUEST2,
> > +   DVFSRC_EMI_REQUEST3,
> > +   DVFSRC_EMI_QOS0,
> > +   DVFSRC_EMI_QOS1,
> > +   DVFSRC_EMI_QOS2,
> > +   DVFSRC_EMI_MD2SPM0,
> > +   DVFSRC_EMI_MD2SPM1,
> > +   DVFSRC_VCORE_REQUEST,
> > +   DVFSRC_VCORE_REQUEST2,
> > +   DVFSRC_VCORE_MD2SPM0,
> > +   DVFSRC_INT,
> > +   DVFSRC_INT_EN,
> > +   DVFSRC_INT_CLR,
> > +   DVFSRC_TIMEOUT_NEXTREQ,
> > +   DVFSRC_LEVEL,
> > +   DVFSRC_LEVEL_LABEL_0_1,
> > +

Re: [RFC PATCH 6/7] soc: mediatek: add MT8183 dvfsrc support

2019-01-02 Thread Nicolas Boichat

On Wed, Jan 2, 2019 at 10:01 PM Henry Chen  wrote:
>
> Add dvfsrc driver for MT8183
>
> Signed-off-by: Henry Chen 
> ---
>  drivers/soc/mediatek/Kconfig  |  15 ++
>  drivers/soc/mediatek/Makefile |   1 +
>  drivers/soc/mediatek/mtk-dvfsrc.c | 473 
> ++
>  3 files changed, 489 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
>
> diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> index a7d0667..f956f03 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -12,6 +12,21 @@ config MTK_INFRACFG
>   INFRACFG controller contains various infrastructure registers not
>   directly associated to any device.
>
> +config MTK_DVFSRC
> +   bool "MediaTek DVFSRC Support"
> +   depends on ARCH_MEDIATEK
> +   default ARCH_MEDIATEK
> +   select REGMAP
> +   select MTK_INFRACFG
> +   select PM_GENERIC_DOMAINS if PM
> +   depends on MTK_SCPSYS
> +   help
> + Say yes here to add support for the MediaTek DVFSRC found
> + on different MediaTek SoCs. The DVFSRC is a proprietary
> + hardware which is used to collect all the requests from
> + system and turn into the decision of minimum Vcore voltage
> + and minimum DRAM frequency to fulfill those requests.
> +
>  config MTK_PMIC_WRAP
> tristate "MediaTek PMIC Wrapper Support"
> depends on RESET_CONTROLLER
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index 9dc6670..5c010b9 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -1,3 +1,4 @@
> +obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
>  obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
>  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
>  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c 
> b/drivers/soc/mediatek/mtk-dvfsrc.c
> new file mode 100644
> index 000..af462a3
> --- /dev/null
> +++ b/drivers/soc/mediatek/mtk-dvfsrc.c
> @@ -0,0 +1,473 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 MediaTek Inc.
> + */
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 

Alphabetical order.

> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include "mtk-scpsys.h"
> +
> +#define DVFSRC_IDLE0x00
> +#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x)
> +#define DVFSRC_GET_CURRENT_LEVEL(x)(((x) >> 16) & 0x)
> +
> +/* macro for irq */
> +#define DVFSRC_IRQ_TIMEOUT_EN  BIT(1)
> +
> +struct dvfsrc_opp {
> +   int vcore_opp;
> +   int dram_opp;
> +};
> +
> +struct dvfsrc_domain {
> +   int id;
> +   int state;
> +};
> +
> +struct mtk_dvfsrc;
> +struct dvfsrc_soc_data {
> +   const int *regs;
> +   int num_opp;
> +   int num_domains;
> +   int dram_sft;
> +   int vcore_sft;
> +   const struct dvfsrc_opp **opps;
> +   struct dvfsrc_domain *domains;
> +   void (*init_soc)(struct mtk_dvfsrc *dvfsrc);
> +   int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
> +   int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
> +};
> +
> +struct mtk_dvfsrc {
> +   struct device *dev;
> +   struct clk *clk_dvfsrc;
> +   const struct dvfsrc_soc_data *dvd;
> +   int dram_type;
> +   int irq;
> +   void __iomem *regs;
> +   struct mutex lock;  /* generic mutex for dvfsrc driver */
> +
> +   struct notifier_block qos_notifier;
> +   struct notifier_block scpsys_notifier;
> +};
> +
> +static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
> +{
> +   return readl(dvfs->regs + dvfs->dvd->regs[offset]);
> +}
> +
> +static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
> +{
> +   writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
> +}
> +
> +enum dvfsrc_regs {
> +   DVFSRC_BASIC_CONTROL,
> +   DVFSRC_SW_REQ,
> +   DVFSRC_SW_REQ2,
> +   DVFSRC_EMI_REQUEST,
> +   DVFSRC_EMI_REQUEST2,
> +   DVFSRC_EMI_REQUEST3,
> +   DVFSRC_EMI_QOS0,
> +   DVFSRC_EMI_QOS1,
> +   DVFSRC_EMI_QOS2,
> +   DVFSRC_EMI_MD2SPM0,
> +   DVFSRC_EMI_MD2SPM1,
> +   DVFSRC_VCORE_REQUEST,
> +   DVFSRC_VCORE_REQUEST2,
> +   DVFSRC_VCORE_MD2SPM0,
> +   DVFSRC_INT,
> +   DVFSRC_INT_EN,
> +   DVFSRC_INT_CLR,
> +   DVFSRC_TIMEOUT_NEXTREQ,
> +   DVFSRC_LEVEL,
> +   DVFSRC_LEVEL_LABEL_0_1,
> +   DVFSRC_LEVEL_LABEL_2_3,
> +   DVFSRC_LEVEL_LABEL_4_5,
> +   DVFSRC_LEVEL_LABEL_6_7,
> +   DVFSRC_LEVEL_LABEL_8_9,
> +   DVFSRC_LEVEL_LABEL_10_11,
> +   DVFSRC_LEVEL_LABEL_12_13,
> +   DVFSRC_LEVEL_LABEL_14_15,
> +   DVFSRC_SW_BW_0,
> +   DVFSRC_QOS_EN,
> +   DVFSRC_FORCE,
> +   DVFSRC_LAST,
> +   DVFSRC_RSRV_0,
> +   DVFSRC_RSRV_1,
> +};
> +

Re: [RFC PATCH 6/7] soc: mediatek: add MT8183 dvfsrc support

Re: [RFC PATCH 6/7] soc: mediatek: add MT8183 dvfsrc support

Re: [RFC PATCH 6/7] soc: mediatek: add MT8183 dvfsrc support

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