Re: [v3 2/2] dt-bindings: nand: Add Cadence NAND controller driver
The 07/09/2019 08:48, Rob Herring wrote: EXTERNAL MAIL On Fri, Jun 14, 2019 at 04:13:01PM +0100, Piotr Sroka wrote: Signed-off-by: Piotr Sroka --- Changes for v3: - add unit suffix for board_delay - move child description to proper place - remove prefix cadence_ for reg and sdma fields Changes for v2: - remove chip dependends parameters from dts bindings - add names for register ranges in dts bindings - add generic bindings to describe NAND chip representation --- .../bindings/mtd/cadence-nand-controller.txt | 51 ++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt diff --git a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt new file mode 100644 index ..e485b87075bd --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt @@ -0,0 +1,51 @@ +* Cadence NAND controller + +Required properties: + - compatible : "cdns,hpnfc" Only 1 version of h/w features and bugs? At the moment, yes. 'hp-nfc' would be a bit more readable IMO. I will replace it. + - reg : Contains two entries, each of which is a tuple consisting of a + physical address and length. The first entry is the address and + length of the controller register set. The second entry is the + address and length of the Slave DMA data port. + - reg-names: should contain "reg" and "sdma" + - interrupts : The interrupt number. + - clocks: phandle of the controller core clock (nf_clk). + +Optional properties: + - dmas: shall reference DMA channel associated to the NAND controller + - cdns,board-delay_ps : Estimated Board delay. The value includes the total s/_/-/ +round trip delay for the signals and is used for deciding on values +associated with data read capture. The example formula for SDR mode is +the following: +board_delay = RE#PAD_delay + PCB trace to device + PCB trace from device ++ DQ PAD delay + +Children nodes represent the available NAND chips. Child nodes... + +Required properties of NAND chips: + - reg: shall contain the native Chip Select ids from 0 to max supported by +the cadence nand flash controller + + +See Documentation/devicetree/bindings/mtd/nand.txt for more details on +generic bindings. + +Example: + +nand_controller: nand-controller @6000 { remove space ^ + + compatible = "cdns,hpnfc"; + reg = <0x6000 0x1>, <0x8000 0x1>; + reg-names = "reg", "sdma"; + clocks = <&nf_clk>; + cdns,board-delay_ps = <4830>; + interrupts = <2 0>; + nand@0 { + reg = <0>; + label = "nand-1"; + }; + nand@1 { + reg = <1>; + label = "nand-2"; + }; + +}; -- 2.15.0 Thanks Piotr
Re: [v3 2/2] dt-bindings: nand: Add Cadence NAND controller driver
On Fri, Jun 14, 2019 at 04:13:01PM +0100, Piotr Sroka wrote: > Signed-off-by: Piotr Sroka > --- > Changes for v3: > - add unit suffix for board_delay > - move child description to proper place > - remove prefix cadence_ for reg and sdma fields > Changes for v2: > - remove chip dependends parameters from dts bindings > - add names for register ranges in dts bindings > - add generic bindings to describe NAND chip representation > --- > .../bindings/mtd/cadence-nand-controller.txt | 51 > ++ > 1 file changed, 51 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > > diff --git > a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > new file mode 100644 > index ..e485b87075bd > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > @@ -0,0 +1,51 @@ > +* Cadence NAND controller > + > +Required properties: > + - compatible : "cdns,hpnfc" Only 1 version of h/w features and bugs? 'hp-nfc' would be a bit more readable IMO. > + - reg : Contains two entries, each of which is a tuple consisting of a > + physical address and length. The first entry is the address and > + length of the controller register set. The second entry is the > + address and length of the Slave DMA data port. > + - reg-names: should contain "reg" and "sdma" > + - interrupts : The interrupt number. > + - clocks: phandle of the controller core clock (nf_clk). > + > +Optional properties: > + - dmas: shall reference DMA channel associated to the NAND controller > + - cdns,board-delay_ps : Estimated Board delay. The value includes the total s/_/-/ > +round trip delay for the signals and is used for deciding on values > +associated with data read capture. The example formula for SDR mode is > +the following: > +board_delay = RE#PAD_delay + PCB trace to device + PCB trace from device > ++ DQ PAD delay > + > +Children nodes represent the available NAND chips. Child nodes... > + > +Required properties of NAND chips: > + - reg: shall contain the native Chip Select ids from 0 to max supported by > +the cadence nand flash controller > + > + > +See Documentation/devicetree/bindings/mtd/nand.txt for more details on > +generic bindings. > + > +Example: > + > +nand_controller: nand-controller @6000 { remove space ^ > + > + compatible = "cdns,hpnfc"; > + reg = <0x6000 0x1>, <0x8000 0x1>; > + reg-names = "reg", "sdma"; > + clocks = <&nf_clk>; > + cdns,board-delay_ps = <4830>; > + interrupts = <2 0>; > + nand@0 { > + reg = <0>; > + label = "nand-1"; > + }; > + nand@1 { > + reg = <1>; > + label = "nand-2"; > + }; > + > +}; > -- > 2.15.0 >