Re: clocksource: dw_apb_timer: commit 6d2e16a3181b broke Arria10 platform

2020-07-31 Thread Serge Semin
On Fri, Jul 31, 2020 at 10:56:37AM -0500, Dinh Nguyen wrote:
> Hi Serge,
> 
> On 7/31/20 1:48 AM, Serge Semin wrote:
> > Hello Dinh,
> > It must be something wrong with your timer2 and timer3 declared in the 
> > Arria10
> > dts because the patch didn't change anything for the first two timers 
> > (timer0 and
> > timer1). It just permits to register all DW APB Timers found in dts.
> > 
> > If those timers are broken, then you should have disabled them in the dts 
> > in the
> > first place. If they are normal, then you need to investigate further why do
> > they cause the kernel panic.
> > 
> 

> Indeed, the dts reg entry for timer3 was broken. Thanks alot for
> exposing the issue. Apologies for the noise.

No worries. Glad I could help.

-Sergey

> 
> Dinh


Re: clocksource: dw_apb_timer: commit 6d2e16a3181b broke Arria10 platform

2020-07-31 Thread Dinh Nguyen
Hi Serge,

On 7/31/20 1:48 AM, Serge Semin wrote:
> Hello Dinh,
> It must be something wrong with your timer2 and timer3 declared in the Arria10
> dts because the patch didn't change anything for the first two timers (timer0 
> and
> timer1). It just permits to register all DW APB Timers found in dts.
> 
> If those timers are broken, then you should have disabled them in the dts in 
> the
> first place. If they are normal, then you need to investigate further why do
> they cause the kernel panic.
> 

Indeed, the dts reg entry for timer3 was broken. Thanks alot for
exposing the issue. Apologies for the noise.

Dinh


Re: clocksource: dw_apb_timer: commit 6d2e16a3181b broke Arria10 platform

2020-07-31 Thread Serge Semin
Hello Dinh,
It must be something wrong with your timer2 and timer3 declared in the Arria10
dts because the patch didn't change anything for the first two timers (timer0 
and
timer1). It just permits to register all DW APB Timers found in dts.

If those timers are broken, then you should have disabled them in the dts in the
first place. If they are normal, then you need to investigate further why do
they cause the kernel panic.

-Sergey

On Thu, Jul 30, 2020 at 09:30:55PM +, Nguyen, Dinh wrote:
> Hi Sergey,
> 
> Commit "6d2e16a3181b clocksource: dw_apb_timer_of: Fix missing clockevent 
> timers" broke the Arria10 platform. See the bootlog here:
> 
> [0.00] Booting Linux on physical CPU 0x0
> [0.00] Linux version 5.8.0-rc7-next-20200730 (dinguyen@linux-builds1) 
> (a
> rm-linux-gnueabihf-gcc (Linaro GCC 7.2-2017.11) 7.2.1 20171011, GNU ld 
> (Linaro_B
> inutils-2017.11) 2.28.2.20170706) #18 SMP Thu Jul 30 16:25:46 CDT 2020
> [0.00] CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7), cr=10c5387d
> [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing 
> instructio
> n cache
> [0.00] OF: fdt: Machine model: Altera SOCFPGA Arria 10
> [0.00] earlycon: uart0 at MMIO32 0xffc02100 (options '115200n8')
> [0.00] printk: bootconsole [uart0] enabled
> [0.00] Memory policy: Data cache writealloc
> [0.00] Zone ranges:
> [0.00]   Normal   [mem 0x-0x2fff]
> [0.00]   HighMem  [mem 0x3000-0x3fff]
> [0.00] Movable zone start for each node
> [0.00] Early memory node ranges
> [0.00]   node   0: [mem 0x-0x3fff]
> [0.00] Initmem setup node 0 [mem 
> 0x-0x3fff]
> [0.00] percpu: Embedded 19 pages/cpu s45132 r8192 d24500 u77824
> [0.00] Built 1 zonelists, mobility grouping on.  Total pages: 260608
> [0.00] Kernel command line: earlycon console=ttyS0,115200 
> root=/dev/nfs
> rw nfsroot=10.122.105.146:/home/dnguyen/rootfs_yocto,tcp ip=dhcp
> [0.00] Dentry cache hash table entries: 131072 (order: 7, 524288 
> bytes,
> linear)
> [0.00] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, 
> li
> near)
> [0.00] mem auto-init: stack:off, heap alloc:off, heap free:off
> [0.00] Memory: 1027232K/1048576K available (8192K kernel code, 690K 
> rwda
> ta, 1792K rodata, 1024K init, 159K bss, 21344K reserved, 0K cma-reserved, 
> 262144
> K highmem)
> [0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
> [0.00] ftrace: allocating 28185 entries in 56 pages
> [0.00] ftrace: allocated 56 pages with 3 groups
> [0.00] rcu: Hierarchical RCU implementation.
> [0.00] rcu: RCU event tracing is enabled.
> [0.00]  Rude variant of Tasks RCU enabled.
> [0.00] rcu: RCU calculated value of scheduler-enlistment delay is 10 
> jif
> fies.
> [0.00] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
> [0.00] L2C-310 erratum 769419 enabled
> [0.00] L2C-310 enabling early BRESP for Cortex-A9
> [0.00] L2C-310: enabling full line of zeros but not enabled in 
> Cortex-A9
> [0.00] L2C-310 ID prefetch enabled, offset 1 lines
> [0.00] L2C-310 dynamic clock gating enabled, standby mode enabled
> [0.00] L2C-310 cache controller enabled, 8 ways, 512 kB
> [0.00] L2C-310: CACHE_ID 0x410030c9, AUX_CTRL 0x76560001
> [0.00] random: get_random_bytes called from start_kernel+0x388/0x528 
> wit
> h crng_init=0
> [0.00] clocksource: timer1: mask: 0x max_cycles: 0x, 
> max
> _idle_ns: 38225208935 ns
> [0.04] sched_clock: 32 bits at 50MHz, resolution 20ns, wraps every 
> 42949
> 672950ns
> [0.007796] Switching to timer-based delay loop, resolution 20ns
> [0.013861] 8<--- cut here ---
> [0.016901] Unhandled fault: imprecise external abort (0x406) at 0x4b96623e
> [0.023828] pgd = (ptrval)
> [0.026520] [4b96623e] *pgd=
> [0.030084] Internal error: : 406 [#1] SMP ARM
> [0.034504] Modules linked in:
> [0.037548] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 
> 5.8.0-rc7-next-20200730
> #18
> [0.044992] Hardware name: Altera SOCFPGA Arria10
> [0.049677] PC is at apbt_enable_int+0x24/0x48
> [0.054098] LR is at dw_apb_clockevent_register+0x3c/0x40
> [0.059468] pc : []lr : []psr: 60d3
> [0.065702] sp : c0c01ef8  ip : c0c01f10  fp : c0c01f0c
> [0.070908] r10: c0b44a3c  r9 :   r8 : c0a5ace0
> [0.076106] r7 : 0013  r6 : ef7f7640  r5 : ef06c0c0  r4 : a5f2106f
> [0.082608] r3 : f081c000  r2 : 012c  r1 : 20d3  r0 : ef06c0c0
> [0.089112] Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment 
> no
> ne
> [0.096384] Control: 10c5387d  Table: 404a  DAC: 0051
> [0.102110] Process swapper/0 (pid: 0, stack