date:20200724

HI,

On Fri, Jul 24, 2020 at 12:54 AM Maxime Ripard  wrote:
>
> Hi,
>
> On Tue, Jul 14, 2020 at 03:20:29PM +0800, Frank Lee wrote:
> > From: Yangtao Li 
> >
> > Allwinner A100 is a new SoC with Cortex-A53 cores, this commit adds
> > the basical DTSI file of it, including the clock, i2c, pins, sid, ths,
> > nmi, and UART support.
> >
> > Signed-off-by: Yangtao Li 
> > ---
> >  .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 ++
> >  1 file changed, 364 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi 
> > b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> > new file mode 100644
> > index ..3fb2443f2121
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> > @@ -0,0 +1,364 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (c) 2020 Yangtao Li 
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/ {
> > + interrupt-parent = <>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "arm,armv8";
>
> You should use the arm,cortex-a53 compatible here, arm,armv8 is for
> software models.
>
> > + sid@3006000 {
>
> The node name is supposed to be the class of the device, and the DT spec
> defines a list of them already. eeprom would be better suited here.

EFuse is more accurate?

Thx,
Yangtao

[PATCH] newport_con: vc_color is now in state

2020-07-24 Thread Jiri Slaby

Since commit 28bc24fc46f9 (vc: separate state), vc->vc_color is known as
vc->state.color. Somehow both me and 0-day bot missed this driver during
the conversion.

So fix the driver now.

Signed-off-by: Jiri Slaby 
Cc: Bartlomiej Zolnierkiewicz 
Cc: dri-de...@lists.freedesktop.org
Cc: linux-fb...@vger.kernel.org
Cc: linux-m...@vger.kernel.org
---
 drivers/video/console/newport_con.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/video/console/newport_con.c 
b/drivers/video/console/newport_con.c
index df3c52d72159..72f146d047d9 100644
--- a/drivers/video/console/newport_con.c
+++ b/drivers/video/console/newport_con.c
@@ -362,12 +362,12 @@ static void newport_clear(struct vc_data *vc, int sy, int 
sx, int height,
 
if (ystart < yend) {
newport_clear_screen(sx << 3, ystart, xend, yend,
-(vc->vc_color & 0xf0) >> 4);
+(vc->state.color & 0xf0) >> 4);
} else {
newport_clear_screen(sx << 3, ystart, xend, 1023,
-(vc->vc_color & 0xf0) >> 4);
+(vc->state.color & 0xf0) >> 4);
newport_clear_screen(sx << 3, 0, xend, yend,
-(vc->vc_color & 0xf0) >> 4);
+(vc->state.color & 0xf0) >> 4);
}
 }
 
@@ -591,11 +591,11 @@ static bool newport_scroll(struct vc_data *vc, unsigned 
int t, unsigned int b,
topscan = (topscan + (lines << 4)) & 0x3ff;
newport_clear_lines(vc->vc_rows - lines,
vc->vc_rows - 1,
-   (vc->vc_color & 0xf0) >> 4);
+   (vc->state.color & 0xf0) >> 4);
} else {
topscan = (topscan + (-lines << 4)) & 0x3ff;
newport_clear_lines(0, lines - 1,
-   (vc->vc_color & 0xf0) >> 4);
+   (vc->state.color & 0xf0) >> 4);
}
npregs->cset.topscan = (topscan - 1) & 0x3ff;
return false;
-- 
2.27.0

Re: [PATCH] xen-netfront: fix potential deadlock in xennet_remove()

2020-07-24 Thread Andrea Righi

On Thu, Jul 23, 2020 at 02:57:22PM -0700, David Miller wrote:
> From: Andrea Righi 
> Date: Wed, 22 Jul 2020 08:52:11 +0200
> 
> > +static int xennet_remove(struct xenbus_device *dev)
> > +{
> > +   struct netfront_info *info = dev_get_drvdata(>dev);
> > +
> > +   dev_dbg(>dev, "%s\n", dev->nodename);
> 
> These kinds of debugging messages provide zero context and are so much
> less useful than simply using tracepoints which are more universally
> available than printk debugging facilities.
> 
> Please remove all of the dev_dbg() calls from this patch.

I didn't add that dev_dbg() call, it's just the old code moved around,
but I agree, I'll remove that call and send a new version of this patch.

Thanks for looking at it!
-Andrea

Re: [PATCH v2 2/3] powerpc/powernv/idle: save-restore DAWR0,DAWRX0 for P10

2020-07-24 Thread Pratik Sampat





On 24/07/20 6:55 am, Michael Neuling wrote:

On Fri, 2020-07-10 at 10:52 +0530, Pratik Rajesh Sampat wrote:

Additional registers DAWR0, DAWRX0 may be lost on Power 10 for
stop levels < 4.
Therefore save the values of these SPRs before entering a  "stop"
state and restore their values on wakeup.

Signed-off-by: Pratik Rajesh Sampat 
---
  arch/powerpc/platforms/powernv/idle.c | 10 ++
  1 file changed, 10 insertions(+)

diff --git a/arch/powerpc/platforms/powernv/idle.c
b/arch/powerpc/platforms/powernv/idle.c
index 19d94d021357..f2e2a6a4c274 100644
--- a/arch/powerpc/platforms/powernv/idle.c
+++ b/arch/powerpc/platforms/powernv/idle.c
@@ -600,6 +600,8 @@ struct p9_sprs {
u64 iamr;
u64 amor;
u64 uamor;
+   u64 dawr0;
+   u64 dawrx0;
  };
  
  static unsigned long power9_idle_stop(unsigned long psscr, bool mmu_on)

@@ -687,6 +689,10 @@ static unsigned long power9_idle_stop(unsigned long
psscr, bool mmu_on)
sprs.iamr   = mfspr(SPRN_IAMR);
sprs.amor   = mfspr(SPRN_AMOR);
sprs.uamor  = mfspr(SPRN_UAMOR);
+   if (cpu_has_feature(CPU_FTR_ARCH_31)) {


You are actually viewing an old version of the patches
The main point of change were based on comments from Nick Piggin, I
have changed the top level function check from ARCH_300 to a P9 PVR
check instead.

A similar thing needs to be done for P10, however as the P10 PVR isn't
exposed yet, I've shelved this particular patch.

Nick's comment to check based on PVR:https://lkml.org/lkml/2020/7/13/1018
v4 of the series:https://lkml.org/lkml/2020/7/21/784

Thanks for your review,
Pratik


Can you add a comment here saying even though DAWR0 is ARCH_30, it's only
required to be saved on 31. Otherwise this looks pretty odd.


+   sprs.dawr0 = mfspr(SPRN_DAWR0);
+   sprs.dawrx0 = mfspr(SPRN_DAWRX0);
+   }
  
  	srr1 = isa300_idle_stop_mayloss(psscr);		/* go idle */
  
@@ -710,6 +716,10 @@ static unsigned long power9_idle_stop(unsigned long

psscr, bool mmu_on)
mtspr(SPRN_IAMR,sprs.iamr);
mtspr(SPRN_AMOR,sprs.amor);
mtspr(SPRN_UAMOR,   sprs.uamor);
+   if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+   mtspr(SPRN_DAWR0, sprs.dawr0);
+   mtspr(SPRN_DAWRX0, sprs.dawrx0);
+   }
  
  		/*

 * Workaround for POWER9 DD2.0, if we lost resources, the ERAT

Re: [PATCH 4/4] dt-binding: mediatek: mt8192: update mtk-wdt document

2020-07-24 Thread Crystal Guo

On Fri, 2020-07-24 at 06:02 +0800, Matthias Brugger wrote:
> 
> On 23/07/2020 23:29, Rob Herring wrote:
> > On Thu, Jul 23, 2020 at 05:07:31PM +0800, Seiya Wang wrote:
> >> From: Crystal Guo 
> >>
> >> update mtk-wdt document for MT8192 platform
> >>
> >> Signed-off-by: Crystal Guo 
> >> ---
> >>   Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 2 ++
> >>   1 file changed, 2 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt 
> >> b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> >> index 4dd36bd3f1ad..d760ca8a630e 100644
> >> --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> >> +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> >> @@ -12,6 +12,8 @@ Required properties:
> >>"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
> >>"mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
> >>"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
> >> +  "mediatek,mt8192-wdt": for MT8192
> >> +
> > 
> > So, not compatible with "mediatek,mt6589-wdt"? Is so, perhaps summarize
> > what the differences are.
> > 
> 
> Hm, looks to me as if the binding description for mt2712 and mt8183 isn't 
> correct, as we have a OF data just as we have for mt8192 now. Could you fix 
> this 
> in a separate patch?
> 
> Regards,
> Matthias
> 
> Besides watchdog, mt8192 toprgu module also provide sub-system software reset 
> features.
> mt2712 and mt8183 are same as mt8192. But mt6589 not support sub-system 
> software reset.
> 
> >>   
> >>   - reg : Specifies base physical address and size of the registers.
> >>   
> >> -- 
> >> 2.14.1

Re: [PATCH v2 04/20] unify generic instances of csum_partial_copy_nocheck()

On Fri, Jul 24, 2020 at 02:25:30AM +0100, Al Viro wrote:
> From: Al Viro 
> 
> quite a few architectures have the same csum_partial_copy_nocheck() -
> simply memcpy() the data and then return the csum of the copy.
> 
> hexagon, parisc, ia64, s390, um: explicitly spelled out that way.
> 
> arc, arm64, csky, h8300, m68k/nommu, microblaze, mips/GENERIC_CSUM, nds32,
> nios2, openrisc, riscv, unicore32: end up picking the same thing spelled
> out in lib/checksum.h (with varying amounts of perversions along the way).
> 
> everybody else (alpha, arm, c6x, m68k/mmu, mips/!GENERIC_CSUM, powerpc,
> sh, sparc, x86, xtensa) have non-generic variants.  For all except c6x
> the declaration is in their asm/checksum.h.  c6x uses the wrapper
> from asm-generic/checksum.h that would normally lead to the lib/checksum.h
> instance, but in case of c6x we end up using an asm function from arch/c6x
> instead.
> 
> Screw that mess - have architectures with private instances define
> _HAVE_ARCH_CSUM_AND_COPY in their asm/checksum.h and have the default
> one right in net/checksum.h conditional on _HAVE_ARCH_CSUM_AND_COPY
> *not* defined.

net-next has a patch from me killing off csum_and_copy_from_user
already:

https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=f1bfd71c8662f20d53e71ef4e18bfb0e5677c27f

[GIT PULL] tpmdd update for Linux v5.9

2020-07-24 Thread Jarkko Sakkinen

Hi

An issue was fixed with the TPM space buffer size. The buffer is used to
store in-TPM objects while swapped out of the TPM for a /dev/tpmrm0
session. The code incorrectly used PAGE_SIZE, which obviously can vary.
With v5.9 changes the buffer has a fixed size of 16 kB.

In addition, the PR contains support for acquiring TPM even log from
TPM2 ACPI table. This method is used by QEMU in particular.

/Jarkko

The following changes since commit f37e99aca03f63aa3f2bd13ceaf769455d12c4b0:

  Merge tag 's390-5.8-6' of 
git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux into master 
(2020-07-23 13:42:46 -0700)

are available in the Git repository at:

  git://git.infradead.org/users/jjs/linux-tpmdd.git tags/tpmdd-next-v5.9

for you to fetch changes up to 85467f63a05c43364ba0b90d0c05bb89191543fa:

  tpm: Add support for event log pointer found in TPM2 ACPI table (2020-07-24 
09:29:21 +0300)


tpmdd updates for Linux v5.9


Jarkko Sakkinen (1):
  tpm: Unify the mismatching TPM space buffer sizes

Stefan Berger (2):
  acpi: Extend TPM2 ACPI table with missing log fields
  tpm: Add support for event log pointer found in TPM2 ACPI table

Tyler Hicks (1):
  tpm: Require that all digests are present in TCG_PCR_EVENT2 structures

 drivers/char/tpm/eventlog/acpi.c | 63 ++--
 drivers/char/tpm/tpm-chip.c  |  9 ++
 drivers/char/tpm/tpm.h   |  5 +++-
 drivers/char/tpm/tpm2-space.c| 26 ++---
 drivers/char/tpm/tpmrm-dev.c |  2 +-
 include/acpi/actbl3.h|  7 +
 include/linux/tpm.h  |  1 +
 include/linux/tpm_eventlog.h | 11 +--
 8 files changed, 82 insertions(+), 42 deletions(-)

net/core/pktgen.c:720:21: sparse: sparse: incorrect type in argument 1 (different address spaces)

2020-07-24 Thread kernel test robot

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
master
head:   f37e99aca03f63aa3f2bd13ceaf769455d12c4b0
commit: 670d0a4b10704667765f7d18f7592993d02783aa sparse: use identifiers to 
define address spaces
date:   5 weeks ago
config: sh-randconfig-s031-20200724 (attached as .config)
compiler: sh4-linux-gcc (GCC) 9.3.0
reproduce:
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.2-93-g4c6cbe55-dirty
git checkout 670d0a4b10704667765f7d18f7592993d02783aa
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 
CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=sh 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 


sparse warnings: (new ones prefixed by >>)

   net/core/pktgen.c:720:21: sparse: sparse: incorrect type in initializer 
(different address spaces) @@ expected char const *__gu_addr @@ got 
char const [noderef] __user * @@
   net/core/pktgen.c:720:21: sparse: expected char const *__gu_addr
   net/core/pktgen.c:720:21: sparse: got char const [noderef] __user *
>> net/core/pktgen.c:720:21: sparse: sparse: incorrect type in argument 1 
>> (different address spaces) @@ expected void const volatile [noderef] 
>> __user * @@ got char const *__gu_addr @@
>> net/core/pktgen.c:720:21: sparse: expected void const volatile [noderef] 
>> __user *
   net/core/pktgen.c:720:21: sparse: got char const *__gu_addr
   net/core/pktgen.c:738:21: sparse: sparse: incorrect type in initializer 
(different address spaces) @@ expected char const *__gu_addr @@ got 
char const [noderef] __user * @@
   net/core/pktgen.c:738:21: sparse: expected char const *__gu_addr
   net/core/pktgen.c:738:21: sparse: got char const [noderef] __user *
   net/core/pktgen.c:738:21: sparse: sparse: incorrect type in argument 1 
(different address spaces) @@ expected void const volatile [noderef] __user 
* @@ got char const *__gu_addr @@
   net/core/pktgen.c:738:21: sparse: expected void const volatile [noderef] 
__user *
   net/core/pktgen.c:738:21: sparse: got char const *__gu_addr
   net/core/pktgen.c:764:21: sparse: sparse: incorrect type in initializer 
(different address spaces) @@ expected char const *__gu_addr @@ got 
char const [noderef] __user * @@
   net/core/pktgen.c:764:21: sparse: expected char const *__gu_addr
   net/core/pktgen.c:764:21: sparse: got char const [noderef] __user *
   net/core/pktgen.c:764:21: sparse: sparse: incorrect type in argument 1 
(different address spaces) @@ expected void const volatile [noderef] __user 
* @@ got char const *__gu_addr @@
   net/core/pktgen.c:764:21: sparse: expected void const volatile [noderef] 
__user *
   net/core/pktgen.c:764:21: sparse: got char const *__gu_addr
   net/core/pktgen.c:781:21: sparse: sparse: incorrect type in initializer 
(different address spaces) @@ expected char const *__gu_addr @@ got 
char const [noderef] __user * @@
   net/core/pktgen.c:781:21: sparse: expected char const *__gu_addr
   net/core/pktgen.c:781:21: sparse: got char const [noderef] __user *
   net/core/pktgen.c:781:21: sparse: sparse: incorrect type in argument 1 
(different address spaces) @@ expected void const volatile [noderef] __user 
* @@ got char const *__gu_addr @@
   net/core/pktgen.c:781:21: sparse: expected void const volatile [noderef] 
__user *
   net/core/pktgen.c:781:21: sparse: got char const *__gu_addr
   net/core/pktgen.c:815:21: sparse: sparse: incorrect type in initializer 
(different address spaces) @@ expected char const *__gu_addr @@ got 
char const [noderef] __user * @@
   net/core/pktgen.c:815:21: sparse: expected char const *__gu_addr
   net/core/pktgen.c:815:21: sparse: got char const [noderef] __user *
   net/core/pktgen.c:815:21: sparse: sparse: incorrect type in argument 1 
(different address spaces) @@ expected void const volatile [noderef] __user 
* @@ got char const *__gu_addr @@
   net/core/pktgen.c:815:21: sparse: expected void const volatile [noderef] 
__user *
   net/core/pktgen.c:815:21: sparse: got char const *__gu_addr
--
>> fs/nfsd/nfs4recover.c:800:13: sparse: sparse: incorrect type in initializer 
>> (different address spaces) @@ expected unsigned char const *__gu_addr @@ 
>> got unsigned char const [noderef] __user * @@
   fs/nfsd/nfs4recover.c:800:13: sparse: expected unsigned char const 
*__gu_addr
>> fs/nfsd/nfs4recover.c:800:13: sparse: got unsigned char const [noderef] 
>> __user *
>> fs/nfsd/nfs4recover.c:800:13: sparse: sparse: incorrect type in argument 1 
>> (different address spaces) @@ expe

arm-linux-gnueabi-ld: section .data VMA overlaps section .ARM.unwind_idx VMA

2020-07-24 Thread kernel test robot

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
master
head:   f37e99aca03f63aa3f2bd13ceaf769455d12c4b0
commit: 58ad13729a8a3e0a354de46eaf9969f9116d4763 vdpa: make vhost, virtio 
depend on menu
date:   3 months ago
config: arm-randconfig-s032-20200723 (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce:
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.2-93-g4c6cbe55-dirty
git checkout 58ad13729a8a3e0a354de46eaf9969f9116d4763
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 
CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=arm 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

>> arm-linux-gnueabi-ld: section .data VMA [40008000,402725b3] 
>> overlaps section .ARM.unwind_idx VMA [3ffb6aa8,4000a7af]
>> arm-linux-gnueabi-ld: section .ARM.unwind_tab VMA 
>> [4000a7b0,4000b68b] overlaps section .data VMA 
>> [40008000,402725b3]

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org


.config.gz
Description: application/gzip

[PATCH v5 00/16] Allwinner A100 Initial support

This patch set adds initial support for allwinner a100 soc,
which is a 64-bit tablet chip.

v5:
-Drop redundant SOB for thermal series patch
-Trival a100 dtsi fix

v4:
-Drop "dt-bindings: pinctrl: sunxi: make gpio banks supplies required"
-Fix dcdc1 regulator name
-Get rid of underscore in dts node name
-Some trivial things in yaml files

v3:
-Add pmu and nmi support
-Add read data mask for calibration
-Code style
-Some trivial things in yaml files

v2:
-Some naming consistency
-Repair email address
-Fix mmc clock
-Don't export system clock
-Fix checkpatch warning
-Drop unneeded pin function, convert to jtag_gpu and i2s_x

Yangtao Li (16):
  dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and
R-CCU
  clk: sunxi-ng: add support for the Allwinner A100 CCU
  dt-bindings: pinctrl: sunxi: Get rid of continual nesting
  dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings
  pinctrl: sunxi: add support for the Allwinner A100 pin controller
  dt-bindings: nvmem: SID: add binding for A100's SID controller
  dt-bindings: thermal: sun8i: Add binding for A100's THS controller
  thermal: sun8i: add TEMP_CALIB_MASK for calibration data in
sun50i_h6_ths_calibrate
  thermal: sun8i: Add A100's THS controller support
  mfd: axp20x: Allow the AXP803 to be probed by I2C
  dt-bindings: irq: sun7i-nmi: fix dt-binding for a80 nmi
  dt-bindings: irq: sun7i-nmi: Add binding for A100's NMI controller
  dt-bindings: i2c: mv64xxx: Add compatible for the A100 i2c node.
  arm64: allwinner: A100: add the basical Allwinner A100 DTSI file
  dt-bindings: arm: sunxi: Add Allwinner A100 Perf1 Board bindings
  arm64: allwinner: A100: add support for Allwinner Perf1 board

 .../devicetree/bindings/arm/sunxi.yaml|5 +
 .../clock/allwinner,sun4i-a10-ccu.yaml|7 +-
 .../bindings/i2c/marvell,mv64xxx-i2c.yaml |3 +
 .../allwinner,sun7i-a20-sc-nmi.yaml   |5 +-
 .../nvmem/allwinner,sun4i-a10-sid.yaml|   19 +-
 .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml  |  139 +-
 .../thermal/allwinner,sun8i-a83t-ths.yaml |6 +-
 arch/arm64/boot/dts/allwinner/Makefile|1 +
 .../allwinner/sun50i-a100-allwinner-perf1.dts |  180 +++
 .../arm64/boot/dts/allwinner/sun50i-a100.dtsi |  364 +
 drivers/clk/sunxi-ng/Kconfig  |   10 +
 drivers/clk/sunxi-ng/Makefile |2 +
 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c  |  214 +++
 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h  |   21 +
 drivers/clk/sunxi-ng/ccu-sun50i-a100.c| 1276 +
 drivers/clk/sunxi-ng/ccu-sun50i-a100.h|   56 +
 drivers/mfd/axp20x-i2c.c  |2 +
 drivers/pinctrl/sunxi/Kconfig |   10 +
 drivers/pinctrl/sunxi/Makefile|2 +
 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c |  105 ++
 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c   |  708 +
 drivers/thermal/sun8i_thermal.c   |   16 +-
 include/dt-bindings/clock/sun50i-a100-ccu.h   |  116 ++
 include/dt-bindings/clock/sun50i-a100-r-ccu.h |   23 +
 include/dt-bindings/reset/sun50i-a100-ccu.h   |   68 +
 include/dt-bindings/reset/sun50i-a100-r-ccu.h |   18 +
 26 files changed, 3308 insertions(+), 68 deletions(-)
 create mode 100644 
arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.h
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
 create mode 100644 include/dt-bindings/clock/sun50i-a100-ccu.h
 create mode 100644 include/dt-bindings/clock/sun50i-a100-r-ccu.h
 create mode 100644 include/dt-bindings/reset/sun50i-a100-ccu.h
 create mode 100644 include/dt-bindings/reset/sun50i-a100-r-ccu.h

-- 
2.24.0

Re: [PATCH v3 2/2] soc: mediatek: add mtk-devapc driver

2020-07-24 Thread Neal Liu

Hi Chun-Kuang,

On Fri, 2020-07-24 at 00:32 +0800, Chun-Kuang Hu wrote:
> Hi, Neal:
> 
> Neal Liu  於 2020年7月23日 週四 下午2:11寫道：
> >
> > Hi Chun-Kuang,
> >
> > On Wed, 2020-07-22 at 22:25 +0800, Chun-Kuang Hu wrote:
> > > Hi, Neal:
> > >
> > > Neal Liu  於 2020年7月22日 週三 上午11:49寫道：
> > > >
> > > > Hi Chun-Kuang,
> > > >
> > > > On Wed, 2020-07-22 at 07:21 +0800, Chun-Kuang Hu wrote:
> > > > > Hi, Neal:
> > > > >
> > > > > Neal Liu  於 2020年7月21日 週二 下午12:00寫道：
> > > > > >
> > > > >
> > > > > > +
> > > > > > +/*
> > > > > > + * mtk_devapc_dump_vio_dbg - get the violation index and dump the 
> > > > > > full violation
> > > > > > + *   debug information.
> > > > > > + */
> > > > > > +static bool mtk_devapc_dump_vio_dbg(struct mtk_devapc_context 
> > > > > > *ctx, u32 vio_idx)
> > > > > > +{
> > > > > > +   u32 shift_bit;
> > > > > > +
> > > > > > +   if (check_vio_mask(ctx, vio_idx))
> > > > > > +   return false;
> > > > > > +
> > > > > > +   if (!check_vio_status(ctx, vio_idx))
> > > > > > +   return false;
> > > > > > +
> > > > > > +   shift_bit = get_shift_group(ctx, vio_idx);
> > > > > > +
> > > > > > +   if (sync_vio_dbg(ctx, shift_bit))
> > > > > > +   return false;
> > > > > > +
> > > > > > +   devapc_extract_vio_dbg(ctx);
> > > > >
> > > > > I think get_shift_group(), sync_vio_dbg(), and
> > > > > devapc_extract_vio_dbg() should be moved out of vio_idx for-loop (the
> > > > > loop in devapc_violation_irq()) because these three function is not
> > > > > related to vio_idx.
> > > > > Another question: when multiple vio_idx violation occur, vio_addr is
> > > > > related to which one vio_idx? The latest happened one?
> > > > >
> > > >
> > > > Actually, it's related to vio_idx. But we don't use it directly on these
> > > > function. I think below snip code might be better way to understand it.
> > > >
> > > > for (...)
> > > > {
> > > > check_vio_mask()
> > > > check_vio_status()
> > > >
> > > > // if get vio_idx, mask it temporarily
> > > > mask_module_irq(true)
> > > > clear_vio_status()
> > > >
> > > > // dump violation info
> > > > get_shift_group()
> > > > sync_vio_dbg()
> > > > devapc_extract_vio_dbg()
> > > >
> > > > // unmask
> > > > mask_module_irq(false)
> > > > }
> > >
> > > This snip code does not explain any thing. I could rewrite this code as:
> > >
> > > for (...)
> > > {
> > > check_vio_mask()
> > > check_vio_status()
> > >
> > > // if get vio_idx, mask it temporarily
> > > mask_module_irq(true)
> > > clear_vio_status()
> > > // unmask
> > > mask_module_irq(false)
> > > }
> > >
> > > // dump violation info
> > > get_shift_group()
> > > sync_vio_dbg()
> > > devapc_extract_vio_dbg()
> > >
> > > And my version is identical with your version, isn't it?
> >
> > Sorry, I did not explain it clearly. Let's me try again.
> > The reason why I put "dump violation info" between mask & unmask context
> > is because it has to stop interrupt first before dump violation info,
> > and then unmask it to prepare next violation.
> > These sequence guarantee that if multiple violation is triggered, we
> > still have information to debug.
> > If the code sequence in your version and multiple violation is
> > triggered, there might be no any information but keeps entering ISR.
> > Finally, system might be abnormal and watchdog timeout.
> > In this case, we still don't have any information to debug.
> 
> I still don't understand why no information to debug. For example when
> vio_idx 5, 10, 15 has violation,
> You would mask vio_idx 5 to get information, but vio_idx 10, 15 does
> not mask yet.
> In your words, when vio_idx 10, 15 not mask, you would not get any
> debug information when you process vio_idx 5.
> 
> In my version, I would clear all status, why keeps entering ISR?

Think about this case, if someone tries to dump "AAA" module's register.
It would keep read reg base, base+0x4, base+0x8, ...
All these registers are in the same slave, which would be same vio_idx.
(Take vio_idx 5 as example)
In this case, vio_idx 5 will keep triggering interrupt. If you did not
do "dump violation info" between mask & unmask, you cannot get any
violation info until the last interrupt being handled.
Normally, system will crash before last interrupt coming.

> 
> >
> > >
> > > >
> > > > About your question, vio_addr would be the first one.
> > >
> > > So other vio_addr would be dropped? Or hardware would keep all
> > > vio_addr and you have some way to get all vio_addr?
> > >
> >
> > In this case, hardware will drop other violation info and keep the first
> > one until it been handled.
> 
> Does 'handled' mean status is cleared?

"handled" means clear status and dump violation info.

> 
> Regards,
> Chun-Kuang.
> 
> >
> > > >
> > > > > > +
> > > > > > +   return true;
> > > > > > +}
> > > > > > +
> > > > > > +/*
> > > > > > + *

[PATCH v5 01/16] dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU

From: Yangtao Li 

This patch adds binding to a100's ccu clock and r-ccu clock.

Signed-off-by: Yangtao Li 
Reviewed-by: Rob Herring 
---
 .../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git 
a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml 
b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
index 4d382128b711..3b45344ed758 100644
--- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
+++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
@@ -36,6 +36,8 @@ properties:
   - allwinner,sun9i-a80-ccu
   - allwinner,sun50i-a64-ccu
   - allwinner,sun50i-a64-r-ccu
+  - allwinner,sun50i-a100-ccu
+  - allwinner,sun50i-a100-r-ccu
   - allwinner,sun50i-h5-ccu
   - allwinner,sun50i-h6-ccu
   - allwinner,sun50i-h6-r-ccu
@@ -78,6 +80,7 @@ if:
 - allwinner,sun8i-a83t-r-ccu
 - allwinner,sun8i-h3-r-ccu
 - allwinner,sun50i-a64-r-ccu
+- allwinner,sun50i-a100-r-ccu
 - allwinner,sun50i-h6-r-ccu
 
 then:
@@ -94,7 +97,9 @@ else:
   if:
 properties:
   compatible:
-const: allwinner,sun50i-h6-ccu
+enum:
+  - allwinner,sun50i-a100-ccu
+  - allwinner,sun50i-h6-ccu
 
   then:
 properties:
-- 
2.24.0

Re: [PATCH] drivers: isdn: capi: Fix data-race bug

2020-07-24 Thread Greg KH

On Fri, Jul 24, 2020 at 10:18:07AM +0530, Madhuparna Bhowmik wrote:
> On Thu, Jul 23, 2020 at 03:11:58PM -0700, David Miller wrote:
> > From: madhuparnabhowmi...@gmail.com
> > Date: Wed, 22 Jul 2020 22:53:29 +0530
> > 
> > > From: Madhuparna Bhowmik 
> > > 
> > > In capi_init(), after register_chrdev() the file operation callbacks
> > > can be called. However capinc_tty_init() is called later.
> > > Since capiminors and capinc_tty_driver are initialized in
> > > capinc_tty_init(), their initialization can race with their usage
> > > in various callbacks like in capi_release().
> > > 
> > > Therefore, call capinc_tty_init() before register_chrdev to avoid
> > > such race conditions.
> > > 
> > > Found by Linux Driver Verification project (linuxtesting.org).
> > > 
> > > Signed-off-by: Madhuparna Bhowmik 
> > 
> > I agree with Arnd that this just exchanges one set of problems for
> > another.
> 
> Thanks Arnd and David, for reviewing the patch.
> Do you have any suggestions on how to fix this correctly?

Based on the installed base of ISDN systems, and the fact that no one
has ever actually hit this race and reported it ever, I wouldn't worry
about it :)

thanks,

greg k-h

[PATCH v5 02/16] clk: sunxi-ng: add support for the Allwinner A100 CCU

From: Yangtao Li 

Add support for a100 in the sunxi-ng CCU framework.

Signed-off-by: Yangtao Li 
---
 drivers/clk/sunxi-ng/Kconfig  |   10 +
 drivers/clk/sunxi-ng/Makefile |2 +
 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c  |  214 +++
 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h  |   21 +
 drivers/clk/sunxi-ng/ccu-sun50i-a100.c| 1276 +
 drivers/clk/sunxi-ng/ccu-sun50i-a100.h|   56 +
 include/dt-bindings/clock/sun50i-a100-ccu.h   |  116 ++
 include/dt-bindings/clock/sun50i-a100-r-ccu.h |   23 +
 include/dt-bindings/reset/sun50i-a100-ccu.h   |   68 +
 include/dt-bindings/reset/sun50i-a100-r-ccu.h |   18 +
 10 files changed, 1804 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.h
 create mode 100644 include/dt-bindings/clock/sun50i-a100-ccu.h
 create mode 100644 include/dt-bindings/clock/sun50i-a100-r-ccu.h
 create mode 100644 include/dt-bindings/reset/sun50i-a100-ccu.h
 create mode 100644 include/dt-bindings/reset/sun50i-a100-r-ccu.h

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index cdf333003c30..ce5f5847d5d3 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -17,6 +17,16 @@ config SUN50I_A64_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
 
+config SUN50I_A100_CCU
+   bool "Support for the Allwinner A100 CCU"
+   default ARM64 && ARCH_SUNXI
+   depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
+config SUN50I_A100_R_CCU
+   bool "Support for the Allwinner A100 PRCM CCU"
+   default ARM64 && ARCH_SUNXI
+   depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
 config SUN50I_H6_CCU
bool "Support for the Allwinner H6 CCU"
default ARM64 && ARCH_SUNXI
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 4c7bee883f2f..3eb5cff40eac 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -23,6 +23,8 @@ obj-y += ccu_mp.o
 # SoC support
 obj-$(CONFIG_SUNIV_F1C100S_CCU)+= ccu-suniv-f1c100s.o
 obj-$(CONFIG_SUN50I_A64_CCU)   += ccu-sun50i-a64.o
+obj-$(CONFIG_SUN50I_A100_CCU)  += ccu-sun50i-a100.o
+obj-$(CONFIG_SUN50I_A100_R_CCU)+= ccu-sun50i-a100-r.o
 obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o
 obj-$(CONFIG_SUN50I_H6_R_CCU)  += ccu-sun50i-h6-r.o
 obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c 
b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
new file mode 100644
index ..a56142b90993
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Yangtao Li 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun50i-a100-r.h"
+
+static const char * const cpus_r_apb2_parents[] = { "dcxo24M", "osc32k",
+"iosc", "pll-periph0" };
+static const struct ccu_mux_var_prediv cpus_r_apb2_predivs[] = {
+   { .index = 3, .shift = 0, .width = 5 },
+};
+
+static struct ccu_div r_cpus_clk = {
+   .div= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+   .mux= {
+   .shift  = 24,
+   .width  = 2,
+
+   .var_predivs= cpus_r_apb2_predivs,
+   .n_var_predivs  = ARRAY_SIZE(cpus_r_apb2_predivs),
+   },
+
+   .common = {
+   .reg= 0x000,
+   .features   = CCU_FEATURE_VARIABLE_PREDIV,
+   .hw.init= CLK_HW_INIT_PARENTS("cpus",
+ cpus_r_apb2_parents,
+ _div_ops,
+ 0),
+   },
+};
+
+static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", _cpus_clk.common.hw, 1, 1, 0);
+
+static struct ccu_div r_apb1_clk = {
+   .div= _SUNXI_CCU_DIV(0, 2),
+
+   .common = {
+   .reg= 0x00c,
+   .hw.init= CLK_HW_INIT("r-apb1",
+ "r-ahb",
+ _div_ops,
+ 0),
+   },
+};
+
+static struct ccu_div r_apb2_clk = {
+   .div= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+   .mux= {
+   .shift  = 24,
+   .width  = 2,
+
+   .var_predivs= cpus_r_apb2_predivs,
+   .n_var_predivs  =

[PATCH v2 3/8] kcsan: Skew delay to be longer for certain access types

For compound instrumentation and assert accesses, skew the watchpoint
delay to be longer if randomized. This is useful to improve race
detection for such accesses.

For compound accesses we should increase the delay as we've aggregated
both read and write instrumentation. By giving up 1 call into the
runtime, we're less likely to set up a watchpoint and thus less likely
to detect a race. We can balance this by increasing the watchpoint
delay.

For assert accesses, we know these are of increased interest, and we
wish to increase our chances of detecting races for such checks.

Note that, kcsan_udelay_{task,interrupt} define the upper bound delays.
When randomized, delays are uniformly distributed between [0, delay].
Skewing the delay does not break this promise as long as the defined
upper bounds are still adhered to. The current skew results in delays
uniformly distributed between [delay/2, delay].

Signed-off-by: Marco Elver 
---
v2:
* Commit message rewording.
---
 kernel/kcsan/core.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/kernel/kcsan/core.c b/kernel/kcsan/core.c
index fb52de2facf3..4633baebf84e 100644
--- a/kernel/kcsan/core.c
+++ b/kernel/kcsan/core.c
@@ -283,11 +283,15 @@ static __always_inline bool kcsan_is_enabled(void)
return READ_ONCE(kcsan_enabled) && get_ctx()->disable_count == 0;
 }
 
-static inline unsigned int get_delay(void)
+static inline unsigned int get_delay(int type)
 {
unsigned int delay = in_task() ? kcsan_udelay_task : 
kcsan_udelay_interrupt;
+   /* For certain access types, skew the random delay to be longer. */
+   unsigned int skew_delay_order =
+   (type & (KCSAN_ACCESS_COMPOUND | KCSAN_ACCESS_ASSERT)) ? 1 : 0;
+
return delay - (IS_ENABLED(CONFIG_KCSAN_DELAY_RANDOMIZE) ?
-   prandom_u32_max(delay) :
+   prandom_u32_max(delay >> skew_delay_order) :
0);
 }
 
@@ -449,7 +453,7 @@ kcsan_setup_watchpoint(const volatile void *ptr, size_t 
size, int type)
 * Delay this thread, to increase probability of observing a racy
 * conflicting access.
 */
-   udelay(get_delay());
+   udelay(get_delay(type));
 
/*
 * Re-read value, and check if it is as expected; if not, we infer a
-- 
2.28.0.rc0.142.g3c755180ce-goog

[PATCH v2 4/8] kcsan: Add missing CONFIG_KCSAN_IGNORE_ATOMICS checks

Add missing CONFIG_KCSAN_IGNORE_ATOMICS checks for the builtin atomics
instrumentation.

Signed-off-by: Marco Elver 
---
v2:
* Add {} for readability.

Added to this series, as it would otherwise cause patch conflicts.
---
 kernel/kcsan/core.c | 30 ++
 1 file changed, 22 insertions(+), 8 deletions(-)

diff --git a/kernel/kcsan/core.c b/kernel/kcsan/core.c
index 4633baebf84e..e43a55643e00 100644
--- a/kernel/kcsan/core.c
+++ b/kernel/kcsan/core.c
@@ -892,14 +892,19 @@ EXPORT_SYMBOL(__tsan_init);
u##bits __tsan_atomic##bits##_load(const u##bits *ptr, int memorder);   
   \
u##bits __tsan_atomic##bits##_load(const u##bits *ptr, int memorder)
   \
{   
   \
-   check_access(ptr, bits / BITS_PER_BYTE, KCSAN_ACCESS_ATOMIC);   
   \
+   if (!IS_ENABLED(CONFIG_KCSAN_IGNORE_ATOMICS)) { 
   \
+   check_access(ptr, bits / BITS_PER_BYTE, 
KCSAN_ACCESS_ATOMIC);  \
+   }   
   \
return __atomic_load_n(ptr, memorder);  
   \
}   
   \
EXPORT_SYMBOL(__tsan_atomic##bits##_load);  
   \
void __tsan_atomic##bits##_store(u##bits *ptr, u##bits v, int 
memorder);   \
void __tsan_atomic##bits##_store(u##bits *ptr, u##bits v, int memorder) 
   \
{   
   \
-   check_access(ptr, bits / BITS_PER_BYTE, KCSAN_ACCESS_WRITE | 
KCSAN_ACCESS_ATOMIC); \
+   if (!IS_ENABLED(CONFIG_KCSAN_IGNORE_ATOMICS)) { 
   \
+   check_access(ptr, bits / BITS_PER_BYTE, 
   \
+KCSAN_ACCESS_WRITE | KCSAN_ACCESS_ATOMIC); 
   \
+   }   
   \
__atomic_store_n(ptr, v, memorder); 
   \
}   
   \
EXPORT_SYMBOL(__tsan_atomic##bits##_store)
@@ -908,8 +913,11 @@ EXPORT_SYMBOL(__tsan_init);
u##bits __tsan_atomic##bits##_##op(u##bits *ptr, u##bits v, int 
memorder); \
u##bits __tsan_atomic##bits##_##op(u##bits *ptr, u##bits v, int 
memorder)  \
{   
   \
-   check_access(ptr, bits / BITS_PER_BYTE, 
   \
-KCSAN_ACCESS_COMPOUND | KCSAN_ACCESS_WRITE | 
KCSAN_ACCESS_ATOMIC);\
+   if (!IS_ENABLED(CONFIG_KCSAN_IGNORE_ATOMICS)) { 
   \
+   check_access(ptr, bits / BITS_PER_BYTE, 
   \
+KCSAN_ACCESS_COMPOUND | KCSAN_ACCESS_WRITE 
|  \
+KCSAN_ACCESS_ATOMIC);  
   \
+   }   
   \
return __atomic_##op##suffix(ptr, v, memorder); 
   \
}   
   \
EXPORT_SYMBOL(__tsan_atomic##bits##_##op)
@@ -937,8 +945,11 @@ EXPORT_SYMBOL(__tsan_init);
int __tsan_atomic##bits##_compare_exchange_##strength(u##bits *ptr, 
u##bits *exp,  \
  u##bits val, int 
mo, int fail_mo)\
{   
   \
-   check_access(ptr, bits / BITS_PER_BYTE, 
   \
-KCSAN_ACCESS_COMPOUND | KCSAN_ACCESS_WRITE | 
KCSAN_ACCESS_ATOMIC);\
+   if (!IS_ENABLED(CONFIG_KCSAN_IGNORE_ATOMICS)) { 
   \
+   check_access(ptr, bits / BITS_PER_BYTE, 
   \
+KCSAN_ACCESS_COMPOUND | KCSAN_ACCESS_WRITE 
|  \
+KCSAN_ACCESS_ATOMIC);  
   \
+   }

[PATCH v2 1/8] kcsan: Support compounded read-write instrumentation

Add support for compounded read-write instrumentation if supported by
the compiler. Adds the necessary instrumentation functions, and a new
type which is used to generate a more descriptive report.

Furthermore, such compounded memory access instrumentation is excluded
from the "assume aligned writes up to word size are atomic" rule,
because we cannot assume that the compiler emits code that is atomic for
compound ops.

LLVM/Clang added support for the feature in:
https://github.com/llvm/llvm-project/commit/785d41a261d136b64ab6c15c5d35f2adc5ad53e3

The new instrumentation is emitted for sets of memory accesses in the
same basic block to the same address with at least one read appearing
before a write. These typically result from compound operations such as
++, --, +=, -=, |=, &=, etc. but also equivalent forms such as "var =
var + 1". Where the compiler determines that it is equivalent to emit a
call to a single __tsan_read_write instead of separate __tsan_read and
__tsan_write, we can then benefit from improved performance and better
reporting for such access patterns.

The new reports now show that the ops are both reads and writes, for
example:

read-write to 0x90548a38 of 8 bytes by task 143 on cpu 3:
 test_kernel_rmw_array+0x45/0xa0
 access_thread+0x71/0xb0
 kthread+0x21e/0x240
 ret_from_fork+0x22/0x30

read-write to 0x90548a38 of 8 bytes by task 144 on cpu 2:
 test_kernel_rmw_array+0x45/0xa0
 access_thread+0x71/0xb0
 kthread+0x21e/0x240
 ret_from_fork+0x22/0x30

Signed-off-by: Marco Elver 
---
 include/linux/kcsan-checks.h | 45 
 kernel/kcsan/core.c  | 23 ++
 kernel/kcsan/report.c|  4 
 scripts/Makefile.kcsan   |  2 +-
 4 files changed, 53 insertions(+), 21 deletions(-)

diff --git a/include/linux/kcsan-checks.h b/include/linux/kcsan-checks.h
index 7b0b9c44f5f3..ab23b38ad93d 100644
--- a/include/linux/kcsan-checks.h
+++ b/include/linux/kcsan-checks.h
@@ -7,19 +7,13 @@
 #include 
 #include 
 
-/*
- * ACCESS TYPE MODIFIERS
- *
- *   : normal read access;
- *   WRITE : write access;
- *   ATOMIC: access is atomic;
- *   ASSERT: access is not a regular access, but an assertion;
- *   SCOPED: access is a scoped access;
- */
-#define KCSAN_ACCESS_WRITE  0x1
-#define KCSAN_ACCESS_ATOMIC 0x2
-#define KCSAN_ACCESS_ASSERT 0x4
-#define KCSAN_ACCESS_SCOPED 0x8
+/* Access types -- if KCSAN_ACCESS_WRITE is not set, the access is a read. */
+#define KCSAN_ACCESS_WRITE (1 << 0) /* Access is a write. */
+#define KCSAN_ACCESS_COMPOUND  (1 << 1) /* Compounded read-write 
instrumentation. */
+#define KCSAN_ACCESS_ATOMIC(1 << 2) /* Access is atomic. */
+/* The following are special, and never due to compiler instrumentation. */
+#define KCSAN_ACCESS_ASSERT(1 << 3) /* Access is an assertion. */
+#define KCSAN_ACCESS_SCOPED(1 << 4) /* Access is a scoped access. */
 
 /*
  * __kcsan_*: Always calls into the runtime when KCSAN is enabled. This may be 
used
@@ -204,6 +198,15 @@ static inline void __kcsan_disable_current(void) { }
 #define __kcsan_check_write(ptr, size) 
\
__kcsan_check_access(ptr, size, KCSAN_ACCESS_WRITE)
 
+/**
+ * __kcsan_check_read_write - check regular read-write access for races
+ *
+ * @ptr: address of access
+ * @size: size of access
+ */
+#define __kcsan_check_read_write(ptr, size)
\
+   __kcsan_check_access(ptr, size, KCSAN_ACCESS_COMPOUND | 
KCSAN_ACCESS_WRITE)
+
 /**
  * kcsan_check_read - check regular read access for races
  *
@@ -221,18 +224,30 @@ static inline void __kcsan_disable_current(void) { }
 #define kcsan_check_write(ptr, size)   
\
kcsan_check_access(ptr, size, KCSAN_ACCESS_WRITE)
 
+/**
+ * kcsan_check_read_write - check regular read-write access for races
+ *
+ * @ptr: address of access
+ * @size: size of access
+ */
+#define kcsan_check_read_write(ptr, size)  
\
+   kcsan_check_access(ptr, size, KCSAN_ACCESS_COMPOUND | 
KCSAN_ACCESS_WRITE)
+
 /*
  * Check for atomic accesses: if atomic accesses are not ignored, this simply
  * aliases to kcsan_check_access(), otherwise becomes a no-op.
  */
 #ifdef CONFIG_KCSAN_IGNORE_ATOMICS
-#define kcsan_check_atomic_read(...)   do { } while (0)
-#define kcsan_check_atomic_write(...)  do { } while (0)
+#define kcsan_check_atomic_read(...)   do { } while (0)
+#define kcsan_check_atomic_write(...)  do { } while (0)
+#define kcsan_check_atomic_read_write(...) do { } while (0)
 #else
 #define kcsan_check_atomic_read(ptr, size) 
\
kcsan_check_access(ptr, size, KCSAN_ACCESS_ATOMIC)
 #define kcsan_check_atomic_write(ptr, size)
\
kcsan_check_access(ptr, size, KCSAN_ACCESS_ATOMIC |

[PATCH v2 0/8] kcsan: Compound read-write instrumentation

This series adds support for enabling compounded read-write
instrumentation, if supported by the compiler (Clang 12 will be the
first compiler to support the feature). The new instrumentation is
emitted for sets of memory accesses in the same basic block to the same
address with at least one read appearing before a write. These typically
result from compound operations such as ++, --, +=, -=, |=, &=, etc. but
also equivalent forms such as "var = var + 1".

We can then benefit from improved performance (fewer instrumentation
calls) and better reporting for such accesses. In addition, existing
explicit instrumentation via instrumented.h was updated to use explicit
read-write instrumentation where appropriate, so we can also benefit
from the better report generation.

v2:
* Fix CC_HAS_TSAN_COMPOUND_READ_BEFORE_WRITE: s/--param -tsan/--param tsan/
* Add some {} for readability.
* Rewrite commit message of 'kcsan: Skew delay to be longer for certain
  access types'.
* Update comment for gen-atomic-instrumented.sh.

Marco Elver (8):
  kcsan: Support compounded read-write instrumentation
  objtool, kcsan: Add __tsan_read_write to uaccess whitelist
  kcsan: Skew delay to be longer for certain access types
  kcsan: Add missing CONFIG_KCSAN_IGNORE_ATOMICS checks
  kcsan: Test support for compound instrumentation
  instrumented.h: Introduce read-write instrumentation hooks
  asm-generic/bitops: Use instrument_read_write() where appropriate
  locking/atomics: Use read-write instrumentation for atomic RMWs

 include/asm-generic/atomic-instrumented.h | 330 +-
 .../asm-generic/bitops/instrumented-atomic.h  |   6 +-
 .../asm-generic/bitops/instrumented-lock.h|   2 +-
 .../bitops/instrumented-non-atomic.h  |   6 +-
 include/linux/instrumented.h  |  30 ++
 include/linux/kcsan-checks.h  |  45 ++-
 kernel/kcsan/core.c   |  51 ++-
 kernel/kcsan/kcsan-test.c |  65 +++-
 kernel/kcsan/report.c |   4 +
 lib/Kconfig.kcsan |   5 +
 scripts/Makefile.kcsan|   2 +-
 scripts/atomic/gen-atomic-instrumented.sh |  21 +-
 tools/objtool/check.c |   5 +
 13 files changed, 354 insertions(+), 218 deletions(-)

-- 
2.28.0.rc0.142.g3c755180ce-goog

[PATCH v2 6/8] instrumented.h: Introduce read-write instrumentation hooks

Introduce read-write instrumentation hooks, to more precisely denote an
operation's behaviour.

KCSAN is able to distinguish compound instrumentation, and with the new
instrumentation we then benefit from improved reporting. More
importantly, read-write compound operations should not implicitly be
treated as atomic, if they aren't actually atomic.

Signed-off-by: Marco Elver 
---
 include/linux/instrumented.h | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/include/linux/instrumented.h b/include/linux/instrumented.h
index 43e6ea591975..42faebbaa202 100644
--- a/include/linux/instrumented.h
+++ b/include/linux/instrumented.h
@@ -42,6 +42,21 @@ static __always_inline void instrument_write(const volatile 
void *v, size_t size
kcsan_check_write(v, size);
 }
 
+/**
+ * instrument_read_write - instrument regular read-write access
+ *
+ * Instrument a regular write access. The instrumentation should be inserted
+ * before the actual write happens.
+ *
+ * @ptr address of access
+ * @size size of access
+ */
+static __always_inline void instrument_read_write(const volatile void *v, 
size_t size)
+{
+   kasan_check_write(v, size);
+   kcsan_check_read_write(v, size);
+}
+
 /**
  * instrument_atomic_read - instrument atomic read access
  *
@@ -72,6 +87,21 @@ static __always_inline void instrument_atomic_write(const 
volatile void *v, size
kcsan_check_atomic_write(v, size);
 }
 
+/**
+ * instrument_atomic_read_write - instrument atomic read-write access
+ *
+ * Instrument an atomic read-write access. The instrumentation should be
+ * inserted before the actual write happens.
+ *
+ * @ptr address of access
+ * @size size of access
+ */
+static __always_inline void instrument_atomic_read_write(const volatile void 
*v, size_t size)
+{
+   kasan_check_write(v, size);
+   kcsan_check_atomic_read_write(v, size);
+}
+
 /**
  * instrument_copy_to_user - instrument reads of copy_to_user
  *
-- 
2.28.0.rc0.142.g3c755180ce-goog

[PATCH v2 7/8] asm-generic/bitops: Use instrument_read_write() where appropriate

Use the new instrument_read_write() where appropriate.

Signed-off-by: Marco Elver 
---
 include/asm-generic/bitops/instrumented-atomic.h | 6 +++---
 include/asm-generic/bitops/instrumented-lock.h   | 2 +-
 include/asm-generic/bitops/instrumented-non-atomic.h | 6 +++---
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/asm-generic/bitops/instrumented-atomic.h 
b/include/asm-generic/bitops/instrumented-atomic.h
index fb2cb33a4013..81915dcd4b4e 100644
--- a/include/asm-generic/bitops/instrumented-atomic.h
+++ b/include/asm-generic/bitops/instrumented-atomic.h
@@ -67,7 +67,7 @@ static inline void change_bit(long nr, volatile unsigned long 
*addr)
  */
 static inline bool test_and_set_bit(long nr, volatile unsigned long *addr)
 {
-   instrument_atomic_write(addr + BIT_WORD(nr), sizeof(long));
+   instrument_atomic_read_write(addr + BIT_WORD(nr), sizeof(long));
return arch_test_and_set_bit(nr, addr);
 }
 
@@ -80,7 +80,7 @@ static inline bool test_and_set_bit(long nr, volatile 
unsigned long *addr)
  */
 static inline bool test_and_clear_bit(long nr, volatile unsigned long *addr)
 {
-   instrument_atomic_write(addr + BIT_WORD(nr), sizeof(long));
+   instrument_atomic_read_write(addr + BIT_WORD(nr), sizeof(long));
return arch_test_and_clear_bit(nr, addr);
 }
 
@@ -93,7 +93,7 @@ static inline bool test_and_clear_bit(long nr, volatile 
unsigned long *addr)
  */
 static inline bool test_and_change_bit(long nr, volatile unsigned long *addr)
 {
-   instrument_atomic_write(addr + BIT_WORD(nr), sizeof(long));
+   instrument_atomic_read_write(addr + BIT_WORD(nr), sizeof(long));
return arch_test_and_change_bit(nr, addr);
 }
 
diff --git a/include/asm-generic/bitops/instrumented-lock.h 
b/include/asm-generic/bitops/instrumented-lock.h
index b9bec468ae03..75ef606f7145 100644
--- a/include/asm-generic/bitops/instrumented-lock.h
+++ b/include/asm-generic/bitops/instrumented-lock.h
@@ -52,7 +52,7 @@ static inline void __clear_bit_unlock(long nr, volatile 
unsigned long *addr)
  */
 static inline bool test_and_set_bit_lock(long nr, volatile unsigned long *addr)
 {
-   instrument_atomic_write(addr + BIT_WORD(nr), sizeof(long));
+   instrument_atomic_read_write(addr + BIT_WORD(nr), sizeof(long));
return arch_test_and_set_bit_lock(nr, addr);
 }
 
diff --git a/include/asm-generic/bitops/instrumented-non-atomic.h 
b/include/asm-generic/bitops/instrumented-non-atomic.h
index 20f788a25ef9..f86234c7c10c 100644
--- a/include/asm-generic/bitops/instrumented-non-atomic.h
+++ b/include/asm-generic/bitops/instrumented-non-atomic.h
@@ -68,7 +68,7 @@ static inline void __change_bit(long nr, volatile unsigned 
long *addr)
  */
 static inline bool __test_and_set_bit(long nr, volatile unsigned long *addr)
 {
-   instrument_write(addr + BIT_WORD(nr), sizeof(long));
+   instrument_read_write(addr + BIT_WORD(nr), sizeof(long));
return arch___test_and_set_bit(nr, addr);
 }
 
@@ -82,7 +82,7 @@ static inline bool __test_and_set_bit(long nr, volatile 
unsigned long *addr)
  */
 static inline bool __test_and_clear_bit(long nr, volatile unsigned long *addr)
 {
-   instrument_write(addr + BIT_WORD(nr), sizeof(long));
+   instrument_read_write(addr + BIT_WORD(nr), sizeof(long));
return arch___test_and_clear_bit(nr, addr);
 }
 
@@ -96,7 +96,7 @@ static inline bool __test_and_clear_bit(long nr, volatile 
unsigned long *addr)
  */
 static inline bool __test_and_change_bit(long nr, volatile unsigned long *addr)
 {
-   instrument_write(addr + BIT_WORD(nr), sizeof(long));
+   instrument_read_write(addr + BIT_WORD(nr), sizeof(long));
return arch___test_and_change_bit(nr, addr);
 }
 
-- 
2.28.0.rc0.142.g3c755180ce-goog

[PATCH v2 2/8] objtool, kcsan: Add __tsan_read_write to uaccess whitelist

Adds the new __tsan_read_write compound instrumentation to objtool's
uaccess whitelist.

Signed-off-by: Marco Elver 
Acked-by: Peter Zijlstra (Intel) 
---
 tools/objtool/check.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/tools/objtool/check.c b/tools/objtool/check.c
index 63d8b630c67a..38d82e705c93 100644
--- a/tools/objtool/check.c
+++ b/tools/objtool/check.c
@@ -528,6 +528,11 @@ static const char *uaccess_safe_builtin[] = {
"__tsan_write4",
"__tsan_write8",
"__tsan_write16",
+   "__tsan_read_write1",
+   "__tsan_read_write2",
+   "__tsan_read_write4",
+   "__tsan_read_write8",
+   "__tsan_read_write16",
"__tsan_atomic8_load",
"__tsan_atomic16_load",
"__tsan_atomic32_load",
-- 
2.28.0.rc0.142.g3c755180ce-goog

[PATCH v2 8/8] locking/atomics: Use read-write instrumentation for atomic RMWs

Use instrument_atomic_read_write() for atomic RMW ops.

Signed-off-by: Marco Elver 
---
v2:
* Update inline comment.
---
 include/asm-generic/atomic-instrumented.h | 330 +++---
 scripts/atomic/gen-atomic-instrumented.sh |  21 +-
 2 files changed, 180 insertions(+), 171 deletions(-)

diff --git a/include/asm-generic/atomic-instrumented.h 
b/include/asm-generic/atomic-instrumented.h
index 379986e40159..cd223b68b69d 100644
--- a/include/asm-generic/atomic-instrumented.h
+++ b/include/asm-generic/atomic-instrumented.h
@@ -60,7 +60,7 @@ atomic_set_release(atomic_t *v, int i)
 static __always_inline void
 atomic_add(int i, atomic_t *v)
 {
-   instrument_atomic_write(v, sizeof(*v));
+   instrument_atomic_read_write(v, sizeof(*v));
arch_atomic_add(i, v);
 }
 #define atomic_add atomic_add
@@ -69,7 +69,7 @@ atomic_add(int i, atomic_t *v)
 static __always_inline int
 atomic_add_return(int i, atomic_t *v)
 {
-   instrument_atomic_write(v, sizeof(*v));
+   instrument_atomic_read_write(v, sizeof(*v));
return arch_atomic_add_return(i, v);
 }
 #define atomic_add_return atomic_add_return
@@ -79,7 +79,7 @@ atomic_add_return(int i, atomic_t *v)
 static __always_inline int
 atomic_add_return_acquire(int i, atomic_t *v)
 {
-   instrument_atomic_write(v, sizeof(*v));
+   instrument_atomic_read_write(v, sizeof(*v));
return arch_atomic_add_return_acquire(i, v);
 }
 #define atomic_add_return_acquire atomic_add_return_acquire
@@ -89,7 +89,7 @@ atomic_add_return_acquire(int i, atomic_t *v)
 static __always_inline int
 atomic_add_return_release(int i, atomic_t *v)
 {
-   instrument_atomic_write(v, sizeof(*v));
+   instrument_atomic_read_write(v, sizeof(*v));
return arch_atomic_add_return_release(i, v);
 }
 #define atomic_add_return_release atomic_add_return_release
@@ -99,7 +99,7 @@ atomic_add_return_release(int i, atomic_t *v)
 static __always_inline int
 atomic_add_return_relaxed(int i, atomic_t *v)
 {
-   instrument_atomic_write(v, sizeof(*v));
+   instrument_atomic_read_write(v, sizeof(*v));
return arch_atomic_add_return_relaxed(i, v);
 }
 #define atomic_add_return_relaxed atomic_add_return_relaxed
@@ -109,7 +109,7 @@ atomic_add_return_relaxed(int i, atomic_t *v)
 static __always_inline int
 atomic_fetch_add(int i, atomic_t *v)
 {
-   instrument_atomic_write(v, sizeof(*v));
+   instrument_atomic_read_write(v, sizeof(*v));
return arch_atomic_fetch_add(i, v);
 }
 #define atomic_fetch_add atomic_fetch_add
@@ -119,7 +119,7 @@ atomic_fetch_add(int i, atomic_t *v)
 static __always_inline int
 atomic_fetch_add_acquire(int i, atomic_t *v)
 {
-   instrument_atomic_write(v, sizeof(*v));
+   instrument_atomic_read_write(v, sizeof(*v));
return arch_atomic_fetch_add_acquire(i, v);
 }
 #define atomic_fetch_add_acquire atomic_fetch_add_acquire
@@ -129,7 +129,7 @@ atomic_fetch_add_acquire(int i, atomic_t *v)
 static __always_inline int
 atomic_fetch_add_release(int i, atomic_t *v)
 {
-   instrument_atomic_write(v, sizeof(*v));
+   instrument_atomic_read_write(v, sizeof(*v));
return arch_atomic_fetch_add_release(i, v);
 }
 #define atomic_fetch_add_release atomic_fetch_add_release
@@ -139,7 +139,7 @@ atomic_fetch_add_release(int i, atomic_t *v)
 static __always_inline int
 atomic_fetch_add_relaxed(int i, atomic_t *v)
 {
-   instrument_atomic_write(v, sizeof(*v));
+   instrument_atomic_read_write(v, sizeof(*v));
return arch_atomic_fetch_add_relaxed(i, v);
 }
 #define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
@@ -148,7 +148,7 @@ atomic_fetch_add_relaxed(int i, atomic_t *v)
 static __always_inline void
 atomic_sub(int i, atomic_t *v)
 {
-   instrument_atomic_write(v, sizeof(*v));
+   instrument_atomic_read_write(v, sizeof(*v));
arch_atomic_sub(i, v);
 }
 #define atomic_sub atomic_sub
@@ -157,7 +157,7 @@ atomic_sub(int i, atomic_t *v)
 static __always_inline int
 atomic_sub_return(int i, atomic_t *v)
 {
-   instrument_atomic_write(v, sizeof(*v));
+   instrument_atomic_read_write(v, sizeof(*v));
return arch_atomic_sub_return(i, v);
 }
 #define atomic_sub_return atomic_sub_return
@@ -167,7 +167,7 @@ atomic_sub_return(int i, atomic_t *v)
 static __always_inline int
 atomic_sub_return_acquire(int i, atomic_t *v)
 {
-   instrument_atomic_write(v, sizeof(*v));
+   instrument_atomic_read_write(v, sizeof(*v));
return arch_atomic_sub_return_acquire(i, v);
 }
 #define atomic_sub_return_acquire atomic_sub_return_acquire
@@ -177,7 +177,7 @@ atomic_sub_return_acquire(int i, atomic_t *v)
 static __always_inline int
 atomic_sub_return_release(int i, atomic_t *v)
 {
-   instrument_atomic_write(v, sizeof(*v));
+   instrument_atomic_read_write(v, sizeof(*v));
return arch_atomic_sub_return_release(i, v);
 }
 #define atomic_sub_return_release atomic_sub_return_release
@@ -187,7 +187,7 @@ atomic_sub_return_release(int i, atomic_t *v)
 static

[PATCH v2 5/8] kcsan: Test support for compound instrumentation

Changes kcsan-test module to support checking reports that include
compound instrumentation. Since we should not fail the test if this
support is unavailable, we have to add a config variable that the test
can use to decide what to check for.

Signed-off-by: Marco Elver 
---
v2:
* Fix CC_HAS_TSAN_COMPOUND_READ_BEFORE_WRITE: s/--param -tsan/--param tsan/
---
 kernel/kcsan/kcsan-test.c | 65 ++-
 lib/Kconfig.kcsan |  5 +++
 2 files changed, 56 insertions(+), 14 deletions(-)

diff --git a/kernel/kcsan/kcsan-test.c b/kernel/kcsan/kcsan-test.c
index 721180cbbab1..ebe7fd245104 100644
--- a/kernel/kcsan/kcsan-test.c
+++ b/kernel/kcsan/kcsan-test.c
@@ -27,6 +27,12 @@
 #include 
 #include 
 
+#ifdef CONFIG_CC_HAS_TSAN_COMPOUND_READ_BEFORE_WRITE
+#define __KCSAN_ACCESS_RW(alt) (KCSAN_ACCESS_COMPOUND | KCSAN_ACCESS_WRITE)
+#else
+#define __KCSAN_ACCESS_RW(alt) (alt)
+#endif
+
 /* Points to current test-case memory access "kernels". */
 static void (*access_kernels[2])(void);
 
@@ -186,20 +192,21 @@ static bool report_matches(const struct expect_report *r)
 
/* Access 1 & 2 */
for (i = 0; i < 2; ++i) {
+   const int ty = r->access[i].type;
const char *const access_type =
-   (r->access[i].type & KCSAN_ACCESS_ASSERT) ?
-   ((r->access[i].type & KCSAN_ACCESS_WRITE) ?
-"assert no accesses" :
-"assert no writes") :
-   ((r->access[i].type & KCSAN_ACCESS_WRITE) ?
-"write" :
-"read");
+   (ty & KCSAN_ACCESS_ASSERT) ?
+ ((ty & KCSAN_ACCESS_WRITE) ?
+  "assert no accesses" :
+  "assert no writes") :
+ ((ty & KCSAN_ACCESS_WRITE) ?
+  ((ty & KCSAN_ACCESS_COMPOUND) ?
+   "read-write" :
+   "write") :
+  "read");
const char *const access_type_aux =
-   (r->access[i].type & KCSAN_ACCESS_ATOMIC) ?
-   " (marked)" :
-   ((r->access[i].type & KCSAN_ACCESS_SCOPED) ?
-" (scoped)" :
-"");
+   (ty & KCSAN_ACCESS_ATOMIC) ?
+ " (marked)" :
+ ((ty & KCSAN_ACCESS_SCOPED) ? " (scoped)" 
: "");
 
if (i == 1) {
/* Access 2 */
@@ -277,6 +284,12 @@ static noinline void test_kernel_write_atomic(void)
WRITE_ONCE(test_var, READ_ONCE_NOCHECK(test_sink) + 1);
 }
 
+static noinline void test_kernel_atomic_rmw(void)
+{
+   /* Use builtin, so we can set up the "bad" atomic/non-atomic scenario. 
*/
+   __atomic_fetch_add(_var, 1, __ATOMIC_RELAXED);
+}
+
 __no_kcsan
 static noinline void test_kernel_write_uninstrumented(void) { test_var++; }
 
@@ -439,8 +452,8 @@ static void test_concurrent_races(struct kunit *test)
const struct expect_report expect = {
.access = {
/* NULL will match any address. */
-   { test_kernel_rmw_array, NULL, 0, KCSAN_ACCESS_WRITE },
-   { test_kernel_rmw_array, NULL, 0, 0 },
+   { test_kernel_rmw_array, NULL, 0, 
__KCSAN_ACCESS_RW(KCSAN_ACCESS_WRITE) },
+   { test_kernel_rmw_array, NULL, 0, __KCSAN_ACCESS_RW(0) 
},
},
};
static const struct expect_report never = {
@@ -629,6 +642,29 @@ static void test_read_plain_atomic_write(struct kunit 
*test)
KUNIT_EXPECT_TRUE(test, match_expect);
 }
 
+/* Test that atomic RMWs generate correct report. */
+__no_kcsan
+static void test_read_plain_atomic_rmw(struct kunit *test)
+{
+   const struct expect_report expect = {
+   .access = {
+   { test_kernel_read, _var, sizeof(test_var), 0 },
+   { test_kernel_atomic_rmw, _var, sizeof(test_var),
+   KCSAN_ACCESS_COMPOUND | KCSAN_ACCESS_WRITE | 
KCSAN_ACCESS_ATOMIC },
+   },
+   };
+   bool match_expect = false;
+
+   if (IS_ENABLED(CONFIG_KCSAN_IGNORE_ATOMICS))
+   return;
+
+   begin_test_checks(test_kernel_read, test_kernel_atomic_rmw);
+   do {
+   match_expect = report_matches();
+   } while (!end_test_checks(match_expect));
+   KUNIT_EXPECT_TRUE(test, match_expect);
+}
+
 /* Zero-sized accesses should never cause data race reports. */

[PATCH v5 03/16] dt-bindings: pinctrl: sunxi: Get rid of continual nesting

From: Yangtao Li 

Rather than a continual nesting of 'else' clauses, just make
each 'if' a new entry under 'allOf' and get rid of the else.

Signed-off-by: Yangtao Li 
Reviewed-by: Rob Herring 
---
 .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml  | 124 ++
 1 file changed, 68 insertions(+), 56 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml 
b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index 7556be6e2754..35a26abb02e7 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -155,62 +155,74 @@ allOf:
   minItems: 5
   maxItems: 5
 
-else:
-  if:
-properties:
-  compatible:
-enum:
-  - allwinner,sun6i-a31-pinctrl
-  - allwinner,sun6i-a31s-pinctrl
-  - allwinner,sun50i-h6-pinctrl
-
-  then:
-properties:
-  interrupts:
-minItems: 4
-maxItems: 4
-
-  else:
-if:
-  properties:
-compatible:
-  enum:
-- allwinner,sun8i-a23-pinctrl
-- allwinner,sun8i-a83t-pinctrl
-- allwinner,sun50i-a64-pinctrl
-- allwinner,sun50i-h5-pinctrl
-- allwinner,suniv-f1c100s-pinctrl
-
-then:
-  properties:
-interrupts:
-  minItems: 3
-  maxItems: 3
-
-else:
-  if:
-properties:
-  compatible:
-enum:
-  - allwinner,sun6i-a31-r-pinctrl
-  - allwinner,sun8i-a33-pinctrl
-  - allwinner,sun8i-h3-pinctrl
-  - allwinner,sun8i-v3-pinctrl
-  - allwinner,sun8i-v3s-pinctrl
-  - allwinner,sun9i-a80-r-pinctrl
-  - allwinner,sun50i-h6-r-pinctrl
-
-  then:
-properties:
-  interrupts:
-minItems: 2
-maxItems: 2
-
-  else:
-properties:
-  interrupts:
-minItems: 1
-maxItems: 1
+  - if:
+  properties:
+compatible:
+  enum:
+- allwinner,sun6i-a31-pinctrl
+- allwinner,sun6i-a31s-pinctrl
+- allwinner,sun50i-h6-pinctrl
+
+then:
+  properties:
+interrupts:
+  minItems: 4
+  maxItems: 4
+
+  - if:
+  properties:
+compatible:
+  enum:
+- allwinner,sun8i-a23-pinctrl
+- allwinner,sun8i-a83t-pinctrl
+- allwinner,sun50i-a64-pinctrl
+- allwinner,sun50i-h5-pinctrl
+- allwinner,suniv-f1c100s-pinctrl
+
+then:
+  properties:
+interrupts:
+  minItems: 3
+  maxItems: 3
+
+  - if:
+  properties:
+compatible:
+  enum:
+- allwinner,sun6i-a31-r-pinctrl
+- allwinner,sun8i-a33-pinctrl
+- allwinner,sun8i-h3-pinctrl
+- allwinner,sun8i-v3-pinctrl
+- allwinner,sun8i-v3s-pinctrl
+- allwinner,sun9i-a80-r-pinctrl
+- allwinner,sun50i-h6-r-pinctrl
+
+then:
+  properties:
+interrupts:
+  minItems: 2
+  maxItems: 2
+
+  - if:
+  properties:
+compatible:
+  enum:
+- allwinner,sun4i-a10-pinctrl
+- allwinner,sun5i-a10s-pinctrl
+- allwinner,sun5i-a13-pinctrl
+- allwinner,sun7i-a20-pinctrl
+- allwinner,sun8i-a23-r-pinctrl
+- allwinner,sun8i-a83t-r-pinctrl
+- allwinner,sun8i-h3-r-pinctrl
+- allwinner,sun8i-r40-pinctrl
+- allwinner,sun50i-a64-r-pinctrl
+- nextthing,gr8-pinctrl
+
+then:
+  properties:
+interrupts:
+  minItems: 1
+  maxItems: 1
 
 additionalProperties: false
 
-- 
2.24.0

Re: [PATCH v5 0/6] arch/x86: kprobes: Remove MODULES dependency

2020-07-24 Thread Jarkko Sakkinen

On Fri, Jul 24, 2020 at 08:05:47AM +0300, Jarkko Sakkinen wrote:
> Remove MODULES dependency by migrating from module_alloc() to the new
> text_alloc() API. Essentially these changes provide preliminaries for
> allowing to compile a static kernel with a proper tracing support.
> 
> The same API can be used later on in other sites that allocate space for
> trampolines, and trivially scaled to other arch's. An arch can inform
> with CONFIG_ARCH_HAS_TEXT_ALLOC that it's providing implementation for
> text_alloc().
> 
> Cc: linux...@kvack.org
> Cc: Andi Kleen 
> Cc: Masami Hiramatsu 
> Cc: Peter Zijlstra 
> 
> v4:
> * Squash lock_modules() patches into one.
> * Remove fallback versions of text_alloc() and text_free(). Instead, use
>   ARCH_HAS_TEXT_ALLOC at site when required.
> * Use lockdep_assert_irqs_enabled() in text_free() instead of
>   WARN_ON(in_interrupt()).
> 
> v3:
> * Make text_alloc() API disjoint.
> * Remove all the possible extra clutter not absolutely required and
>   split into more logical pieces.
> 
> Jarkko Sakkinen (6):
>   kprobes: Remove dependency to the module_mutex
>   vmalloc: Add text_alloc() and text_free()
>   arch/x86: Implement text_alloc() and text_free()
>   arch/x86: kprobes: Use text_alloc() and text_free()
>   kprobes: Use text_alloc() and text_free()
>   kprobes: Remove CONFIG_MODULES dependency
> 
>  arch/Kconfig   |  2 +-
>  arch/x86/Kconfig   |  3 ++
>  arch/x86/kernel/Makefile   |  1 +
>  arch/x86/kernel/kprobes/core.c |  4 +--
>  arch/x86/kernel/text_alloc.c   | 41 +++
>  include/linux/module.h | 32 ++
>  include/linux/vmalloc.h| 17 ++
>  kernel/kprobes.c   | 61 +++---
>  kernel/trace/trace_kprobe.c| 20 ---
>  9 files changed, 147 insertions(+), 34 deletions(-)
>  create mode 100644 arch/x86/kernel/text_alloc.c
> 
> -- 
> 2.25.1
> 

Duplicates were caused by Internet connection breaking up in the
middle. Apologies.

/Jarkko

[PATCH v5 04/16] dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings

From: Yangtao Li 

Add device tree binding Documentation details for A100 pinctrl driver,
which has a r pin controller and a pin controller with more irq lines.

Signed-off-by: Yangtao Li 
Reviewed-by: Rob Herring 
---
 .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml  | 15 +++
 1 file changed, 15 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml 
b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index 35a26abb02e7..34a17d5c6135 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -48,6 +48,8 @@ properties:
   - allwinner,sun9i-a80-r-pinctrl
   - allwinner,sun50i-a64-pinctrl
   - allwinner,sun50i-a64-r-pinctrl
+  - allwinner,sun50i-a100-pinctrl
+  - allwinner,sun50i-a100-r-pinctrl
   - allwinner,sun50i-h5-pinctrl
   - allwinner,sun50i-h6-pinctrl
   - allwinner,sun50i-h6-r-pinctrl
@@ -143,6 +145,18 @@ allOf:
   # boards are defining it at the moment so it would generate a lot of
   # warnings.
 
+  - if:
+  properties:
+compatible:
+  enum:
+- allwinner,sun50i-a100-pinctrl
+
+then:
+  properties:
+interrupts:
+  minItems: 7
+  maxItems: 7
+
   - if:
   properties:
 compatible:
@@ -216,6 +230,7 @@ allOf:
 - allwinner,sun8i-h3-r-pinctrl
 - allwinner,sun8i-r40-pinctrl
 - allwinner,sun50i-a64-r-pinctrl
+- allwinner,sun50i-a100-r-pinctrl
 - nextthing,gr8-pinctrl
 
 then:
-- 
2.24.0

Re: [PATCH 3/4] watchdog: mt8192: add wdt support

2020-07-24 Thread Crystal Guo

On Fri, 2020-07-24 at 06:00 +0800, Matthias Brugger wrote:
> 
> On 23/07/2020 11:07, Seiya Wang wrote:
> > From: Crystal Guo 
> > 
> > add driver setting to support mt8192 wdt
> > 
> > Signed-off-by: Crystal Guo 
> > ---
> >   drivers/watchdog/mtk_wdt.c | 5 +
> >   1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
> > index d6a6393f609d..ad23596170af 100644
> > --- a/drivers/watchdog/mtk_wdt.c
> > +++ b/drivers/watchdog/mtk_wdt.c
> > @@ -76,6 +76,10 @@ static const struct mtk_wdt_data mt8183_data = {
> > .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
> >   };
> >   
> > +static const struct mtk_wdt_data mt8192_data = {
> > +   .toprgu_sw_rst_num = 23,
> 
> Should be defined in include/dt-bindings/reset-controller/mt8192-resets.h

mt8xxx-resets.h actually just used to define TOPRGU_SW_RST_NUM, may be
it's more easier to maintain by define it at OF data directly, instead
of resubmit the mt8xxx-reset.h and add
"include/dt-bindings/reset-controller/mt8xxx-resets.h" at mtk_wdt.c.

Regards
Crystal Guo

> 
> > +};
> > +
> >   static int toprgu_reset_update(struct reset_controller_dev *rcdev,
> >unsigned long id, bool assert)
> >   {
> > @@ -322,6 +326,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = {
> > { .compatible = "mediatek,mt2712-wdt", .data = _data },
> > { .compatible = "mediatek,mt6589-wdt" },
> > { .compatible = "mediatek,mt8183-wdt", .data = _data },
> > +   { .compatible = "mediatek,mt8192-wdt", .data = _data },
> > { /* sentinel */ }
> >   };
> >   MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
> >

Re: [PATCH v7 3/3] arm64: implement KPROBES_ON_FTRACE

2020-07-24 Thread Jisheng Zhang

On Tue, 21 Jul 2020 22:24:55 +0900 Masami Hiramatsu wrote:

> 
> 
> Hi Jisheng,

Hi,

> 
> Would you be still working on this series?

I will rebase the implementation on the latest code, then try to address
your comments and Mark's comments. I will send out patches in this weekend.

> 
> If you are still want to put a probe on func+4, it is OK if you can
> completely emulate the 1st instruction. (lr save on the stack and
> change the regs->sp)

Will check which is the better solution.

Thank you very much

Re: [PATCH v3 02/10] powerpc/smp: Merge Power9 topology with Power topology

On Thu, Jul 23, 2020 at 02:21:08PM +0530, Srikar Dronamraju wrote:
> A new sched_domain_topology_level was added just for Power9. However the
> same can be achieved by merging powerpc_topology with power9_topology
> and makes the code more simpler especially when adding a new sched
> domain.
> 
> Cc: linuxppc-dev 
> Cc: LKML 
> Cc: Michael Ellerman 
> Cc: Nicholas Piggin 
> Cc: Anton Blanchard 
> Cc: Oliver O'Halloran 
> Cc: Nathan Lynch 
> Cc: Michael Neuling 
> Cc: Gautham R Shenoy 
> Cc: Ingo Molnar 
> Cc: Peter Zijlstra 
> Cc: Valentin Schneider 
> Cc: Jordan Niethe 
> Signed-off-by: Srikar Dronamraju 

LGTM.


Reviewed-by: Gautham R. Shenoy 

> ---
> Changelog v1 -> v2:
>   Replaced a reference to cpu_smt_mask with per_cpu(cpu_sibling_map, cpu)
>   since cpu_smt_mask is only defined under CONFIG_SCHED_SMT
> 
>  arch/powerpc/kernel/smp.c | 33 ++---
>  1 file changed, 10 insertions(+), 23 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
> index edf94ca64eea..283a04e54f52 100644
> --- a/arch/powerpc/kernel/smp.c
> +++ b/arch/powerpc/kernel/smp.c
> @@ -1313,7 +1313,7 @@ int setup_profiling_timer(unsigned int multiplier)
>  }
> 
>  #ifdef CONFIG_SCHED_SMT
> -/* cpumask of CPUs with asymetric SMT dependancy */
> +/* cpumask of CPUs with asymmetric SMT dependency */
>  static int powerpc_smt_flags(void)
>  {
>   int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES;
> @@ -1326,14 +1326,6 @@ static int powerpc_smt_flags(void)
>  }
>  #endif
> 
> -static struct sched_domain_topology_level powerpc_topology[] = {
> -#ifdef CONFIG_SCHED_SMT
> - { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) },
> -#endif
> - { cpu_cpu_mask, SD_INIT_NAME(DIE) },
> - { NULL, },
> -};
> -
>  /*
>   * P9 has a slightly odd architecture where pairs of cores share an L2 cache.
>   * This topology makes it *much* cheaper to migrate tasks between adjacent 
> cores
> @@ -1351,7 +1343,13 @@ static int powerpc_shared_cache_flags(void)
>   */
>  static const struct cpumask *shared_cache_mask(int cpu)
>  {
> - return cpu_l2_cache_mask(cpu);
> + if (shared_caches)
> + return cpu_l2_cache_mask(cpu);
> +
> + if (has_big_cores)
> + return cpu_smallcore_mask(cpu);
> +
> + return per_cpu(cpu_sibling_map, cpu);
>  }
> 
>  #ifdef CONFIG_SCHED_SMT
> @@ -1361,7 +1359,7 @@ static const struct cpumask *smallcore_smt_mask(int cpu)
>  }
>  #endif
> 
> -static struct sched_domain_topology_level power9_topology[] = {
> +static struct sched_domain_topology_level powerpc_topology[] = {
>  #ifdef CONFIG_SCHED_SMT
>   { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) },
>  #endif
> @@ -1386,21 +1384,10 @@ void __init smp_cpus_done(unsigned int max_cpus)
>  #ifdef CONFIG_SCHED_SMT
>   if (has_big_cores) {
>   pr_info("Big cores detected but using small core scheduling\n");
> - power9_topology[0].mask = smallcore_smt_mask;
>   powerpc_topology[0].mask = smallcore_smt_mask;
>   }
>  #endif
> - /*
> -  * If any CPU detects that it's sharing a cache with another CPU then
> -  * use the deeper topology that is aware of this sharing.
> -  */
> - if (shared_caches) {
> - pr_info("Using shared cache scheduler topology\n");
> - set_sched_topology(power9_topology);
> - } else {
> - pr_info("Using standard scheduler topology\n");
> - set_sched_topology(powerpc_topology);
> - }
> + set_sched_topology(powerpc_topology);
>  }
> 
>  #ifdef CONFIG_HOTPLUG_CPU
> -- 
> 2.18.2
>

[PATCH v5 05/16] pinctrl: sunxi: add support for the Allwinner A100 pin controller

From: Yangtao Li 

This commit introduces support for the pin controller on A100.

Signed-off-by: Yangtao Li 
---
 drivers/pinctrl/sunxi/Kconfig |  10 +
 drivers/pinctrl/sunxi/Makefile|   2 +
 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c | 105 +++
 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c   | 708 ++
 4 files changed, 825 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f7aae200ee15..593293584ecc 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -94,6 +94,16 @@ config PINCTRL_SUN50I_A64_R
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
 
+config PINCTRL_SUN50I_A100
+   bool "Support for the Allwinner A100 PIO"
+   default ARM64 && ARCH_SUNXI
+   select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A100_R
+   bool "Support for the Allwinner A100 R-PIO"
+   default ARM64 && ARCH_SUNXI
+   select PINCTRL_SUNXI
+
 config PINCTRL_SUN50I_H5
bool "Support for the Allwinner H5 PIO"
default ARM64 && ARCH_SUNXI
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index fafcdae8134f..8b7ff0dc3bdf 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -13,6 +13,8 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
 obj-$(CONFIG_PINCTRL_SUN50I_A64)   += pinctrl-sun50i-a64.o
 obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o
+obj-$(CONFIG_PINCTRL_SUN50I_A100)  += pinctrl-sun50i-a100.o
+obj-$(CONFIG_PINCTRL_SUN50I_A100_R)+= pinctrl-sun50i-a100-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)   += pinctrl-sun8i-a83t.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c 
b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
new file mode 100644
index ..21054fcacd34
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Yangtao Li 
+ *
+ * Based on:
+ * huangshuosheng 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin a100_r_pins[] = {
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c0"),/* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c0"),/* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart0"),   /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart0"),   /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c1"),/* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+ SUNXI_FUNCTION(0x0,

Re: [PATCH v3 04/10] powerpc/smp: Move topology fixups into a new function

On Thu, Jul 23, 2020 at 02:21:10PM +0530, Srikar Dronamraju wrote:
> Move topology fixup based on the platform attributes into its own
> function which is called just before set_sched_topology.
> 
> Cc: linuxppc-dev 
> Cc: LKML 
> Cc: Michael Ellerman 
> Cc: Nicholas Piggin 
> Cc: Anton Blanchard 
> Cc: Oliver O'Halloran 
> Cc: Nathan Lynch 
> Cc: Michael Neuling 
> Cc: Gautham R Shenoy 
> Cc: Ingo Molnar 
> Cc: Peter Zijlstra 
> Cc: Valentin Schneider 
> Cc: Jordan Niethe 
> Signed-off-by: Srikar Dronamraju 


Reviewed-by: Gautham R. Shenoy 
> ---
> Changelog v2 -> v3:
>   Rewrote changelog (Gautham)
>   Renamed to powerpc/smp: Move topology fixups into  a new function
> 
>  arch/powerpc/kernel/smp.c | 17 +++--
>  1 file changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
> index a685915e5941..da27f6909be1 100644
> --- a/arch/powerpc/kernel/smp.c
> +++ b/arch/powerpc/kernel/smp.c
> @@ -1368,6 +1368,16 @@ int setup_profiling_timer(unsigned int multiplier)
>   return 0;
>  }
> 
> +static void fixup_topology(void)
> +{
> +#ifdef CONFIG_SCHED_SMT
> + if (has_big_cores) {
> + pr_info("Big cores detected but using small core scheduling\n");
> + powerpc_topology[0].mask = smallcore_smt_mask;
> + }
> +#endif
> +}
> +
>  void __init smp_cpus_done(unsigned int max_cpus)
>  {
>   /*
> @@ -1381,12 +1391,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
> 
>   dump_numa_cpu_topology();
> 
> -#ifdef CONFIG_SCHED_SMT
> - if (has_big_cores) {
> - pr_info("Big cores detected but using small core scheduling\n");
> - powerpc_topology[0].mask = smallcore_smt_mask;
> - }
> -#endif
> + fixup_topology();
>   set_sched_topology(powerpc_topology);
>  }
> 
> -- 
> 2.18.2
>

Re: [PATCH] regulator: fix memory leak on error path of regulator_register()

2020-07-24 Thread Markus Elfring

> … introduced as a side ef another …

Would the following wording variant be more appropriate?

  … introduced as a side effect of another …


How do you think about to replace the wording “…, I believe …”
by an imperative description?

Regards,
Markus

[PATCH v5 06/16] dt-bindings: nvmem: SID: add binding for A100's SID controller

From: Yangtao Li 

Add a binding for A100's SID controller.

Signed-off-by: Yangtao Li 
Reviewed-by: Rob Herring 
---
 .../nvmem/allwinner,sun4i-a10-sid.yaml| 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml 
b/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml
index daf1321d76ad..6687ab720304 100644
--- a/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml
+++ b/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml
@@ -15,14 +15,17 @@ allOf:
 
 properties:
   compatible:
-enum:
-  - allwinner,sun4i-a10-sid
-  - allwinner,sun7i-a20-sid
-  - allwinner,sun8i-a83t-sid
-  - allwinner,sun8i-h3-sid
-  - allwinner,sun50i-a64-sid
-  - allwinner,sun50i-h5-sid
-  - allwinner,sun50i-h6-sid
+oneOf:
+  - const: allwinner,sun4i-a10-sid
+  - const: allwinner,sun7i-a20-sid
+  - const: allwinner,sun8i-a83t-sid
+  - const: allwinner,sun8i-h3-sid
+  - const: allwinner,sun50i-a64-sid
+  - items:
+  - const: allwinner,sun50i-a100-sid
+  - const: allwinner,sun50i-a64-sid
+  - const: allwinner,sun50i-h5-sid
+  - const: allwinner,sun50i-h6-sid
 
   reg:
 maxItems: 1
-- 
2.24.0

Re: [PATCH v2 05/10] powerpc/smp: Dont assume l2-cache to be superset of sibling

On Wed, Jul 22, 2020 at 12:27:47PM +0530, Srikar Dronamraju wrote:
> * Gautham R Shenoy  [2020-07-22 11:51:14]:
> 
> > Hi Srikar,
> > 
> > > diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
> > > index 72f16dc0cb26..57468877499a 100644
> > > --- a/arch/powerpc/kernel/smp.c
> > > +++ b/arch/powerpc/kernel/smp.c
> > > @@ -1196,6 +1196,7 @@ static bool update_mask_by_l2(int cpu, struct 
> > > cpumask *(*mask_fn)(int))
> > >   if (!l2_cache)
> > >   return false;
> > > 
> > > + cpumask_set_cpu(cpu, mask_fn(cpu));
> > 
> > 
> > Ok, we need to do this because "cpu" is not yet set in the
> > cpu_online_mask. Prior to your patch the "cpu" was getting set in
> > cpu_l2_cache_map(cpu) as a side-effect of the code that is removed in
> > the patch.
> > 
> 
> Right.
> 
> > 
> > >   for_each_cpu(i, cpu_online_mask) {
> > >   /*
> > >* when updating the marks the current CPU has not been marked
> > > @@ -1278,29 +1279,30 @@ static void add_cpu_to_masks(int cpu)
> > >* add it to it's own thread sibling mask.
> > >*/
> > >   cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
> > > + cpumask_set_cpu(cpu, cpu_core_mask(cpu));
> 
> Note: Above, we are explicitly setting the cpu_core_mask.

You are right. I missed this.

> 
> > > 
> > >   for (i = first_thread; i < first_thread + threads_per_core; i++)
> > >   if (cpu_online(i))
> > >   set_cpus_related(i, cpu, cpu_sibling_mask);
> > > 
> > >   add_cpu_to_smallcore_masks(cpu);
> > > - /*
> > > -  * Copy the thread sibling mask into the cache sibling mask
> > > -  * and mark any CPUs that share an L2 with this CPU.
> > > -  */
> > > - for_each_cpu(i, cpu_sibling_mask(cpu))
> > > - set_cpus_related(cpu, i, cpu_l2_cache_mask);
> > >   update_mask_by_l2(cpu, cpu_l2_cache_mask);
> > > 
> > > - /*
> > > -  * Copy the cache sibling mask into core sibling mask and mark
> > > -  * any CPUs on the same chip as this CPU.
> > > -  */
> > > - for_each_cpu(i, cpu_l2_cache_mask(cpu))
> > > - set_cpus_related(cpu, i, cpu_core_mask);
> > > + if (pkg_id == -1) {
> > 
> > I suppose this "if" condition is an optimization, since if pkg_id != -1,
> > we anyway set these CPUs in the cpu_core_mask below.
> > 
> > However...
> 
> This is not just an optimization.
> The hunk removed would only work if cpu_l2_cache_mask is bigger than
> cpu_sibling_mask. (this was the previous assumption that we want to break)
> If the cpu_sibling_mask is bigger than cpu_l2_cache_mask and pkg_id is -1,
> then setting only cpu_l2_cache_mask in cpu_core_mask will result in a broken 
> topology.
> 
> > 
> > > + struct cpumask *(*mask)(int) = cpu_sibling_mask;
> > > +
> > > + /*
> > > +  * Copy the sibling mask into core sibling mask and
> > > +  * mark any CPUs on the same chip as this CPU.
> > > +  */
> > > + if (shared_caches)
> > > + mask = cpu_l2_cache_mask;
> > > +
> > > + for_each_cpu(i, mask(cpu))
> > > + set_cpus_related(cpu, i, cpu_core_mask);
> > > 
> > > - if (pkg_id == -1)
> > >   return;
> > > + }
> > 
> > 
> > ... since "cpu" is not yet set in the cpu_online_mask, do we not miss 
> > setting
> > "cpu" in the cpu_core_mask(cpu) in the for-loop below ?
> > 
> > 
> 
> As noted above, we are setting before. So we don't missing the cpu and hence
> have not different from before.


Fair enough.

> 
> > --
> > Thanks and Regards
> > gautham.
> 
> -- 
> Thanks and Regards
> Srikar Dronamraju

[PATCH v5 07/16] dt-bindings: thermal: sun8i: Add binding for A100's THS controller

From: Yangtao Li 

Add a binding for A100's ths controller.

Signed-off-by: Yangtao Li 
Reviewed-by: Rob Herring 
---
 .../bindings/thermal/allwinner,sun8i-a83t-ths.yaml  | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git 
a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml 
b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
index 87369264feb9..9d40fc7ff6fd 100644
--- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
+++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
@@ -17,6 +17,7 @@ properties:
   - allwinner,sun8i-h3-ths
   - allwinner,sun8i-r40-ths
   - allwinner,sun50i-a64-ths
+  - allwinner,sun50i-a100-ths
   - allwinner,sun50i-h5-ths
   - allwinner,sun50i-h6-ths
 
@@ -61,7 +62,9 @@ allOf:
   properties:
 compatible:
   contains:
-const: allwinner,sun50i-h6-ths
+enum:
+  - allwinner,sun50i-a100-ths
+  - allwinner,sun50i-h6-ths
 
 then:
   properties:
@@ -103,6 +106,7 @@ allOf:
   - const: allwinner,sun8i-h3-ths
   - const: allwinner,sun8i-r40-ths
   - const: allwinner,sun50i-a64-ths
+  - const: allwinner,sun50i-a100-ths
   - const: allwinner,sun50i-h5-ths
   - const: allwinner,sun50i-h6-ths
 
-- 
2.24.0

Re: [PATCH v3 05/10] powerpc/smp: Dont assume l2-cache to be superset of sibling



On Thu, Jul 23, 2020 at 02:21:11PM +0530, Srikar Dronamraju wrote:
> Current code assumes that cpumask of cpus sharing a l2-cache mask will
> always be a superset of cpu_sibling_mask.
> 
> Lets stop that assumption. cpu_l2_cache_mask is a superset of
> cpu_sibling_mask if and only if shared_caches is set.
> 
> Cc: linuxppc-dev 
> Cc: LKML 
> Cc: Michael Ellerman 
> Cc: Nicholas Piggin 
> Cc: Anton Blanchard 
> Cc: Oliver O'Halloran 
> Cc: Nathan Lynch 
> Cc: Michael Neuling 
> Cc: Gautham R Shenoy 
> Cc: Ingo Molnar 
> Cc: Peter Zijlstra 
> Cc: Valentin Schneider 
> Cc: Jordan Niethe 
> Signed-off-by: Srikar Dronamraju 

Reviewed-by: Gautham R. Shenoy 

> ---
> Changelog v1 -> v2:
>   Set cpumask after verifying l2-cache. (Gautham)
> 
>  arch/powerpc/kernel/smp.c | 28 +++-
>  1 file changed, 15 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
> index da27f6909be1..d997c7411664 100644
> --- a/arch/powerpc/kernel/smp.c
> +++ b/arch/powerpc/kernel/smp.c
> @@ -1194,6 +1194,7 @@ static bool update_mask_by_l2(int cpu, struct cpumask 
> *(*mask_fn)(int))
>   if (!l2_cache)
>   return false;
> 
> + cpumask_set_cpu(cpu, mask_fn(cpu));
>   for_each_cpu(i, cpu_online_mask) {
>   /*
>* when updating the marks the current CPU has not been marked
> @@ -1276,29 +1277,30 @@ static void add_cpu_to_masks(int cpu)
>* add it to it's own thread sibling mask.
>*/
>   cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
> + cpumask_set_cpu(cpu, cpu_core_mask(cpu));
> 
>   for (i = first_thread; i < first_thread + threads_per_core; i++)
>   if (cpu_online(i))
>   set_cpus_related(i, cpu, cpu_sibling_mask);
> 
>   add_cpu_to_smallcore_masks(cpu);
> - /*
> -  * Copy the thread sibling mask into the cache sibling mask
> -  * and mark any CPUs that share an L2 with this CPU.
> -  */
> - for_each_cpu(i, cpu_sibling_mask(cpu))
> - set_cpus_related(cpu, i, cpu_l2_cache_mask);
>   update_mask_by_l2(cpu, cpu_l2_cache_mask);
> 
> - /*
> -  * Copy the cache sibling mask into core sibling mask and mark
> -  * any CPUs on the same chip as this CPU.
> -  */
> - for_each_cpu(i, cpu_l2_cache_mask(cpu))
> - set_cpus_related(cpu, i, cpu_core_mask);
> + if (pkg_id == -1) {
> + struct cpumask *(*mask)(int) = cpu_sibling_mask;
> +
> + /*
> +  * Copy the sibling mask into core sibling mask and
> +  * mark any CPUs on the same chip as this CPU.
> +  */
> + if (shared_caches)
> + mask = cpu_l2_cache_mask;
> +
> + for_each_cpu(i, mask(cpu))
> + set_cpus_related(cpu, i, cpu_core_mask);
> 
> - if (pkg_id == -1)
>   return;
> + }
> 
>   for_each_cpu(i, cpu_online_mask)
>   if (get_physical_package_id(i) == pkg_id)
> -- 
> 2.18.2
>

[PATCH v5 08/16] thermal: sun8i: add TEMP_CALIB_MASK for calibration data in sun50i_h6_ths_calibrate

From: Yangtao Li 

For sun50i_h6_ths_calibrate(), the data read from nvmem needs a round of
calculation. On the other hand, the newer SOC may store other data in
the space other than 12bit sensor data. Add mask operation to read data
to avoid conversion error.

Signed-off-by: Yangtao Li 
---
 drivers/thermal/sun8i_thermal.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index 74d73be16496..f423d44b9290 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -244,7 +244,7 @@ static int sun50i_h6_ths_calibrate(struct ths_device *tmdev,
ft_temp = (caldata[0] & FT_TEMP_MASK) * 100;
 
for (i = 0; i < tmdev->chip->sensor_num; i++) {
-   int sensor_reg = caldata[i + 1];
+   int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
int cdata, offset;
int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
 
-- 
2.24.0

[PATCH v5 09/16] thermal: sun8i: Add A100's THS controller support

From: Yangtao Li 

This patch add thermal sensor controller support for A100,
which is similar to the previous ones.

Signed-off-by: Yangtao Li 
---
 drivers/thermal/sun8i_thermal.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index f423d44b9290..f8b13071a6f4 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -590,6 +590,19 @@ static const struct ths_thermal_chip sun50i_a64_ths = {
.calc_temp = sun8i_ths_calc_temp,
 };
 
+static const struct ths_thermal_chip sun50i_a100_ths = {
+   .sensor_num = 3,
+   .has_bus_clk_reset = true,
+   .ft_deviation = 8000,
+   .offset = 187744,
+   .scale = 672,
+   .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
+   .calibrate = sun50i_h6_ths_calibrate,
+   .init = sun50i_h6_thermal_init,
+   .irq_ack = sun50i_h6_irq_ack,
+   .calc_temp = sun8i_ths_calc_temp,
+};
+
 static const struct ths_thermal_chip sun50i_h5_ths = {
.sensor_num = 2,
.has_mod_clk = true,
@@ -619,6 +632,7 @@ static const struct of_device_id of_ths_match[] = {
{ .compatible = "allwinner,sun8i-h3-ths", .data = _h3_ths },
{ .compatible = "allwinner,sun8i-r40-ths", .data = _r40_ths },
{ .compatible = "allwinner,sun50i-a64-ths", .data = _a64_ths },
+   { .compatible = "allwinner,sun50i-a100-ths", .data = _a100_ths },
{ .compatible = "allwinner,sun50i-h5-ths", .data = _h5_ths },
{ .compatible = "allwinner,sun50i-h6-ths", .data = _h6_ths },
{ /* sentinel */ },
-- 
2.24.0

[PATCH v5 10/16] mfd: axp20x: Allow the AXP803 to be probed by I2C

From: Yangtao Li 

The AXP803 can be used both using the RSB proprietary bus, or a more
traditional I2C bus.

Let's add that possibility.

Signed-off-by: Yangtao Li 
Acked-by: Chen-Yu Tsai 
---
 drivers/mfd/axp20x-i2c.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
index 14f9df74f855..446a7d0bbb47 100644
--- a/drivers/mfd/axp20x-i2c.c
+++ b/drivers/mfd/axp20x-i2c.c
@@ -63,6 +63,7 @@ static const struct of_device_id axp20x_i2c_of_match[] = {
{ .compatible = "x-powers,axp209", .data = (void *)AXP209_ID },
{ .compatible = "x-powers,axp221", .data = (void *)AXP221_ID },
{ .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
+   { .compatible = "x-powers,axp803", .data = (void *)AXP803_ID },
{ .compatible = "x-powers,axp806", .data = (void *)AXP806_ID },
{ },
 };
@@ -74,6 +75,7 @@ static const struct i2c_device_id axp20x_i2c_id[] = {
{ "axp209", 0 },
{ "axp221", 0 },
{ "axp223", 0 },
+   { "axp803", 0 },
{ "axp806", 0 },
{ },
 };
-- 
2.24.0

Re: [PATCH] tty: serial: qcom_geni_serial: To correct logic for QUP HW version

2020-07-24 Thread Greg Kroah-Hartman

On Fri, Jul 24, 2020 at 11:44:02AM +0530, Paras Sharma wrote:
> To correct the logic to detect whether the QUP HW version is greater
>  than 2.5.

The subject line and here does not make any sense.  Can you reword this
as what the problem is and why you need to change this?

> 
> Signed-off-by: Paras Sharma 
> ---
>  drivers/tty/serial/qcom_geni_serial.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/tty/serial/qcom_geni_serial.c 
> b/drivers/tty/serial/qcom_geni_serial.c
> index 1ed3d35..5b0efb49 100644
> --- a/drivers/tty/serial/qcom_geni_serial.c
> +++ b/drivers/tty/serial/qcom_geni_serial.c
> @@ -954,7 +954,8 @@ static void qcom_geni_serial_set_termios(struct uart_port 
> *uport,
>   sampling_rate = UART_OVERSAMPLING;
>   /* Sampling rate is halved for IP versions >= 2.5 */
>   ver = geni_se_get_qup_hw_version(>se);
> - if (GENI_SE_VERSION_MAJOR(ver) >= 2 && GENI_SE_VERSION_MINOR(ver) >= 5)
> + if ((GENI_SE_VERSION_MAJOR(ver) >= 2 && GENI_SE_VERSION_MINOR(ver) >= 5)
> + || GENI_SE_VERSION_MAJOR(ver) >= 3)

Odd coding style :(

Please fix all of the above up and resubmit a v2.

thanks,

greg k-h

[PATCH v2 1/2] perf tools: Fix record failure when mixed with ARM SPE event

When recording with cache-misses and arm_spe_x event, i found that
it will just fail without showing any error info if i put cache-misses
after 'arm_spe_x' event.

[root@localhost 0620]# perf record -e cache-misses -e \
arm_spe_0/ts_enable=1,pct_enable=1,pa_enable=1,load_filter=1,\
jitter=1,store_filter=1,min_latency=0/ sleep 1
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.067 MB perf.data ]
[root@localhost 0620]# perf record -e \
arm_spe_0/ts_enable=1,pct_enable=1,pa_enable=1,load_filter=1,jitter=1,\
store_filter=1,min_latency=0/ -e cache-misses sleep 1
[root@localhost 0620]#

The current code can only work if the only event to be traced is an
'arm_spe_x', or if it is the last event to be specified. Otherwise the
last event type will be checked against all the arm_spe_pmus[i]->types,
none will match and an out of bound 'i' index will be used in
arm_spe_recording_init().

We don't support concurrent multiple arm_spe_x events currently, that
is checked in arm_spe_recording_options(), and it will show the relevant
info. So add the check and record of the first found 'arm_spe_pmu' to
fix this issue here.

Fixes: ffd3d18c20b8d ("perf tools: Add ARM Statistical Profiling Extensions 
(SPE) support")
Signed-off-by: Wei Li 
---
 tools/perf/arch/arm/util/auxtrace.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tools/perf/arch/arm/util/auxtrace.c 
b/tools/perf/arch/arm/util/auxtrace.c
index 0a6e75b8777a..28a5d0c18b1d 100644
--- a/tools/perf/arch/arm/util/auxtrace.c
+++ b/tools/perf/arch/arm/util/auxtrace.c
@@ -56,7 +56,7 @@ struct auxtrace_record
struct perf_pmu *cs_etm_pmu;
struct evsel *evsel;
bool found_etm = false;
-   bool found_spe = false;
+   struct perf_pmu *found_spe = NULL;
static struct perf_pmu **arm_spe_pmus = NULL;
static int nr_spes = 0;
int i = 0;
@@ -74,12 +74,12 @@ struct auxtrace_record
evsel->core.attr.type == cs_etm_pmu->type)
found_etm = true;
 
-   if (!nr_spes)
+   if (!nr_spes || found_spe)
continue;
 
for (i = 0; i < nr_spes; i++) {
if (evsel->core.attr.type == arm_spe_pmus[i]->type) {
-   found_spe = true;
+   found_spe = arm_spe_pmus[i];
break;
}
}
@@ -96,7 +96,7 @@ struct auxtrace_record
 
 #if defined(__aarch64__)
if (found_spe)
-   return arm_spe_recording_init(err, arm_spe_pmus[i]);
+   return arm_spe_recording_init(err, found_spe);
 #endif
 
/*
-- 
2.17.1

[PATCH v2 2/2] perf tools: ARM SPE code cleanup

- Firstly, the function auxtrace_record__init() will be invoked only
  once, the variable "arm_spe_pmus" will not be used afterwards, thus
  we don't need to check "arm_spe_pmus" is NULL or not;
- Another reason is, even though SPE is micro-architecture dependent,
  but so far it only supports "statistical-profiling-extension-v1" and
  we have no chance to use multiple SPE's PMU events in Perf command.

So remove the useless check code to make it clear.

Signed-off-by: Wei Li 
---
 tools/perf/arch/arm/util/auxtrace.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/tools/perf/arch/arm/util/auxtrace.c 
b/tools/perf/arch/arm/util/auxtrace.c
index 28a5d0c18b1d..b187bddbd01a 100644
--- a/tools/perf/arch/arm/util/auxtrace.c
+++ b/tools/perf/arch/arm/util/auxtrace.c
@@ -57,17 +57,15 @@ struct auxtrace_record
struct evsel *evsel;
bool found_etm = false;
struct perf_pmu *found_spe = NULL;
-   static struct perf_pmu **arm_spe_pmus = NULL;
-   static int nr_spes = 0;
+   struct perf_pmu **arm_spe_pmus = NULL;
+   int nr_spes = 0;
int i = 0;
 
if (!evlist)
return NULL;
 
cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME);
-
-   if (!arm_spe_pmus)
-   arm_spe_pmus = find_all_arm_spe_pmus(_spes, err);
+   arm_spe_pmus = find_all_arm_spe_pmus(_spes, err);
 
evlist__for_each_entry(evlist, evsel) {
if (cs_etm_pmu &&
@@ -84,6 +82,7 @@ struct auxtrace_record
}
}
}
+   free(arm_spe_pmus);
 
if (found_etm && found_spe) {
pr_err("Concurrent ARM Coresight ETM and SPE operation not 
currently supported\n");
-- 
2.17.1

[PATCH v2 0/2] perf tools: Fix record failure when mixed with ARM SPE event

v1 -> v2:
 - Optimize code in patch 1 as Mathieu adviced.
 - Fix memleak in patch 2.
 - Detail the commit info to explain the reason.

This patch set fixes perf record failure when we mix arm_spe_x event
with other events in specific order.

Wei Li (2):
  perf tools: Fix record failure when mixed with ARM SPE event
  perf tools: ARM SPE code cleanup

 tools/perf/arch/arm/util/auxtrace.c | 17 -
 1 file changed, 8 insertions(+), 9 deletions(-)

-- 
2.17.1

Re: [RFC PATCH 09/16] sched/fair: core wide cfs task priority comparison(Internet mail)

2020-07-24 Thread Aaron Lu

On Wed, Jul 22, 2020 at 12:23:44AM +, benbjiang(蒋彪) wrote:
> 
> 
> > +/*
> > + * This function takes care of adjusting the min_vruntime of siblings of
> > + * a core during coresched enable/disable.
> > + * This is called in stop machine context so no need to take the rq lock.
> Hi,
> 
> IMHO, it seems that stop machine context cannot guarantee race free. The 
> param *cpu* maybe not *this_cpu*, rq lock should be taken even in stop 
> machine context, and irq should be disabled too, to avoid potential races 
> with other contexts.
> 

In stop machine context, all CPUs except the active ones are spinning
with irq disabled and in this invocation of stop_machine(), only one
CPU is active so I don't think race is possible.

Re: [PATCH] sched/deadline: dome some cleanup for push_dl_task()

2020-07-24 Thread Juri Lelli

Hi,

On 07/07/20 00:04, Peng Liu wrote:
> 'commit 840d719604b0 ("sched/deadline: Update rq_clock of later_rq when 
> pushing a task")'
> introduced the update_rq_clock() to fix the "used-before-update" bug.
> 
> 'commit f4904815f97a ("sched/deadline: Fix double accounting of rq/running bw 
> in push & pull")'
> took away the bug source(add_running_bw()).
> 
> We no longer need to update rq_clock in advance, let activate_task()
> worry about that.
> 
> Signed-off-by: Peng Liu 
> ---
>  kernel/sched/deadline.c | 8 +---
>  1 file changed, 1 insertion(+), 7 deletions(-)
> 
> diff --git a/kernel/sched/deadline.c b/kernel/sched/deadline.c
> index 504d2f51b0d6..c3fa11f84d93 100644
> --- a/kernel/sched/deadline.c
> +++ b/kernel/sched/deadline.c
> @@ -2104,13 +2104,7 @@ static int push_dl_task(struct rq *rq)
>  
>   deactivate_task(rq, next_task, 0);
>   set_task_cpu(next_task, later_rq->cpu);
> -
> - /*
> -  * Update the later_rq clock here, because the clock is used
> -  * by the cpufreq_update_util() inside __add_running_bw().
> -  */
> - update_rq_clock(later_rq);
> - activate_task(later_rq, next_task, ENQUEUE_NOCLOCK);
> + activate_task(later_rq, next_task, 0);
>   ret = 1;

The change looks good to me, since now add_running_bw() is called later
by enqueue_task_dl(), but rq_clock has already been updated by core's
enqueue_task().

Daniel, Dietmar, a second pair of eyes (since you authored the commits
above)?

I'd chage subject to something like "sched/deadline: Stop updating
rq_clock before pushing a task".

Thanks,

Juri

[PATCH v5 11/16] dt-bindings: irq: sun7i-nmi: fix dt-binding for a80 nmi

From: Yangtao Li 

There is no one use "allwinner,sun9i-a80-sc-nmi". The A80 uses
"allwinner,sun9i-a80-nmi".

Let's fix it.

Signed-off-by: Yangtao Li 
Acked-by: Rob Herring 
---
 .../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml| 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
 
b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
index 7cd6b8bacfa0..d8fe2d9a307b 100644
--- 
a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
@@ -29,7 +29,7 @@ properties:
   - items:
   - const: allwinner,sun8i-a83t-r-intc
   - const: allwinner,sun6i-a31-r-intc
-  - const: allwinner,sun9i-a80-sc-nmi
+  - const: allwinner,sun9i-a80-nmi
   - items:
   - const: allwinner,sun50i-a64-r-intc
   - const: allwinner,sun6i-a31-r-intc
-- 
2.24.0

[PATCH 2/2] fsi/sbefifo: Fix reset timeout

2020-07-24 Thread Joel Stanley

From: Joachim Fenkes 

On BMCs with lower timer resolution than 1ms, msleep(1) will take
way longer than 1ms, so looping 10k times won't wait for 10s but
significantly longer.

Fix this by using jiffies like the rest of the code.

Fixes: 9f4a8a2d7f9d ("fsi/sbefifo: Add driver for the SBE FIFO")
Signed-off-by: Joachim Fenkes 
Signed-off-by: Joel Stanley 
---
 drivers/fsi/fsi-sbefifo.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/fsi/fsi-sbefifo.c b/drivers/fsi/fsi-sbefifo.c
index 655b45c1f6ba..3ad9510ad4a4 100644
--- a/drivers/fsi/fsi-sbefifo.c
+++ b/drivers/fsi/fsi-sbefifo.c
@@ -325,6 +325,7 @@ static int sbefifo_up_write(struct sbefifo *sbefifo, __be32 
word)
 static int sbefifo_request_reset(struct sbefifo *sbefifo)
 {
struct device *dev = >fsi_dev->dev;
+   unsigned long end_time;
u32 status, timeout;
int rc;
 
@@ -341,7 +342,8 @@ static int sbefifo_request_reset(struct sbefifo *sbefifo)
}
 
/* Wait for it to complete */
-   for (timeout = 0; timeout < SBEFIFO_RESET_TIMEOUT; timeout++) {
+   end_time = jiffies + msecs_to_jiffies(SBEFIFO_RESET_TIMEOUT);
+   while (!time_after(jiffies, end_time)) {
rc = sbefifo_regr(sbefifo, SBEFIFO_UP | SBEFIFO_STS, );
if (rc) {
dev_err(dev, "Failed to read UP fifo status during 
reset"
@@ -355,7 +357,7 @@ static int sbefifo_request_reset(struct sbefifo *sbefifo)
return 0;
}
 
-   msleep(1);
+   cond_resched();
}
dev_err(dev, "FIFO reset timed out\n");
 
-- 
2.27.0

[PATCH 0/2] fsi: SBE FIFO fixes

2020-07-24 Thread Joel Stanley

Two SBE FIFO fixes by Joachim.

Joachim Fenkes (2):
  fsi/sbefifo: Clean up correct FIFO when receiving reset request from
SBE
  fsi/sbefifo: Fix reset timeout

 drivers/fsi/fsi-sbefifo.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

-- 
2.27.0

[PATCH 1/2] fsi/sbefifo: Clean up correct FIFO when receiving reset request from SBE

2020-07-24 Thread Joel Stanley

From: Joachim Fenkes 

When the SBE requests a reset via the down FIFO, that is also the
FIFO we should go and reset ;)

Fixes: 9f4a8a2d7f9d ("fsi/sbefifo: Add driver for the SBE FIFO")
Signed-off-by: Joachim Fenkes 
Signed-off-by: Joel Stanley 
---
 drivers/fsi/fsi-sbefifo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/fsi/fsi-sbefifo.c b/drivers/fsi/fsi-sbefifo.c
index f54df9ebc8b3..655b45c1f6ba 100644
--- a/drivers/fsi/fsi-sbefifo.c
+++ b/drivers/fsi/fsi-sbefifo.c
@@ -400,7 +400,7 @@ static int sbefifo_cleanup_hw(struct sbefifo *sbefifo)
/* The FIFO already contains a reset request from the SBE ? */
if (down_status & SBEFIFO_STS_RESET_REQ) {
dev_info(dev, "Cleanup: FIFO reset request set, resetting\n");
-   rc = sbefifo_regw(sbefifo, SBEFIFO_UP, SBEFIFO_PERFORM_RESET);
+   rc = sbefifo_regw(sbefifo, SBEFIFO_DOWN, SBEFIFO_PERFORM_RESET);
if (rc) {
sbefifo->broken = true;
dev_err(dev, "Cleanup: Reset reg write failed, 
rc=%d\n", rc);
-- 
2.27.0

Re: [PATCH 23/23] MAINTAINERS: Add Krzysztof Kozlowski as maintainer of memory controllers

2020-07-24 Thread Krzysztof Kozlowski

On Thu, Jul 23, 2020 at 10:12:36AM -0700, Florian Fainelli wrote:
> On 7/23/20 12:37 AM, Krzysztof Kozlowski wrote:
> > The specific drivers in drivers/memory usually go via architecture (e.g.
> > ARM SoC) maintainers but the generic parts (of_memory.[ch]) lacked any
> > care.
> > 
> > Signed-off-by: Krzysztof Kozlowski 
> 
> Acked-by: Florian Fainelli 
> 
> What does this mean for specific drivers? For instance I tend to send
> updates to brcmstb_dpfe.c through the Broadcom ARM SoC pull requests,
> shall I continue to do this, or are you going to send memory controller
> subsystem pull requests including that file in the future?

If that's okay, I intend to take the drivers patches as well. I will
rephrase the commit message.

Thanks for the feddback.

Best regards,
Krzysztof

Re: [PATCH] keys: asymmetric: fix error return code in software_key_query()

2020-07-24 Thread Jarkko Sakkinen

On Thu, Jul 23, 2020 at 08:42:25AM +0100, David Howells wrote:
> Jarkko Sakkinen  wrote:
> 
> > Why f1774cb8956a lacked any possible testing? It extends ABI anyway.
> > 
> > I think it is a kind of change that would require more screening before
> > getting applied.
> 
> Yeah.  It went in via a round-about route.  I left off development of it when
> the tpm stuff I wrote broke because the tpm2 stuff went in upstream.  I then
> handed the patches off to Denis who did the tpm support, but I never got my
> stuff finished enough to work out how to do the testsuite (since it would
> involve using a tpm).  However, since I did the PKCS#8 testing module as well,
> I guess I don't need that to at least test the API.  I'll look at using that
> to add some tests.  Any suggestions as to how to do testing via the tpm?
> 
> David

The unfortunate thing is that I was not involved with asym_tpm.c review
process in any possible way, which means that at the moment I lack both:

1. Knowledge of crypto/asymmetric_keys.
2. How asym_tpm.c is implemented.

I only became aware of asym_tpm.c's existence last Sep [*].

I'll put to my backlog to try TPM asymmetric keys (earliest when I'm back
from vacation 08/10).

[*] 
https://lore.kernel.org/linux-integrity/20190926171601.30404-1-jarkko.sakki...@linux.intel.com/

/Jarkko

[PATCH v5 12/16] dt-bindings: irq: sun7i-nmi: Add binding for A100's NMI controller

From: Yangtao Li 

Add a binding for A100's nmi controller.

Signed-off-by: Yangtao Li 
Acked-by: Rob Herring 
---
 .../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml   | 3 +++
 1 file changed, 3 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
 
b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
index d8fe2d9a307b..8acca0ae3129 100644
--- 
a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
@@ -33,6 +33,9 @@ properties:
   - items:
   - const: allwinner,sun50i-a64-r-intc
   - const: allwinner,sun6i-a31-r-intc
+  - items:
+  - const: allwinner,sun50i-a100-nmi
+  - const: allwinner,sun9i-a80-nmi
   - items:
   - const: allwinner,sun50i-h6-r-intc
   - const: allwinner,sun6i-a31-r-intc
-- 
2.24.0

RE: rtsx_pci not restoring ASPM state after suspend/resume

2020-07-24 Thread 吳昊澄 Ricky

Hi James, Bjorn,

The Card reader(10ec:5287) is a combo chip with Ethernet(10ec:8168), we think 
it is not cause by setting our device config space in idle time.
We dis/enable the ASPM(setting config space) at busy/idle time, it can make our 
R/W performances well not a work around function
PCI Host and Device setting self config space and do handshaking, we think it 
does not affect the system

Ricky 

> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: Friday, July 24, 2020 1:13 AM
> To: 吳昊澄 Ricky; Rui Feng
> Cc: Arnd Bergmann; Greg Kroah-Hartman; James Ettle; Len Brown; Puranjay
> Mohan; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Jacopo De
> Simoi
> Subject: Re: rtsx_pci not restoring ASPM state after suspend/resume
> 
> [+cc Jacopo]
> 
> On Thu, Jul 23, 2020 at 11:56:22AM -0500, Bjorn Helgaas wrote:
> > James reported this issue with rtsx_pci; can you guys please take a
> > look at it?  https://bugzilla.kernel.org/show_bug.cgi?id=208117
> >
> > There's a lot of good info in the bugzilla already.
> 
> Likely duplicate: https://bugzilla.kernel.org/show_bug.cgi?id=198951
> 
> Jacopo, could you please attach a complete dmesg log and "sudo lspci
> -vv" output to your bugzilla?
> 
> --Please consider the environment before printing this e-mail.

[PATCH v5 13/16] dt-bindings: i2c: mv64xxx: Add compatible for the A100 i2c node.

From: Yangtao Li 

Allwinner A100 have a mv64xxx i2c interface available to be used.

Signed-off-by: Yangtao Li 
Reviewed-by: Rob Herring 
---
 Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml 
b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
index 2ceb05ba2df5..5b5ae402f97a 100644
--- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
@@ -26,6 +26,9 @@ properties:
   - items:
   - const: allwinner,sun50i-a64-i2c
   - const: allwinner,sun6i-a31-i2c
+  - items:
+  - const: allwinner,sun50i-a100-i2c
+  - const: allwinner,sun6i-a31-i2c
   - items:
   - const: allwinner,sun50i-h6-i2c
   - const: allwinner,sun6i-a31-i2c
-- 
2.24.0

[PATCH v6 2/4] clocksource/drivers: Add CLINT timer driver

We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e.
RISC-V NoMMU kernel).

The CLINT MMIO device provides three things:
1. 64bit free running counter register
2. 64bit per-CPU time compare registers
3. 32bit per-CPU inter-processor interrupt registers

Unlike other timer devices, CLINT provides IPI registers along with
timer registers. To use CLINT IPI registers, the CLINT timer driver
provides IPI related callbacks to arch/riscv.

Signed-off-by: Anup Patel 
Tested-by: Emil Renner Berhing 
Acked-by: Daniel Lezcano 
---
 drivers/clocksource/Kconfig   |   9 ++
 drivers/clocksource/Makefile  |   1 +
 drivers/clocksource/timer-clint.c | 226 ++
 include/linux/cpuhotplug.h|   1 +
 4 files changed, 237 insertions(+)
 create mode 100644 drivers/clocksource/timer-clint.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 91418381fcd4..41f1c147c178 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -658,6 +658,15 @@ config RISCV_TIMER
  is accessed via both the SBI and the rdcycle instruction.  This is
  required for all RISC-V systems.
 
+config CLINT_TIMER
+   bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
+   depends on GENERIC_SCHED_CLOCK && RISCV
+   select TIMER_PROBE
+   select TIMER_OF
+   help
+ This option enables the CLINT timer for RISC-V systems.  The CLINT
+ driver is usually used for NoMMU RISC-V systems.
+
 config CSKY_MP_TIMER
bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
depends on CSKY
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index bdda1a2e4097..18e700e703a0 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_CLKSRC_ST_LPC)   += clksrc_st_lpc.o
 obj-$(CONFIG_X86_NUMACHIP) += numachip.o
 obj-$(CONFIG_ATCPIT100_TIMER)  += timer-atcpit100.o
 obj-$(CONFIG_RISCV_TIMER)  += timer-riscv.o
+obj-$(CONFIG_CLINT_TIMER)  += timer-clint.o
 obj-$(CONFIG_CSKY_MP_TIMER)+= timer-mp-csky.o
 obj-$(CONFIG_GX6605S_TIMER)+= timer-gx6605s.o
 obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o
diff --git a/drivers/clocksource/timer-clint.c 
b/drivers/clocksource/timer-clint.c
new file mode 100644
index ..8eeafa82c03d
--- /dev/null
+++ b/drivers/clocksource/timer-clint.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
+ * CLINT MMIO timer device.
+ */
+
+#define pr_fmt(fmt) "clint: " fmt
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CLINT_IPI_OFF  0
+#define CLINT_TIMER_CMP_OFF0x4000
+#define CLINT_TIMER_VAL_OFF0xbff8
+
+/* CLINT manages IPI and Timer for RISC-V M-mode  */
+static u32 __iomem *clint_ipi_base;
+static u64 __iomem *clint_timer_cmp;
+static u64 __iomem *clint_timer_val;
+static unsigned long clint_timer_freq;
+static unsigned int clint_timer_irq;
+
+static void clint_send_ipi(const struct cpumask *target)
+{
+   unsigned int cpu;
+
+   for_each_cpu(cpu, target)
+   writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
+}
+
+static void clint_clear_ipi(void)
+{
+   writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
+}
+
+static struct riscv_ipi_ops clint_ipi_ops = {
+   .ipi_inject = clint_send_ipi,
+   .ipi_clear = clint_clear_ipi,
+};
+
+#ifdef CONFIG_64BIT
+#define clint_get_cycles() readq_relaxed(clint_timer_val)
+#else
+#define clint_get_cycles() readl_relaxed(clint_timer_val)
+#define clint_get_cycles_hi()  readl_relaxed(((u32 *)clint_timer_val) + 1)
+#endif
+
+#ifdef CONFIG_64BIT
+static u64 notrace clint_get_cycles64(void)
+{
+   return clint_get_cycles();
+}
+#else /* CONFIG_64BIT */
+static u64 notrace clint_get_cycles64(void)
+{
+   u32 hi, lo;
+
+   do {
+   hi = clint_get_cycles_hi();
+   lo = clint_get_cycles();
+   } while (hi != clint_get_cycles_hi());
+
+   return ((u64)hi << 32) | lo;
+}
+#endif /* CONFIG_64BIT */
+
+static u64 clint_rdtime(struct clocksource *cs)
+{
+   return clint_get_cycles64();
+}
+
+static struct clocksource clint_clocksource = {
+   .name   = "clint_clocksource",
+   .rating = 300,
+   .mask   = CLOCKSOURCE_MASK(64),
+   .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+   .read   = clint_rdtime,
+};
+
+static int clint_clock_next_event(unsigned long delta,
+  struct clock_event_device *ce)
+{
+   void __iomem *r = clint_timer_cmp +
+ cpuid_to_hartid_map(smp_processor_id());
+
+   csr_set(CSR_IE, IE_TIE);
+

[PATCH v6 1/4] RISC-V: Add mechanism to provide custom IPI operations

We add mechanism to set custom IPI operations so that CLINT driver
from drivers directory can provide custom IPI operations.

Signed-off-by: Anup Patel 
Tested-by: Emil Renner Berhing 
Reviewed-by: Atish Patra 
---
 arch/riscv/include/asm/clint.h | 25 
 arch/riscv/include/asm/smp.h   | 19 +++
 arch/riscv/kernel/clint.c  | 23 --
 arch/riscv/kernel/sbi.c| 14 +++
 arch/riscv/kernel/smp.c| 43 +++---
 arch/riscv/kernel/smpboot.c|  3 +--
 6 files changed, 79 insertions(+), 48 deletions(-)

diff --git a/arch/riscv/include/asm/clint.h b/arch/riscv/include/asm/clint.h
index a279b17a6aad..adaba98a7d6c 100644
--- a/arch/riscv/include/asm/clint.h
+++ b/arch/riscv/include/asm/clint.h
@@ -6,34 +6,9 @@
 #include 
 
 #ifdef CONFIG_RISCV_M_MODE
-extern u32 __iomem *clint_ipi_base;
-
 void clint_init_boot_cpu(void);
-
-static inline void clint_send_ipi_single(unsigned long hartid)
-{
-   writel(1, clint_ipi_base + hartid);
-}
-
-static inline void clint_send_ipi_mask(const struct cpumask *mask)
-{
-   int cpu;
-
-   for_each_cpu(cpu, mask)
-   clint_send_ipi_single(cpuid_to_hartid_map(cpu));
-}
-
-static inline void clint_clear_ipi(unsigned long hartid)
-{
-   writel(0, clint_ipi_base + hartid);
-}
 #else /* CONFIG_RISCV_M_MODE */
 #define clint_init_boot_cpu()  do { } while (0)
-
-/* stubs to for code is only reachable under IS_ENABLED(CONFIG_RISCV_M_MODE): 
*/
-void clint_send_ipi_single(unsigned long hartid);
-void clint_send_ipi_mask(const struct cpumask *hartid_mask);
-void clint_clear_ipi(unsigned long hartid);
 #endif /* CONFIG_RISCV_M_MODE */
 
 #endif /* _ASM_RISCV_CLINT_H */
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 40bb1c15a731..68de78a8eba6 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -15,6 +15,11 @@
 struct seq_file;
 extern unsigned long boot_cpu_hartid;
 
+struct riscv_ipi_ops {
+   void (*ipi_inject)(const struct cpumask *target);
+   void (*ipi_clear)(void);
+};
+
 #ifdef CONFIG_SMP
 /*
  * Mapping between linux logical cpu index and hartid.
@@ -40,6 +45,12 @@ void arch_send_call_function_single_ipi(int cpu);
 int riscv_hartid_to_cpuid(int hartid);
 void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out);
 
+/* Set custom IPI operations */
+void riscv_set_ipi_ops(struct riscv_ipi_ops *ops);
+
+/* Clear IPI for current CPU */
+void riscv_clear_ipi(void);
+
 /*
  * Obtains the hart ID of the currently executing task.  This relies on
  * THREAD_INFO_IN_TASK, but we define that unconditionally.
@@ -78,6 +89,14 @@ static inline void riscv_cpuid_to_hartid_mask(const struct 
cpumask *in,
cpumask_set_cpu(boot_cpu_hartid, out);
 }
 
+static inline void riscv_set_ipi_ops(struct riscv_ipi_ops *ops)
+{
+}
+
+static inline void riscv_clear_ipi(void)
+{
+}
+
 #endif /* CONFIG_SMP */
 
 #if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP)
diff --git a/arch/riscv/kernel/clint.c b/arch/riscv/kernel/clint.c
index 3647980d14c3..a9845ee023e2 100644
--- a/arch/riscv/kernel/clint.c
+++ b/arch/riscv/kernel/clint.c
@@ -5,11 +5,11 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
-#include 
 
 /*
  * This is the layout used by the SiFive clint, which is also shared by the 
qemu
@@ -21,6 +21,24 @@
 
 u32 __iomem *clint_ipi_base;
 
+static void clint_send_ipi(const struct cpumask *target)
+{
+   unsigned int cpu;
+
+   for_each_cpu(cpu, target)
+   writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
+}
+
+static void clint_clear_ipi(void)
+{
+   writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
+}
+
+static struct riscv_ipi_ops clint_ipi_ops = {
+   .ipi_inject = clint_send_ipi,
+   .ipi_clear = clint_clear_ipi,
+};
+
 void clint_init_boot_cpu(void)
 {
struct device_node *np;
@@ -40,5 +58,6 @@ void clint_init_boot_cpu(void)
riscv_time_cmp = base + CLINT_TIME_CMP_OFF;
riscv_time_val = base + CLINT_TIME_VAL_OFF;
 
-   clint_clear_ipi(boot_cpu_hartid);
+   clint_clear_ipi();
+   riscv_set_ipi_ops(_ipi_ops);
 }
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index f383ef5672b2..226ccce0f9e0 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -547,6 +547,18 @@ static inline long sbi_get_firmware_version(void)
return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION);
 }
 
+static void sbi_send_cpumask_ipi(const struct cpumask *target)
+{
+   struct cpumask hartid_mask;
+
+   riscv_cpuid_to_hartid_mask(target, _mask);
+
+   sbi_send_ipi(cpumask_bits(_mask));
+}
+
+static struct riscv_ipi_ops sbi_ipi_ops = {
+   .ipi_inject = sbi_send_cpumask_ipi
+};
 
 int __init sbi_init(void)
 {
@@ -587,5 +599,7 @@ int __init sbi_init(void)
__sbi_rfence= __sbi_rfence_v01;
}
 
+   riscv_set_ipi_ops(_ipi_ops);
+

[PATCH v6 0/4] Dedicated CLINT timer driver

The current RISC-V timer driver is convoluted and implements two
distinct timers:
 1. S-mode timer: This is for Linux RISC-V S-mode with MMU. The
clocksource is implemented using TIME CSR and clockevent device
is implemented using SBI Timer calls.
 2. M-mode timer: This is for Linux RISC-V M-mode without MMU. The
clocksource is implemented using CLINT MMIO time register and
clockevent device is implemented using CLINT MMIO timecmp registers.

This patchset removes clint related code from RISC-V timer driver and
arch/riscv directory. Instead, the series adds a dedicated MMIO based
CLINT driver under drivers/clocksource directory which can be used by
Linux RISC-V M-mode (i.e NoMMU Linux RISC-V).

The patchset is based up Linux-5.8-rc6 and can be found at riscv_clint_v6
branch of: https://github.com/avpatel/linux.git

This series is tested on:
 1. QEMU RV64 virt machine using Linux RISC-V S-mode
 2. QEMU RV32 virt machine using Linux RISC-V S-mode
 3. QEMU RV64 virt machine using Linux RISC-V M-mode (i.e. NoMMU)

Changes since v5:
 - Fixed order of compatible strings in PATCH4
 - Added "additionalProperties: false" in PATCH4
 - Fixed register space size for example DT node in PATCH4

Changes since v4:
 - Rebased series on Linux-5.8-rc6
 - Updated Kconfig option as suggested by Daniel in PATCH2
 - Removed per-CPU registered flag in PATCH2
 - Addressed nit comments from Atish in PATCH2

Changes since v3:
 - Updated commit description of PATCH2
 - Use clint_get_cycles64() in clint_rdtime() of PATCH2
 - Call clockevents_config_and_register() only once for each CPU in
   clint_timer_starting_cpu of PATCH2
 - Select CLINT timer driver from platform Kconfig in PATCH3
 - Fixed 'make dt_binding_check' for PATCH4

Changes since v2:
 - Rebased series on Linux-5.8-rc5
 - Squashed PATCH3 onto PATCH2 to preserve GIT bisectability
 - Moved PATCH4 before PATCH2 to preserve GIT bisectability
 - Replaced CLINT dt-bindings text document with YAML schema
 - Use SiFive CLINT compatible string as per SiFive IP block versioning

Changes since v1:
 - Rebased series on Linux-5.8-rc2
 - Added pr_warn() for case where ipi_ops not available in PATCH1
 - Updated ipi_inject() prototype to use "struct cpumask *" in PATCH1
 - Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4
 - Added riscv,clint0 compatible string in DT bindings document

Anup Patel (4):
  RISC-V: Add mechanism to provide custom IPI operations
  clocksource/drivers: Add CLINT timer driver
  RISC-V: Remove CLINT related code from timer and arch
  dt-bindings: timer: Add CLINT bindings

 .../bindings/timer/sifive,clint.yaml  |  60 +
 arch/riscv/Kconfig|   2 +-
 arch/riscv/Kconfig.socs   |   2 +
 arch/riscv/configs/nommu_virt_defconfig   |   7 +-
 arch/riscv/include/asm/clint.h|  39 ---
 arch/riscv/include/asm/smp.h  |  19 ++
 arch/riscv/include/asm/timex.h|  28 +--
 arch/riscv/kernel/Makefile|   2 +-
 arch/riscv/kernel/clint.c |  44 
 arch/riscv/kernel/sbi.c   |  14 ++
 arch/riscv/kernel/setup.c |   2 -
 arch/riscv/kernel/smp.c   |  44 ++--
 arch/riscv/kernel/smpboot.c   |   4 +-
 drivers/clocksource/Kconfig   |  12 +-
 drivers/clocksource/Makefile  |   1 +
 drivers/clocksource/timer-clint.c | 226 ++
 drivers/clocksource/timer-riscv.c |  17 +-
 include/linux/cpuhotplug.h|   1 +
 18 files changed, 371 insertions(+), 153 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.yaml
 delete mode 100644 arch/riscv/include/asm/clint.h
 delete mode 100644 arch/riscv/kernel/clint.c
 create mode 100644 drivers/clocksource/timer-clint.c

-- 
2.25.1

[PATCH v5 14/16] arm64: allwinner: A100: add the basical Allwinner A100 DTSI file

From: Yangtao Li 

Allwinner A100 is a new SoC with Cortex-A53 cores, this commit adds
the basical DTSI file of it, including the clock, i2c, pins, sid, ths,
nmi, and UART support.

Signed-off-by: Yangtao Li 
---
 .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 ++
 1 file changed, 364 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
new file mode 100644
index ..cc321c04f121
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (c) 2020 Yangtao Li 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   compatible = "arm,cortex-a53";
+   device_type = "cpu";
+   reg = <0x0>;
+   enable-method = "psci";
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a53";
+   device_type = "cpu";
+   reg = <0x1>;
+   enable-method = "psci";
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a53";
+   device_type = "cpu";
+   reg = <0x2>;
+   enable-method = "psci";
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a53";
+   device_type = "cpu";
+   reg = <0x3>;
+   enable-method = "psci";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-1.0";
+   method = "smc";
+   };
+
+   dcxo24M: dcxo24M-clk {
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   clock-output-names = "dcxo24M";
+   #clock-cells = <0>;
+   };
+
+   iosc: internal-osc-clk {
+   compatible = "fixed-clock";
+   clock-frequency = <1600>;
+   clock-accuracy = <3>;
+   clock-output-names = "iosc";
+   #clock-cells = <0>;
+   };
+
+   osc32k: osc32k-clk {
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "osc32k";
+   #clock-cells = <0>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupts = ,
+,
+,
+;
+   };
+
+   soc {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0 0 0x3fff>;
+
+   ccu: clock@3001000 {
+   compatible = "allwinner,sun50i-a100-ccu";
+   reg = <0x03001000 0x1000>;
+   clocks = <>, <>, <>;
+   clock-names = "hosc", "losc", "iosc";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+   gic: interrupt-controller@3021000 {
+   compatible = "arm,gic-400";
+   reg = <0x03021000 0x1000>, <0x03022000 0x2000>,
+ <0x03024000 0x2000>, <0x03026000 0x2000>;
+   interrupts = ;
+   interrupt-controller;
+   #interrupt-cells = <3>;
+   };
+
+   efuse@3006000 {
+   compatible = "allwinner,sun50i-a100-sid",
+"allwinner,sun50i-a64-sid";
+   reg = <0x03006000 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   ths_calibration: calib@14 {
+   reg = <0x14 8>;
+   };
+   };
+
+   pio: pinctrl@300b000 {
+   compatible = "allwinner,sun50i-a100-pinctrl";
+   reg = <0x0300b000 0x400>;
+   interrupts = ,
+,
+,
+,
+,
+,
+;
+   clocks = < CLK_APB1>, <>, <>;
+   clock-names = "apb", "hosc", "losc";
+   gpio-controller;
+   #gpio-cells = <3>;
+   interrupt-controller;
+

[PATCH v6 4/4] dt-bindings: timer: Add CLINT bindings

We add DT bindings documentation for CLINT device.

Signed-off-by: Anup Patel 
Reviewed-by: Palmer Dabbelt 
Tested-by: Emil Renner Berhing 
---
 .../bindings/timer/sifive,clint.yaml  | 60 +++
 1 file changed, 60 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.yaml

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml 
b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
new file mode 100644
index ..2a0e9cd9fbcf
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive Core Local Interruptor
+
+maintainers:
+  - Palmer Dabbelt 
+  - Anup Patel 
+
+description:
+  SiFive (and other RISC-V) SOCs include an implementation of the SiFive
+  Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
+  interrupts. It directly connects to the timer and inter-processor interrupt
+  lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
+  interrupt controller is the parent interrupt controller for CLINT device.
+  The clock frequency of CLINT is specified via "timebase-frequency" DT
+  property of "/cpus" DT node. The "timebase-frequency" DT property is
+  described in Documentation/devicetree/bindings/riscv/cpus.yaml
+
+properties:
+  compatible:
+items:
+  - const: sifive,fu540-c000-clint
+  - const: sifive,clint0
+
+description:
+  Should be "sifive,-clint" and "sifive,clint".
+  Supported compatible strings are -
+  "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
+  onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive
+  CLINT v0 IP block with no chip integration tweaks.
+  Please refer to sifive-blocks-ip-versioning.txt for details
+
+  reg:
+maxItems: 1
+
+  interrupts-extended:
+minItems: 1
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+
+examples:
+  - |
+timer@200 {
+  compatible = "sifive,fu540-c000-clint", "sifive,clint0";
+  interrupts-extended = < 3  7
+  3  7
+  3  7
+  3  7>;
+   reg = <0x200 0x1>;
+};
+...
-- 
2.25.1

[PATCH v6 3/4] RISC-V: Remove CLINT related code from timer and arch

Right now the RISC-V timer driver is convoluted to support:
1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for
   clocksource and SBI timer calls for clockevent device.
2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO
   counter register for clocksource and CLINT MMIO compare register
   for clockevent device.

We now have a separate CLINT timer driver which also provide CLINT
based IPI operations so let's remove CLINT MMIO related code from
arch/riscv directory and RISC-V timer driver.

Signed-off-by: Anup Patel 
Tested-by: Emil Renner Berhing 
Acked-by: Daniel Lezcano 
---
 arch/riscv/Kconfig  |  2 +-
 arch/riscv/Kconfig.socs |  2 +
 arch/riscv/configs/nommu_virt_defconfig |  7 +--
 arch/riscv/include/asm/clint.h  | 14 --
 arch/riscv/include/asm/timex.h  | 28 +++
 arch/riscv/kernel/Makefile  |  2 +-
 arch/riscv/kernel/clint.c   | 63 -
 arch/riscv/kernel/setup.c   |  2 -
 arch/riscv/kernel/smp.c |  1 -
 arch/riscv/kernel/smpboot.c |  1 -
 drivers/clocksource/Kconfig |  3 +-
 drivers/clocksource/timer-riscv.c   | 17 +--
 12 files changed, 16 insertions(+), 126 deletions(-)
 delete mode 100644 arch/riscv/include/asm/clint.h
 delete mode 100644 arch/riscv/kernel/clint.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fedb4a72b29a..57a72ae23d10 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -74,7 +74,7 @@ config RISCV
select PCI_DOMAINS_GENERIC if PCI
select PCI_MSI if PCI
select RISCV_INTC
-   select RISCV_TIMER
+   select RISCV_TIMER if RISCV_SBI
select SPARSEMEM_STATIC if 32BIT
select SPARSE_IRQ
select SYSCTL_EXCEPTION_TRACE
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 6c88148f1b9b..8a55f6156661 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -12,6 +12,7 @@ config SOC_SIFIVE
 
 config SOC_VIRT
bool "QEMU Virt Machine"
+   select CLINT_TIMER if RISCV_M_MODE
select POWER_RESET
select POWER_RESET_SYSCON
select POWER_RESET_SYSCON_POWEROFF
@@ -24,6 +25,7 @@ config SOC_VIRT
 config SOC_KENDRYTE
bool "Kendryte K210 SoC"
depends on !MMU
+   select CLINT_TIMER if RISCV_M_MODE
select SERIAL_SIFIVE if TTY
select SERIAL_SIFIVE_CONSOLE if TTY
select SIFIVE_PLIC
diff --git a/arch/riscv/configs/nommu_virt_defconfig 
b/arch/riscv/configs/nommu_virt_defconfig
index cf74e179bf90..cf9388184aa3 100644
--- a/arch/riscv/configs/nommu_virt_defconfig
+++ b/arch/riscv/configs/nommu_virt_defconfig
@@ -26,6 +26,7 @@ CONFIG_EXPERT=y
 CONFIG_SLOB=y
 # CONFIG_SLAB_MERGE_DEFAULT is not set
 # CONFIG_MMU is not set
+CONFIG_SOC_VIRT=y
 CONFIG_MAXPHYSMEM_2GB=y
 CONFIG_SMP=y
 CONFIG_CMDLINE="root=/dev/vda rw earlycon=uart8250,mmio,0x1000,115200n8 
console=ttyS0"
@@ -48,7 +49,6 @@ CONFIG_VIRTIO_BLK=y
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_LDISC_AUTOLOAD is not set
-# CONFIG_DEVMEM is not set
 CONFIG_SERIAL_8250=y
 # CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
 CONFIG_SERIAL_8250_CONSOLE=y
@@ -56,16 +56,13 @@ CONFIG_SERIAL_8250_NR_UARTS=1
 CONFIG_SERIAL_8250_RUNTIME_UARTS=1
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
+# CONFIG_DEVMEM is not set
 # CONFIG_HWMON is not set
-# CONFIG_LCD_CLASS_DEVICE is not set
-# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
 # CONFIG_VGA_CONSOLE is not set
 # CONFIG_HID is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_VIRTIO_MMIO=y
 CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
-CONFIG_SIFIVE_PLIC=y
-# CONFIG_VALIDATE_FS_PARSER is not set
 CONFIG_EXT2_FS=y
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY_USER is not set
diff --git a/arch/riscv/include/asm/clint.h b/arch/riscv/include/asm/clint.h
deleted file mode 100644
index adaba98a7d6c..
--- a/arch/riscv/include/asm/clint.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_RISCV_CLINT_H
-#define _ASM_RISCV_CLINT_H 1
-
-#include 
-#include 
-
-#ifdef CONFIG_RISCV_M_MODE
-void clint_init_boot_cpu(void);
-#else /* CONFIG_RISCV_M_MODE */
-#define clint_init_boot_cpu()  do { } while (0)
-#endif /* CONFIG_RISCV_M_MODE */
-
-#endif /* _ASM_RISCV_CLINT_H */
diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
index bad2a7c2cda5..a3fb85d505d4 100644
--- a/arch/riscv/include/asm/timex.h
+++ b/arch/riscv/include/asm/timex.h
@@ -7,41 +7,27 @@
 #define _ASM_RISCV_TIMEX_H
 
 #include 
-#include 
 
 typedef unsigned long cycles_t;
 
-extern u64 __iomem *riscv_time_val;
-extern u64 __iomem *riscv_time_cmp;
-
-#ifdef CONFIG_64BIT
-#define mmio_get_cycles()  readq_relaxed(riscv_time_val)
-#else
-#define mmio_get_cycles()  readl_relaxed(riscv_time_val)
-#define mmio_get_cycles_hi()   readl_relaxed(((u32 *)riscv_time_val) + 1)
-#endif
-
 static inline

[PATCH] perf bench: Add benchmark of find_next_bit

2020-07-24 Thread Ian Rogers

for_each_set_bit, or similar functions like for_each_cpu, may be hot
within the kernel. If many bits were set then one could imagine on
Intel a "bt" instruction with every bit may be faster than the function
call and word length find_next_bit logic. Add a benchmark to measure
this.

This benchmark on AMD rome and Intel skylakex shows "bt" is not a good
option except for very small bitmaps.

Signed-off-by: Ian Rogers 
---
 tools/perf/bench/Build|   1 +
 tools/perf/bench/bench.h  |   1 +
 tools/perf/bench/find-bit-bench.c | 135 ++
 tools/perf/builtin-bench.c|   1 +
 4 files changed, 138 insertions(+)
 create mode 100644 tools/perf/bench/find-bit-bench.c

diff --git a/tools/perf/bench/Build b/tools/perf/bench/Build
index 768e408757a0..fb114bca3a8d 100644
--- a/tools/perf/bench/Build
+++ b/tools/perf/bench/Build
@@ -10,6 +10,7 @@ perf-y += epoll-wait.o
 perf-y += epoll-ctl.o
 perf-y += synthesize.o
 perf-y += kallsyms-parse.o
+perf-y += find-bit-bench.o
 
 perf-$(CONFIG_X86_64) += mem-memcpy-x86-64-lib.o
 perf-$(CONFIG_X86_64) += mem-memcpy-x86-64-asm.o
diff --git a/tools/perf/bench/bench.h b/tools/perf/bench/bench.h
index 61cae4966cae..3291b0fe 100644
--- a/tools/perf/bench/bench.h
+++ b/tools/perf/bench/bench.h
@@ -35,6 +35,7 @@ int bench_sched_messaging(int argc, const char **argv);
 int bench_sched_pipe(int argc, const char **argv);
 int bench_mem_memcpy(int argc, const char **argv);
 int bench_mem_memset(int argc, const char **argv);
+int bench_mem_find_bit(int argc, const char **argv);
 int bench_futex_hash(int argc, const char **argv);
 int bench_futex_wake(int argc, const char **argv);
 int bench_futex_wake_parallel(int argc, const char **argv);
diff --git a/tools/perf/bench/find-bit-bench.c 
b/tools/perf/bench/find-bit-bench.c
new file mode 100644
index ..1aadbd9d7e86
--- /dev/null
+++ b/tools/perf/bench/find-bit-bench.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Benchmark find_next_bit and related bit operations.
+ *
+ * Copyright 2020 Google LLC.
+ */
+#include 
+#include "bench.h"
+#include "../util/stat.h"
+#include 
+#include 
+#include 
+#include 
+
+static unsigned int outer_iterations = 5;
+static unsigned int inner_iterations = 10;
+
+static const struct option options[] = {
+   OPT_UINTEGER('i', "outer-iterations", _iterations,
+   "Number of outerer iterations used"),
+   OPT_UINTEGER('j', "inner-iterations", _iterations,
+   "Number of outerer iterations used"),
+   OPT_END()
+};
+
+static const char *const bench_usage[] = {
+   "perf bench mem find_bit ",
+   NULL
+};
+
+static unsigned int accumulator;
+static unsigned int use_of_val;
+
+static noinline void workload(int val)
+{
+   use_of_val += val;
+   accumulator++;
+}
+
+#if defined(__i386__) || defined(__x86_64__)
+static bool asm_test_bit(long nr, const unsigned long *addr)
+{
+   bool oldbit;
+
+   asm volatile("bt %2,%1"
+: "=@ccc" (oldbit)
+: "m" (*(unsigned long *)addr), "Ir" (nr) : "memory");
+
+   return oldbit;
+}
+#else
+#define asm_test_bit test_bit
+#endif
+
+static int do_for_each_set_bit(unsigned int num_bits)
+{
+   unsigned long *to_test = bitmap_alloc(num_bits);
+   struct timeval start, end, diff;
+   u64 runtime_us;
+   struct stats fb_time_stats, tb_time_stats;
+   double time_average, time_stddev;
+   unsigned int bit, i, j;
+   unsigned int set_bits, skip;
+   unsigned int old;
+
+   init_stats(_time_stats);
+   init_stats(_time_stats);
+
+   for (set_bits = 1; set_bits <= num_bits; set_bits <<= 1) {
+   bitmap_zero(to_test, num_bits);
+   skip = num_bits / set_bits;
+   for (i = 0; i < num_bits; i += skip)
+   set_bit(i, to_test);
+
+   for (i = 0; i < outer_iterations; i++) {
+   old = accumulator;
+   gettimeofday(, NULL);
+   for (j = 0; j < inner_iterations; j++) {
+   for_each_set_bit(bit, to_test, num_bits)
+   workload(bit);
+   }
+   gettimeofday(, NULL);
+   assert(old + (inner_iterations * set_bits) == 
accumulator);
+   timersub(, , );
+   runtime_us = diff.tv_sec * USEC_PER_SEC + diff.tv_usec;
+   update_stats(_time_stats, runtime_us);
+
+   old = accumulator;
+   gettimeofday(, NULL);
+   for (j = 0; j < inner_iterations; j++) {
+   for (bit = 0; bit < num_bits; bit++) {
+   if (asm_test_bit(bit, to_test))
+   workload(bit);
+   }
+   }
+

Re: [PATCH v5 1/4] riscv: Move kernel mapping to vmalloc zone

2020-07-24 Thread Arnd Bergmann

On Wed, Jul 22, 2020 at 11:06 PM Atish Patra  wrote:
>
> On Wed, Jul 22, 2020 at 1:23 PM Arnd Bergmann  wrote:
> >
> > I just noticed that rv32 allows 2GB of lowmem rather than just the usual
> > 768MB or 1GB, at the expense of addressable user memory. This seems
> > like an unusual choice, but I also don't see any reason to change this
> > or make it more flexible unless actual users appear.
> >
>
> I am a bit confused here. As per my understanding, RV32 supports 1GB
> of lowmem only
> as the page offset is set to 0xC000. The config option
> MAXPHYSMEM_2GB is misleading
> as RV32 actually allows 1GB of physical memory only.

Ok, in that case I was apparently misled by the Kconfig option name.

I just tried building a kernel to see what the boundaries actually are,
as this is not the only confusing bit. Here is what I see:

0x9dc0 TASK_SIZE/FIXADDR_START   /* code comment says 0x9fc0 */
0x9e00 FIXADDR_TOP/PCI_IO_START
0x9f00 PCI_IO_END/VMEMMAP_START
0xa000 VMEMMAP_END/VMALLOC_START
0xc000 VMALLOC_END/PAGE_OFFSET

Having exactly 1GB of linear map does make a lot of sense. Having PCI I/O,
vmemmap and fixmap come out of the user range means you get slightly
different behavior in user space if there are any changes to that set, but
that is probably fine as well, if you want the flexibility to go to a 2GB linear
map and expect user space to deal with that as well.

There is one common trick from arm32 however that you might want to
consider: if vmalloc was moved above the linear map rather than below,
the size of the vmalloc area can dynamically depend on the amount of
RAM that is actually present rather than be set to a fixed value.

On arm32, there is around 240MB of vmalloc space if the linear map
is fully populated with RAM, but it can grow to use all of the avaialable
address space if less RAM was detected at boot time (up to 3GB
depending on CONFIG_VMSPLIT).

> Any memory blocks beyond
> DRAM + 1GB are removed in setup_bootmem. IMHO, The current config
> should clarify that.
>
> Moreover, we should add 2G split under a separate configuration if we
> want to support that.

Right. It's probably not needed immediately, but can't hurt either.

Arnd

[PATCH v5 15/16] dt-bindings: arm: sunxi: Add Allwinner A100 Perf1 Board bindings

From: Yangtao Li 

Document board compatible names for Allwinner A100 Perf1 Board.

Signed-off-by: Yangtao Li 
Reviewed-by: Rob Herring 
---
 Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml 
b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 87817ff0cd35..dbec66c1377a 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -16,6 +16,11 @@ properties:
   compatible:
 oneOf:
 
+  - description: Allwinner A100 Perf1 Board
+items:
+  - const: allwinner,a100-perf1
+  - const: allwinner,sun50i-a100
+
   - description: Allwinner A23 Evaluation Board
 items:
   - const: allwinner,sun8i-a23-evb
-- 
2.24.0

[PATCH v5 16/16] arm64: allwinner: A100: add support for Allwinner Perf1 board

From: Yangtao Li 

A100 perf1 is an Allwinner A100-based SBC, with the following features:

- 1GiB DDR3 DRAM
- AXP803 PMIC
- 2 USB 2.0 ports
- MicroSD slot and on-board eMMC module
- on-board Nand flash
- ···

Adds initial support for it, including UART and PMU.

Signed-off-by: Yangtao Li 
---
 arch/arm64/boot/dts/allwinner/Makefile|   1 +
 .../allwinner/sun50i-a100-allwinner-perf1.dts | 180 ++
 2 files changed, 181 insertions(+)
 create mode 100644 
arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts

diff --git a/arch/arm64/boot/dts/allwinner/Makefile 
b/arch/arm64/boot/dts/allwinner/Makefile
index e4d3cd0ac5bb..ab780dbdd17b 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts 
b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
new file mode 100644
index ..d34c2bb1079f
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (c) 2020 Yangtao Li 
+ */
+
+/dts-v1/;
+
+#include "sun50i-a100.dtsi"
+
+/{
+   model = "Allwinner A100 Perf1";
+   compatible = "allwinner,a100-perf1", "allwinner,sun50i-a100";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   vcc-pb-supply = <_dcdc1>;
+   vcc-pc-supply = <_eldo1>;
+   vcc-pd-supply = <_dcdc1>;
+   vcc-pe-supply = <_dldo2>;
+   vcc-pf-supply = <_dcdc1>;
+   vcc-pg-supply = <_dldo1>;
+   vcc-ph-supply = <_dcdc1>;
+};
+
+_pio {
+   /*
+* FIXME: We can't add that supply for now since it would
+* create a circular dependency between pinctrl, the regulator
+* and the RSB Bus.
+*
+* vcc-pl-supply = <_aldo3>;
+*/
+};
+
+_i2c0 {
+   status = "okay";
+
+   axp803: pmic@34 {
+   compatible = "x-powers,axp803";
+   reg = <0x34>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
+   };
+};
+
+#include "axp803.dtsi"
+
+_power_supply {
+   status = "okay";
+};
+
+_aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-name = "vcc-dram-1";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-usb-pl";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-io-usb-pd-emmc-nand-card";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   /*
+* FIXME: update min and max before support dvfs.
+*/
+   regulator-min-microvolt = <50>;
+   regulator-max-microvolt = <130>;
+   regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+_dcdc4 {
+   regulator-always-on;
+   regulator-min-microvolt = <95>;
+   regulator-max-microvolt = <95>;
+   regulator-name = "vdd-sys-usb-dram";
+};
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram-2";
+};
+
+_dldo1 {
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pg-dcxo-wifi";
+};
+
+_dldo2 {
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <280>;
+   regulator-name = "vcc-pe-csi";
+};
+
+_dldo3 {
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "ldo-avdd-csi";
+};
+
+_dldo4 {
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <280>;
+   regulator-name = "avcc-csi";
+};
+
+_eldo1 {
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-name = "vcc-pc-lvds-csi-efuse-emmc-nand";
+};
+
+_eldo2 {
+

Re: [PATCH] sched/fair: consider sched-idle CPU when selecting idle core

2020-07-24 Thread Vincent Guittot

On Fri, 24 Jul 2020 at 01:39, Jiang Biao  wrote:
>
> From: Jiang Biao 
>
> Sched-idle CPU has been considered in select_idle_cpu and
> select_idle_smt, it also needs to be considered in select_idle_core to
> be consistent and keep the same *idle* policy.

In the case of select_idle_core, we are looking for a core that is
fully idle but if one CPU of the core is running a sched_idle task,
the core will not be idle and we might end up having  the wakeup task
on a CPU and a sched_idle task on another CPU of the core which is not
what we want

>
> Signed-off-by: Jiang Biao 
> ---
>  kernel/sched/fair.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
> index 04fa8dbcfa4d..f430a9820d08 100644
> --- a/kernel/sched/fair.c
> +++ b/kernel/sched/fair.c
> @@ -6014,7 +6014,7 @@ void __update_idle_core(struct rq *rq)
> if (cpu == core)
> continue;
>
> -   if (!available_idle_cpu(cpu))
> +   if (!available_idle_cpu(cpu) && !sched_idle_cpu(cpu))
> goto unlock;
> }
>
> @@ -6045,7 +6045,7 @@ static int select_idle_core(struct task_struct *p, 
> struct sched_domain *sd, int
> bool idle = true;
>
> for_each_cpu(cpu, cpu_smt_mask(core)) {
> -   if (!available_idle_cpu(cpu)) {
> +   if (!available_idle_cpu(cpu) && !sched_idle_cpu(cpu)) 
> {
> idle = false;
> break;
> }
> --
> 2.21.0
>
>

Re: strace of io_uring events?

2020-07-24 Thread Stefano Garzarella

On Thu, Jul 23, 2020 at 09:37:40AM -0400, Colin Walters wrote:
> On Tue, Jul 21, 2020, at 11:58 AM, Stefano Garzarella wrote:
> 
> > my use case concerns virtualization. The idea, that I described in the
> > proposal of io-uring restrictions [1], is to share io_uring CQ and SQ queues
> > with a guest VM for block operations.
> 
> Virtualization being a strong security barrier is in eternal conflict
> with maximizing performance.  All of these "let's add a special
> guest/host channel" are high risk areas.
> 
> And this effort in particular - is it *really* worth it to expose a
> brand new, fast moving Linux kernel interface (that probably hasn't
> been fuzzed as much as it needs to be) to virtual machines?
> 

It is an experiment to explore the potential of io_uring. In addition
the restrictions can also be useful for other use case, for example if
a process  wants to allow another process to use io_uring, but only allowing
a subset of operations.

> People who want maximum performance at the cost of a bit of security
> already have the choice to use Linux containers, where they can use
> io_uring natively.
> 

Thanks,
Stefano

Re: [PATCH] amdgpu_dm: fix nonblocking atomic commit use-after-free

2020-07-24 Thread Christian König

Am 24.07.20 um 00:58 schrieb Mazin Rezk:

On Thursday, July 23, 2020 6:32 PM, Kees Cook wrote:

On Thu, Jul 23, 2020 at 09:10:15PM +, Mazin Rezk wrote:

When amdgpu_dm_atomic_commit_tail is running in the workqueue,
drm_atomic_state_put will get called while amdgpu_dm_atomic_commit_tail is
running, causing a race condition where state (and then dm_state) is
sometimes freed while amdgpu_dm_atomic_commit_tail is running. This bug has
occurred since 5.7-rc1 and is well documented among polaris11 users [1].
Prior to 5.7, this was not a noticeable issue since the freelist pointer
was stored at the beginning of dm_state (base), which was unused. After
changing the freelist pointer to be stored in the middle of the struct, the
freelist pointer overwrote the context, causing dc_state to become garbage
data and made the call to dm_enable_per_frame_crtc_master_sync dereference
a freelist pointer.
This patch fixes the aforementioned issue by calling drm_atomic_state_get
in amdgpu_dm_atomic_commit before drm_atomic_helper_commit is called and
drm_atomic_state_put after amdgpu_dm_atomic_commit_tail is complete.
According to my testing on 5.8.0-rc6, this should fix bug 207383 on
Bugzilla [1].
[1]
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.kernel.org%2Fshow_bug.cgi%3Fid%3D207383data=02%7C01%7Charry.wentland%40amd.com%7C53cc9cffb1d244d7b43508d82f5bed1b%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637311419153032496sdata=t45vmEJ80UXOmRfndGfe69AOedtkFUwDqvWgGDrSuOk%3Dreserved=0

Nice work tracking this down!

Fixes: 3202fa62f ("slub: relocate freelist pointer to middle of object")

I do, however, object to this Fixes tag. :) The flaw appears to have
been with amdgpu_dm's reference tracking of "state" in the nonblocking
case. (How this reference counting is supposed to work correctly, though,
I'm not sure.) If I look at where the drm helper was split from being
the default callback, it looks like this was what introduced the bug:

da5c47f682ab ("drm/amd/display: Remove acrtc->stream")

? 3202fa62f certainly exposed it much more quickly, but there was a race
even without 3202fa62f where something could have realloced the memory
and written over it.

---

Kees Cook

Thanks, I'll be sure to avoid using 3202fa62f as the cause next time.
I just thought to do that because it was what made the use-after-free cause
a noticeable bug.

Also, by the way, I just realised the patch didn't completely solve the bug.
Sorry about that, making an LKML thread on this was hasty on my part. Should
I get further confirmation from the Bugzilla thread before submitting a patch
for this bug in the future?

Submitting stuff as early as possible is mostly a good idea. Just if the
code is utterly broken or completely unreadable you should probably
expect a harsh response :)

Maybe ask for more testing in the commit message if you are not 100%
sure if that really fixes a bug or not.

Regards,
Christian.

Thanks,
Mazin Rezk

[PATCH] perf: arm-spe: Fix check error when synthesizing events

In arm_spe_read_record(), when we are processing an events packet,
'decoder->packet.index' is the length of payload, which has been
transformed in payloadlen(). So correct the check of 'idx'.

Signed-off-by: Wei Li 
---
 tools/perf/util/arm-spe-decoder/arm-spe-decoder.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c 
b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c
index 302a14d0aca9..93e063f22be5 100644
--- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c
@@ -182,15 +182,15 @@ static int arm_spe_read_record(struct arm_spe_decoder 
*decoder)
if (payload & BIT(EV_TLB_ACCESS))
decoder->record.type |= ARM_SPE_TLB_ACCESS;
 
-   if ((idx == 1 || idx == 2 || idx == 3) &&
+   if ((idx == 2 || idx == 4 || idx == 8) &&
(payload & BIT(EV_LLC_MISS)))
decoder->record.type |= ARM_SPE_LLC_MISS;
 
-   if ((idx == 1 || idx == 2 || idx == 3) &&
+   if ((idx == 2 || idx == 4 || idx == 8) &&
(payload & BIT(EV_LLC_ACCESS)))
decoder->record.type |= ARM_SPE_LLC_ACCESS;
 
-   if ((idx == 1 || idx == 2 || idx == 3) &&
+   if ((idx == 2 || idx == 4 || idx == 8) &&
(payload & BIT(EV_REMOTE_ACCESS)))
decoder->record.type |= ARM_SPE_REMOTE_ACCESS;
 
-- 
2.17.1

Re: [PATCH 3/3] memory: introduce an option to force onlining of hotplug memory

2020-07-24 Thread Michal Hocko

On Thu 23-07-20 19:39:54, David Hildenbrand wrote:
[...]
> Yeah, might require some code churn. It just feels wrong to involve
> buddy concepts (e.g., onlining pages, calling memory notifiers, exposing
> memory block devices) and introducing hacks (forced onlining) just to
> get a memmap+identity mapping+iomem resource. I think reserving such a
> region during boot as suggested is the easiest approach, but I am
> *absolutely* not an expert on all these XEN-specific things :)

I am late to the discussion but FTR I completely agree.
-- 
Michal Hocko
SUSE Labs

Re: [PATCH net-next v2 3/7] net: macb: parse PHY nodes found under an MDIO node

2020-07-24 Thread Claudiu.Beznea



On 23.07.2020 21:59, Florian Fainelli wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the 
> content is safe
> 
> On 7/21/20 10:13 AM, Codrin Ciubotariu wrote:
>> The MACB embeds an MDIO bus controller. For this reason, the PHY nodes
>> were represented as sub-nodes in the MACB node. Generally, the
>> Ethernet controller is different than the MDIO controller, so the PHYs
>> are probed by a separate MDIO driver. Since adding the PHY nodes directly
>> under the ETH node became deprecated, we adjust the MACB driver to look
>> for an MDIO node and register the subnode MDIO devices.
>>
>> Signed-off-by: Codrin Ciubotariu 
>> ---
>>
>> Changes in v2:
>>  - readded newline removed by mistake;
>>
>>  drivers/net/ethernet/cadence/macb_main.c | 10 ++
>>  1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/net/ethernet/cadence/macb_main.c 
>> b/drivers/net/ethernet/cadence/macb_main.c
>> index 89fe7af5e408..b25c64b45148 100644
>> --- a/drivers/net/ethernet/cadence/macb_main.c
>> +++ b/drivers/net/ethernet/cadence/macb_main.c
>> @@ -740,10 +740,20 @@ static int macb_mii_probe(struct net_device *dev)
>>  static int macb_mdiobus_register(struct macb *bp)
>>  {
>>   struct device_node *child, *np = bp->pdev->dev.of_node;
>> + struct device_node *mdio_node;
>> + int ret;
>>
>>   if (of_phy_is_fixed_link(np))
>>   return mdiobus_register(bp->mii_bus);
> 
> Does not this need changing as well? Consider the use case of having
> your MACB Ethernet node have a fixed-link property to describe how it
> connects to a switch, and your MACB MDIO controller, expressed as a
> sub-node, describing the MDIO attached switch it connects to.

Just asking, does this worth having/changing it as long as there is no in
kernel board/configuration that could benefit off?

Thank you,
Claudiu Beznea

> 
>>
>> + /* if an MDIO node is present, it should contain the PHY nodes */
>> + mdio_node = of_get_child_by_name(np, "mdio");
>> + if (mdio_node) {
>> + ret = of_mdiobus_register(bp->mii_bus, mdio_node);
>> + of_node_put(mdio_node);
>> + return ret;
>> + }
>> +
>>   /* Only create the PHY from the device tree if at least one PHY is
>>* described. Otherwise scan the entire MDIO bus. We do this to support
>>* old device tree that did not follow the best practices and did not
>>
> 
> 
> --
> Florian
>

RE: [PATCH v6 0/9] remoteproc: Add support for attaching with rproc

2020-07-24 Thread Peng Fan

> Subject: [PATCH v6 0/9] remoteproc: Add support for attaching with rproc

For the series, 

Tested-by: Peng Fan 

Regards,
Peng.
> 
> This set provides functionality allowing the remoteproc core to attach to a
> remote processor that was started by another entity.
> 
> New in V6:
> 1) Added Arnaud's reviewed-by and tested-by tags.
> 
> Applies cleanly on rproc-next (0cf17702d872)
> 
> Thanks,
> Mathieu
> 
> Mathieu Poirier (9):
>   remoteproc: Add new RPROC_DETACHED state
>   remoteproc: Add new attach() remoteproc operation
>   remoteproc: Introducing function rproc_attach()
>   remoteproc: Introducing function rproc_actuate()
>   remoteproc: Introducing function rproc_validate()
>   remoteproc: Refactor function rproc_boot()
>   remoteproc: Refactor function rproc_trigger_auto_boot()
>   remoteproc: Refactor function rproc_free_vring()
>   remoteproc: Properly handle firmware name when attaching
> 
>  drivers/remoteproc/remoteproc_core.c | 213
> +--
>  drivers/remoteproc/remoteproc_internal.h |   8 +
>  drivers/remoteproc/remoteproc_sysfs.c|  17 +-
>  include/linux/remoteproc.h   |   9 +-
>  4 files changed, 230 insertions(+), 17 deletions(-)
> 
> --
> 2.25.1

[PATCH 05/14] md: update the optimal I/O size on reshape

The raid5 and raid10 drivers currently update the read-ahead size,
but not the optimal I/O size on reshape.  To prepare for deriving the
read-ahead size from the optimal I/O size make sure it is updated
as well.

Signed-off-by: Christoph Hellwig 
---
 drivers/md/raid10.c | 22 ++
 drivers/md/raid5.c  | 10 --
 2 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c
index b1d0c9d4ef7757..9f88ff9bdee437 100644
--- a/drivers/md/raid10.c
+++ b/drivers/md/raid10.c
@@ -3695,10 +3695,20 @@ static struct r10conf *setup_conf(struct mddev *mddev)
return ERR_PTR(err);
 }
 
+static void raid10_set_io_opt(struct r10conf *conf)
+{
+   int raid_disks = conf->geo.raid_disks;
+
+   if (!(conf->geo.raid_disks % conf->geo.near_copies))
+   raid_disks /= conf->geo.near_copies;
+   blk_queue_io_opt(conf->mddev->queue, (conf->mddev->chunk_sectors << 9) *
+raid_disks);
+}
+
 static int raid10_run(struct mddev *mddev)
 {
struct r10conf *conf;
-   int i, disk_idx, chunk_size;
+   int i, disk_idx;
struct raid10_info *disk;
struct md_rdev *rdev;
sector_t size;
@@ -3734,18 +3744,13 @@ static int raid10_run(struct mddev *mddev)
mddev->thread = conf->thread;
conf->thread = NULL;
 
-   chunk_size = mddev->chunk_sectors << 9;
if (mddev->queue) {
blk_queue_max_discard_sectors(mddev->queue,
  mddev->chunk_sectors);
blk_queue_max_write_same_sectors(mddev->queue, 0);
blk_queue_max_write_zeroes_sectors(mddev->queue, 0);
-   blk_queue_io_min(mddev->queue, chunk_size);
-   if (conf->geo.raid_disks % conf->geo.near_copies)
-   blk_queue_io_opt(mddev->queue, chunk_size * 
conf->geo.raid_disks);
-   else
-   blk_queue_io_opt(mddev->queue, chunk_size *
-(conf->geo.raid_disks / 
conf->geo.near_copies));
+   blk_queue_io_min(mddev->queue, mddev->chunk_sectors << 9);
+   raid10_set_io_opt(conf);
}
 
rdev_for_each(rdev, mddev) {
@@ -4719,6 +4724,7 @@ static void end_reshape(struct r10conf *conf)
stripe /= conf->geo.near_copies;
if (conf->mddev->queue->backing_dev_info->ra_pages < 2 * stripe)
conf->mddev->queue->backing_dev_info->ra_pages = 2 * 
stripe;
+   raid10_set_io_opt(conf);
}
conf->fullsync = 0;
 }
diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index d7780b1dd0c528..68e41ce3ca75cc 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -7123,6 +7123,12 @@ static int only_parity(int raid_disk, int algo, int 
raid_disks, int max_degraded
return 0;
 }
 
+static void raid5_set_io_opt(struct r5conf *conf)
+{
+   blk_queue_io_opt(conf->mddev->queue, (conf->chunk_sectors << 9) *
+(conf->raid_disks - conf->max_degraded));
+}
+
 static int raid5_run(struct mddev *mddev)
 {
struct r5conf *conf;
@@ -7412,8 +7418,7 @@ static int raid5_run(struct mddev *mddev)
 
chunk_size = mddev->chunk_sectors << 9;
blk_queue_io_min(mddev->queue, chunk_size);
-   blk_queue_io_opt(mddev->queue, chunk_size *
-(conf->raid_disks - conf->max_degraded));
+   raid5_set_io_opt(conf);
mddev->queue->limits.raid_partial_stripes_expensive = 1;
/*
 * We can only discard a whole stripe. It doesn't make sense to
@@ -8006,6 +8011,7 @@ static void end_reshape(struct r5conf *conf)
   / PAGE_SIZE);
if (conf->mddev->queue->backing_dev_info->ra_pages < 2 
* stripe)
conf->mddev->queue->backing_dev_info->ra_pages 
= 2 * stripe;
+   raid5_set_io_opt(conf);
}
}
 }
-- 
2.27.0

[PATCH 07/14] block: make QUEUE_SYSFS_BIT_FNS a little more useful

Generate the queue_sysfs_entry given that we have all the required
information for it, and rename the generated show and store methods
to match the other ones in the file.

Signed-off-by: Christoph Hellwig 
Reviewed-by: Johannes Thumshirn 
---
 block/blk-sysfs.c | 31 +--
 1 file changed, 9 insertions(+), 22 deletions(-)

diff --git a/block/blk-sysfs.c b/block/blk-sysfs.c
index ce418d9128a0b2..cfbb039da8751f 100644
--- a/block/blk-sysfs.c
+++ b/block/blk-sysfs.c
@@ -257,16 +257,16 @@ static ssize_t queue_max_hw_sectors_show(struct 
request_queue *q, char *page)
return queue_var_show(max_hw_sectors_kb, (page));
 }
 
-#define QUEUE_SYSFS_BIT_FNS(name, flag, neg)   \
+#define QUEUE_SYSFS_BIT_FNS(_name, flag, neg)  \
 static ssize_t \
-queue_show_##name(struct request_queue *q, char *page) \
+queue_##_name##_show(struct request_queue *q, char *page)  \
 {  \
int bit;\
bit = test_bit(QUEUE_FLAG_##flag, >queue_flags); \
return queue_var_show(neg ? !bit : bit, page);  \
 }  \
 static ssize_t \
-queue_store_##name(struct request_queue *q, const char *page, size_t count) \
+queue_##_name##_store(struct request_queue *q, const char *page, size_t count) 
\
 {  \
unsigned long val;  \
ssize_t ret;\
@@ -281,7 +281,12 @@ queue_store_##name(struct request_queue *q, const char 
*page, size_t count) \
else\
blk_queue_flag_clear(QUEUE_FLAG_##flag, q); \
return ret; \
-}
+}  \
+static struct queue_sysfs_entry queue_##_name##_entry = {  \
+   .attr   = { .name = __stringify(_name), .mode = 0644 }, \
+   .show   = queue_##_name##_show, \
+   .store  = queue_##_name##_store,\
+};
 
 QUEUE_SYSFS_BIT_FNS(nonrot, NONROT, 1);
 QUEUE_SYSFS_BIT_FNS(random, ADD_RANDOM, 0);
@@ -661,12 +666,6 @@ static struct queue_sysfs_entry 
queue_zone_append_max_entry = {
.show = queue_zone_append_max_show,
 };
 
-static struct queue_sysfs_entry queue_nonrot_entry = {
-   .attr = {.name = "rotational", .mode = 0644 },
-   .show = queue_show_nonrot,
-   .store = queue_store_nonrot,
-};
-
 static struct queue_sysfs_entry queue_zoned_entry = {
.attr = {.name = "zoned", .mode = 0444 },
.show = queue_zoned_show,
@@ -699,18 +698,6 @@ static struct queue_sysfs_entry queue_rq_affinity_entry = {
.store = queue_rq_affinity_store,
 };
 
-static struct queue_sysfs_entry queue_iostats_entry = {
-   .attr = {.name = "iostats", .mode = 0644 },
-   .show = queue_show_iostats,
-   .store = queue_store_iostats,
-};
-
-static struct queue_sysfs_entry queue_random_entry = {
-   .attr = {.name = "add_random", .mode = 0644 },
-   .show = queue_show_random,
-   .store = queue_store_random,
-};
-
 static struct queue_sysfs_entry queue_poll_entry = {
.attr = {.name = "io_poll", .mode = 0644 },
.show = queue_poll_show,
-- 
2.27.0

[PATCH 08/14] block: add helper macros for queue sysfs entries

Add two helpers macros to avoid boilerplate code for the queue sysfs
entries.

Signed-off-by: Christoph Hellwig 
Reviewed-by: Johannes Thumshirn 
---
 block/blk-sysfs.c | 248 +++---
 1 file changed, 58 insertions(+), 190 deletions(-)

diff --git a/block/blk-sysfs.c b/block/blk-sysfs.c
index cfbb039da8751f..9bb4e42fb73265 100644
--- a/block/blk-sysfs.c
+++ b/block/blk-sysfs.c
@@ -551,201 +551,69 @@ static ssize_t queue_dax_show(struct request_queue *q, 
char *page)
return queue_var_show(blk_queue_dax(q), page);
 }
 
-static struct queue_sysfs_entry queue_requests_entry = {
-   .attr = {.name = "nr_requests", .mode = 0644 },
-   .show = queue_requests_show,
-   .store = queue_requests_store,
-};
-
-static struct queue_sysfs_entry queue_ra_entry = {
-   .attr = {.name = "read_ahead_kb", .mode = 0644 },
-   .show = queue_ra_show,
-   .store = queue_ra_store,
-};
-
-static struct queue_sysfs_entry queue_max_sectors_entry = {
-   .attr = {.name = "max_sectors_kb", .mode = 0644 },
-   .show = queue_max_sectors_show,
-   .store = queue_max_sectors_store,
-};
+#define QUEUE_RO_ENTRY(_prefix, _name) \
+static struct queue_sysfs_entry _prefix##_entry = {\
+   .attr   = { .name = _name, .mode = 0444 },  \
+   .show   = _prefix##_show,   \
+};
+
+#define QUEUE_RW_ENTRY(_prefix, _name) \
+static struct queue_sysfs_entry _prefix##_entry = {\
+   .attr   = { .name = _name, .mode = 0644 },  \
+   .show   = _prefix##_show,   \
+   .store  = _prefix##_store,  \
+};
+
+QUEUE_RW_ENTRY(queue_requests, "nr_requests");
+QUEUE_RW_ENTRY(queue_ra, "read_ahead_kb");
+QUEUE_RW_ENTRY(queue_max_sectors, "max_sectors_kb");
+QUEUE_RO_ENTRY(queue_max_hw_sectors, "max_hw_sectors_kb");
+QUEUE_RO_ENTRY(queue_max_segments, "max_segments");
+QUEUE_RO_ENTRY(queue_max_integrity_segments, "max_integrity_segments");
+QUEUE_RO_ENTRY(queue_max_segment_size, "max_segment_size");
+QUEUE_RW_ENTRY(elv_iosched, "scheduler");
+
+QUEUE_RO_ENTRY(queue_logical_block_size, "logical_block_size");
+QUEUE_RO_ENTRY(queue_physical_block_size, "physical_block_size");
+QUEUE_RO_ENTRY(queue_chunk_sectors, "chunk_sectors");
+QUEUE_RO_ENTRY(queue_io_min, "minimum_io_size");
+QUEUE_RO_ENTRY(queue_io_opt, "optimal_io_size");
+
+QUEUE_RO_ENTRY(queue_max_discard_segments, "max_discard_segments");
+QUEUE_RO_ENTRY(queue_discard_granularity, "discard_granularity");
+QUEUE_RO_ENTRY(queue_discard_max_hw, "discard_max_hw_bytes");
+QUEUE_RW_ENTRY(queue_discard_max, "discard_max_bytes");
+QUEUE_RO_ENTRY(queue_discard_zeroes_data, "discard_zeroes_data");
+
+QUEUE_RO_ENTRY(queue_write_same_max, "write_same_max_bytes");
+QUEUE_RO_ENTRY(queue_write_zeroes_max, "write_zeroes_max_bytes");
+QUEUE_RO_ENTRY(queue_zone_append_max, "zone_append_max_bytes");
+
+QUEUE_RO_ENTRY(queue_zoned, "zoned");
+QUEUE_RO_ENTRY(queue_nr_zones, "nr_zones");
+QUEUE_RO_ENTRY(queue_max_open_zones, "max_open_zones");
+QUEUE_RO_ENTRY(queue_max_active_zones, "max_active_zones");
+
+QUEUE_RW_ENTRY(queue_nomerges, "nomerges");
+QUEUE_RW_ENTRY(queue_rq_affinity, "rq_affinity");
+QUEUE_RW_ENTRY(queue_poll, "io_poll");
+QUEUE_RW_ENTRY(queue_poll_delay, "io_poll_delay");
+QUEUE_RW_ENTRY(queue_wc, "write_cache");
+QUEUE_RO_ENTRY(queue_fua, "fua");
+QUEUE_RO_ENTRY(queue_dax, "dax");
+QUEUE_RW_ENTRY(queue_io_timeout, "io_timeout");
+QUEUE_RW_ENTRY(queue_wb_lat, "wbt_lat_usec");
 
-static struct queue_sysfs_entry queue_max_hw_sectors_entry = {
-   .attr = {.name = "max_hw_sectors_kb", .mode = 0444 },
-   .show = queue_max_hw_sectors_show,
-};
-
-static struct queue_sysfs_entry queue_max_segments_entry = {
-   .attr = {.name = "max_segments", .mode = 0444 },
-   .show = queue_max_segments_show,
-};
-
-static struct queue_sysfs_entry queue_max_discard_segments_entry = {
-   .attr = {.name = "max_discard_segments", .mode = 0444 },
-   .show = queue_max_discard_segments_show,
-};
-
-static struct queue_sysfs_entry queue_max_integrity_segments_entry = {
-   .attr = {.name = "max_integrity_segments", .mode = 0444 },
-   .show = queue_max_integrity_segments_show,
-};
-
-static struct queue_sysfs_entry queue_max_segment_size_entry = {
-   .attr = {.name = "max_segment_size", .mode = 0444 },
-   .show = queue_max_segment_size_show,
-};
-
-static struct queue_sysfs_entry queue_iosched_entry = {
-   .attr = {.name = "scheduler", .mode = 0644 },
-   .show = elv_iosched_show,
-   .store = elv_iosched_store,
-};
+#ifdef CONFIG_BLK_DEV_THROTTLING_LOW
+QUEUE_RW_ENTRY(blk_throtl_sample, "throttle_sample_time");
+#endif
 
+/* legacy alias for logical_block_size: */
 static struct queue_sysfs_entry queue_hw_sector_size_entry = {
.attr = {.name = "hw_sector_size", .mode = 0444 },
.show = queue_logical_block_size_show,
 };
 
-static struct queue_sysfs_entry

[PATCH 10/14] bdi: remove BDI_CAP_SYNCHRONOUS_IO

BDI_CAP_SYNCHRONOUS_IO is only checked in the swap code, and used to
decided if ->rw_page can be used on a block device.  Just check up for
the method instead.  The only complication is that zram needs a second
set of block_device_operations as it can switch between modes that
actually support ->rw_page and those who don't.

Signed-off-by: Christoph Hellwig 
---
 drivers/block/brd.c   |  1 -
 drivers/block/zram/zram_drv.c | 19 +--
 drivers/nvdimm/btt.c  |  2 --
 drivers/nvdimm/pmem.c |  1 -
 include/linux/backing-dev.h   |  9 -
 mm/swapfile.c |  2 +-
 6 files changed, 14 insertions(+), 20 deletions(-)

diff --git a/drivers/block/brd.c b/drivers/block/brd.c
index 2723a70eb85593..cc49a921339f77 100644
--- a/drivers/block/brd.c
+++ b/drivers/block/brd.c
@@ -403,7 +403,6 @@ static struct brd_device *brd_alloc(int i)
disk->flags = GENHD_FL_EXT_DEVT;
sprintf(disk->disk_name, "ram%d", i);
set_capacity(disk, rd_size * 2);
-   brd->brd_queue->backing_dev_info->capabilities |= 
BDI_CAP_SYNCHRONOUS_IO;
 
/* Tell the block layer that this is not a rotational device */
blk_queue_flag_set(QUEUE_FLAG_NONROT, brd->brd_queue);
diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c
index 9100ac36670afc..d73ddf018fa65f 100644
--- a/drivers/block/zram/zram_drv.c
+++ b/drivers/block/zram/zram_drv.c
@@ -52,6 +52,9 @@ static unsigned int num_devices = 1;
  */
 static size_t huge_class_size;
 
+static const struct block_device_operations zram_devops;
+static const struct block_device_operations zram_wb_devops;
+
 static void zram_free_page(struct zram *zram, size_t index);
 static int zram_bvec_read(struct zram *zram, struct bio_vec *bvec,
u32 index, int offset, struct bio *bio);
@@ -408,8 +411,7 @@ static void reset_bdev(struct zram *zram)
zram->backing_dev = NULL;
zram->old_block_size = 0;
zram->bdev = NULL;
-   zram->disk->queue->backing_dev_info->capabilities |=
-   BDI_CAP_SYNCHRONOUS_IO;
+   zram->disk->fops = _devops;
kvfree(zram->bitmap);
zram->bitmap = NULL;
 }
@@ -528,8 +530,7 @@ static ssize_t backing_dev_store(struct device *dev,
 * freely but in fact, IO is going on so finally could cause
 * use-after-free when the IO is really done.
 */
-   zram->disk->queue->backing_dev_info->capabilities &=
-   ~BDI_CAP_SYNCHRONOUS_IO;
+   zram->disk->fops = _wb_devops;
up_write(>init_lock);
 
pr_info("setup backing device %s\n", file_name);
@@ -1819,6 +1820,13 @@ static const struct block_device_operations zram_devops 
= {
.owner = THIS_MODULE
 };
 
+static const struct block_device_operations zram_wb_devops = {
+   .open = zram_open,
+   .submit_bio = zram_submit_bio,
+   .swap_slot_free_notify = zram_slot_free_notify,
+   .owner = THIS_MODULE
+};
+
 static DEVICE_ATTR_WO(compact);
 static DEVICE_ATTR_RW(disksize);
 static DEVICE_ATTR_RO(initstate);
@@ -1946,8 +1954,7 @@ static int zram_add(void)
if (ZRAM_LOGICAL_BLOCK_SIZE == PAGE_SIZE)
blk_queue_max_write_zeroes_sectors(zram->disk->queue, UINT_MAX);
 
-   zram->disk->queue->backing_dev_info->capabilities |=
-   (BDI_CAP_STABLE_WRITES | BDI_CAP_SYNCHRONOUS_IO);
+   zram->disk->queue->backing_dev_info->capabilities |= 
BDI_CAP_STABLE_WRITES;
device_add_disk(NULL, zram->disk, zram_disk_attr_groups);
 
strlcpy(zram->compressor, default_compressor, sizeof(zram->compressor));
diff --git a/drivers/nvdimm/btt.c b/drivers/nvdimm/btt.c
index 412d21d8f64351..b4184dc9b41eb4 100644
--- a/drivers/nvdimm/btt.c
+++ b/drivers/nvdimm/btt.c
@@ -1540,8 +1540,6 @@ static int btt_blk_init(struct btt *btt)
btt->btt_disk->private_data = btt;
btt->btt_disk->queue = btt->btt_queue;
btt->btt_disk->flags = GENHD_FL_EXT_DEVT;
-   btt->btt_disk->queue->backing_dev_info->capabilities |=
-   BDI_CAP_SYNCHRONOUS_IO;
 
blk_queue_logical_block_size(btt->btt_queue, btt->sector_size);
blk_queue_max_hw_sectors(btt->btt_queue, UINT_MAX);
diff --git a/drivers/nvdimm/pmem.c b/drivers/nvdimm/pmem.c
index 94790e6e0e4ce1..436b83fb24ad61 100644
--- a/drivers/nvdimm/pmem.c
+++ b/drivers/nvdimm/pmem.c
@@ -478,7 +478,6 @@ static int pmem_attach_disk(struct device *dev,
disk->queue = q;
disk->flags = GENHD_FL_EXT_DEVT;
disk->private_data  = pmem;
-   disk->queue->backing_dev_info->capabilities |= BDI_CAP_SYNCHRONOUS_IO;
nvdimm_namespace_disk_name(ndns, disk->disk_name);
set_capacity(disk, (pmem->size - pmem->pfn_pad - pmem->data_offset)
/ 512);
diff --git a/include/linux/backing-dev.h b/include/linux/backing-dev.h
index 52583b6f2ea05d..860ea33571bce5 100644
---

[PATCH 14/14] bdi: replace BDI_CAP_NO_{WRITEBACK,ACCT_DIRTY} with a single flag

Replace the two negative flags that are always used together with a
single positive flag that indicates the writeback capability instead
of two related non-capabilities.  Also remove the pointless wrappers
to just check the flag.

Signed-off-by: Christoph Hellwig 
---
 fs/9p/vfs_file.c|  2 +-
 fs/fs-writeback.c   |  7 +++---
 include/linux/backing-dev.h | 48 -
 mm/backing-dev.c|  6 ++---
 mm/filemap.c|  4 ++--
 mm/memcontrol.c |  2 +-
 mm/memory-failure.c |  2 +-
 mm/migrate.c|  2 +-
 mm/mmap.c   |  2 +-
 mm/page-writeback.c | 12 +-
 10 files changed, 29 insertions(+), 58 deletions(-)

diff --git a/fs/9p/vfs_file.c b/fs/9p/vfs_file.c
index 92cd1d80218d70..5479d894a10696 100644
--- a/fs/9p/vfs_file.c
+++ b/fs/9p/vfs_file.c
@@ -625,7 +625,7 @@ static void v9fs_mmap_vm_close(struct vm_area_struct *vma)
 
inode = file_inode(vma->vm_file);
 
-   if (!mapping_cap_writeback_dirty(inode->i_mapping))
+   if (!mapping_can_writeback(inode->i_mapping))
wbc.nr_to_write = 0;
 
might_sleep();
diff --git a/fs/fs-writeback.c b/fs/fs-writeback.c
index a605c3dddabc76..e62e48fecff4f9 100644
--- a/fs/fs-writeback.c
+++ b/fs/fs-writeback.c
@@ -2318,7 +2318,7 @@ void __mark_inode_dirty(struct inode *inode, int flags)
 
wb = locked_inode_to_wb_and_lock_list(inode);
 
-   WARN(bdi_cap_writeback_dirty(wb->bdi) &&
+   WARN((wb->bdi->capabilities & BDI_CAP_WRITEBACK) &&
 !test_bit(WB_registered, >state),
 "bdi-%s not registered\n", bdi_dev_name(wb->bdi));
 
@@ -2343,7 +2343,8 @@ void __mark_inode_dirty(struct inode *inode, int flags)
 * to make sure background write-back happens
 * later.
 */
-   if (bdi_cap_writeback_dirty(wb->bdi) && wakeup_bdi)
+   if (wakeup_bdi &&
+   (wb->bdi->capabilities & BDI_CAP_WRITEBACK))
wb_wakeup_delayed(wb);
return;
}
@@ -2578,7 +2579,7 @@ int write_inode_now(struct inode *inode, int sync)
.range_end = LLONG_MAX,
};
 
-   if (!mapping_cap_writeback_dirty(inode->i_mapping))
+   if (!mapping_can_writeback(inode->i_mapping))
wbc.nr_to_write = 0;
 
might_sleep();
diff --git a/include/linux/backing-dev.h b/include/linux/backing-dev.h
index b217344a2c63be..44df4fcef65c1e 100644
--- a/include/linux/backing-dev.h
+++ b/include/linux/backing-dev.h
@@ -110,27 +110,14 @@ int bdi_set_max_ratio(struct backing_dev_info *bdi, 
unsigned int max_ratio);
 /*
  * Flags in backing_dev_info::capability
  *
- * The first three flags control whether dirty pages will contribute to the
- * VM's accounting and whether writepages() should be called for dirty pages
- * (something that would not, for example, be appropriate for ramfs)
- *
- * WARNING: these flags are closely related and should not normally be
- * used separately.  The BDI_CAP_NO_ACCT_AND_WRITEBACK combines these
- * three flags into a single convenience macro.
- *
- * BDI_CAP_NO_ACCT_DIRTY:  Dirty pages shouldn't contribute to accounting
- * BDI_CAP_NO_WRITEBACK:   Don't write pages back
- * BDI_CAP_WRITEBACK_ACCT: Automatically account writeback pages
- * BDI_CAP_STRICTLIMIT:Keep number of dirty pages below bdi threshold.
+ * BDI_CAP_WRITEBACK:  Supports dirty page writeback, and dirty pages
+ * should contribute to accounting
+ * BDI_CAP_WRITEBACK_ACCT: Automatically account writeback pages
+ * BDI_CAP_STRICTLIMIT:Keep number of dirty pages below bdi 
threshold
  */
-#define BDI_CAP_NO_ACCT_DIRTY  0x0001
-#define BDI_CAP_NO_WRITEBACK   0x0002
-#define BDI_CAP_WRITEBACK_ACCT 0x0004
-#define BDI_CAP_STRICTLIMIT0x0010
-#define BDI_CAP_CGROUP_WRITEBACK 0x0020
-
-#define BDI_CAP_NO_ACCT_AND_WRITEBACK \
-   (BDI_CAP_NO_WRITEBACK | BDI_CAP_NO_ACCT_DIRTY)
+#define BDI_CAP_WRITEBACK  (1 << 0)
+#define BDI_CAP_WRITEBACK_ACCT (1 << 1)
+#define BDI_CAP_STRICTLIMIT(1 << 2)
 
 extern struct backing_dev_info noop_backing_dev_info;
 
@@ -169,24 +156,9 @@ static inline int wb_congested(struct bdi_writeback *wb, 
int cong_bits)
 long congestion_wait(int sync, long timeout);
 long wait_iff_congested(int sync, long timeout);
 
-static inline bool bdi_cap_writeback_dirty(struct backing_dev_info *bdi)
-{
-   return !(bdi->capabilities & BDI_CAP_NO_WRITEBACK);
-}
-
-static inline bool bdi_cap_account_dirty(struct backing_dev_info *bdi)
-{
-   return !(bdi->capabilities & BDI_CAP_NO_ACCT_DIRTY);
-}
-
-static inline bool mapping_cap_writeback_dirty(struct address_space *mapping)
-{
-

[PATCH 01/14] fs: remove the unused SB_I_MULTIROOT flag

The last user of SB_I_MULTIROOT is disappeared with commit f2aedb713c28
("NFS: Add fs_context support.")

Signed-off-by: Christoph Hellwig 
Reviewed-by: Johannes Thumshirn 
---
 fs/namei.c | 4 ++--
 include/linux/fs.h | 1 -
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/fs/namei.c b/fs/namei.c
index 72d4219c93acb7..e9ff0d54a110a7 100644
--- a/fs/namei.c
+++ b/fs/namei.c
@@ -568,8 +568,8 @@ static bool path_connected(struct vfsmount *mnt, struct 
dentry *dentry)
 {
struct super_block *sb = mnt->mnt_sb;
 
-   /* Bind mounts and multi-root filesystems can have disconnected paths */
-   if (!(sb->s_iflags & SB_I_MULTIROOT) && (mnt->mnt_root == sb->s_root))
+   /* Bind mounts can have disconnected paths */
+   if (mnt->mnt_root == sb->s_root)
return true;
 
return is_subdir(dentry, mnt->mnt_root);
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 41cd993ec0f686..236543605dd118 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -1366,7 +1366,6 @@ extern int send_sigurg(struct fown_struct *fown);
 #define SB_I_CGROUPWB  0x0001  /* cgroup-aware writeback enabled */
 #define SB_I_NOEXEC0x0002  /* Ignore executables on this fs */
 #define SB_I_NODEV 0x0004  /* Ignore devices on this fs */
-#define SB_I_MULTIROOT 0x0008  /* Multiple roots to the dentry tree */
 
 /* sb->s_iflags to limit user namespace mounts */
 #define SB_I_USERNS_VISIBLE0x0010 /* fstype already mounted */
-- 
2.27.0

[PATCH 06/14] block: lift setting the readahead size into the block layer

Drivers shouldn't really mess with the readahead size, as that is a VM
concept.  Instead set it based on the optimal I/O size by lifting the
algorithm from the md driver when registering the disk.  Also set
bdi->io_pages there as well by applying the same scheme based on
max_sectors.

Signed-off-by: Christoph Hellwig 
---
 block/blk-settings.c |  5 ++---
 block/blk-sysfs.c|  1 -
 block/genhd.c| 13 +++--
 drivers/block/aoe/aoeblk.c   |  2 --
 drivers/block/drbd/drbd_nl.c | 12 +---
 drivers/md/bcache/super.c|  4 
 drivers/md/dm-table.c|  3 ---
 drivers/md/raid0.c   | 16 
 drivers/md/raid10.c  | 24 +---
 drivers/md/raid5.c   | 13 +
 10 files changed, 16 insertions(+), 77 deletions(-)

diff --git a/block/blk-settings.c b/block/blk-settings.c
index 76a7e03bcd6cac..01049e9b998f1d 100644
--- a/block/blk-settings.c
+++ b/block/blk-settings.c
@@ -452,6 +452,8 @@ EXPORT_SYMBOL(blk_limits_io_opt);
 void blk_queue_io_opt(struct request_queue *q, unsigned int opt)
 {
blk_limits_io_opt(>limits, opt);
+   q->backing_dev_info->ra_pages =
+   max(queue_io_opt(q) * 2 / PAGE_SIZE, VM_READAHEAD_PAGES);
 }
 EXPORT_SYMBOL(blk_queue_io_opt);
 
@@ -628,9 +630,6 @@ void disk_stack_limits(struct gendisk *disk, struct 
block_device *bdev,
printk(KERN_NOTICE "%s: Warning: Device %s is misaligned\n",
   top, bottom);
}
-
-   t->backing_dev_info->io_pages =
-   t->limits.max_sectors >> (PAGE_SHIFT - 9);
 }
 EXPORT_SYMBOL(disk_stack_limits);
 
diff --git a/block/blk-sysfs.c b/block/blk-sysfs.c
index 7dda709f3ccb6f..ce418d9128a0b2 100644
--- a/block/blk-sysfs.c
+++ b/block/blk-sysfs.c
@@ -245,7 +245,6 @@ queue_max_sectors_store(struct request_queue *q, const char 
*page, size_t count)
 
spin_lock_irq(>queue_lock);
q->limits.max_sectors = max_sectors_kb << 1;
-   q->backing_dev_info->io_pages = max_sectors_kb >> (PAGE_SHIFT - 10);
spin_unlock_irq(>queue_lock);
 
return ret;
diff --git a/block/genhd.c b/block/genhd.c
index 8b1e9f48957cb5..097d4e4bc0b8a2 100644
--- a/block/genhd.c
+++ b/block/genhd.c
@@ -775,6 +775,7 @@ static void __device_add_disk(struct device *parent, struct 
gendisk *disk,
  const struct attribute_group **groups,
  bool register_queue)
 {
+   struct request_queue *q = disk->queue;
dev_t devt;
int retval;
 
@@ -785,7 +786,7 @@ static void __device_add_disk(struct device *parent, struct 
gendisk *disk,
 * registration.
 */
if (register_queue)
-   elevator_init_mq(disk->queue);
+   elevator_init_mq(q);
 
/* minors == 0 indicates to use ext devt from part0 and should
 * be accompanied with EXT_DEVT flag.  Make sure all
@@ -815,10 +816,18 @@ static void __device_add_disk(struct device *parent, 
struct gendisk *disk,
disk->flags |= GENHD_FL_SUPPRESS_PARTITION_INFO;
disk->flags |= GENHD_FL_NO_PART_SCAN;
} else {
-   struct backing_dev_info *bdi = disk->queue->backing_dev_info;
+   struct backing_dev_info *bdi = q->backing_dev_info;
struct device *dev = disk_to_dev(disk);
int ret;
 
+   /*
+* For read-ahead of large files to be effective, we need to
+* readahead at least twice the optimal I/O size.
+*/
+   bdi->ra_pages = max(queue_io_opt(q) * 2 / PAGE_SIZE,
+   VM_READAHEAD_PAGES);
+   bdi->io_pages = queue_max_sectors(q) >> (PAGE_SHIFT - 9);
+
/* Register BDI before referencing it from bdev */
dev->devt = devt;
ret = bdi_register(bdi, "%u:%u", MAJOR(devt), MINOR(devt));
diff --git a/drivers/block/aoe/aoeblk.c b/drivers/block/aoe/aoeblk.c
index 5ca7216e9e01f3..89b33b402b4e52 100644
--- a/drivers/block/aoe/aoeblk.c
+++ b/drivers/block/aoe/aoeblk.c
@@ -347,7 +347,6 @@ aoeblk_gdalloc(void *vp)
mempool_t *mp;
struct request_queue *q;
struct blk_mq_tag_set *set;
-   enum { KB = 1024, MB = KB * KB, READ_AHEAD = 2 * MB, };
ulong flags;
int late = 0;
int err;
@@ -407,7 +406,6 @@ aoeblk_gdalloc(void *vp)
WARN_ON(d->gd);
WARN_ON(d->flags & DEVFL_UP);
blk_queue_max_hw_sectors(q, BLK_DEF_MAX_SECTORS);
-   q->backing_dev_info->ra_pages = READ_AHEAD / PAGE_SIZE;
d->bufpool = mp;
d->blkq = gd->queue = q;
q->queuedata = d;
diff --git a/drivers/block/drbd/drbd_nl.c b/drivers/block/drbd/drbd_nl.c
index 650372ee2c7822..212bf711fb6b41 100644
--- a/drivers/block/drbd/drbd_nl.c
+++ b/drivers/block/drbd/drbd_nl.c
@@ -1360,18 +1360,8 @@ static void drbd_setup_queue_param(struct drbd_device 
*device,

bdi cleanups v3

Hi Jens,

this series contains a bunch of different BDI cleanups.  The biggest item
is to isolate block drivers from the BDI in preparation of changing the
lifetime of the block device BDI in a follow up series.


Changes since v2:
 - fix a rw_page return value check
 - fix various changelogs

Changes since v1:
 - rebased to the for-5.9/block-merge branch
 - explicitly set the readahead to 0 for ubifs, vboxsf and mtd
 - split the zram block_device operations
 - let rw_page users fall back to bios in swap_readpage


Diffstat:
 block/blk-core.c  |2 
 block/blk-integrity.c |4 
 block/blk-mq-debugfs.c|1 
 block/blk-settings.c  |5 
 block/blk-sysfs.c |  282 ++
 block/genhd.c |   13 +
 drivers/block/aoe/aoeblk.c|2 
 drivers/block/brd.c   |1 
 drivers/block/drbd/drbd_nl.c  |   18 --
 drivers/block/drbd/drbd_req.c |4 
 drivers/block/rbd.c   |2 
 drivers/block/zram/zram_drv.c |   19 +-
 drivers/md/bcache/super.c |4 
 drivers/md/dm-table.c |9 -
 drivers/md/raid0.c|   16 --
 drivers/md/raid10.c   |   46 ++
 drivers/md/raid5.c|   31 +---
 drivers/mmc/core/queue.c  |3 
 drivers/mtd/mtdcore.c |1 
 drivers/nvdimm/btt.c  |2 
 drivers/nvdimm/pmem.c |1 
 drivers/nvme/host/core.c  |3 
 drivers/nvme/host/multipath.c |   10 -
 drivers/scsi/iscsi_tcp.c  |4 
 fs/9p/vfs_file.c  |2 
 fs/9p/vfs_super.c |4 
 fs/afs/super.c|1 
 fs/btrfs/disk-io.c|2 
 fs/fs-writeback.c |7 -
 fs/fuse/inode.c   |4 
 fs/namei.c|4 
 fs/nfs/super.c|9 -
 fs/super.c|2 
 fs/ubifs/super.c  |1 
 fs/vboxsf/super.c |1 
 include/linux/backing-dev.h   |   78 +--
 include/linux/blkdev.h|3 
 include/linux/drbd.h  |1 
 include/linux/fs.h|2 
 mm/backing-dev.c  |   12 -
 mm/filemap.c  |4 
 mm/memcontrol.c   |2 
 mm/memory-failure.c   |2 
 mm/migrate.c  |2 
 mm/mmap.c |2 
 mm/page-writeback.c   |   18 +-
 mm/page_io.c  |   18 +-
 mm/swapfile.c |4 
 48 files changed, 204 insertions(+), 464 deletions(-)

[PATCH 03/14] drbd: remove RB_CONGESTED_REMOTE

This case isn't ever used.

Signed-off-by: Christoph Hellwig 
Reviewed-by: Johannes Thumshirn 
---
 drivers/block/drbd/drbd_req.c | 4 
 include/linux/drbd.h  | 1 -
 2 files changed, 5 deletions(-)

diff --git a/drivers/block/drbd/drbd_req.c b/drivers/block/drbd/drbd_req.c
index 674be09b2da94a..4d944f2eb56efa 100644
--- a/drivers/block/drbd/drbd_req.c
+++ b/drivers/block/drbd/drbd_req.c
@@ -901,13 +901,9 @@ static bool drbd_may_do_local_read(struct drbd_device 
*device, sector_t sector,
 static bool remote_due_to_read_balancing(struct drbd_device *device, sector_t 
sector,
enum drbd_read_balancing rbm)
 {
-   struct backing_dev_info *bdi;
int stripe_shift;
 
switch (rbm) {
-   case RB_CONGESTED_REMOTE:
-   bdi = 
device->ldev->backing_bdev->bd_disk->queue->backing_dev_info;
-   return bdi_read_congested(bdi);
case RB_LEAST_PENDING:
return atomic_read(>local_cnt) >
atomic_read(>ap_pending_cnt) + 
atomic_read(>rs_pending_cnt);
diff --git a/include/linux/drbd.h b/include/linux/drbd.h
index 5755537b51b114..6a8286132751df 100644
--- a/include/linux/drbd.h
+++ b/include/linux/drbd.h
@@ -94,7 +94,6 @@ enum drbd_read_balancing {
RB_PREFER_REMOTE,
RB_ROUND_ROBIN,
RB_LEAST_PENDING,
-   RB_CONGESTED_REMOTE,
RB_32K_STRIPING,
RB_64K_STRIPING,
RB_128K_STRIPING,
-- 
2.27.0

[PATCH 12/14] bdi: replace BDI_CAP_STABLE_WRITES with a queue and a sb flag

The BDI_CAP_STABLE_WRITES is one of the few bits of information in the
backing_dev_info shared between the block drivers and the writeback code.
To help untangling the dependency replace it with a queue flag and a
superblock flag derived from it.  This also helps with the case of e.g.
a file system requiring stable writes due to its own checksumming, but
not forcing it on other users of the block device like the swap code.

One downside is that we can't support the stable_pages_required bdi
attribute in sysfs anymore.  It is replaced with a queue attribute, that
can also be made writable for easier testing.

Signed-off-by: Christoph Hellwig 
---
 block/blk-integrity.c |  4 ++--
 block/blk-mq-debugfs.c|  1 +
 block/blk-sysfs.c |  2 ++
 drivers/block/rbd.c   |  2 +-
 drivers/block/zram/zram_drv.c |  2 +-
 drivers/md/dm-table.c |  6 +++---
 drivers/md/raid5.c|  8 
 drivers/mmc/core/queue.c  |  3 +--
 drivers/nvme/host/core.c  |  3 +--
 drivers/nvme/host/multipath.c | 10 +++---
 drivers/scsi/iscsi_tcp.c  |  4 ++--
 fs/super.c|  2 ++
 include/linux/backing-dev.h   |  6 --
 include/linux/blkdev.h|  3 +++
 include/linux/fs.h|  1 +
 mm/backing-dev.c  |  6 ++
 mm/page-writeback.c   |  2 +-
 mm/swapfile.c |  2 +-
 18 files changed, 31 insertions(+), 36 deletions(-)

diff --git a/block/blk-integrity.c b/block/blk-integrity.c
index c03705cbb9c9f2..2b36a8f9b81390 100644
--- a/block/blk-integrity.c
+++ b/block/blk-integrity.c
@@ -408,7 +408,7 @@ void blk_integrity_register(struct gendisk *disk, struct 
blk_integrity *template
bi->tuple_size = template->tuple_size;
bi->tag_size = template->tag_size;
 
-   disk->queue->backing_dev_info->capabilities |= BDI_CAP_STABLE_WRITES;
+   blk_queue_flag_set(QUEUE_FLAG_STABLE_WRITES, disk->queue);
 
 #ifdef CONFIG_BLK_INLINE_ENCRYPTION
if (disk->queue->ksm) {
@@ -428,7 +428,7 @@ EXPORT_SYMBOL(blk_integrity_register);
  */
 void blk_integrity_unregister(struct gendisk *disk)
 {
-   disk->queue->backing_dev_info->capabilities &= ~BDI_CAP_STABLE_WRITES;
+   blk_queue_flag_clear(QUEUE_FLAG_STABLE_WRITES, disk->queue);
memset(>queue->integrity, 0, sizeof(struct blk_integrity));
 }
 EXPORT_SYMBOL(blk_integrity_unregister);
diff --git a/block/blk-mq-debugfs.c b/block/blk-mq-debugfs.c
index 3f09bcb8a6fd7e..5a7d870eff2f89 100644
--- a/block/blk-mq-debugfs.c
+++ b/block/blk-mq-debugfs.c
@@ -116,6 +116,7 @@ static const char *const blk_queue_flag_name[] = {
QUEUE_FLAG_NAME(SAME_FORCE),
QUEUE_FLAG_NAME(DEAD),
QUEUE_FLAG_NAME(INIT_DONE),
+   QUEUE_FLAG_NAME(STABLE_WRITES),
QUEUE_FLAG_NAME(POLL),
QUEUE_FLAG_NAME(WC),
QUEUE_FLAG_NAME(FUA),
diff --git a/block/blk-sysfs.c b/block/blk-sysfs.c
index 9bb4e42fb73265..4a3799ed33f775 100644
--- a/block/blk-sysfs.c
+++ b/block/blk-sysfs.c
@@ -291,6 +291,7 @@ static struct queue_sysfs_entry queue_##_name##_entry = {   
\
 QUEUE_SYSFS_BIT_FNS(nonrot, NONROT, 1);
 QUEUE_SYSFS_BIT_FNS(random, ADD_RANDOM, 0);
 QUEUE_SYSFS_BIT_FNS(iostats, IO_STAT, 0);
+QUEUE_SYSFS_BIT_FNS(stable_writes, STABLE_WRITES, 0);
 #undef QUEUE_SYSFS_BIT_FNS
 
 static ssize_t queue_zoned_show(struct request_queue *q, char *page)
@@ -645,6 +646,7 @@ static struct attribute *queue_attrs[] = {
_nomerges_entry.attr,
_rq_affinity_entry.attr,
_iostats_entry.attr,
+   _stable_writes_entry.attr,
_random_entry.attr,
_poll_entry.attr,
_wc_entry.attr,
diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c
index 4f61e920946144..4a8515acccb3bf 100644
--- a/drivers/block/rbd.c
+++ b/drivers/block/rbd.c
@@ -5022,7 +5022,7 @@ static int rbd_init_disk(struct rbd_device *rbd_dev)
}
 
if (!ceph_test_opt(rbd_dev->rbd_client->client, NOCRC))
-   q->backing_dev_info->capabilities |= BDI_CAP_STABLE_WRITES;
+   blk_queue_flag_set(QUEUE_FLAG_STABLE_WRITES, q);
 
/*
 * disk_release() expects a queue ref from add_disk() and will
diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c
index d73ddf018fa65f..e6ed9c9f500a42 100644
--- a/drivers/block/zram/zram_drv.c
+++ b/drivers/block/zram/zram_drv.c
@@ -1954,7 +1954,7 @@ static int zram_add(void)
if (ZRAM_LOGICAL_BLOCK_SIZE == PAGE_SIZE)
blk_queue_max_write_zeroes_sectors(zram->disk->queue, UINT_MAX);
 
-   zram->disk->queue->backing_dev_info->capabilities |= 
BDI_CAP_STABLE_WRITES;
+   blk_queue_flag_set(QUEUE_FLAG_STABLE_WRITES, zram->disk->queue);
device_add_disk(NULL, zram->disk, zram_disk_attr_groups);
 
strlcpy(zram->compressor, default_compressor, sizeof(zram->compressor));
diff --git a/drivers/md/dm-table.c b/drivers/md/dm-table.c
index 324a42ed2f8894..e1adec51cb5b41 100644
--- a/drivers/md/dm-table.c
+++

[PATCH 13/14] bdi: invert BDI_CAP_NO_ACCT_WB

Replace BDI_CAP_NO_ACCT_WB with a positive BDI_CAP_WRITEBACK_ACCT to
make the checks more obvious.  Also remove the pointless
bdi_cap_account_writeback wrapper that just obsfucates the check.

Signed-off-by: Christoph Hellwig 
---
 fs/fuse/inode.c |  3 ++-
 include/linux/backing-dev.h | 13 +++--
 mm/backing-dev.c|  1 +
 mm/page-writeback.c |  4 ++--
 4 files changed, 8 insertions(+), 13 deletions(-)

diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c
index 17b00670fb539e..581329203d6860 100644
--- a/fs/fuse/inode.c
+++ b/fs/fuse/inode.c
@@ -1050,7 +1050,8 @@ static int fuse_bdi_init(struct fuse_conn *fc, struct 
super_block *sb)
return err;
 
/* fuse does it's own writeback accounting */
-   sb->s_bdi->capabilities = BDI_CAP_NO_ACCT_WB | BDI_CAP_STRICTLIMIT;
+   sb->s_bdi->capabilities &= ~BDI_CAP_WRITEBACK_ACCT;
+   sb->s_bdi->capabilities |= BDI_CAP_STRICTLIMIT;
 
/*
 * For a single fuse filesystem use max 1% of dirty +
diff --git a/include/linux/backing-dev.h b/include/linux/backing-dev.h
index 5da4ea3dd0cc5c..b217344a2c63be 100644
--- a/include/linux/backing-dev.h
+++ b/include/linux/backing-dev.h
@@ -120,17 +120,17 @@ int bdi_set_max_ratio(struct backing_dev_info *bdi, 
unsigned int max_ratio);
  *
  * BDI_CAP_NO_ACCT_DIRTY:  Dirty pages shouldn't contribute to accounting
  * BDI_CAP_NO_WRITEBACK:   Don't write pages back
- * BDI_CAP_NO_ACCT_WB: Don't automatically account writeback pages
+ * BDI_CAP_WRITEBACK_ACCT: Automatically account writeback pages
  * BDI_CAP_STRICTLIMIT:Keep number of dirty pages below bdi threshold.
  */
 #define BDI_CAP_NO_ACCT_DIRTY  0x0001
 #define BDI_CAP_NO_WRITEBACK   0x0002
-#define BDI_CAP_NO_ACCT_WB 0x0004
+#define BDI_CAP_WRITEBACK_ACCT 0x0004
 #define BDI_CAP_STRICTLIMIT0x0010
 #define BDI_CAP_CGROUP_WRITEBACK 0x0020
 
 #define BDI_CAP_NO_ACCT_AND_WRITEBACK \
-   (BDI_CAP_NO_WRITEBACK | BDI_CAP_NO_ACCT_DIRTY | BDI_CAP_NO_ACCT_WB)
+   (BDI_CAP_NO_WRITEBACK | BDI_CAP_NO_ACCT_DIRTY)
 
 extern struct backing_dev_info noop_backing_dev_info;
 
@@ -179,13 +179,6 @@ static inline bool bdi_cap_account_dirty(struct 
backing_dev_info *bdi)
return !(bdi->capabilities & BDI_CAP_NO_ACCT_DIRTY);
 }
 
-static inline bool bdi_cap_account_writeback(struct backing_dev_info *bdi)
-{
-   /* Paranoia: BDI_CAP_NO_WRITEBACK implies BDI_CAP_NO_ACCT_WB */
-   return !(bdi->capabilities & (BDI_CAP_NO_ACCT_WB |
- BDI_CAP_NO_WRITEBACK));
-}
-
 static inline bool mapping_cap_writeback_dirty(struct address_space *mapping)
 {
return bdi_cap_writeback_dirty(inode_to_bdi(mapping->host));
diff --git a/mm/backing-dev.c b/mm/backing-dev.c
index 41ec322090fca6..5f5958e1d39060 100644
--- a/mm/backing-dev.c
+++ b/mm/backing-dev.c
@@ -744,6 +744,7 @@ struct backing_dev_info *bdi_alloc(int node_id)
kfree(bdi);
return NULL;
}
+   bdi->capabilities = BDI_CAP_WRITEBACK_ACCT;
bdi->ra_pages = VM_READAHEAD_PAGES;
return bdi;
 }
diff --git a/mm/page-writeback.c b/mm/page-writeback.c
index 27a10536adad30..44c4a588f48df5 100644
--- a/mm/page-writeback.c
+++ b/mm/page-writeback.c
@@ -2740,7 +2740,7 @@ int test_clear_page_writeback(struct page *page)
if (ret) {
__xa_clear_mark(>i_pages, page_index(page),
PAGECACHE_TAG_WRITEBACK);
-   if (bdi_cap_account_writeback(bdi)) {
+   if (bdi->capabilities & BDI_CAP_WRITEBACK_ACCT) {
struct bdi_writeback *wb = inode_to_wb(inode);
 
dec_wb_stat(wb, WB_WRITEBACK);
@@ -2793,7 +2793,7 @@ int __test_set_page_writeback(struct page *page, bool 
keep_write)
   PAGECACHE_TAG_WRITEBACK);
 
xas_set_mark(, PAGECACHE_TAG_WRITEBACK);
-   if (bdi_cap_account_writeback(bdi))
+   if (bdi->capabilities & BDI_CAP_WRITEBACK_ACCT)
inc_wb_stat(inode_to_wb(inode), WB_WRITEBACK);
 
/*
-- 
2.27.0

[PATCH 09/14] bdi: remove BDI_CAP_CGROUP_WRITEBACK

Just checking SB_I_CGROUPWB for cgroup writeback support is enough.
Either the file system allocates its own bdi (e.g. btrfs), in which case
it is known to support cgroup writeback, or the bdi comes from the block
layer, which always supports cgroup writeback.

Signed-off-by: Christoph Hellwig 
Reviewed-by: Johannes Thumshirn 
---
 block/blk-core.c| 1 -
 fs/btrfs/disk-io.c  | 1 -
 include/linux/backing-dev.h | 8 +++-
 3 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/block/blk-core.c b/block/blk-core.c
index ea1665de7a2079..68db7e745b49dd 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -538,7 +538,6 @@ struct request_queue *blk_alloc_queue(int node_id)
if (!q->stats)
goto fail_stats;
 
-   q->backing_dev_info->capabilities = BDI_CAP_CGROUP_WRITEBACK;
q->node = node_id;
 
timer_setup(>backing_dev_info->laptop_mode_wb_timer,
diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
index f92c45fe019c48..4b5a8640329e4c 100644
--- a/fs/btrfs/disk-io.c
+++ b/fs/btrfs/disk-io.c
@@ -3032,7 +3032,6 @@ int __cold open_ctree(struct super_block *sb, struct 
btrfs_fs_devices *fs_device
goto fail_sb_buffer;
}
 
-   sb->s_bdi->capabilities |= BDI_CAP_CGROUP_WRITEBACK;
sb->s_bdi->ra_pages *= btrfs_super_num_devices(disk_super);
sb->s_bdi->ra_pages = max(sb->s_bdi->ra_pages, SZ_4M / PAGE_SIZE);
 
diff --git a/include/linux/backing-dev.h b/include/linux/backing-dev.h
index 0b06b2d26c9aa3..52583b6f2ea05d 100644
--- a/include/linux/backing-dev.h
+++ b/include/linux/backing-dev.h
@@ -123,7 +123,6 @@ int bdi_set_max_ratio(struct backing_dev_info *bdi, 
unsigned int max_ratio);
  * BDI_CAP_NO_ACCT_WB: Don't automatically account writeback pages
  * BDI_CAP_STRICTLIMIT:Keep number of dirty pages below bdi threshold.
  *
- * BDI_CAP_CGROUP_WRITEBACK: Supports cgroup-aware writeback.
  * BDI_CAP_SYNCHRONOUS_IO: Device is so fast that asynchronous IO would be
  *inefficient.
  */
@@ -233,9 +232,9 @@ int inode_congested(struct inode *inode, int cong_bits);
  * inode_cgwb_enabled - test whether cgroup writeback is enabled on an inode
  * @inode: inode of interest
  *
- * cgroup writeback requires support from both the bdi and filesystem.
- * Also, both memcg and iocg have to be on the default hierarchy.  Test
- * whether all conditions are met.
+ * Cgroup writeback requires support from the filesystem.  Also, both memcg and
+ * iocg have to be on the default hierarchy.  Test whether all conditions are
+ * met.
  *
  * Note that the test result may change dynamically on the same inode
  * depending on how memcg and iocg are configured.
@@ -247,7 +246,6 @@ static inline bool inode_cgwb_enabled(struct inode *inode)
return cgroup_subsys_on_dfl(memory_cgrp_subsys) &&
cgroup_subsys_on_dfl(io_cgrp_subsys) &&
bdi_cap_account_dirty(bdi) &&
-   (bdi->capabilities & BDI_CAP_CGROUP_WRITEBACK) &&
(inode->i_sb->s_iflags & SB_I_CGROUPWB);
 }
 
-- 
2.27.0

[PATCH 11/14] mm: use SWP_SYNCHRONOUS_IO more intelligently

There is no point in trying to call bdev_read_page if SWP_SYNCHRONOUS_IO
is not set, as the device won't support it.

Signed-off-by: Christoph Hellwig 
---
 mm/page_io.c | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/mm/page_io.c b/mm/page_io.c
index ccda7679008851..7eef3c84766abc 100644
--- a/mm/page_io.c
+++ b/mm/page_io.c
@@ -403,15 +403,17 @@ int swap_readpage(struct page *page, bool synchronous)
goto out;
}
 
-   ret = bdev_read_page(sis->bdev, swap_page_sector(page), page);
-   if (!ret) {
-   if (trylock_page(page)) {
-   swap_slot_free_notify(page);
-   unlock_page(page);
-   }
+   if (sis->flags & SWP_SYNCHRONOUS_IO) {
+   ret = bdev_read_page(sis->bdev, swap_page_sector(page), page);
+   if (!ret) {
+   if (trylock_page(page)) {
+   swap_slot_free_notify(page);
+   unlock_page(page);
+   }
 
-   count_vm_event(PSWPIN);
-   goto out;
+   count_vm_event(PSWPIN);
+   goto out;
+   }
}
 
ret = 0;
-- 
2.27.0

[PATCH 02/14] drbd: remove dead code in device_to_statistics

Ever since the switch to blk-mq, a lower device not used for VM
writeback will not be marked congested, so the check will never
trigger.

Signed-off-by: Christoph Hellwig 
---
 drivers/block/drbd/drbd_nl.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/block/drbd/drbd_nl.c b/drivers/block/drbd/drbd_nl.c
index d0d9a549b58388..650372ee2c7822 100644
--- a/drivers/block/drbd/drbd_nl.c
+++ b/drivers/block/drbd/drbd_nl.c
@@ -3370,7 +3370,6 @@ static void device_to_statistics(struct device_statistics 
*s,
if (get_ldev(device)) {
struct drbd_md *md = >ldev->md;
u64 *history_uuids = (u64 *)s->history_uuids;
-   struct request_queue *q;
int n;
 
spin_lock_irq(>uuid_lock);
@@ -3384,11 +3383,6 @@ static void device_to_statistics(struct 
device_statistics *s,
spin_unlock_irq(>uuid_lock);
 
s->dev_disk_flags = md->flags;
-   q = bdev_get_queue(device->ldev->backing_bdev);
-   s->dev_lower_blocked =
-   bdi_congested(q->backing_dev_info,
- (1 << WB_async_congested) |
- (1 << WB_sync_congested));
put_ldev(device);
}
s->dev_size = drbd_get_capacity(device->this_bdev);
-- 
2.27.0

[PATCH 04/14] bdi: initialize ->ra_pages in bdi_init