Re: [PATCH 2/4] pwm: atmel-tcb: Add .owner to struct pwm_ops
On 31/03/2013 05:15, Axel Lin wrote:
Add missing .owner of struct pwm_ops. This prevents the module from being
removed from underneath its users.
Signed-off-by: Axel Lin axel@ingics.com
Acked-by: Boris BREZILLON linux-...@overkiz.com
---
drivers/pwm/pwm-atmel-tcb.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
index 16cb530..0a7b658 100644
--- a/drivers/pwm/pwm-atmel-tcb.c
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -358,6 +358,7 @@ static const struct pwm_ops atmel_tcb_pwm_ops = {
.set_polarity = atmel_tcb_pwm_set_polarity,
.enable = atmel_tcb_pwm_enable,
.disable = atmel_tcb_pwm_disable,
+ .owner = THIS_MODULE,
};
static int atmel_tcb_pwm_probe(struct platform_device *pdev)
--
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[PATCH] ARM: at91/tc: fix clock source id for tc block 1
This patch fixes wrong clock request for TC block 2.
The second block was using t0_clk, t1_clk and t2_clk clks instead of
t3_clk, t4_clk and t5_clk clks.
Signed-off-by: Boris BREZILLON linux-...@overkiz.com
---
drivers/misc/atmel_tclib.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/misc/atmel_tclib.c b/drivers/misc/atmel_tclib.c
index c8d8e38..768a988 100644
--- a/drivers/misc/atmel_tclib.c
+++ b/drivers/misc/atmel_tclib.c
@@ -142,6 +142,8 @@ static int __init tc_probe(struct platform_device *pdev)
struct atmel_tc *tc;
struct clk *clk;
int irq;
+ charclk_id[7];
+ int clk_offset;
if (!platform_get_resource(pdev, IORESOURCE_MEM, 0))
return -EINVAL;
@@ -156,25 +158,31 @@ static int __init tc_probe(struct platform_device *pdev)
tc-pdev = pdev;
- clk = clk_get(pdev-dev, t0_clk);
- if (IS_ERR(clk)) {
- kfree(tc);
- return -EINVAL;
- }
-
/* Now take SoC information if available */
if (pdev-dev.of_node) {
const struct of_device_id *match;
match = of_match_node(atmel_tcb_dt_ids, pdev-dev.of_node);
if (match)
tc-tcb_config = match-data;
+ clk_offset = of_alias_get_id(tc-pdev-dev.of_node, tcb);
+ } else
+ clk_offset = pdev-id;
+ clk_offset *= 3;
+
+ snprintf(clk_id, sizeof(clk_id), t%d_clk, clk_offset++);
+ clk = clk_get(pdev-dev, clk_id);
+ if (IS_ERR(clk)) {
+ kfree(tc);
+ return -EINVAL;
}
tc-clk[0] = clk;
- tc-clk[1] = clk_get(pdev-dev, t1_clk);
+ snprintf(clk_id, sizeof(clk_id), t%d_clk, clk_offset++);
+ tc-clk[1] = clk_get(pdev-dev, clk_id);
if (IS_ERR(tc-clk[1]))
tc-clk[1] = clk;
- tc-clk[2] = clk_get(pdev-dev, t2_clk);
+ snprintf(clk_id, sizeof(clk_id), t%d_clk, clk_offset++);
+ tc-clk[2] = clk_get(pdev-dev, clk_id);
if (IS_ERR(tc-clk[2]))
tc-clk[2] = clk;
--
1.7.9.5
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[PATCH RESEND] pwm: pwm-atmel-tcb: pinctrl support
Setup tcb pins using pinctrl subsystem.
Signed-off-by: Boris BREZILLON linux-...@overkiz.com
---
drivers/pwm/pwm-atmel-tcb.c |9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
index 16cb530..985b7bf 100644
--- a/drivers/pwm/pwm-atmel-tcb.c
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -21,6 +21,7 @@
#include linux/pwm.h
#include linux/of_device.h
#include linux/slab.h
+#include linux/pinctrl/consumer.h
#define NPWM 6
@@ -365,6 +366,7 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev)
struct atmel_tcb_pwm_chip *tcbpwm;
struct device_node *np = pdev-dev.of_node;
struct atmel_tc *tc;
+ struct pinctrl *pinctrl;
int err;
int tcblock;
@@ -389,6 +391,13 @@ static int atmel_tcb_pwm_probe(struct platform_device
*pdev)
return -ENOMEM;
}
+ pinctrl = devm_pinctrl_get_select_default(pdev-dev);
+ if (IS_ERR(pinctrl)) {
+ atmel_tc_free(tc);
+ dev_err(pdev-dev, failed to get pinctrl config\n);
+ return PTR_ERR(pinctrl);
+ }
+
tcbpwm-chip.dev = pdev-dev;
tcbpwm-chip.ops = atmel_tcb_pwm_ops;
tcbpwm-chip.of_xlate = of_pwm_xlate_with_flags;
--
1.7.9.5
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Re: [PATCH] ARM: at91/tc: fix clock source id for tc block 1
On 03/04/2013 09:26, Nicolas Ferre wrote:
On 04/03/2013 06:45 AM, Jean-Christophe PLAGNIOL-VILLARD :
On 18:46 Tue 02 Apr , Boris BREZILLON wrote:
This patch fixes wrong clock request for TC block 2.
The second block was using t0_clk, t1_clk and t2_clk clks instead of
t3_clk, t4_clk and t5_clk clks.
this is intended as we have 3 clock per device
You're right.
True.
Boris, did you hit an issue with former code that your patch is solving?
What is the reason for this patch?
I should have taken a closer look at the code before sending this patch.
I mistook clk name for conid devid association.
As I am enabling the tc block 1 clocks in the bootstrap code, I thought
this was the reason for these clocks to be enabled after the kernel boot.
But I tried to disable these clocks in the bootstrap and this works fine.
Sorry if I bothered you.
Best Regards,
Boris
Thanks, best regards,
Signed-off-by: Boris BREZILLON linux-...@overkiz.com
---
drivers/misc/atmel_tclib.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/misc/atmel_tclib.c b/drivers/misc/atmel_tclib.c
index c8d8e38..768a988 100644
--- a/drivers/misc/atmel_tclib.c
+++ b/drivers/misc/atmel_tclib.c
@@ -142,6 +142,8 @@ static int __init tc_probe(struct platform_device *pdev)
struct atmel_tc *tc;
struct clk *clk;
int irq;
+ charclk_id[7];
+ int clk_offset;
if (!platform_get_resource(pdev, IORESOURCE_MEM, 0))
return -EINVAL;
@@ -156,25 +158,31 @@ static int __init tc_probe(struct platform_device *pdev)
tc-pdev = pdev;
- clk = clk_get(pdev-dev, t0_clk);
- if (IS_ERR(clk)) {
- kfree(tc);
- return -EINVAL;
- }
-
/* Now take SoC information if available */
if (pdev-dev.of_node) {
const struct of_device_id *match;
match = of_match_node(atmel_tcb_dt_ids, pdev-dev.of_node);
if (match)
tc-tcb_config = match-data;
+ clk_offset = of_alias_get_id(tc-pdev-dev.of_node, tcb);
+ } else
+ clk_offset = pdev-id;
+ clk_offset *= 3;
+
+ snprintf(clk_id, sizeof(clk_id), t%d_clk, clk_offset++);
+ clk = clk_get(pdev-dev, clk_id);
+ if (IS_ERR(clk)) {
+ kfree(tc);
+ return -EINVAL;
}
tc-clk[0] = clk;
- tc-clk[1] = clk_get(pdev-dev, t1_clk);
+ snprintf(clk_id, sizeof(clk_id), t%d_clk, clk_offset++);
+ tc-clk[1] = clk_get(pdev-dev, clk_id);
if (IS_ERR(tc-clk[1]))
tc-clk[1] = clk;
- tc-clk[2] = clk_get(pdev-dev, t2_clk);
+ snprintf(clk_id, sizeof(clk_id), t%d_clk, clk_offset++);
+ tc-clk[2] = clk_get(pdev-dev, clk_id);
if (IS_ERR(tc-clk[2]))
tc-clk[2] = clk;
--
1.7.9.5
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[PATCH 1/1] pwm: atmel: add Timer Counter Block PWM driver
Add TCB PWM driver.
Add device tree binding.
Signed-off-by: Boris BREZILLON linux-...@overkiz.com
--
create mode 100644 Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
create mode 100644 drivers/pwm/pwm-atmel-tcb.c
diff --git a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
new file mode 100644
index 000..7644889
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
@@ -0,0 +1,15 @@
+Atmel TCB PWM controller
+
+Required properties:
+- compatible: should be atmel,tcb-pwm
+- #pwm-cells: should be 2. The first cell specifies the per-chip index
+ of the PWM to use and the second cell is the period in nanoseconds.
+- atmel,tc-block: the Timer Counter block to use as a PWM chip.
+
+Example:
+
+pwm: pwm@80064000 {
+ compatible = fsl,imx28-pwm, fsl,imx23-pwm;
+ #pwm-cells = 2;
+ atmel,tc-block = 1;
+};
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index e513cd9..bda52f7 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -37,6 +37,14 @@ config PWM_AB8500
To compile this driver as a module, choose M here: the module
will be called pwm-ab8500.
+config PWM_ATMEL_TCB
+ bool TC Block PWM
+ depends on ATMEL_TCLIB
+ select HAVE_PWM
+ default y
+ help
+ Select this to get 6 PWM devices.
+
config PWM_BFIN
tristate Blackfin PWM support
depends on BFIN_GPTIMERS
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 62a2963..94ba21e 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_PWM) += core.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
+obj-$(CONFIG_PWM_ATMEL_TCB)+= pwm-atmel-tcb.o
obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o
obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
new file mode 100644
index 000..d5a87cc
--- /dev/null
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (C) Overkiz SAS 2012
+ *
+ * Author: Boris BREZILLON b.brezil...@overkiz.com
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#include linux/module.h
+#include linux/init.h
+#include linux/clocksource.h
+#include linux/clockchips.h
+#include linux/interrupt.h
+#include linux/irq.h
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/ioport.h
+#include linux/io.h
+#include linux/platform_device.h
+#include linux/atmel_tc.h
+#include linux/pwm.h
+#include linux/of_device.h
+#include linux/slab.h
+
+#define NPWM 6
+
+struct atmel_tcb_pwm_device {
+ u8 polarity : 1;
+ u8 clk : 3;
+ u32 duty;
+ u32 period;
+};
+
+struct atmel_tcb_pwm_chip {
+ struct pwm_chip chip;
+ spinlock_t lock;
+ struct atmel_tc *tc;
+ struct atmel_tcb_pwm_device pwms[NPWM];
+};
+
+static inline struct atmel_tcb_pwm_chip *to_atmel_tcb_pwm_chip(struct pwm_chip
*chip)
+{
+ return container_of(chip, struct atmel_tcb_pwm_chip, chip);
+}
+
+static int atmel_tcb_pwm_set_polarity (struct pwm_chip *chip, struct
pwm_device *pwm,
+ enum pwm_polarity polarity)
+{
+ struct atmel_tcb_pwm_device *tcbpwm =
+ (struct atmel_tcb_pwm_device *)pwm_get_chip_data(pwm);
+
+ tcbpwm-polarity = polarity;
+
+ return 0;
+}
+
+static int atmel_tcb_pwm_request (struct pwm_chip *chip, struct pwm_device
*pwm)
+{
+ struct atmel_tcb_pwm_chip *tcbpwmc = to_atmel_tcb_pwm_chip(chip);
+ struct atmel_tcb_pwm_device *tcbpwm = (tcbpwmc-pwms[pwm-hwpwm]);
+ struct atmel_tc *tc = tcbpwmc-tc;
+ void __iomem *regs = tc-regs;
+ u32 reg;
+
+ pwm_set_chip_data(pwm, tcbpwm);
+ tcbpwm-polarity = PWM_POLARITY_NORMAL;
+ tcbpwm-duty = 0;
+ tcbpwm-period = 0;
+ tcbpwm-clk = 0;
+ spin_lock(tcbpwmc-lock);
+ reg = __raw_readl (regs + ATMEL_TC_REG(pwm-hwpwm / 2, CMR));
+ if (reg ATMEL_TC_WAVE) {
+ tcbpwm-duty = __raw_readl (regs + ((pwm-hwpwm % 2) ?
+ ATMEL_TC_REG(pwm-hwpwm / 2, RB) :
+ ATMEL_TC_REG(pwm-hwpwm / 2, RA)));
+
+
+ tcbpwm-clk = reg ATMEL_TC_TCCLKS;
+ tcbpwm-period = __raw_readl (regs + ATMEL_TC_REG(pwm-hwpwm /
2, RC));
+ reg = (ATMEL_TC_TCCLKS |
+ ATMEL_TC_ACPA | ATMEL_TC_ACPC | ATMEL_TC_AEEVT
| ATMEL_TC_ASWTRG |
+ ATMEL_TC_BCPB | ATMEL_TC_BCPC | ATMEL_TC_BEEVT
| ATMEL_TC_BSWTRG);
+ }
+ else
+ reg = 0;
+ reg |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
+ __raw_writel (reg, regs + ATMEL_TC_REG(pwm-hwpwm / 2, CMR));
+ spin_unlock(tcbpwmc-lock);
+
+ clk_enable (tc-clk[pwm-hwpwm / 2]);
+
+ return 0;
+}
+
+static void
[PATCH 0/1] pwm: atmel: TCB pwm driver
Hello, This patch adds support for Timer Counter Block PWM. TCB PWM chip provides 6 pwm devices. This PWM devices are grouped by 2 (0/1, 2/3 and 4/5). The PWM devices in a given group must use the same period_ns value. Regards, Boris -- Boris BREZILLON (1): pwm: atmel: add Timer Counter Block PWM driver .../devicetree/bindings/pwm/atmel-tcb-pwm.txt | 15 + drivers/pwm/Kconfig|8 + drivers/pwm/Makefile |1 + drivers/pwm/pwm-atmel-tcb.c| 335 4 files changed, 359 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt create mode 100644 drivers/pwm/pwm-atmel-tcb.c -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2] pwm: atmel: add Timer Counter Block PWM driver
Hello,
This patch adds a PWM driver based on Atmel Timer Counter Block.
Timer Counter Block is used in Waveform generator mode.
A Timer Counter Block provides up to 6 PWM devices grouped by 2:
* group 0 = PWM 0 and 1
* group 1 = PWM 1 and 2
* group 2 = PMW 3 and 4
PWM devices in a given group must be configured with the same
period value.
If a PWM device in a group tries to change the period value and
the other device is already configured with a different value an
error will be returned.
This driver requires device tree support.
The Timer Counter Block number used to create a PWM chip is
given by tc-block field in an atmel,pwm-tcb compatible node.
Regards,
Boris
Changes since v1:
- Fix device tree binding Documentation
- Fix Kconfig issues (missing OF dependency,
deprecated HAVE_PWM select, ...)
- Fix various coding style issues.
- Cleanup code and add some comments.
Signed-off-by: Boris BREZILLON linux-...@overkiz.com
---
create mode 100644 Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
create mode 100644 drivers/pwm/pwm-atmel-tcb.c
diff --git a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
new file mode 100644
index 000..3f0f0f6
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
@@ -0,0 +1,15 @@
+Atmel TCB PWM controller
+
+Required properties:
+- compatible: should be atmel,tcb-pwm
+- #pwm-cells: should be 2. The first cell specifies the per-chip index
+ of the PWM to use and the second cell is the period in nanoseconds.
+- tc-block: the Timer Counter block to use as a PWM chip.
+
+Example:
+
+pwm {
+ compatible = atmel,tcb-pwm;
+ #pwm-cells = 2;
+ tc-block = 1;
+};
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index e513cd9..2f4941b 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -37,6 +37,18 @@ config PWM_AB8500
To compile this driver as a module, choose M here: the module
will be called pwm-ab8500.
+config PWM_ATMEL_TCB
+ tristate TC Block PWM
+ depends on ATMEL_TCLIB OF
+ help
+ Generic PWM framework driver for Atmel Timer Counter Block.
+
+ A Timer Counter Block provides 6 PWM devices grouped by 2.
+ Devices in a given group must have the same period.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-atmel-tc.
+
config PWM_BFIN
tristate Blackfin PWM support
depends on BFIN_GPTIMERS
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 62a2963..94ba21e 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_PWM) += core.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
+obj-$(CONFIG_PWM_ATMEL_TCB)+= pwm-atmel-tcb.o
obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o
obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
new file mode 100644
index 000..5b24bdd
--- /dev/null
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -0,0 +1,433 @@
+/*
+ * Copyright (C) Overkiz SAS 2012
+ *
+ * Author: Boris BREZILLON b.brezil...@overkiz.com
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include linux/module.h
+#include linux/init.h
+#include linux/clocksource.h
+#include linux/clockchips.h
+#include linux/interrupt.h
+#include linux/irq.h
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/ioport.h
+#include linux/io.h
+#include linux/platform_device.h
+#include linux/atmel_tc.h
+#include linux/pwm.h
+#include linux/of_device.h
+#include linux/slab.h
+
+#define NPWM 6
+
+struct atmel_tcb_pwm_device {
+ enum pwm_polarity polarity; /* PWM polarity */
+ unsigned clk; /* PWM clock divisor */
+ unsigned duty; /* PWM duty expressed in clk cycles */
+ unsigned period; /* PWM period expressed in clk cycles */
+};
+
+struct atmel_tcb_pwm_chip {
+ struct pwm_chip chip;
+ spinlock_t lock;
+ struct atmel_tc *tc;
+ struct atmel_tcb_pwm_device *pwms[NPWM];
+};
+
+static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
+{
+ return container_of(chip, struct atmel_tcb_pwm_chip, chip);
+}
+
+static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ enum pwm_polarity polarity)
+{
+ struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
+
+ tcbpwm-polarity = polarity;
+
+ return 0;
+}
+
+static int atmel_tcb_pwm_request(struct pwm_chip *chip,
+ struct pwm_device *pwm)
+{
+ struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
+ struct atmel_tcb_pwm_device *tcbpwm;
+ struct atmel_tc *tc = tcbpwmc-tc;
+ void __iomem
Re: [PATCH v3] pwm: atmel: add Timer Counter Block PWM driver
On 19/12/2012 12:26, Thierry Reding wrote:
On Mon, Dec 17, 2012 at 12:13:30PM +0100, Boris BREZILLON wrote:
Hello,
This patch adds a PWM driver based on Atmel Timer Counter Block.
Timer Counter Block is used in Waveform generator mode.
A Timer Counter Block provides up to 6 PWM devices grouped by 2:
* group 0 = PWM 0 and 1
* group 1 = PWM 1 and 2
* group 2 = PMW 3 and 4
PWM devices in a given group must be configured with the same
period value.
If a PWM device in a group tries to change the period value and
the other device is already configured with a different value an
error will be returned.
This driver requires device tree support.
The Timer Counter Block number used to create a PWM chip is
given by tc-block field in an atmel,pwm-tcb compatible node.
The device tree binding says that the compatible value should be
atmel,tcb-pwm, not atmel,pwm-tcb.
diff --git a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
new file mode 100644
index 000..bd99fdd
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
@@ -0,0 +1,18 @@
+Atmel TCB PWM controller
+
+Required properties:
+- compatible: should be atmel,tcb-pwm
+- #pwm-cells: should be 3. The first cell specifies the per-chip index
Should be 3. Capital S since you terminate the sentence with a full
stop.
+ of the PWM to use, the second cell is the period in nanoseconds and
+ bit 0 in the third cell is used to encode the polarity of PWM output.
+ Set bit 0 of the third in PWM specifier to 1 for inverse polarity
of the third cell
+ set to 0 for normal polarity.
+- tc-block: the Timer Counter block to use as a PWM chip.
Also: The Timer Counter... because of the terminating full stop.
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index e513cd9..2f4941b 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -37,6 +37,18 @@ config PWM_AB8500
To compile this driver as a module, choose M here: the module
will be called pwm-ab8500.
+config PWM_ATMEL_TCB
+tristate TC Block PWM
+depends on ATMEL_TCLIB OF
+help
+ Generic PWM framework driver for Atmel Timer Counter Block.
+
+ A Timer Counter Block provides 6 PWM devices grouped by 2.
+ Devices in a given group must have the same period.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-atmel-tc.
The Makefile says it is called pwm-atmel-tc_b_.
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
[...]
+static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ enum pwm_polarity polarity)
The arguments are no longer properly aligned.
+static int atmel_tcb_pwm_request(struct pwm_chip *chip,
+ struct pwm_device *pwm)
Same here.
+} else
+cmr = 0;
+cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
There should be a blank line between the above two lines for better
readability.
+/* If duty is 0 reverse polarity */
+if (tcbpwm-duty == 0)
+polarity = !polarity;
+
+if (polarity == PWM_POLARITY_INVERSED) {
+if (index == 0)
+newcmr |= ATMEL_TC_ASWTRG_CLEAR;
+else
+newcmr |= ATMEL_TC_BSWTRG_CLEAR;
+} else {
+if (index == 0)
+newcmr |= ATMEL_TC_ASWTRG_SET;
+else
+newcmr |= ATMEL_TC_BSWTRG_SET;
+}
+
+spin_lock(tcbpwmc-lock);
+cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
+
+/* flush old setting */
+if (index == 0)
+cmr = ~(ATMEL_TC_ACPA | ATMEL_TC_ACPC |
+ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG);
+else
+cmr = ~(ATMEL_TC_BCPB | ATMEL_TC_BCPC |
+ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG);
These should be aligned differently:
cmr = ~(ATMEL_TC_ACPA | ATMEL_TC_ACPC | ATMEL_TC_AEEVT |
ATMEL_TC_ASWTRG);
Although maybe you should define a mask for this since you reuse the
exact same sequence in atmel_tcb_pwm_enable().
+
+/* configure new setting */
+cmr |= newcmr;
+__raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
I wonder why you bother setting newcmr and OR'ing it into cmr. Couldn't
you just mask all previous settings in cmr first, then OR the new bits?
I did this to keep the locked portion of code as small as possible:
I prepare the mask to apply to cmr register before getting the lock.
But I can do it this way if you prefer:
spin_lock(tcbpwmc-lock);
cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
/* flush old setting and set the new one */
if (index == 0
[PATCH v4] pwm: atmel: add Timer Counter Block PWM driver
Hi,
This patch adds a PWM driver based on Atmel Timer Counter Block.
Timer Counter Block is used in Waveform generator mode.
A Timer Counter Block provides up to 6 PWM devices grouped by 2:
* group 0 = PWM 0 and 1
* group 1 = PWM 1 and 2
* group 2 = PMW 3 and 4
PWM devices in a given group must be configured with the same
period value.
If a PWM device in a group tries to change the period value and
the other device is already configured with a different value an
error will be returned.
This driver requires device tree support.
The Timer Counter Block number used to create a PWM chip is
given by tc-block field in an atmel,tcb-pwm compatible node.
This patch was tested on kizbox board (at91sam9g20 SoC) with
pwm-leds.
Regards,
Boris
Signed-off-by: Boris BREZILLON linux-...@overkiz.com
---
Changes since v1:
- Fix device tree binding Documentation
- Fix Kconfig issues (missing OF dependency,
deprecated HAVE_PWM select, ...)
- Fix various coding style issues.
- Cleanup code and add some comments.
Changes since v2:
- Replace kzalloc/kfree with managed versions
(devm_kzalloc/devm_kfree).
- Add one cell to device tree binding to support polarity
flag.
- Replace min computation (2 div - 1 mul + 1 div).
Changes since v3:
- Fix device tree binding Documentation
- Fix Kconfig description
- Fix coding style issues (function parameters alignment)
- Replace 10 value with NSEC_PER_SEC macro
- Get rid of newcmr variable in enable/disable functions
- Remove unneeded devm_kfree
- Add missing atmel_tc_free
.../devicetree/bindings/pwm/atmel-tcb-pwm.txt | 18 +
drivers/pwm/Kconfig| 12 +
drivers/pwm/Makefile |1 +
drivers/pwm/pwm-atmel-tcb.c| 428
4 files changed, 459 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
create mode 100644 drivers/pwm/pwm-atmel-tcb.c
diff --git a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
new file mode 100644
index 000..de0eaed
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
@@ -0,0 +1,18 @@
+Atmel TCB PWM controller
+
+Required properties:
+- compatible: should be atmel,tcb-pwm
+- #pwm-cells: Should be 3. The first cell specifies the per-chip index
+ of the PWM to use, the second cell is the period in nanoseconds and
+ bit 0 in the third cell is used to encode the polarity of PWM output.
+ Set bit 0 of the third cell in PWM specifier to 1 for inverse polarity
+ set to 0 for normal polarity.
+- tc-block: The Timer Counter block to use as a PWM chip.
+
+Example:
+
+pwm {
+ compatible = atmel,tcb-pwm;
+ #pwm-cells = 3;
+ tc-block = 1;
+};
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index e513cd9..10b6afc 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -37,6 +37,18 @@ config PWM_AB8500
To compile this driver as a module, choose M here: the module
will be called pwm-ab8500.
+config PWM_ATMEL_TCB
+ tristate TC Block PWM
+ depends on ATMEL_TCLIB OF
+ help
+ Generic PWM framework driver for Atmel Timer Counter Block.
+
+ A Timer Counter Block provides 6 PWM devices grouped by 2.
+ Devices in a given group must have the same period.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-atmel-tcb.
+
config PWM_BFIN
tristate Blackfin PWM support
depends on BFIN_GPTIMERS
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 62a2963..94ba21e 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_PWM) += core.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
+obj-$(CONFIG_PWM_ATMEL_TCB)+= pwm-atmel-tcb.o
obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o
obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
new file mode 100644
index 000..c466a09
--- /dev/null
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -0,0 +1,428 @@
+/*
+ * Copyright (C) Overkiz SAS 2012
+ *
+ * Author: Boris BREZILLON b.brezil...@overkiz.com
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include linux/module.h
+#include linux/init.h
+#include linux/clocksource.h
+#include linux/clockchips.h
+#include linux/interrupt.h
+#include linux/irq.h
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/ioport.h
+#include linux/io.h
+#include linux/platform_device.h
+#include linux/atmel_tc.h
+#include linux/pwm.h
+#include linux/of_device.h
+#include linux/slab.h
+
+#define NPWM 6
+
+#define ATMEL_TC_ACMR_MASK
[PATCH v4 RESEND] pwm: atmel: add Timer Counter Block PWM driver
Hi,
Sorry for resend. The previous version still has alignment issues on
atmel_tcb_pwm_set_polarity, atmel_tcb_pwm_request and
atmel_tcb_pwm_config function parameters.
This patch adds a PWM driver based on Atmel Timer Counter Block.
Timer Counter Block is used in Waveform generator mode.
A Timer Counter Block provides up to 6 PWM devices grouped by 2:
* group 0 = PWM 0 and 1
* group 1 = PWM 1 and 2
* group 2 = PMW 3 and 4
PWM devices in a given group must be configured with the same
period value.
If a PWM device in a group tries to change the period value and
the other device is already configured with a different value an
error will be returned.
This driver requires device tree support.
The Timer Counter Block number used to create a PWM chip is
given by tc-block field in an atmel,tcb-pwm compatible node.
This patch was tested on kizbox board (at91sam9g20 SoC) with
pwm-leds.
Regards,
Boris
Signed-off-by: Boris BREZILLON linux-...@overkiz.com
---
Changes since v1:
- Fix device tree binding Documentation
- Fix Kconfig issues (missing OF dependency,
deprecated HAVE_PWM select, ...)
- Fix various coding style issues.
- Cleanup code and add some comments.
Changes since v2:
- Replace kzalloc/kfree with managed versions
(devm_kzalloc/devm_kfree).
- Add one cell to device tree binding to support polarity
flag.
- Replace min computation (2 div - 1 mul + 1 div).
Changes since v3:
- Fix device tree binding Documentation
- Fix Kconfig description
- Fix coding style issues (function parameters alignment)
- Replace 10 value with NSEC_PER_SEC macro
- Get rid of newcmr variable in enable/disable functions
- Remove unneeded devm_kfree
- Add missing atmel_tc_free
.../devicetree/bindings/pwm/atmel-tcb-pwm.txt | 18 +
drivers/pwm/Kconfig| 12 +
drivers/pwm/Makefile |1 +
drivers/pwm/pwm-atmel-tcb.c| 428
4 files changed, 459 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
create mode 100644 drivers/pwm/pwm-atmel-tcb.c
diff --git a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
new file mode 100644
index 000..de0eaed
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
@@ -0,0 +1,18 @@
+Atmel TCB PWM controller
+
+Required properties:
+- compatible: should be atmel,tcb-pwm
+- #pwm-cells: Should be 3. The first cell specifies the per-chip index
+ of the PWM to use, the second cell is the period in nanoseconds and
+ bit 0 in the third cell is used to encode the polarity of PWM output.
+ Set bit 0 of the third cell in PWM specifier to 1 for inverse polarity
+ set to 0 for normal polarity.
+- tc-block: The Timer Counter block to use as a PWM chip.
+
+Example:
+
+pwm {
+ compatible = atmel,tcb-pwm;
+ #pwm-cells = 3;
+ tc-block = 1;
+};
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index e513cd9..10b6afc 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -37,6 +37,18 @@ config PWM_AB8500
To compile this driver as a module, choose M here: the module
will be called pwm-ab8500.
+config PWM_ATMEL_TCB
+ tristate TC Block PWM
+ depends on ATMEL_TCLIB OF
+ help
+ Generic PWM framework driver for Atmel Timer Counter Block.
+
+ A Timer Counter Block provides 6 PWM devices grouped by 2.
+ Devices in a given group must have the same period.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-atmel-tcb.
+
config PWM_BFIN
tristate Blackfin PWM support
depends on BFIN_GPTIMERS
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 62a2963..94ba21e 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_PWM) += core.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
+obj-$(CONFIG_PWM_ATMEL_TCB)+= pwm-atmel-tcb.o
obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o
obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
new file mode 100644
index 000..4852f66
--- /dev/null
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -0,0 +1,428 @@
+/*
+ * Copyright (C) Overkiz SAS 2012
+ *
+ * Author: Boris BREZILLON b.brezil...@overkiz.com
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include linux/module.h
+#include linux/init.h
+#include linux/clocksource.h
+#include linux/clockchips.h
+#include linux/interrupt.h
+#include linux/irq.h
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/ioport.h
+#include linux/io.h
+#include linux
[PATCH v3] pwm: atmel: add Timer Counter Block PWM driver
Hello,
This patch adds a PWM driver based on Atmel Timer Counter Block.
Timer Counter Block is used in Waveform generator mode.
A Timer Counter Block provides up to 6 PWM devices grouped by 2:
* group 0 = PWM 0 and 1
* group 1 = PWM 1 and 2
* group 2 = PMW 3 and 4
PWM devices in a given group must be configured with the same
period value.
If a PWM device in a group tries to change the period value and
the other device is already configured with a different value an
error will be returned.
This driver requires device tree support.
The Timer Counter Block number used to create a PWM chip is
given by tc-block field in an atmel,pwm-tcb compatible node.
This patch was tested on kizbox board (at91sam9g20 SoC) with
pwm-leds.
Regards,
Boris
Signed-off-by: Boris BREZILLON linux-...@overkiz.com
---
Changes since v1:
- Fix device tree binding Documentation
- Fix Kconfig issues (missing OF dependency,
deprecated HAVE_PWM select, ...)
- Fix various coding style issues.
- Cleanup code and add some comments.
Changes since v2:
- Replace kzalloc/kfree with managed versions
(devm_kzalloc/devm_kfree).
- Add one cell to device tree binding to support polarity
flag.
- Replace min computation (2 div - 1 mul + 1 div).
.../devicetree/bindings/pwm/atmel-tcb-pwm.txt | 18 +
drivers/pwm/Kconfig| 12 +
drivers/pwm/Makefile |1 +
drivers/pwm/pwm-atmel-tcb.c| 437
4 files changed, 468 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
create mode 100644 drivers/pwm/pwm-atmel-tcb.c
diff --git a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
new file mode 100644
index 000..bd99fdd
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
@@ -0,0 +1,18 @@
+Atmel TCB PWM controller
+
+Required properties:
+- compatible: should be atmel,tcb-pwm
+- #pwm-cells: should be 3. The first cell specifies the per-chip index
+ of the PWM to use, the second cell is the period in nanoseconds and
+ bit 0 in the third cell is used to encode the polarity of PWM output.
+ Set bit 0 of the third in PWM specifier to 1 for inverse polarity
+ set to 0 for normal polarity.
+- tc-block: the Timer Counter block to use as a PWM chip.
+
+Example:
+
+pwm {
+ compatible = atmel,tcb-pwm;
+ #pwm-cells = 3;
+ tc-block = 1;
+};
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index e513cd9..2f4941b 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -37,6 +37,18 @@ config PWM_AB8500
To compile this driver as a module, choose M here: the module
will be called pwm-ab8500.
+config PWM_ATMEL_TCB
+ tristate TC Block PWM
+ depends on ATMEL_TCLIB OF
+ help
+ Generic PWM framework driver for Atmel Timer Counter Block.
+
+ A Timer Counter Block provides 6 PWM devices grouped by 2.
+ Devices in a given group must have the same period.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-atmel-tc.
+
config PWM_BFIN
tristate Blackfin PWM support
depends on BFIN_GPTIMERS
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 62a2963..94ba21e 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_PWM) += core.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
+obj-$(CONFIG_PWM_ATMEL_TCB)+= pwm-atmel-tcb.o
obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o
obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
new file mode 100644
index 000..cd343ee
--- /dev/null
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -0,0 +1,437 @@
+/*
+ * Copyright (C) Overkiz SAS 2012
+ *
+ * Author: Boris BREZILLON b.brezil...@overkiz.com
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include linux/module.h
+#include linux/init.h
+#include linux/clocksource.h
+#include linux/clockchips.h
+#include linux/interrupt.h
+#include linux/irq.h
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/ioport.h
+#include linux/io.h
+#include linux/platform_device.h
+#include linux/atmel_tc.h
+#include linux/pwm.h
+#include linux/of_device.h
+#include linux/slab.h
+
+#define NPWM 6
+
+struct atmel_tcb_pwm_device {
+ enum pwm_polarity polarity; /* PWM polarity */
+ unsigned clk; /* PWM clock divisor */
+ unsigned duty; /* PWM duty expressed in clk cycles */
+ unsigned period; /* PWM period expressed in clk cycles */
+};
+
+struct atmel_tcb_pwm_chip {
+ struct pwm_chip chip;
+ spinlock_t lock;
+ struct atmel_tc *tc;
+ struct
Re: [PATCH v4 RESEND] pwm: atmel: add Timer Counter Block PWM driver
On 08/01/2013 08:10, Thierry Reding wrote:
On Thu, Dec 20, 2012 at 10:12:56AM +0100, Boris BREZILLON wrote:
Hi,
Sorry for resend. The previous version still has alignment issues on
atmel_tcb_pwm_set_polarity, atmel_tcb_pwm_request and
atmel_tcb_pwm_config function parameters.
This patch adds a PWM driver based on Atmel Timer Counter Block.
Timer Counter Block is used in Waveform generator mode.
A Timer Counter Block provides up to 6 PWM devices grouped by 2:
* group 0 = PWM 0 and 1
* group 1 = PWM 1 and 2
* group 2 = PMW 3 and 4
Should this be PWM 2 and 3 and PWM 4 and 5? Or is PWM 1 shared
between groups 0 and 1?
This is a mistake, this should be:
* group 0 = PWM 0 and 1
* group 1 = PWM 2 and 3
* group 2 = PMW 4 and 5
+static int atmel_tcb_pwm_request(struct pwm_chip *chip,
+ struct pwm_device *pwm)
+{
[...]
+clk_enable(tc-clk[group]);
You need to check the return value of clk_enable(). There's always a
small possibility that it may fail.
+static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device
*pwm)
+{
[...]
+/* If duty is 0 reverse polarity */
+if (tcbpwm-duty == 0)
+polarity = !polarity;
Rather than commenting on what the code does, this should say why it
does so.
Is this an acceptable explanation ?
/*
* If duty is 0 the timer will be stopped and we have to
* configure the output correctly on software trigger:
* - set output to high if PWM_POLARITY_INVERSED
* - set output to low if PWM_POLARITY_NORMAL
*
* This is why we're reverting polarity in this case.
*/
+static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device
*pwm)
+{
[...]
+/* If duty is 0 reverse polarity */
+if (tcbpwm-duty == 0)
+polarity = !polarity;
Same here.
+static int atmel_tcb_pwm_probe(struct platform_device *pdev)
+{
[...]
+struct atmel_tcb_pwm_chip *tcbpwm;
+struct device_node *np = pdev-dev.of_node;
+struct atmel_tc *tc;
+int err;
+int tcblock;
+
+err = of_property_read_u32(np, tc-block, tcblock);
+if (err 0) {
+dev_err(pdev-dev,
+failed to get tc block number from device tree (error:
%d)\n,
Maybe: failed to get Timer Counter Block number... to make it
consistent with the error message below:
+tc = atmel_tc_alloc(tcblock, tcb-pwm);
+if (tc == NULL) {
+dev_err(pdev-dev, failed to allocate Timer Counter Block\n);
+return -ENOMEM;
+}
[...]
+static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
+{ .compatible = atmel,tcb-pwm, },
+{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);
This is still wrong.
+static struct platform_driver atmel_tcb_pwm_driver = {
+.driver = {
+.name = atmel-tcb-pwm,
+.of_match_table = atmel_tcb_pwm_dt_ids,
+},
+.probe = atmel_tcb_pwm_probe,
+.remove = atmel_tcb_pwm_remove,
+};
+module_platform_driver(atmel_tcb_pwm_driver);
+
+MODULE_AUTHOR(Boris BREZILLON b.brezil...@overkiz.com);
+MODULE_DESCRIPTION(Atmel Timer Counter Pulse Width Modulation Driver);
+MODULE_ALIAS(platform:atmel-tcb-pwm);
I don't think you needMODULE_ALIAS() if the alias is the same as the
driver name.
Thierry
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Re: [PATCH v4 RESEND] pwm: atmel: add Timer Counter Block PWM driver
On 08/01/2013 08:10, Thierry Reding wrote:
On Thu, Dec 20, 2012 at 10:12:56AM +0100, Boris BREZILLON wrote:
Hi,
Sorry for resend. The previous version still has alignment issues on
atmel_tcb_pwm_set_polarity, atmel_tcb_pwm_request and
atmel_tcb_pwm_config function parameters.
This patch adds a PWM driver based on Atmel Timer Counter Block.
Timer Counter Block is used in Waveform generator mode.
A Timer Counter Block provides up to 6 PWM devices grouped by 2:
* group 0 = PWM 0 and 1
* group 1 = PWM 1 and 2
* group 2 = PMW 3 and 4
Should this be PWM 2 and 3 and PWM 4 and 5? Or is PWM 1 shared
between groups 0 and 1?
+static int atmel_tcb_pwm_request(struct pwm_chip *chip,
+ struct pwm_device *pwm)
+{
[...]
+clk_enable(tc-clk[group]);
You need to check the return value of clk_enable(). There's always a
small possibility that it may fail.
+static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device
*pwm)
+{
[...]
+/* If duty is 0 reverse polarity */
+if (tcbpwm-duty == 0)
+polarity = !polarity;
Rather than commenting on what the code does, this should say why it
does so.
+static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device
*pwm)
+{
[...]
+/* If duty is 0 reverse polarity */
+if (tcbpwm-duty == 0)
+polarity = !polarity;
Same here.
+static int atmel_tcb_pwm_probe(struct platform_device *pdev)
+{
[...]
+struct atmel_tcb_pwm_chip *tcbpwm;
+struct device_node *np = pdev-dev.of_node;
+struct atmel_tc *tc;
+int err;
+int tcblock;
+
+err = of_property_read_u32(np, tc-block, tcblock);
+if (err 0) {
+dev_err(pdev-dev,
+failed to get tc block number from device tree (error:
%d)\n,
Maybe: failed to get Timer Counter Block number... to make it
consistent with the error message below:
Do I have to break the error string so that the line does not exceed 80
characters ?
Checkpath script does not complain about it, and the CodingStyle file specify
that visible
strings should not be broken...
Same question applies to this error, which I converted to a multi-line error in
a previous patch version:
dev_err(chip-dev,
failed to configure period_ns:\n
the other PWM device in this group is already\n
configured with a different period_ns value\n);
+tc = atmel_tc_alloc(tcblock, tcb-pwm);
+if (tc == NULL) {
+dev_err(pdev-dev, failed to allocate Timer Counter Block\n);
+return -ENOMEM;
+}
[...]
+static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
+{ .compatible = atmel,tcb-pwm, },
+{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);
This is still wrong.
+static struct platform_driver atmel_tcb_pwm_driver = {
+.driver = {
+.name = atmel-tcb-pwm,
+.of_match_table = atmel_tcb_pwm_dt_ids,
+},
+.probe = atmel_tcb_pwm_probe,
+.remove = atmel_tcb_pwm_remove,
+};
+module_platform_driver(atmel_tcb_pwm_driver);
+
+MODULE_AUTHOR(Boris BREZILLON b.brezil...@overkiz.com);
+MODULE_DESCRIPTION(Atmel Timer Counter Pulse Width Modulation Driver);
+MODULE_ALIAS(platform:atmel-tcb-pwm);
I don't think you needMODULE_ALIAS() if the alias is the same as the
driver name.
Thierry
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[PATCH v5] pwm: atmel: add Timer Counter Block PWM driver
Hi,
This patch adds a PWM driver based on Atmel Timer Counter Block.
Timer Counter Block is used in Waveform generator mode.
A Timer Counter Block provides up to 6 PWM devices grouped by 2:
* group 0 = PWM 0 and 1
* group 1 = PWM 2 and 3
* group 2 = PMW 4 and 5
PWM devices in a given group must be configured with the same
period value.
If a PWM device in a group tries to change the period value and
the other device is already configured with a different value an
error will be returned.
This driver requires device tree support.
The Timer Counter Block number used to create a PWM chip is
given by tc-block field in an atmel,tcb-pwm compatible node.
This patch was tested on kizbox board (at91sam9g20 SoC) with
pwm-leds.
Regards,
Boris
Signed-off-by: Boris BREZILLON linux-...@overkiz.com
---
Changes since v1:
- Fix device tree binding Documentation
- Fix Kconfig issues (missing OF dependency,
deprecated HAVE_PWM select, ...)
- Fix various coding style issues.
- Cleanup code and add some comments.
Changes since v2:
- Replace kzalloc/kfree with managed versions
(devm_kzalloc/devm_kfree).
- Add one cell to device tree binding to support polarity
flag.
- Replace min computation (2 div - 1 mul + 1 div).
Changes since v3:
- Fix device tree binding Documentation
- Fix Kconfig description
- Fix coding style issues (function parameters alignment)
- Replace 10 value with NSEC_PER_SEC macro
- Get rid of newcmr variable in enable/disable functions
- Remove unneeded devm_kfree
- Add missing atmel_tc_free
Changes since v4:
- Add missing comments
- Fix coding style issues (multi-line error string)
- Fix wrong MODULE_DEVICE_TABLE setting
- Remove unneeded MODULE_ALIAS declaration
.../devicetree/bindings/pwm/atmel-tcb-pwm.txt | 18 +
drivers/pwm/Kconfig| 12 +
drivers/pwm/Makefile |1 +
drivers/pwm/pwm-atmel-tcb.c| 445
4 files changed, 476 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
create mode 100644 drivers/pwm/pwm-atmel-tcb.c
diff --git a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
new file mode 100644
index 000..de0eaed
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
@@ -0,0 +1,18 @@
+Atmel TCB PWM controller
+
+Required properties:
+- compatible: should be atmel,tcb-pwm
+- #pwm-cells: Should be 3. The first cell specifies the per-chip index
+ of the PWM to use, the second cell is the period in nanoseconds and
+ bit 0 in the third cell is used to encode the polarity of PWM output.
+ Set bit 0 of the third cell in PWM specifier to 1 for inverse polarity
+ set to 0 for normal polarity.
+- tc-block: The Timer Counter block to use as a PWM chip.
+
+Example:
+
+pwm {
+ compatible = atmel,tcb-pwm;
+ #pwm-cells = 3;
+ tc-block = 1;
+};
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index e513cd9..10b6afc 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -37,6 +37,18 @@ config PWM_AB8500
To compile this driver as a module, choose M here: the module
will be called pwm-ab8500.
+config PWM_ATMEL_TCB
+ tristate TC Block PWM
+ depends on ATMEL_TCLIB OF
+ help
+ Generic PWM framework driver for Atmel Timer Counter Block.
+
+ A Timer Counter Block provides 6 PWM devices grouped by 2.
+ Devices in a given group must have the same period.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-atmel-tcb.
+
config PWM_BFIN
tristate Blackfin PWM support
depends on BFIN_GPTIMERS
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 62a2963..94ba21e 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_PWM) += core.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
+obj-$(CONFIG_PWM_ATMEL_TCB)+= pwm-atmel-tcb.o
obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o
obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
new file mode 100644
index 000..16cb530
--- /dev/null
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -0,0 +1,445 @@
+/*
+ * Copyright (C) Overkiz SAS 2012
+ *
+ * Author: Boris BREZILLON b.brezil...@overkiz.com
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include linux/module.h
+#include linux/init.h
+#include linux/clocksource.h
+#include linux/clockchips.h
+#include linux/interrupt.h
+#include linux/irq.h
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/ioport.h
Re: [PATCH v5] pwm: atmel: add Timer Counter Block PWM driver
On 09/01/2013 08:46, Thierry Reding wrote: On Tue, Jan 08, 2013 at 04:36:42PM +0100, Boris BREZILLON wrote: Hi, This patch adds a PWM driver based on Atmel Timer Counter Block. Timer Counter Block is used in Waveform generator mode. A Timer Counter Block provides up to 6 PWM devices grouped by 2: * group 0 = PWM 0 and 1 * group 1 = PWM 2 and 3 * group 2 = PMW 4 and 5 PWM devices in a given group must be configured with the same period value. If a PWM device in a group tries to change the period value and the other device is already configured with a different value an error will be returned. This driver requires device tree support. The Timer Counter Block number used to create a PWM chip is given by tc-block field in an atmel,tcb-pwm compatible node. This patch was tested on kizbox board (at91sam9g20 SoC) with pwm-leds. Regards, Boris Signed-off-by: Boris BREZILLON linux-...@overkiz.com --- Changes since v1: - Fix device tree binding Documentation - Fix Kconfig issues (missing OF dependency, deprecated HAVE_PWM select, ...) - Fix various coding style issues. - Cleanup code and add some comments. Changes since v2: - Replace kzalloc/kfree with managed versions (devm_kzalloc/devm_kfree). - Add one cell to device tree binding to support polarity flag. - Replace min computation (2 div - 1 mul + 1 div). Changes since v3: - Fix device tree binding Documentation - Fix Kconfig description - Fix coding style issues (function parameters alignment) - Replace 10 value with NSEC_PER_SEC macro - Get rid of newcmr variable in enable/disable functions - Remove unneeded devm_kfree - Add missing atmel_tc_free Changes since v4: - Add missing comments - Fix coding style issues (multi-line error string) - Fix wrong MODULE_DEVICE_TABLE setting - Remove unneeded MODULE_ALIAS declaration .../devicetree/bindings/pwm/atmel-tcb-pwm.txt | 18 + drivers/pwm/Kconfig| 12 + drivers/pwm/Makefile |1 + drivers/pwm/pwm-atmel-tcb.c| 445 4 files changed, 476 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt create mode 100644 drivers/pwm/pwm-atmel-tcb.c Applied with minor changes to the commit message, thanks. Thierry Thanks -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: at91/dt: split sama5d3 definition
This patch splits the sama5d3 SoCs definition:
- a common base for all sama5d3 SoCs (sama5d3.dtsi)
- several optional peripheral definitions which will be included by sama5d3
specific SoCs (sama5d3_'periph name'.dtsi)
- sama5d3 specific SoC definitions (sama5d3x.dtsi)
This provides a better representation of the real hardware (drop unneed
dt nodes) and avoids peripheral id conflict (which is not the case for
current sama5d3 SoCs, but could be if other SoCs of this family are
released).
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/sama5d3.dtsi | 203 ---
arch/arm/boot/dts/sama5d31.dtsi | 16 +++
arch/arm/boot/dts/sama5d31ek.dts|3 +-
arch/arm/boot/dts/sama5d33.dtsi | 14 +++
arch/arm/boot/dts/sama5d33ek.dts|1 +
arch/arm/boot/dts/sama5d34.dtsi | 16 +++
arch/arm/boot/dts/sama5d34ek.dts|1 +
arch/arm/boot/dts/sama5d35.dtsi | 18
arch/arm/boot/dts/sama5d35ek.dts|1 +
arch/arm/boot/dts/sama5d3_can.dtsi | 54 ++
arch/arm/boot/dts/sama5d3_emac.dtsi | 44
arch/arm/boot/dts/sama5d3_gmac.dtsi | 77 +
arch/arm/boot/dts/sama5d3_lcd.dtsi | 55 ++
arch/arm/boot/dts/sama5d3_mci2.dtsi | 47
arch/arm/boot/dts/sama5d3_tcb1.dtsi | 27 +
arch/arm/boot/dts/sama5d3_uart.dtsi | 53 +
arch/arm/boot/dts/sama5d3xcm.dtsi |1 -
17 files changed, 426 insertions(+), 205 deletions(-)
create mode 100644 arch/arm/boot/dts/sama5d31.dtsi
create mode 100644 arch/arm/boot/dts/sama5d33.dtsi
create mode 100644 arch/arm/boot/dts/sama5d34.dtsi
create mode 100644 arch/arm/boot/dts/sama5d35.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_can.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_emac.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_gmac.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_lcd.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_mci2.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_tcb1.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_uart.dtsi
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index a1d5e25..b72f310 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -31,7 +31,6 @@
gpio3 = pioD;
gpio4 = pioE;
tcb0 = tcb0;
- tcb1 = tcb1;
i2c0 = i2c0;
i2c1 = i2c1;
i2c2 = i2c2;
@@ -100,15 +99,6 @@
status = disabled;
};
- can0: can@f000c000 {
- compatible = atmel,at91sam9x5-can;
- reg = 0xf000c000 0x300;
- interrupts = 40 IRQ_TYPE_LEVEL_HIGH 3;
- pinctrl-names = default;
- pinctrl-0 = pinctrl_can0_rx_tx;
- status = disabled;
- };
-
tcb0: timer@f001 {
compatible = atmel,at91sam9x5-tcb;
reg = 0xf001 0x100;
@@ -161,15 +151,6 @@
status = disabled;
};
- macb0: ethernet@f0028000 {
- compatible = cdns,pc302-gem, cdns,gem;
- reg = 0xf0028000 0x100;
- interrupts = 34 IRQ_TYPE_LEVEL_HIGH 3;
- pinctrl-names = default;
- pinctrl-0 = pinctrl_macb0_data_rgmii
pinctrl_macb0_signal_rgmii;
- status = disabled;
- };
-
isi: isi@f0034000 {
compatible = atmel,at91sam9g45-isi;
reg = 0xf0034000 0x4000;
@@ -190,19 +171,6 @@
#size-cells = 0;
};
- mmc2: mmc@f8004000 {
- compatible = atmel,hsmci;
- reg = 0xf8004000 0x600;
- interrupts = 23 IRQ_TYPE_LEVEL_HIGH 0;
- dmas = dma1 2 AT91_DMA_CFG_PER_ID(1);
- dma-names = rxtx;
- pinctrl-names = default;
- pinctrl-0 = pinctrl_mmc2_clk_cmd_dat0
pinctrl_mmc2_dat1_3;
- status = disabled;
- #address-cells = 1;
- #size-cells = 0;
- };
-
spi1: spi@f8008000 {
#address-cells = 1;
#size-cells = 0;
@@ -226,20 +194,6 @@
status = disabled
Re: [PATCH] ARM: at91/dt: split sam9x5 peripheral definitions
Hello Richard,
On 07/08/2013 12:38, Richard Genoud wrote:
2013/8/7 Boris BREZILLON b.brezil...@overkiz.com:
This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific
sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
This provides a better representation of the real hardware (drop unneeded
dt nodes) and avoids future peripheral id conflict (lcdc and isi both use
peripheral id 25).
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/at91sam9g25.dtsi |2 +
arch/arm/boot/dts/at91sam9g35.dtsi |1 +
arch/arm/boot/dts/at91sam9x25.dtsi | 24 ++-
arch/arm/boot/dts/at91sam9x35.dtsi |1 +
arch/arm/boot/dts/at91sam9x5.dtsi| 67 --
arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 56 +
arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 44
arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 51 +++
8 files changed, 158 insertions(+), 88 deletions(-)
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi
[snip]
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
new file mode 100644
index 000..5589579
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -0,0 +1,51 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 4 USART.
One minor comment mistake here !
Nice catch!
I'll fix it for the next version.
BTW did you test it (I didn't: I don't have any board with this SoC
family) ?
This separation was formerly done in the at91 common clk series but I
removed it
from the new version (which I will submit soon) to ease the review and
tests.
Best Regards,
Boris
+ *
+ * Copyright (C) 2013 Boris BREZILLON b.brezil...@overkiz.com
+ *
+ * Licensed under GPLv2.
+ */
+
+#include dt-bindings/pinctrl/at91.h
+#include dt-bindings/interrupt-controller/irq.h
+
+/ {
+ ahb {
+ apb {
+ pinctrl@f400 {
+ usart3 {
+ pinctrl_usart3: usart3-0 {
+ atmel,pins =
+ AT91_PIOC 22
AT91_PERIPH_B AT91_PINCTRL_PULL_UP/* PC22 periph B with pullup */
+AT91_PIOC 23
AT91_PERIPH_B AT91_PINCTRL_NONE; /* PC23 periph B */
+ };
+
+ pinctrl_usart3_rts: usart3_rts-0 {
+ atmel,pins =
+ AT91_PIOC 24
AT91_PERIPH_B AT91_PINCTRL_NONE; /* PC24 periph B */
+ };
+
+ pinctrl_usart3_cts: usart3_cts-0 {
+ atmel,pins =
+ AT91_PIOC 25
AT91_PERIPH_B AT91_PINCTRL_NONE; /* PC25 periph B */
+ };
+
+ pinctrl_usart3_sck: usart3_sck-0 {
+ atmel,pins =
+ AT91_PIOC 26
AT91_PERIPH_B AT91_PINCTRL_NONE; /* PC26 periph B */
+ };
+ };
+ };
+
+ usart3: serial@f8028000 {
+ compatible = atmel,at91sam9260-usart;
+ reg = 0xf8028000 0x200;
+ interrupts = 8 IRQ_TYPE_LEVEL_HIGH 5;
+ pinctrl-names = default;
+ pinctrl-0 = pinctrl_usart3;
+ status = disabled;
+ };
+ };
+ };
+};
--
1.7.9.5
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[PATCH] ARM: at91/dt: split sam9x5 peripheral definitions
This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific
sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
This provides a better representation of the real hardware (drop unneeded
dt nodes) and avoids future peripheral id conflict (lcdc and isi both use
peripheral id 25).
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/at91sam9g25.dtsi |2 +
arch/arm/boot/dts/at91sam9g35.dtsi |1 +
arch/arm/boot/dts/at91sam9x25.dtsi | 24 ++-
arch/arm/boot/dts/at91sam9x35.dtsi |1 +
arch/arm/boot/dts/at91sam9x5.dtsi| 67 --
arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 56 +
arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 44
arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 51 +++
8 files changed, 158 insertions(+), 88 deletions(-)
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi
b/arch/arm/boot/dts/at91sam9g25.dtsi
index b4ec6fe..17b8799 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -7,6 +7,8 @@
*/
#include at91sam9x5.dtsi
+#include at91sam9x5_usart3.dtsi
+#include at91sam9x5_macb0.dtsi
/ {
model = Atmel AT91SAM9G25 SoC;
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi
b/arch/arm/boot/dts/at91sam9g35.dtsi
index bebf9f5..e35c2fc 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -7,6 +7,7 @@
*/
#include at91sam9x5.dtsi
+#include at91sam9x5_macb0.dtsi
/ {
model = Atmel AT91SAM9G35 SoC;
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi
b/arch/arm/boot/dts/at91sam9x25.dtsi
index 49e94ab..c255421 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -7,6 +7,9 @@
*/
#include at91sam9x5.dtsi
+#include at91sam9x5_usart3.dtsi
+#include at91sam9x5_macb0.dtsi
+#include at91sam9x5_macb1.dtsi
/ {
model = Atmel AT91SAM9X25 SoC;
@@ -22,27 +25,6 @@
0x8000 0xfffd 0xb83f /*
pioC */
0x003f 0x003f8000 0x /*
pioD */
;
-
- macb1 {
- pinctrl_macb1_rmii: macb1_rmii-0 {
- atmel,pins =
- AT91_PIOC 16
AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
-AT91_PIOC 18
AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
-AT91_PIOC 19
AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
-AT91_PIOC 20
AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
-AT91_PIOC 21
AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
-AT91_PIOC 27
AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
-AT91_PIOC 28
AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
-AT91_PIOC 29
AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
-AT91_PIOC 30
AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
-AT91_PIOC 31
AT91_PERIPH_B AT91_PINCTRL_NONE; /* PC31 periph B */
- };
- };
- };
-
- macb1: ethernet@f803 {
- pinctrl-names = default;
- pinctrl-0 = pinctrl_macb1_rmii;
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi
b/arch/arm/boot/dts/at91sam9x35.dtsi
index 1a3d525..8eac66c 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -7,6 +7,7 @@
*/
#include at91sam9x5.dtsi
+#include at91sam9x5_macb0.dtsi
/ {
model = Atmel AT91SAM9X35 SoC;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi
b/arch/arm/boot/dts/at91sam9x5.dtsi
index 57d45f5..05f4c74 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -206,29 +206,6 @@
};
};
- usart3 {
- pinctrl_usart3: usart3
[PATCH] ARM: at91: add missing uart clocks DT entries
Add clocks to clock lookup table for uart DT entries.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/mach-at91/at91sam9x5.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 2abee66..916e5a1 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -227,6 +227,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID(usart, f802.serial, usart1_clk),
CLKDEV_CON_DEV_ID(usart, f8024000.serial, usart2_clk),
CLKDEV_CON_DEV_ID(usart, f8028000.serial, usart3_clk),
+ CLKDEV_CON_DEV_ID(usart, f804.serial, uart0_clk),
+ CLKDEV_CON_DEV_ID(usart, f8044000.serial, uart1_clk),
CLKDEV_CON_DEV_ID(t0_clk, f8008000.timer, tcb0_clk),
CLKDEV_CON_DEV_ID(t0_clk, f800c000.timer, tcb0_clk),
CLKDEV_CON_DEV_ID(mci_clk, f0008000.mmc, mmc0_clk),
--
1.7.9.5
--
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Re: [PATCH] ARM: at91/dt: split sam9x5 peripheral definitions
Hello Thomas, Sorry for the noise, this mail was filtered by LKML and LAKML beacause thunderbird added HTML contents. On 07/08/2013 18:08, Thomas Petazzoni wrote: Dear Boris BREZILLON, On Wed, 7 Aug 2013 12:14:26 +0200, Boris BREZILLON wrote: This patch splits the sam9x5 peripheral definitions into: - a common base for all sam9x5 SoCs (at91sam9x5.dtsi) - several optional peripheral definitions which will be included by specific sam9x5 SoCs (at91sam9x5_'periph name'.dtsi) This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25). Signed-off-by: Boris BREZILLONb.brezil...@overkiz.com --- arch/arm/boot/dts/at91sam9g25.dtsi |2 + arch/arm/boot/dts/at91sam9g35.dtsi |1 + arch/arm/boot/dts/at91sam9x25.dtsi | 24 ++- arch/arm/boot/dts/at91sam9x35.dtsi |1 + arch/arm/boot/dts/at91sam9x5.dtsi| 67 -- arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 56 + arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 44 arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 51 +++ 8 files changed, 158 insertions(+), 88 deletions(-) create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi Hum, do we really want to have .dtsi files per peripheral? I might have overlooked this, but I think it's the first time we would have this in arch/arm/boot/dts. It's not one .dtsi file for each available peripheral but for each **optional** peripheral (those which are not available for all sam9x5 SoCs). For example: macb0 is available in this SoCs: - 9g25 - 9g35 - 9x25 - 9x35 and not available in 9g15 SoC. And we have different combinatory for each of the optional devices. IMHO, defining the unneeded dt nodes in the common sam9x5.dtsi is a bad idea, because the dtb footprint will be bigger for SoC which does not have the optional peripherals and the dt hardware representation will be false. I see two options to solve this issue: 1) define a .dtsi file describing the optional peripherals and include these .dtsi in the SoC.dtsi file (as I proposed, but maybe the names are not appropriate) 2) copy the peripheral definitions in each SoC .dtsi file I prefer option 1) as it's safer than copying the definition (update of dtsi is easier and there is no risk to introduce a new bug when copying definitions). Please, tell me if you see other options, or if you think this issue should not be solved. Best Regards, Boris Thomas -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
On 26/07/2013 16:10, Richard Genoud wrote: On 17/07/2013 15:34, Boris BREZILLON wrote: Hello, This patch series is a proposal to move at91 clock implementation to common clk framework. Most of the clock provided by the PMC (Power Management Controller) are implemented : - main clock (main oscillator) - pll clocks - master clock - programmable clocks - utmi clock - peripheral clocks - system clocks This implementation is compatible with device tree: the goal is to define the whole clock tree in the device tree (all currently available dt SoCs and boards are patched to support dt clocks). Please feel free to comment the dt bindinds. I removed the register_clocks function in SoC supporting dt boards only: - at91sam9x5 SoCs - at91sam9n12 SoC - sama5d3 SoCs This patch series is based on linux-next and has been tested on sama5d31ek board using device tree. It compiles for other SoCs and both with and without dt support, but it has not been tested. BTW could other people test it on other boards (I only have a kizbox and a sama5d31ek dev kit). Best Regards, Boris Changes since v1: - fix bugs in pll, programmable and system clock implementations (wrong bit position). - add usb clock configuration support (ohci and udc drivers + clk_lookup for non dt boards) - rework of the system clock interfaces (no need to define a parent clock, system clock is a gate with no rate info) - change system, peripheral and programmable clk dt bindings (1 master node and multiple child nodes each defining a system/peripheral or prog clock) - fix bugs in sama5 dt definition Hi Boris, First of all: Big thumbs up for this work ! Then, I tested the serie on at91sam9g35ek (sam9x5 familly), and I see some problems: kernel is next-20130725 with the v4 serie of ARM: at91: prepare transition to common clk framework and v2 serie of ARM: at91: move to common clk framework [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 3.11.0-rc2-next-20130725+ (rgenoud@lnx-rg) (gcc version 4.7.3 (Buildroot 2013.05-00157-g6d1e60b-dirty) ) #61 Fri Jul 26 15:30:13 CEST 2013 [0.00] CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177 [0.00] CPU: VIVT data cache, VIVT instruction cache [0.00] Machine: Atmel AT91SAM (Device Tree), model: Atmel AT91SAM9G35-EK [0.00] bootconsole [earlycon0] enabled [0.00] Memory policy: ECC disabled, Data cache writeback [0.00] AT91: Detected soc type: at91sam9x5 [0.00] AT91: Detected soc subtype: at91sam9g35 [0.00] AT91: sram at 0x30 of 0x8000 mapped at 0xfef7 [0.00] On node 0 totalpages: 32768 [0.00] free_area_init_node: node 0, pgdat c039d208, node_mem_map c03b5000 [0.00] Normal zone: 256 pages used for memmap [0.00] Normal zone: 0 pages reserved [0.00] Normal zone: 32768 pages, LIFO batch:7 [0.00] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 [0.00] pcpu-alloc: [0] 0 [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 [0.00] Kernel command line: console=ttyS0,115200 loglevel=8 ip=dhcp root=/dev/nfs nfsroot=10.128.0.9:/nfsroot,v3 rw earlyprintk [0.00] PID hash table entries: 512 (order: -1, 2048 bytes) [0.00] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) [0.00] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) [0.00] Memory: 126044K/131072K available (2804K kernel code, 126K rwdata, 592K rodata, 141K init, 93K bss, 5028K reserved) [0.00] Virtual kernel memory layout: [0.00] vector : 0x - 0x1000 ( 4 kB) [0.00] fixmap : 0xfff0 - 0xfffe ( 896 kB) [0.00] vmalloc : 0xc880 - 0xff00 ( 872 MB) [0.00] lowmem : 0xc000 - 0xc800 ( 128 MB) [0.00] .text : 0xc0008000 - 0xc0359550 (3398 kB) [0.00] .init : 0xc035a000 - 0xc037d61c ( 142 kB) [0.00] .data : 0xc037e000 - 0xc039d920 ( 127 kB) [0.00].bss : 0xc039d920 - 0xc03b4ff4 ( 94 kB) [0.00] NR_IRQS:16 nr_irqs:16 16 [0.00] AT91: PIT: mck rate = 0 [0.00] [ cut here ] [0.00] WARNING: CPU: 0 PID: 0 at arch/arm/mach-at91/at91sam926x_time.c:259 at91sam926x_pit_init+0x114/0x234() [0.00] CPU: 0 PID: 0 Comm: swapper Not tainted 3.11.0-rc2-next-20130725+ #61 [0.00] [c000ca18] (unwind_backtrace+0x0/0xe0) from [c000b0f0] (show_stack+0x10/0x14) [0.00] [c000b0f0] (show_stack+0x10/0x14) from [c00144e0] (warn_slowpath_common+0x5c/0x7c) [0.00] [c00144e0] (warn_slowpath_common+0x5c/0x7c) from [c00145b8] (warn_slowpath_null+0x18/0x1c) [0.00] [c00145b8] (warn_slowpath_null+0x18/0x1c) from [c03607b0] (at91sam926x_pit_init+0x114/0x234) [0.00] [c03607b0] (at91sam926x_pit_init+0x114/0x234) from [c035ca4c] (time_init+0x1c
Re: [PATCH v2 02/42] ARM: at91: add PMC main clock
On 17/07/2013 15:40, Boris BREZILLON wrote:
This is the at91 main oscillator clock implementation using common
clk framework.
If rate is not provided during clock registraction it is computed using
the slow clock (main clk parent in this case) rate and the MCFR register.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/clk/at91/Makefile |5 ++
drivers/clk/at91/clk-main.c | 106 +++
include/linux/clk/at91.h| 10
3 files changed, 121 insertions(+)
create mode 100644 drivers/clk/at91/Makefile
create mode 100644 drivers/clk/at91/clk-main.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
new file mode 100644
index 000..42c084e
--- /dev/null
+++ b/drivers/clk/at91/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for at91 specific clk
+#
+
+obj-y += clk-main.o
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
new file mode 100644
index 000..738fa39
--- /dev/null
+++ b/drivers/clk/at91/clk-main.c
@@ -0,0 +1,106 @@
+/*
+ * drivers/clk/at91/clk-main.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON b.brezil...@overkiz.com
+ *
+ * This mainram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/clk/at91.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/io.h
+
+#define to_clk_main(hw) container_of(hw, struct clk_main, hw)
+struct clk_main {
+ struct clk_hw hw;
+ unsigned long rate;
+};
+
+static unsigned long clk_main_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ struct clk_main *clkmain = to_clk_main(hw);
+ if (clkmain-rate)
+ return clkmain-rate;
+ while ((tmp = at91_pmc_read(AT91_CKGR_MCFR)) AT91_PMC_MAINRDY)
+ ;
wrong test here, should be:
while (!((tmp = at91_pmc_read(AT91_CKGR_MCFR)) AT91_PMC_MAINRDY))
;
+ tmp = AT91_PMC_MAINF;
+ clkmain-rate = (tmp * parent_rate) / 16;
+ return clkmain-rate;
+}
+
+static const struct clk_ops main_ops = {
+ .recalc_rate = clk_main_recalc_rate,
+};
+
+struct clk * __init
+at91_clk_register_main(const char *name,
+ const char *parent_name,
+ unsigned long rate)
+{
+ struct clk_main *clkmain;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ if (!rate !parent_name)
+ return ERR_PTR(-EINVAL);
+
+ clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
+ if (!clkmain)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = main_ops;
+ init.parent_names = parent_name ? parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = parent_name ? 0 : CLK_IS_ROOT;
+
+ clkmain-hw.init = init;
+ clkmain-rate = rate;
+
+ clk = clk_register(NULL, clkmain-hw);
+
+ if (IS_ERR(clk))
+ kfree(clkmain);
+
+ return clk;
+}
+
+
+
+#if defined(CONFIG_OF)
+static void __init
+of_at91_clk_main_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np-name;
+ u32 rate = 0;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ of_property_read_string(np, clock-output-names, name);
+ of_property_read_u32(np, clock-frequency, rate);
+
+ clk = at91_clk_register_main(name, parent_name, rate);
+
+ if (!IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
+{
+ of_at91_clk_main_setup(np);
+}
+CLK_OF_DECLARE(at91rm9200_clk_main, atmel,at91rm9200-clk-main,
+ of_at91rm9200_clk_main_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 0ce9586..8e83942 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -16,6 +16,8 @@
#ifndef AT91_PMC_H
#define AT91_PMC_H
+#include linux/clk-provider.h
+
#ifndef __ASSEMBLY__
extern void __iomem *at91_pmc_base;
@@ -187,4 +189,12 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_PCR_DIV8 0x3
/* Peripheral clock is MCK/8 */
#define AT91_PMC_PCR_EN (0x128) /*
Enable */
+
+
+
+struct clk * __init
+at91_clk_register_main(const char *name,
+ const char *parent_name,
+ unsigned long rate);
+
#endif
--
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Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
On 26/07/2013 17:44, boris brezillon wrote: On 26/07/2013 16:10, Richard Genoud wrote: On 17/07/2013 15:34, Boris BREZILLON wrote: Hello, This patch series is a proposal to move at91 clock implementation to common clk framework. Most of the clock provided by the PMC (Power Management Controller) are implemented : - main clock (main oscillator) - pll clocks - master clock - programmable clocks - utmi clock - peripheral clocks - system clocks This implementation is compatible with device tree: the goal is to define the whole clock tree in the device tree (all currently available dt SoCs and boards are patched to support dt clocks). Please feel free to comment the dt bindinds. I removed the register_clocks function in SoC supporting dt boards only: - at91sam9x5 SoCs - at91sam9n12 SoC - sama5d3 SoCs This patch series is based on linux-next and has been tested on sama5d31ek board using device tree. It compiles for other SoCs and both with and without dt support, but it has not been tested. BTW could other people test it on other boards (I only have a kizbox and a sama5d31ek dev kit). Best Regards, Boris Changes since v1: - fix bugs in pll, programmable and system clock implementations (wrong bit position). - add usb clock configuration support (ohci and udc drivers + clk_lookup for non dt boards) - rework of the system clock interfaces (no need to define a parent clock, system clock is a gate with no rate info) - change system, peripheral and programmable clk dt bindings (1 master node and multiple child nodes each defining a system/peripheral or prog clock) - fix bugs in sama5 dt definition Hi Boris, First of all: Big thumbs up for this work ! Then, I tested the serie on at91sam9g35ek (sam9x5 familly), and I see some problems: kernel is next-20130725 with the v4 serie of ARM: at91: prepare transition to common clk framework and v2 serie of ARM: at91: move to common clk framework [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 3.11.0-rc2-next-20130725+ (rgenoud@lnx-rg) (gcc version 4.7.3 (Buildroot 2013.05-00157-g6d1e60b-dirty) ) #61 Fri Jul 26 15:30:13 CEST 2013 [0.00] CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177 [0.00] CPU: VIVT data cache, VIVT instruction cache [0.00] Machine: Atmel AT91SAM (Device Tree), model: Atmel AT91SAM9G35-EK [0.00] bootconsole [earlycon0] enabled [0.00] Memory policy: ECC disabled, Data cache writeback [0.00] AT91: Detected soc type: at91sam9x5 [0.00] AT91: Detected soc subtype: at91sam9g35 [0.00] AT91: sram at 0x30 of 0x8000 mapped at 0xfef7 [0.00] On node 0 totalpages: 32768 [0.00] free_area_init_node: node 0, pgdat c039d208, node_mem_map c03b5000 [0.00] Normal zone: 256 pages used for memmap [0.00] Normal zone: 0 pages reserved [0.00] Normal zone: 32768 pages, LIFO batch:7 [0.00] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 [0.00] pcpu-alloc: [0] 0 [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 [0.00] Kernel command line: console=ttyS0,115200 loglevel=8 ip=dhcp root=/dev/nfs nfsroot=10.128.0.9:/nfsroot,v3 rw earlyprintk [0.00] PID hash table entries: 512 (order: -1, 2048 bytes) [0.00] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) [0.00] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) [0.00] Memory: 126044K/131072K available (2804K kernel code, 126K rwdata, 592K rodata, 141K init, 93K bss, 5028K reserved) [0.00] Virtual kernel memory layout: [0.00] vector : 0x - 0x1000 ( 4 kB) [0.00] fixmap : 0xfff0 - 0xfffe ( 896 kB) [0.00] vmalloc : 0xc880 - 0xff00 ( 872 MB) [0.00] lowmem : 0xc000 - 0xc800 ( 128 MB) [0.00] .text : 0xc0008000 - 0xc0359550 (3398 kB) [0.00] .init : 0xc035a000 - 0xc037d61c ( 142 kB) [0.00] .data : 0xc037e000 - 0xc039d920 ( 127 kB) [0.00].bss : 0xc039d920 - 0xc03b4ff4 ( 94 kB) [0.00] NR_IRQS:16 nr_irqs:16 16 [0.00] AT91: PIT: mck rate = 0 [0.00] [ cut here ] [0.00] WARNING: CPU: 0 PID: 0 at arch/arm/mach-at91/at91sam926x_time.c:259 at91sam926x_pit_init+0x114/0x234() [0.00] CPU: 0 PID: 0 Comm: swapper Not tainted 3.11.0-rc2-next-20130725+ #61 [0.00] [c000ca18] (unwind_backtrace+0x0/0xe0) from [c000b0f0] (show_stack+0x10/0x14) [0.00] [c000b0f0] (show_stack+0x10/0x14) from [c00144e0] (warn_slowpath_common+0x5c/0x7c) [0.00] [c00144e0] (warn_slowpath_common+0x5c/0x7c) from [c00145b8] (warn_slowpath_null+0x18/0x1c) [0.00] [c00145b8] (warn_slowpath_null+0x18/0x1c) from [c03607b0] (at91sam926x_pit_init+0x114/0x234) [0.00] [c03607b0] (at91sam926x_pit_init+0x114/0x234) from
Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
Hello, This email is a feedback on the discussion I had with Jean-Christophe last Wednesday. As discussed with him, I will try to split this patch series in order to 1) limit the number of patches to review 2) limit the number of SoCs/boards to test The new at91 clk support on non-dt boards was also discussed, and Jean-Christophe thinks this is not mandatory (and should be dropped). Does anyone see an interest in keeping this support in the next version of the patch series ? Here is how he though this patch series could be splitted: 1) at91 common clk implemenations + 1 SoC and the associated dt boards 2) 1 SoC and the associated dt boards ...)1 SoC and the associated dt boards I tried to prepare the first new patch series by including only at91sam9260/9g20 SoCs and boards but I failed. In fact I succeed but it breaks multi-soc support (using dt) because we can't use both the common clk framework and the at91 specific clk framework (they both provides the same set of functions and structures definitions). Should I break the multi-soc support to add at91 common clk ? The only SoC that could be added without breaking multi-soc support is the sama5 as it uses a different arm architecture (ARMv7) and thus cannot be compiled in the same kernel as other at91 socs. Should I choose the sama5 for the next patch series ? Jean-Christophe, could you at least review the 11 first patches of this series ? I won't send any new version until I get some feedback from you on the clk implementations and dt bindings... Berst Regards, Boris Le 17/07/2013 15:34, Boris BREZILLON a écrit : Hello, This patch series is a proposal to move at91 clock implementation to common clk framework. Most of the clock provided by the PMC (Power Management Controller) are implemented : - main clock (main oscillator) - pll clocks - master clock - programmable clocks - utmi clock - peripheral clocks - system clocks This implementation is compatible with device tree: the goal is to define the whole clock tree in the device tree (all currently available dt SoCs and boards are patched to support dt clocks). Please feel free to comment the dt bindinds. I removed the register_clocks function in SoC supporting dt boards only: - at91sam9x5 SoCs - at91sam9n12 SoC - sama5d3 SoCs This patch series is based on linux-next and has been tested on sama5d31ek board using device tree. It compiles for other SoCs and both with and without dt support, but it has not been tested. BTW could other people test it on other boards (I only have a kizbox and a sama5d31ek dev kit). Best Regards, Boris Changes since v1: - fix bugs in pll, programmable and system clock implementations (wrong bit position). - add usb clock configuration support (ohci and udc drivers + clk_lookup for non dt boards) - rework of the system clock interfaces (no need to define a parent clock, system clock is a gate with no rate info) - change system, peripheral and programmable clk dt bindings (1 master node and multiple child nodes each defining a system/peripheral or prog clock) - fix bugs in sama5 dt definition Boris BREZILLON (42): ARM: at91: move at91_pmc.h to include/linux/clk/at91.h ARM: at91: add PMC main clock ARM: at91: add PMC pll clocks ARM: at91: add PMC master clock ARM: at91: add PMC system clocks ARM: at91: add PMC peripheral clocks ARM: at91: add PMC programmable clocks ARM: at91: add PMC utmi clock ARM: at91: add PMC usb clock ARM: at91: add PMC smd clock ARM: at91: add PMC clk device tree binding doc. ARM: at91: move to common clk framework ARM: at91: move at91rm9200 SoC to new at91 clk implem ARM: at91: move at91sam9260 SoC to new at91 clk implem ARM: at91: move at91sam9261 SoC to new at91 clk implem ARM: at91: move at91sam9263 SoC to new at91 clk implem ARM: at91: move at91sam9g45 SoC to new at91 clk implem ARM: at91: move at91sam9n12 SoC to new at91 clk implem ARM: at91: move at91sam9rl SoC to new at91 clk implem ARM: at91: move at91sam9x5 SoCs to new at91 clk implem ARM: at91: move at91sam9 SoCs to new at91 clk implem ARM: at91: move sama5d3 SoCs to new at91 clk implem ARM: at91: move at91rm9200 boards to new at91 clk implem ARM: at91: move at91sam9 boards to new at91 clk implem ARM: at91: move pit timer to common clk framework USB: ohci-at91: add usb_clk for transition to common clk framework usb: gadget: at91_udc: add usb_clk for transition to common clk framework ARM: at91/dt: move at91rm9200 SoC to new at91 clk implem ARM: at91/dt: move at91sam9260 SoC to new at91 clk implem ARM: at91/dt: move at91sam9263 SoC to new at91 clk implem ARM: at91/dt: move at91sam9g45 SoC to new at91 clk implem ARM: at91/dt: move at91sam9n12 SoC to new at91 clk implem ARM: at91/dt: move at91sam9x5 SoCs to new at91 clk implem ARM: at91/dt: move at91sam9g20 SoC to new at91 clk implem ARM: at91/dt: move sama5d3 SoCs to new
Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
On 29/07/2013 16:18, Richard Genoud wrote:
2013/7/29 boris brezillon b.brezil...@overkiz.com:
On 29/07/2013 10:00, Richard Genoud wrote:
2013/7/26 boris brezillon b.brezil...@overkiz.com:
On 26/07/2013 17:44, boris brezillon wrote:
I found 2 bugs:
1) the main frequency ready test in recalc_rate function is wrong
2) the common clk framework uses the first match for dt clk registration
and main clk has this compatible property:
compatible = atmel,at91rm9200-clk-main, fixed-clock;
As a result the main clk is always bound to the fixed-clock driver
which set the clock frequency to 0 if 'clock-frequency' property is
missing.
These bugs will be fixed in next version.
Tell me if you want need thesse patches for testing purpose.
Hi Boris,
I tested your patch, the clock is not at 0 anymore:
AT91: PIT: mck rate = 833
And it's booting correctly.
There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
not 27). (patch attached)
And yes, I could use your patches for some more tests !
Thanks,
Richard.
Hi Richard,
Thanks for the bug report.
You'll find in attachements the pre-v3 series fixing the detected bugs
(including the ssc clock id bug).
If you need anything else please let me know.
Working on sam9g35ek !
you can add my:
Tested-by: Richard Genoud richard.gen...@gmail.com
One remark though:
Maybe it would be interesting to keep using the defines in the device
tree for peripheral IDs.
For instance, in arch/arm/boot/dts/at91sam9x5.dtsi : (patch 33)
ssc_clk@28 {
id = 28;
};
May be more readable with the SSC id AT91SAM9X5_ID_SSC, as it was
defined in arch/arm/mach-at91/at91sam9x5.c (removed with patch 20)
IMHO, all AT91SAM9X5_ID_xxx in
arch/arm/mach-at91/include/mach/at91sam9x5.h can me moved in
include/dt-bindings/ and used in at91sam9x5.dtsi
This was requested by Jean-Christophe too.
I'll add these macro files and make use of it in next version.
BTW where should I put these macro files
(include/dt-bindings/at91/'soc-name'/peripherals.h) ?
Should I use macros for address fied of clocks or just for id property
(or drop the address) ?
ssc_clk@AT91SAM9X5_ID_SSC {
id = AT91SAM9X5_ID_SSC;
};
or
ssc_clk@28 {
id = AT91SAM9X5_ID_SSC;
};
or
ssc_clk {
id = AT91SAM9X5_ID_SSC;
};
Best regards,
Richard.
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Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
On 29/07/2013 17:09, Richard Genoud wrote:
2013/7/29 boris brezillon b.brezil...@overkiz.com:
On 29/07/2013 16:18, Richard Genoud wrote:
2013/7/29 boris brezillon b.brezil...@overkiz.com:
On 29/07/2013 10:00, Richard Genoud wrote:
2013/7/26 boris brezillon b.brezil...@overkiz.com:
On 26/07/2013 17:44, boris brezillon wrote:
I found 2 bugs:
1) the main frequency ready test in recalc_rate function is wrong
2) the common clk framework uses the first match for dt clk
registration
and main clk has this compatible property:
compatible = atmel,at91rm9200-clk-main, fixed-clock;
As a result the main clk is always bound to the fixed-clock driver
which set the clock frequency to 0 if 'clock-frequency' property
is
missing.
These bugs will be fixed in next version.
Tell me if you want need thesse patches for testing purpose.
Hi Boris,
I tested your patch, the clock is not at 0 anymore:
AT91: PIT: mck rate = 833
And it's booting correctly.
There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
not 27). (patch attached)
And yes, I could use your patches for some more tests !
Thanks,
Richard.
Hi Richard,
Thanks for the bug report.
You'll find in attachements the pre-v3 series fixing the detected bugs
(including the ssc clock id bug).
If you need anything else please let me know.
Working on sam9g35ek !
you can add my:
Tested-by: Richard Genoud richard.gen...@gmail.com
One remark though:
Maybe it would be interesting to keep using the defines in the device
tree for peripheral IDs.
For instance, in arch/arm/boot/dts/at91sam9x5.dtsi : (patch 33)
ssc_clk@28 {
id = 28;
};
May be more readable with the SSC id AT91SAM9X5_ID_SSC, as it was
defined in arch/arm/mach-at91/at91sam9x5.c (removed with patch 20)
IMHO, all AT91SAM9X5_ID_xxx in
arch/arm/mach-at91/include/mach/at91sam9x5.h can me moved in
include/dt-bindings/ and used in at91sam9x5.dtsi
This was requested by Jean-Christophe too.
I'll add these macro files and make use of it in next version.
BTW where should I put these macro files
(include/dt-bindings/at91/'soc-name'/peripherals.h) ?
That sounds correct I suppose.
Ok, I will use this path pattern.
Should I use macros for address fied of clocks or just for id property (or
drop the address) ?
ssc_clk@AT91SAM9X5_ID_SSC {
id = AT91SAM9X5_ID_SSC;
};
or
ssc_clk@28 {
id = AT91SAM9X5_ID_SSC;
};
or
ssc_clk {
id = AT91SAM9X5_ID_SSC;
};
I would drop the address, since the names are always different (for
instance, dma0_clk and dma1_clk are used).
Ok, I'll drop the address.
And the define should also be used here:
ssc0: ssc@f001 { [...]
clocks = periph AT91SAM9X5_ID_SSC;
[...]
}
Yes of course, and it should be used for interrupt ids too (but this
will not be part of this series :)).
Thanks for your review.
Best Regards,
Boris
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Re: [PATCH] pinctrl: at91: choose appropriate handler for level interrupts
On 29/07/2013 17:42, Linus Walleij wrote: On Sat, Jul 20, 2013 at 4:51 PM, Boris BREZILLON b.brezil...@overkiz.com wrote: The current implementation handle both edge and level interrupts with the 'handle_simple_irq' handler. Level interrupts are active as long as the pin stays at the configured level (low or high). In this case we have to use 'handle_level_irq' which mask the interrupt until the handle has treated it. Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com Nicolas/Jean-Christophe: any opinion on this patch? I am tempted to just apply it and see if you react to it :-) Hello, Just for clarification, without this patch the kernel hangs if you request a threaded irq on level state (low or high). This was tested on sama5ek board. Best Regards, Boris Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
On 29/07/2013 17:09, Richard Genoud wrote:
2013/7/29 boris brezillon b.brezil...@overkiz.com:
On 29/07/2013 16:18, Richard Genoud wrote:
2013/7/29 boris brezillon b.brezil...@overkiz.com:
On 29/07/2013 10:00, Richard Genoud wrote:
2013/7/26 boris brezillon b.brezil...@overkiz.com:
On 26/07/2013 17:44, boris brezillon wrote:
I found 2 bugs:
1) the main frequency ready test in recalc_rate function is wrong
2) the common clk framework uses the first match for dt clk
registration
and main clk has this compatible property:
compatible = atmel,at91rm9200-clk-main, fixed-clock;
As a result the main clk is always bound to the fixed-clock driver
which set the clock frequency to 0 if 'clock-frequency' property
is
missing.
These bugs will be fixed in next version.
Tell me if you want need thesse patches for testing purpose.
Hi Boris,
I tested your patch, the clock is not at 0 anymore:
AT91: PIT: mck rate = 833
And it's booting correctly.
There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
not 27). (patch attached)
And yes, I could use your patches for some more tests !
Thanks,
Richard.
Hi Richard,
Thanks for the bug report.
You'll find in attachements the pre-v3 series fixing the detected bugs
(including the ssc clock id bug).
If you need anything else please let me know.
Working on sam9g35ek !
you can add my:
Tested-by: Richard Genoud richard.gen...@gmail.com
One remark though:
Maybe it would be interesting to keep using the defines in the device
tree for peripheral IDs.
For instance, in arch/arm/boot/dts/at91sam9x5.dtsi : (patch 33)
ssc_clk@28 {
id = 28;
};
May be more readable with the SSC id AT91SAM9X5_ID_SSC, as it was
defined in arch/arm/mach-at91/at91sam9x5.c (removed with patch 20)
IMHO, all AT91SAM9X5_ID_xxx in
arch/arm/mach-at91/include/mach/at91sam9x5.h can me moved in
include/dt-bindings/ and used in at91sam9x5.dtsi
This was requested by Jean-Christophe too.
I'll add these macro files and make use of it in next version.
BTW where should I put these macro files
(include/dt-bindings/at91/'soc-name'/peripherals.h) ?
That sounds correct I suppose.
I guess I should do the same for system clks :-).
Should I use macros for address fied of clocks or just for id property (or
drop the address) ?
ssc_clk@AT91SAM9X5_ID_SSC {
id = AT91SAM9X5_ID_SSC;
};
or
ssc_clk@28 {
id = AT91SAM9X5_ID_SSC;
};
or
ssc_clk {
id = AT91SAM9X5_ID_SSC;
};
I would drop the address, since the names are always different (for
instance, dma0_clk and dma1_clk are used).
And the define should also be used here:
ssc0: ssc@f001 { [...]
clocks = periph AT91SAM9X5_ID_SSC;
[...]
}
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[PATCH] net/cadence/macb: fix kernel Oops if no PHY were discovered during probe
Test the presence of a PHY device before printing attached PHY informations. Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com --- drivers/net/ethernet/cadence/macb.c |6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c index e866608..fd3b67f 100644 --- a/drivers/net/ethernet/cadence/macb.c +++ b/drivers/net/ethernet/cadence/macb.c @@ -1868,8 +1868,10 @@ static int __init macb_probe(struct platform_device *pdev) dev-irq, dev-dev_addr); phydev = bp-phy_dev; - netdev_info(dev, attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n, - phydev-drv-name, dev_name(phydev-dev), phydev-irq); + if (phydev) + netdev_info(dev, attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n, + phydev-drv-name, dev_name(phydev-dev), + phydev-irq); return 0; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH 0/3] pinctrl: at91: add support for generic pinconf
Hello, This patch series is an attempt to add support for generic pin config syntax to at91 pinctrl driver. My primary goal is to add support for output configuration from dt definition. This is needed to fully move at91rm9200ek board to dt (other boards may have the same needs). This board use a pin to drive an external switch which select between 2 functionnalities: - mmc interface - spi interface The pin level is currently configured in the board init (init_machine) function based on user config choices (CONFIG_MTD_AT91_DATAFLASH_CARD). Instead of adding a new flag to the current (native) pin config binding, I tried to add support for the generic pin config used by some pinctrl drivers (i.e. rockchip). Is this the right way to do this or should I add a new at91 native flags for output config (OUTPUT_HIGH/LOW) ? The second patch introduce a new config parameter to add a glitch filter on a specific pin. Glitch filter is similar to bounce filter (or debounce) but with a smaller delay (expressed in nsecs ?). I'm not sure this is the right approach. Maybe we should reuse the debounce parameter and add a flag to specify the delay unit (usec or nsec). What do you think ? The third patch migrate sama5 dt boards to the new generic config syntax. Please feel free to share your thoughts. Best Regards, Boris Boris BREZILLON (3): pinctrl: add new generic pinconf config for deglitch filter pinctrl: at91: add support for generic pinconf ARM: at91/dt: move sama5 to generic pinconf .../bindings/pinctrl/atmel,at91-pinctrl.txt| 43 ++- .../bindings/pinctrl/pinctrl-bindings.txt |1 + arch/arm/boot/dts/sama5d3.dtsi | 363 ++-- arch/arm/boot/dts/sama5d3xdm.dtsi |2 +- arch/arm/boot/dts/sama5d3xmb.dtsi | 12 +- drivers/pinctrl/Kconfig|2 +- drivers/pinctrl/pinconf-generic.c |2 + drivers/pinctrl/pinctrl-at91.c | 265 +- include/linux/pinctrl/pinconf-generic.h|5 + 9 files changed, 494 insertions(+), 201 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH 1/3] pinctrl: add new generic pinconf config for deglitch filter
Add a new parameter to support deglitch filter configuration.
A deglitch filter works like a debounce filter but with a smaller
delay (nanoseconds).
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
.../bindings/pinctrl/pinctrl-bindings.txt |1 +
drivers/pinctrl/pinconf-generic.c |2 ++
include/linux/pinctrl/pinconf-generic.h|5 +
3 files changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
index 1958ca9..2f7613e 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -154,6 +154,7 @@ drive-strength - sink or source at most X mA
input-schmitt-enable - enable schmitt-trigger mode
input-schmitt-disable - disable schmitt-trigger mode
input-debounce - debounce mode with debound time X
+input-deglitch - deglitch mode
low-power-enable - enable low power mode
low-power-disable - disable low power mode
output-low - set the pin to output mode with low level
diff --git a/drivers/pinctrl/pinconf-generic.c
b/drivers/pinctrl/pinconf-generic.c
index 2c62225..f14a386 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -51,6 +51,7 @@ static struct pin_config_item conf_items[] = {
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, input schmitt enabled,
NULL),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, input schmitt trigger, NULL),
PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, input debounce, usec),
+ PCONFDUMP(PIN_CONFIG_INPUT_DEGLITCH, input deglitch, NULL),
PCONFDUMP(PIN_CONFIG_POWER_SOURCE, pin power source, selector),
PCONFDUMP(PIN_CONFIG_SLEW_RATE, slew rate, NULL),
PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, pin low power, mode),
@@ -163,6 +164,7 @@ static struct pinconf_generic_dt_params dt_params[] = {
{ input-schmitt-enable, PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
{ input-schmitt-disable, PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
{ input-debounce, PIN_CONFIG_INPUT_DEBOUNCE, 0 },
+ { input-deglitch, PIN_CONFIG_INPUT_DEGLITCH, 0 },
{ low-power-enable, PIN_CONFIG_LOW_POWER_MODE, 1 },
{ low-power-disable, PIN_CONFIG_LOW_POWER_MODE, 0 },
{ output-low, PIN_CONFIG_OUTPUT, 0, },
diff --git a/include/linux/pinctrl/pinconf-generic.h
b/include/linux/pinctrl/pinconf-generic.h
index fb90ef5..aa06535 100644
--- a/include/linux/pinctrl/pinconf-generic.h
+++ b/include/linux/pinctrl/pinconf-generic.h
@@ -72,6 +72,10 @@
* which means it will wait for signals to settle when reading inputs. The
* argument gives the debounce time in usecs. Setting the
* argument to zero turns debouncing off.
+ * @PIN_CONFIG_INPUT_DEGLITCH: this will configure the pin to deglitch mode,
+ * which means it will wait for signals to settle when reading inputs. The
+ * If the argument != 0, deglitch mode is enabled. If it's 0, deglitch
+ * mode is disabled.
* @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
* supplies, the argument to this parameter (on a custom format) tells
* the driver which alternative power source to use.
@@ -102,6 +106,7 @@ enum pin_config_param {
PIN_CONFIG_INPUT_SCHMITT_ENABLE,
PIN_CONFIG_INPUT_SCHMITT,
PIN_CONFIG_INPUT_DEBOUNCE,
+ PIN_CONFIG_INPUT_DEGLITCH,
PIN_CONFIG_POWER_SOURCE,
PIN_CONFIG_SLEW_RATE,
PIN_CONFIG_LOW_POWER_MODE,
--
1.7.9.5
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[RFC PATCH 2/3] pinctrl: at91: add support for generic pinconf
Add support for generic pin configuration to pinctrl-at91 driver.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
.../bindings/pinctrl/atmel,at91-pinctrl.txt| 43 +++-
drivers/pinctrl/Kconfig|2 +-
drivers/pinctrl/pinctrl-at91.c | 265 ++--
3 files changed, 289 insertions(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index 7ccae49..7a7c0c4 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -18,7 +18,9 @@ mode) this pin can work on and the 'config' configures
various pad settings
such as pull-up, multi drive, etc.
Required properties for iomux controller:
-- compatible: atmel,at91rm9200-pinctrl
+- compatible: atmel,at91rm9200-pinctrl or atmel,at91sam9x5-pinctrl.
+ Add generic-pinconf to the compatible string list to use the generic pin
+ configuration syntax.
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
@@ -83,6 +85,11 @@ Required properties for pin configuration node:
setting. The format is atmel,pins = PIN_BANK PIN_BANK_NUM PERIPH CONFIG.
The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
+ Dependending on the presence of the generic-pinconf string in the
+ compatible property the 4th cell is:
+ * a phandle referencing a generic pin config node (refer to
+ pinctrl-bindings.txt)
+ * an integer defining the pin config (see the following description)
Bits used for CONFIG:
PULL_UP(1 0): indicate this pin need a pull up.
@@ -132,6 +139,40 @@ pinctrl@f400 {
};
};
+or
+
+pinctrl@f400 {
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ compatible = atmel,at91rm9200-pinctrl, generic-pinconf,
simple-bus;
+ reg = 0xf400 0x600;
+
+ atmel,mux-mask =
+ /*A B */
+ 0x 0xffc00c3b /* pioA */
+ 0x 0x7fff3ccf /* pioB */
+ 0x 0x007f /* pioC */
+ ;
+
+ pcfg_none: pcfg_none {
+ bias-disable;
+ };
+
+ pcfg_pull_up: pcfg_pull_up {
+ bias-pullup;
+ };
+
+ /* shared pinctrl settings */
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins =
+ 1 14 0x1 pcfg_none/* PB14 periph
A */
+1 15 0x1 pcfg_pull_up; /* PB15 periph
A with pullup */
+ };
+ };
+};
+
dbgu: serial@f200 {
compatible = atmel,at91sam9260-usart;
reg = 0xf200 0x200;
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index bdb1a87..55a4f2c 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -54,7 +54,7 @@ config PINCTRL_AT91
depends on OF
depends on ARCH_AT91
select PINMUX
- select PINCONF
+ select GENERIC_PINCONF
help
Say Y here to enable the at91 pinctrl driver
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 7cce066..1994dd2 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -23,6 +23,7 @@
#include linux/gpio.h
#include linux/pinctrl/machine.h
#include linux/pinctrl/pinconf.h
+#include linux/pinctrl/pinconf-generic.h
#include linux/pinctrl/pinctrl.h
#include linux/pinctrl/pinmux.h
/* Since we request GPIOs from ourself */
@@ -32,6 +33,7 @@
#include mach/at91_pio.h
#include core.h
+#include pinconf.h
#define MAX_NB_GPIO_PER_BANK 32
@@ -85,6 +87,21 @@ enum at91_mux {
AT91_MUX_PERIPH_D = 4,
};
+struct at91_generic_pinconf {
+ unsigned long *configs;
+ unsigned intnconfigs;
+};
+
+enum at91_pinconf_type {
+ AT91_PINCONF_NATIVE,
+ AT91_PINCONF_GENERIC,
+};
+
+union at91_pinconf {
+ unsigned long native;
+ struct at91_generic_pinconf generic;
+};
+
/**
* struct at91_pmx_pin - describes an At91 pin mux
* @bank: the bank of the pin
@@ -93,10 +110,11 @@ enum at91_mux {
* @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
*/
struct at91_pmx_pin {
- uint32_tbank;
- uint32_tpin;
- enum at91_mux mux;
- unsigned long conf;
+ uint32_tbank;
+ uint32_tpin;
+ enum at91_mux mux;
+ enum at91_pinconf_type conftype;
+ union at91_pinconf conf;
};
/**
@@ -278,8 +296,16 @@ static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN
[RFC PATCH 3/3] ARM: at91/dt: move sama5 to generic pinconf
Add generic pinconf definitions and reference appropriate configs in
atmel,pins properties.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/sama5d3.dtsi| 363 +++--
arch/arm/boot/dts/sama5d3xdm.dtsi |2 +-
arch/arm/boot/dts/sama5d3xmb.dtsi | 12 +-
3 files changed, 197 insertions(+), 180 deletions(-)
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index a1d5e25..3e38383 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -402,7 +402,7 @@
pinctrl@f200 {
#address-cells = 1;
#size-cells = 1;
- compatible = atmel,at91sam9x5-pinctrl,
atmel,at91rm9200-pinctrl, simple-bus;
+ compatible = atmel,at91sam9x5-pinctrl,
atmel,at91rm9200-pinctrl, generic-pinconf, simple-bus;
ranges = 0xf200 0xf200 0xa00;
atmel,mux-mask =
/* A B C */
@@ -413,206 +413,223 @@
0x 0xbf9f8000 0x1800
/* pioE */
;
+ pcfg_none: pcfg_none {
+ bias-disable;
+ };
+
+ pcfg_pull_up: pcfg_pull_up {
+ bias-pull-up;
+ };
+
+ pcfg_deglitch: pcfg_deglitch {
+ input-deglitch = 1;
+ };
+
+ pcfg_pull_up_deglitch: pcfg_pull_up_deglitch {
+ bias-pull-up;
+ input-deglitch = 1;
+ };
+
/* shared pinctrl settings */
adc0 {
pinctrl_adc0_adtrg: adc0_adtrg {
atmel,pins =
- AT91_PIOD 19
AT91_PERIPH_A AT91_PINCTRL_NONE; /* PD19 periph A ADTRG */
+ AT91_PIOD 19
AT91_PERIPH_A pcfg_none;/* PD19 periph A ADTRG */
};
pinctrl_adc0_ad0: adc0_ad0 {
atmel,pins =
- AT91_PIOD 20
AT91_PERIPH_A AT91_PINCTRL_NONE; /* PD20 periph A AD0 */
+ AT91_PIOD 20
AT91_PERIPH_A pcfg_none;/* PD20 periph A AD0 */
};
pinctrl_adc0_ad1: adc0_ad1 {
atmel,pins =
- AT91_PIOD 21
AT91_PERIPH_A AT91_PINCTRL_NONE; /* PD21 periph A AD1 */
+ AT91_PIOD 21
AT91_PERIPH_A pcfg_none;/* PD21 periph A AD1 */
};
pinctrl_adc0_ad2: adc0_ad2 {
atmel,pins =
- AT91_PIOD 22
AT91_PERIPH_A AT91_PINCTRL_NONE; /* PD22 periph A AD2 */
+ AT91_PIOD 22
AT91_PERIPH_A pcfg_none;/* PD22 periph A AD2 */
};
pinctrl_adc0_ad3: adc0_ad3 {
atmel,pins =
- AT91_PIOD 23
AT91_PERIPH_A AT91_PINCTRL_NONE; /* PD23 periph A AD3 */
+ AT91_PIOD 23
AT91_PERIPH_A pcfg_none;/* PD23 periph A AD3 */
};
pinctrl_adc0_ad4: adc0_ad4 {
atmel,pins =
- AT91_PIOD 24
AT91_PERIPH_A AT91_PINCTRL_NONE; /* PD24 periph A AD4 */
+ AT91_PIOD 24
AT91_PERIPH_A pcfg_none;/* PD24 periph A AD4 */
};
pinctrl_adc0_ad5: adc0_ad5 {
atmel,pins =
- AT91_PIOD 25
AT91_PERIPH_A AT91_PINCTRL_NONE; /* PD25 periph A AD5 */
+ AT91_PIOD 25
Re: [RFC PATCH 0/3] pinctrl: at91: add support for generic pinconf
On 24/08/2013 23:32, Boris BREZILLON wrote: Hello, This patch series is an attempt to add support for generic pin config syntax to at91 pinctrl driver. My primary goal is to add support for output configuration from dt definition. This is needed to fully move at91rm9200ek board to dt (other boards may have the same needs). This board use a pin to drive an external switch which select between 2 functionnalities: - mmc interface - spi interface The pin level is currently configured in the board init (init_machine) function based on user config choices (CONFIG_MTD_AT91_DATAFLASH_CARD). Instead of adding a new flag to the current (native) pin config binding, I tried to add support for the generic pin config used by some pinctrl drivers (i.e. rockchip). Is this the right way to do this or should I add a new at91 native flags for output config (OUTPUT_HIGH/LOW) ? The second patch introduce a new config parameter to add a glitch filter on a specific pin. The first patch, not the second. Glitch filter is similar to bounce filter (or debounce) but with a smaller delay (expressed in nsecs ?). I'm not sure this is the right approach. Maybe we should reuse the debounce parameter and add a flag to specify the delay unit (usec or nsec). What do you think ? The third patch migrate sama5 dt boards to the new generic config syntax. Please feel free to share your thoughts. Best Regards, Boris Boris BREZILLON (3): pinctrl: add new generic pinconf config for deglitch filter pinctrl: at91: add support for generic pinconf ARM: at91/dt: move sama5 to generic pinconf .../bindings/pinctrl/atmel,at91-pinctrl.txt| 43 ++- .../bindings/pinctrl/pinctrl-bindings.txt |1 + arch/arm/boot/dts/sama5d3.dtsi | 363 ++-- arch/arm/boot/dts/sama5d3xdm.dtsi |2 +- arch/arm/boot/dts/sama5d3xmb.dtsi | 12 +- drivers/pinctrl/Kconfig|2 +- drivers/pinctrl/pinconf-generic.c |2 + drivers/pinctrl/pinctrl-at91.c | 265 +- include/linux/pinctrl/pinconf-generic.h|5 + 9 files changed, 494 insertions(+), 201 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 2/5] mmc: atmel-mci: prepare clk before calling enable
Hello Chris, On 25/08/2013 05:18, Chris Ball wrote: Hi, On Thu, Jul 18 2013, Boris BREZILLON wrote: Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to avoid common clk framework warnings. Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com Acked-by: Ludovic Desroches ludovic.desroc...@atmel.com Okay, pushed to mmc-next for 3.12. Thanks. Boris, you got feedback from Thomas Petazzoni and Russell King, but you didn't CC either of them on the patch v4 I didn't knew I had to add the reviewers of a patch in the cc list of the future versions. I'll do it next time. , and you didn't write a changelog explaining the differences between patches v3 and v4 -- please do both of those next time. The changelog is in the cover letter (Changes since v3). But I didn't send you this cover letter. Also, it looks like the Ack from Ludovic happened away from the MMC list, since I don't see a message from Ludovic on the thread here. It would be better if the Ack happened somewhere I can see it. The 'Acked-by: Ludovic Desroches ludovic.desroc...@atmel.com' was added in the 2nd version of this patch series. But I don't know if I should have kept it in this version since this patch has evolved. Thanks for these feebacks, I'm still learning the good practices of the kernel submission process. I'll check these points next time. Best Regards, Boris Thanks, - Chris. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] net/cadence/macb: fix kernel Oops if no PHY were discovered during probe
Hello Bo, On 26/08/2013 11:09, Bo Shen wrote: Hi Boris, On 08/25/2013 03:21 AM, Boris BREZILLON wrote: Test the presence of a PHY device before printing attached PHY informations. Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com --- drivers/net/ethernet/cadence/macb.c |6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c index e866608..fd3b67f 100644 --- a/drivers/net/ethernet/cadence/macb.c +++ b/drivers/net/ethernet/cadence/macb.c @@ -1868,8 +1868,10 @@ static int __init macb_probe(struct platform_device *pdev) dev-irq, dev-dev_addr); phydev = bp-phy_dev; -netdev_info(dev, attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n, -phydev-drv-name, dev_name(phydev-dev), phydev-irq); +if (phydev) +netdev_info(dev, attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n, +phydev-drv-name, dev_name(phydev-dev), +phydev-irq); Actually no need this check, if PHY is attached failed, the macb driver probe will fail, then it won't show this message. You're right (thanks for pointing this out). Indeed this is a bug I introduced in this patch series ( https://lkml.org/lkml/2013/8/22/381). In macb_mii_init function, the err field may be set to 0 (instead of the default -ENXIO value) if no PHY is discovered. As macb_mii_probe return code is not copied to err, this result in a 0 return even if macb_mii_probe failed. Nicolas, forget about this patch, I'll fix this in the appropriate patch series (except if you plan to add dynamic MAC/PHY association, and treat missing PHY during probe process as an acceptable result :-)). Best Regards, Boris BREZILLON return 0; Best Regards, Bo Shen -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 0/2] net/cadence/macb: add support for dt phy definition
Hello, This patch series adds support for ethernet phy definition using device tree. This may help in moving some at91 boards to dt (some of them define an interrupt pin). Tested on samad31ek. Best Regards, Boris Changes since v1: - fix wrong macb_mii_init return code when no PHY device is discovered Boris BREZILLON (2): net/cadence/macb: add support for dt phy definition ARM: at91/dt: define phy available on sama5d3 mother board arch/arm/boot/dts/sama5d3xmb.dtsi |8 ++ drivers/net/ethernet/cadence/macb.c | 47 +++ 2 files changed, 45 insertions(+), 10 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 2/2] ARM: at91/dt: define phy available on sama5d3 mother board
This patch describe the phy used on atmel sama5d3 mother board:
- phy address
- phy interrupt pin
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/sama5d3xmb.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi
b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 8a9e05d..e9521d5 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -81,6 +81,14 @@
macb1: ethernet@f802c000 {
phy-mode = rmii;
+
+ #address-cells = 1;
+ #size-cells = 0;
+ phy0: ethernet-phy@0 {
+ interrupt-parent = pioE;
+ interrupts = 30 IRQ_TYPE_EDGE_FALLING;
+ reg = 1;
+ };
};
pinctrl@f200 {
--
1.7.9.5
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[PATCH v2 1/2] net/cadence/macb: add support for dt phy definition
The macb driver only handle PHY description through platform_data
(macb_platform_data).
Thus, when using dt you cannot define phy properties like phy address or
phy irq pin.
This patch makes use of the of_mdiobus_register to add support for
phy device definition using dt.
A fallback to the autoscan procedure is added in case there is no phy
devices defined in dt.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/net/ethernet/cadence/macb.c | 47 +++
1 file changed, 37 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/ethernet/cadence/macb.c
index e866608..7660c45 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -27,6 +27,7 @@
#include linux/phy.h
#include linux/of.h
#include linux/of_device.h
+#include linux/of_mdio.h
#include linux/of_net.h
#include linux/pinctrl/consumer.h
@@ -275,7 +276,7 @@ static int macb_mii_probe(struct net_device *dev)
phydev = phy_find_first(bp-mii_bus);
if (!phydev) {
netdev_err(dev, no PHY found\n);
- return -1;
+ return -ENXIO;
}
pdata = dev_get_platdata(bp-pdev-dev);
@@ -314,6 +315,7 @@ static int macb_mii_probe(struct net_device *dev)
int macb_mii_init(struct macb *bp)
{
struct macb_platform_data *pdata;
+ struct device_node *np;
int err = -ENXIO, i;
/* Enable management port */
@@ -335,26 +337,51 @@ int macb_mii_init(struct macb *bp)
bp-mii_bus-parent = bp-dev-dev;
pdata = bp-pdev-dev.platform_data;
- if (pdata)
- bp-mii_bus-phy_mask = pdata-phy_mask;
-
bp-mii_bus-irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
if (!bp-mii_bus-irq) {
err = -ENOMEM;
goto err_out_free_mdiobus;
}
- for (i = 0; i PHY_MAX_ADDR; i++)
- bp-mii_bus-irq[i] = PHY_POLL;
-
dev_set_drvdata(bp-dev-dev, bp-mii_bus);
- if (mdiobus_register(bp-mii_bus))
+ np = bp-pdev-dev.of_node;
+ if (np) {
+ /* try dt phy registration */
+ err = of_mdiobus_register(bp-mii_bus, np);
+
+ /* fallback to standard phy registration if no phy were
+ found during dt phy registration */
+ if (!err !phy_find_first(bp-mii_bus)) {
+ for (i = 0; i PHY_MAX_ADDR; i++) {
+ struct phy_device *phydev;
+
+ phydev = mdiobus_scan(bp-mii_bus, i);
+ if (IS_ERR(phydev)) {
+ err = PTR_ERR(phydev);
+ break;
+ }
+ }
+
+ if (err)
+ goto err_out_unregister_bus;
+ }
+ } else {
+ for (i = 0; i PHY_MAX_ADDR; i++)
+ bp-mii_bus-irq[i] = PHY_POLL;
+
+ if (pdata)
+ bp-mii_bus-phy_mask = pdata-phy_mask;
+
+ err = mdiobus_register(bp-mii_bus);
+ }
+
+ if (err)
goto err_out_free_mdio_irq;
- if (macb_mii_probe(bp-dev) != 0) {
+ err = macb_mii_probe(bp-dev);
+ if (err)
goto err_out_unregister_bus;
- }
return 0;
--
1.7.9.5
--
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Re: [PATCH v2 2/4] watchdog: at91sam9_wdt: update device tree doc
Hello,
I missed Grant's ack on this patch:
Acked-by: Grant Likelygrant.lik...@linaro.org
Best Regards,
Boris
On 21/06/2013 09:23, Boris BREZILLON wrote:
Add new at91sam9 watchdog properties to the documentation.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
.../devicetree/bindings/watchdog/atmel-wdt.txt | 30 ++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
index fcdd48f..e043106 100644
--- a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
@@ -9,11 +9,37 @@ Required properties:
Optional properties:
- timeout-sec: contains the watchdog timeout in seconds.
+- interrupts : Should contain WDT interrupt.
+- atmel,max-heartbeat-sec : Should contain the maximum heartbeat value in
+ seconds. This value should be less than 16. It is used to compute the
+ WDV field.
+- atmel,min-heartbeat-sec : Should contain the minimum heartbeat value in
+ seconds. This value should be less than 4 times the max-heartbeat-sec
+ value. It is used to compute the WDD field.
+- atmel,watchdog-type : Should be hardware or software. Hardware watchdog
+ use the at91 watchdog reset. Software watchdog use the watchdog
+ interrupt to trigger a software reset.
+- atmel,reset-type : Should be proc or all.
+ all : assert peripherals and processor reset signals
+ proc : assert the processor reset signal
+ This is valid only when using hardware watchdog.
+- atmel,disable : Should be present if you want to disable the watchdog.
+- atmel,idle-halt : Should be present if you want to stop the watchdog when
+ entering idle state.
+- atmel,dbg-halt : Should be present if you want to stop the watchdog when
+ entering debug state.
Example:
-
watchdog@fd40 {
compatible = atmel,at91sam9260-wdt;
reg = 0xfd40 0x10;
- timeout-sec = 10;
+ interrupts = 1 IRQ_TYPE_LEVEL_HIGH 7;
+ timeout-sec = 15;
+ atmel,watchdog-type = hardware;
+ atmel,reset-type = all;
+ atmel,dbg-halt;
+ atmel,idle-halt;
+ atmel,max-heartbeat-sec = 16;
+ atmel,min-heartbeat-sec = 0;
+ status = okay;
};
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Re: [PATCH v2 0/4] watchdog: at91sam9_wdt: handle already configured wdt
Hello Yang, Did you test/review this series ? If you did, could you add your Acked, Reviewed and/or Tested-by. I'd really like to get this series merged to mainline. Thanks. Best Regards, Boris On 21/06/2013 09:19, Boris BREZILLON wrote: Hello, This patch series is a porposal to enhance the sam9 watchdog timer support. The at91sam9 watchdog timer can only be configured once, and the current implementation tries to configure it in a static way: - 2 seconds timeout - wdt restart every 500ms If the timer has already been configured with different values, it returns an error and do not create any watchdog device. This is not critical if the watchdog is disabled, but if it has been enabled with different timeout values it will lead to a SoC reset. This patch series tries to address this issue by adapting the heartbeat value according the WDT timer config: - it first tries to configure the timer as requested. - if it fails it fallbacks to the current config, adapting its heartbeat timer to the needs This patch series also move to a dynamically allocated at91wdt device instead of the static instance. I'm not sure this is the best solution, so please tell me if you prefer to keep static instance of watchdog. It adds a new at91 wdt type: software. This new type make use of the at91 wdt interrupt to trigger a software reboot. Finally it adds several properties to the device tree bindings. Best Regards, Boris Change since v1: - fix typo in documentaion - fix irq dt definition for sama5d3 SoC Boris BREZILLON (4): watchdog: at91sam9_wdt: better watchdog support watchdog: at91sam9_wdt: update device tree doc ARM: at91/dt: add sam9 watchdog default options to SoCs ARM: at91/dt: add watchdog properties to kizbox board .../devicetree/bindings/watchdog/atmel-wdt.txt | 30 +- arch/arm/boot/dts/at91sam9260.dtsi |5 + arch/arm/boot/dts/at91sam9263.dtsi |5 + arch/arm/boot/dts/at91sam9g45.dtsi |5 + arch/arm/boot/dts/at91sam9n12.dtsi |5 + arch/arm/boot/dts/at91sam9x5.dtsi |5 + arch/arm/boot/dts/kizbox.dts |6 + arch/arm/boot/dts/sama5d3.dtsi |5 + drivers/watchdog/at91sam9_wdt.c| 319 +++- 9 files changed, 300 insertions(+), 85 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 2/2] ARM: at91/dt: define phy available on sama5d3 mother board
Hello Sergei,
On 26/08/2013 15:21, Sergei Shtylyov wrote:
Hello.
On 26-08-2013 16:35, Boris BREZILLON wrote:
This patch describe the phy used on atmel sama5d3 mother board:
- phy address
- phy interrupt pin
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/sama5d3xmb.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi
b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 8a9e05d..e9521d5 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -81,6 +81,14 @@
macb1: ethernet@f802c000 {
phy-mode = rmii;
+
+#address-cells = 1;
+#size-cells = 0;
+phy0: ethernet-phy@0 {
Address part of the node name doesn't match the reg property.
Indeed, I based my definition on arch/arc/boot/dts/angel4.dts where phy
is registered like this :
phy0: ethernet-phy@0 {
reg = 1;
};
I think it's buggy there too, because I checked other dts files and they
all put the same address
after @ and in reg register.
I'll fix this fot the next version.
Thanks
Best Regards,
Boris
+interrupt-parent = pioE;
+interrupts = 30 IRQ_TYPE_EDGE_FALLING;
+reg = 1;
+};
WBR, Sergei
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Re: [RFC PATCH 1/3] pinctrl: add new generic pinconf config for deglitch filter
Hello Stephen, On 26/08/2013 18:50, Stephen Warren wrote: On 08/24/2013 03:35 PM, Boris BREZILLON wrote: Add a new parameter to support deglitch filter configuration. A deglitch filter works like a debounce filter but with a smaller delay (nanoseconds). Why not use the existing debounce property, just with a small delay specified. It seems like that's exactly what the property is for? That's one of the question I asked in my cover letter :-) Indeed the at91 deglitch filter delay is not configurable and is statically assigned to half a master clk cycle (if master clk = 133MHz - 8 ns). The debounce property argument is currently expressed in usecs. This will result in always selecting the debounce filter (which is also available on at91 SoCs) over the deglitch filter. Could we add a flag in the deglitch argument to specify the delay unit (nsecs or usecs) ? Best Regards, Boris -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 2/3] pinctrl: at91: add support for generic pinconf
On 26/08/2013 18:53, Stephen Warren wrote: On 08/24/2013 03:37 PM, Boris BREZILLON wrote: Add support for generic pin configuration to pinctrl-at91 driver. diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt Required properties for iomux controller: -- compatible: atmel,at91rm9200-pinctrl +- compatible: atmel,at91rm9200-pinctrl or atmel,at91sam9x5-pinctrl. You seem to also be adding a second chip name to the list here, which is more than the patch subject/description imply you're doing... This is an update of the documentation: atmel,at91sam9x5-pinctrl compatible is already used in the pinctrl driver but the documention was not updated. But I agree, this should not be part of this series. + Add generic-pinconf to the compatible string list to use the generic pin + configuration syntax. generic-pinconf is too generic of a compatible value for this binding to define. Instead, I think you want to either: a) Use compatible=atmel,at91rm9200-pinctrl for the old binding, use compatible=atmel,at91rm9200-pinctrl-generic for the new binding or: b) Define Boolean property atmel,generic-pinconf (perhaps a better name could be chosen?). If it's not present, parse the node assuming the old binding. If it is present, parse the node assuming the new binding. Okay. I thought this property string could be generic as it may concern other drivers too (in order to keep compatibility with old dt ABI and add support the generic pinconf binding). Anyway, I prefer the first proposition. pinctrl single driver is already using these names: |compatible = pinctrl-single for non generic pinconf binding ||compatible = pinconf-single ||for generic pinconf binding| So I think we should use something similar: |compatible = atmel,at91xx-pinctrl for non generic pinconf binding ||compatible = |||atmel,at91xx-|pinconf ||for generic pinconf binding| What do you think ? Best Regards, Boris -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 2/3] pinctrl: at91: add support for generic pinconf
Hello Jean-Christophe,
Le 26/08/2013 19:53, Jean-Christophe PLAGNIOL-VILLARD a écrit :
On 23:37 Sat 24 Aug , Boris BREZILLON wrote:
Add support for generic pin configuration to pinctrl-at91 driver.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
.../bindings/pinctrl/atmel,at91-pinctrl.txt| 43 +++-
drivers/pinctrl/Kconfig|2 +-
drivers/pinctrl/pinctrl-at91.c | 265 ++--
3 files changed, 289 insertions(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index 7ccae49..7a7c0c4 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -18,7 +18,9 @@ mode) this pin can work on and the 'config' configures
various pad settings
such as pull-up, multi drive, etc.
Required properties for iomux controller:
-- compatible: atmel,at91rm9200-pinctrl
+- compatible: atmel,at91rm9200-pinctrl or atmel,at91sam9x5-pinctrl.
+ Add generic-pinconf to the compatible string list to use the generic pin
+ configuration syntax.
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
@@ -83,6 +85,11 @@ Required properties for pin configuration node:
setting. The format is atmel,pins = PIN_BANK PIN_BANK_NUM PERIPH CONFIG.
The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
+ Dependending on the presence of the generic-pinconf string in the
+ compatible property the 4th cell is:
+ * a phandle referencing a generic pin config node (refer to
+ pinctrl-bindings.txt)
+ * an integer defining the pin config (see the following description)
Bits used for CONFIG:
PULL_UP (1 0): indicate this pin need a pull up.
@@ -132,6 +139,40 @@ pinctrl@f400 {
};
};
+or
+
+pinctrl@f400 {
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ compatible = atmel,at91rm9200-pinctrl, generic-pinconf,
simple-bus;
nack your break the backword compatibility
if we use a old kernel with this new dt nothing will work
as the old kernel will never known the the generic-pinconf means anything
Your're right, I didn't think of this case (old kernel with new dt).
if we want to use generic-pinconf support you *CAN NOT* use
atmel,at91rm9200-pinctrl
in the compatible
What about using atmel,at91xx-pinconf instead of
atmel,at91xx-pinctrl to notify
the generic pinconf compatibility (as done by single pinctrl driver) ?
+ reg = 0xf400 0x600;
+
+ atmel,mux-mask =
+ /*A B */
+ 0x 0xffc00c3b /* pioA */
+ 0x 0x7fff3ccf /* pioB */
+ 0x 0x007f /* pioC */
+ ;
+
+ pcfg_none: pcfg_none {
+ bias-disable;
+ };
+
+ pcfg_pull_up: pcfg_pull_up {
+ bias-pullup;
+ };
+
+ /* shared pinctrl settings */
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins =
+ 1 14 0x1 pcfg_none /* PB14 periph
A */
+1 15 0x1 pcfg_pull_up;/* PB15 periph
A with pullup */
+ };
+ };
+};
+
dbgu: serial@f200 {
compatible = atmel,at91sam9260-usart;
reg = 0xf200 0x200;
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index bdb1a87..55a4f2c 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -54,7 +54,7 @@ config PINCTRL_AT91
depends on OF
depends on ARCH_AT91
select PINMUX
- select PINCONF
+ select GENERIC_PINCONF
help
Say Y here to enable the at91 pinctrl driver
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 7cce066..1994dd2 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -23,6 +23,7 @@
#include linux/gpio.h
#include linux/pinctrl/machine.h
#include linux/pinctrl/pinconf.h
+#include linux/pinctrl/pinconf-generic.h
#include linux/pinctrl/pinctrl.h
#include linux/pinctrl/pinmux.h
/* Since we request GPIOs from ourself */
@@ -32,6 +33,7 @@
#include mach/at91_pio.h
#include core.h
+#include pinconf.h
#define MAX_NB_GPIO_PER_BANK 32
@@ -85,6 +87,21 @@ enum at91_mux {
AT91_MUX_PERIPH_D = 4,
};
+struct at91_generic_pinconf {
+ unsigned long *configs;
+ unsigned intnconfigs;
+};
+
+enum at91_pinconf_type {
+ AT91_PINCONF_NATIVE,
+ AT91_PINCONF_GENERIC,
+};
+
+union at91_pinconf {
+ unsigned long native;
+ struct at91_generic_pinconf
Re: [RFC PATCH 2/3] pinctrl: at91: add support for generic pinconf
Le 26/08/2013 21:18, Jean-Christophe PLAGNIOL-VILLARD a écrit :
On 20:45 Mon 26 Aug , boris brezillon wrote:
Hello Jean-Christophe,
Le 26/08/2013 19:53, Jean-Christophe PLAGNIOL-VILLARD a écrit :
On 23:37 Sat 24 Aug , Boris BREZILLON wrote:
Add support for generic pin configuration to pinctrl-at91 driver.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
.../bindings/pinctrl/atmel,at91-pinctrl.txt| 43 +++-
drivers/pinctrl/Kconfig|2 +-
drivers/pinctrl/pinctrl-at91.c | 265 ++--
3 files changed, 289 insertions(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index 7ccae49..7a7c0c4 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -18,7 +18,9 @@ mode) this pin can work on and the 'config' configures
various pad settings
such as pull-up, multi drive, etc.
Required properties for iomux controller:
-- compatible: atmel,at91rm9200-pinctrl
+- compatible: atmel,at91rm9200-pinctrl or atmel,at91sam9x5-pinctrl.
+ Add generic-pinconf to the compatible string list to use the generic pin
+ configuration syntax.
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
@@ -83,6 +85,11 @@ Required properties for pin configuration node:
setting. The format is atmel,pins = PIN_BANK PIN_BANK_NUM PERIPH CONFIG.
The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
+ Dependending on the presence of the generic-pinconf string in the
+ compatible property the 4th cell is:
+ * a phandle referencing a generic pin config node (refer to
+ pinctrl-bindings.txt)
+ * an integer defining the pin config (see the following description)
Bits used for CONFIG:
PULL_UP (1 0): indicate this pin need a pull up.
@@ -132,6 +139,40 @@ pinctrl@f400 {
};
};
+or
+
+pinctrl@f400 {
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ compatible = atmel,at91rm9200-pinctrl, generic-pinconf,
simple-bus;
nack your break the backword compatibility
if we use a old kernel with this new dt nothing will work
as the old kernel will never known the the generic-pinconf means anything
Your're right, I didn't think of this case (old kernel with new dt).
if we want to use generic-pinconf support you *CAN NOT* use
atmel,at91rm9200-pinctrl
in the compatible
What about using atmel,at91xx-pinconf instead of
atmel,at91xx-pinctrl to notify
the generic pinconf compatibility (as done by single pinctrl driver) ?
no as the rm9200 IP and sam9x5 IP are only partially compatible
you MUST distinguish them
What I meant is use the -pinctrl and -pinconf suffixes to
differentiate between native and generic
pinconf bindings and keep the IP names as it is right now (replace xx
with the IP name) to differentiate
the IP versions.
This gives us the following compatible strings:
atmel,at91rm9200-pinctrl
atmel,at91rm9200-pinconf
atmel,at91sam9x5-pinctrl
atmel,at91sam9x5-pinconf
+ reg = 0xf400 0x600;
+
+ atmel,mux-mask =
+ /*A B */
+ 0x 0xffc00c3b /* pioA */
+ 0x 0x7fff3ccf /* pioB */
+ 0x 0x007f /* pioC */
+ ;
+
+ pcfg_none: pcfg_none {
+ bias-disable;
+ };
+
+ pcfg_pull_up: pcfg_pull_up {
+ bias-pullup;
+ };
+
+ /* shared pinctrl settings */
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins =
+ 1 14 0x1 pcfg_none /* PB14 periph
A */
+1 15 0x1 pcfg_pull_up;/* PB15 periph
A with pullup */
+ };
+ };
+};
+
dbgu: serial@f200 {
compatible = atmel,at91sam9260-usart;
reg = 0xf200 0x200;
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index bdb1a87..55a4f2c 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -54,7 +54,7 @@ config PINCTRL_AT91
depends on OF
depends on ARCH_AT91
select PINMUX
- select PINCONF
+ select GENERIC_PINCONF
help
Say Y here to enable the at91 pinctrl driver
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 7cce066..1994dd2 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -23,6 +23,7 @@
#include linux/gpio.h
#include linux/pinctrl/machine.h
#include linux/pinctrl/pinconf.h
+#include linux/pinctrl/pinconf-generic.h
#include linux/pinctrl/pinctrl.h
#include linux/pinctrl/pinmux.h
Re: [RFC PATCH 2/3] pinctrl: at91: add support for generic pinconf
On 27/08/2013 05:54, Stephen Warren wrote:
On 08/26/2013 12:45 PM, boris brezillon wrote:
Hello Jean-Christophe,
Le 26/08/2013 19:53, Jean-Christophe PLAGNIOL-VILLARD a écrit :
On 23:37 Sat 24 Aug , Boris BREZILLON wrote:
Add support for generic pin configuration to pinctrl-at91 driver.
...
a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
...
configures various pad settings
such as pull-up, multi drive, etc.
Required properties for iomux controller:
-- compatible: atmel,at91rm9200-pinctrl
+- compatible: atmel,at91rm9200-pinctrl or atmel,at91sam9x5-pinctrl.
+ Add generic-pinconf to the compatible string list to use the
generic pin
...
+pinctrl@f400 {
+#address-cells = 1;
+#size-cells = 1;
+ranges;
+compatible = atmel,at91rm9200-pinctrl, generic-pinconf,
simple-bus;
nack your break the backword compatibility
if we use a old kernel with this new dt nothing will work
as the old kernel will never known the the generic-pinconf means
anything
Your're right, I didn't think of this case (old kernel with new dt).
Well, just to be clear: If a new DT uses a new compatible value of any
kind, be it adding generic-pinconf or switching to foo-yyy rather
than foo-yyy, it won't be compatible... That somewhat implies that you
can't ever replace an old binding with something new.
That's absolutely right, however the behaviour won't be the same in both
cases.
1) If your (new) dt defines its pinctrl using the foo-pinconf
compatible string and
your (old) kernel does not support it, the pinctrl will never probe
the pinctrl definitions.
Moreover, if you want to define both old (foo-pinctrl) and new
(foo-pinconf) pinctrl
definitions in your dt in order to support several kernel versions,
nothing prevents you
from doing it.
2) In the other hand, if you use an additional generic-pinconf
compatible string to signify
wether or not the pinctrl definition use the generic pinconf dt
binding, the (old) kernel
will probe the pinctrl definitions, ignore the generic-pinconf
string, and fail when parsing
the pinctrl configuration nodes (which are invalid pinctrl function
nodes in the current dt binding).
We have the same problem when using the 'atmel,generic-pinconf'
property inside a pinctrl node:
old kernels won't take this property into account.
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Re: [RFC PATCH 1/3] pinctrl: add new generic pinconf config for deglitch filter
On 27/08/2013 05:55, Stephen Warren wrote: On 08/26/2013 11:01 AM, boris brezillon wrote: Hello Stephen, On 26/08/2013 18:50, Stephen Warren wrote: On 08/24/2013 03:35 PM, Boris BREZILLON wrote: Add a new parameter to support deglitch filter configuration. A deglitch filter works like a debounce filter but with a smaller delay (nanoseconds). Why not use the existing debounce property, just with a small delay specified. It seems like that's exactly what the property is for? That's one of the question I asked in my cover letter :-) Indeed the at91 deglitch filter delay is not configurable and is statically assigned to half a master clk cycle (if master clk = 133MHz - 8 ns). The debounce property argument is currently expressed in usecs. This will result in always selecting the debounce filter (which is also available on at91 SoCs) over the deglitch filter. Could we add a flag in the deglitch argument to specify the delay unit (nsecs or usecs) ? If the value is hard-coded in HW, why not use non-zero (or 1) to enable and zero to disable? Indeed at91 pins support both deglitch and debounce filter and I have to choose between the two given the argument value (in usec). Here's what I can do: if (arg = 1/2 * slowclock)/* debounce case */ /* choose debounce filter and configure the delay according to the given argument value */ else /* deglitch case */ /* choose deglitch filter */ Slow clock is running at 32KHz which gives a 30 usec clock cycle. (this kind of thing is why I'm not convinced that generic pinconf works so well... What if we need psecs in the future?) Should I keep the at91 native pinconf binding and add the missing flags to this binding (OUTPUT configuration flags) ? This was another question I asked in my cover letter: wether or not the generic pinconf binding should be used. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 2/3] pinctrl: at91: add support for generic pinconf
On 27/08/2013 05:57, Stephen Warren wrote: On 08/26/2013 11:17 AM, boris brezillon wrote: On 26/08/2013 18:53, Stephen Warren wrote: On 08/24/2013 03:37 PM, Boris BREZILLON wrote: Add support for generic pin configuration to pinctrl-at91 driver. diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt Required properties for iomux controller: -- compatible: atmel,at91rm9200-pinctrl +- compatible: atmel,at91rm9200-pinctrl or atmel,at91sam9x5-pinctrl. You seem to also be adding a second chip name to the list here, which is more than the patch subject/description imply you're doing... This is an update of the documentation: atmel,at91sam9x5-pinctrl compatible is already used in the pinctrl driver but the documention was not updated. But I agree, this should not be part of this series. + Add generic-pinconf to the compatible string list to use the generic pin + configuration syntax. generic-pinconf is too generic of a compatible value for this binding to define. Instead, I think you want to either: a) Use compatible=atmel,at91rm9200-pinctrl for the old binding, use compatible=atmel,at91rm9200-pinctrl-generic for the new binding or: b) Define Boolean property atmel,generic-pinconf (perhaps a better name could be chosen?). If it's not present, parse the node assuming the old binding. If it is present, parse the node assuming the new binding. Okay. I thought this property string could be generic as it may concern other drivers too (in order to keep compatibility with old dt ABI and add support the generic pinconf binding). Anyway, I prefer the first proposition. pinctrl single driver is already using these names: |compatible = pinctrl-single for non generic pinconf binding ||compatible = pinconf-single ||for generic pinconf binding| So I think we should use something similar: |compatible = atmel,at91xx-pinctrl for non generic pinconf binding ||compatible = |||atmel,at91xx-|pinconf ||for generic pinconf binding| What do you think ? Hmmm. It is a little odd to switch out the compatible value and invent a new binding for the same HW. Isn't it possible to define both sets of properties in the binding, and have drivers look for either? Do you mean something like: atmel,pins = xxx;/* current dt binding */ atmel,generic-pins = yyy;/* new dt binding */ If that's what you had in mind, it will be a little bit tricky to handle, because AFAIK the pinconf_ops callbacks do not give me any element I could use to deduce the type of pinconf (generic or native). This implies I have to know early during the probe process which kind of binding is in use. Please tell me if I missed some key points, and this can be easily done. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 0/2] net/cadence/macb: add support for dt phy definition
Hello, This patch series adds support for ethernet phy definition using device tree. This may help in moving some at91 boards to dt (some of them define an interrupt pin). Tested on samad31ek. Best Regards, Boris Changes since v2: - fix wrong address of phy0 dt node Changes since v1: - fix wrong macb_mii_init return code when no PHY device is discovered Boris BREZILLON (2): net/cadence/macb: add support for dt phy definition ARM: at91/dt: define phy available on sama5d3 mother board arch/arm/boot/dts/sama5d3xmb.dtsi |8 ++ drivers/net/ethernet/cadence/macb.c | 48 +++ 2 files changed, 46 insertions(+), 10 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 1/2] net/cadence/macb: add support for dt phy definition
The macb driver only handle PHY description through platform_data
(macb_platform_data).
Thus, when using dt you cannot define phy properties like phy address or
phy irq pin.
This patch makes use of the of_mdiobus_register to add support for
phy device definition using dt.
A fallback to the autoscan procedure is added in case there is no phy
devices defined in dt.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/net/ethernet/cadence/macb.c | 48 +++
1 file changed, 38 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/ethernet/cadence/macb.c
index e866608..393afeb 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -27,6 +27,7 @@
#include linux/phy.h
#include linux/of.h
#include linux/of_device.h
+#include linux/of_mdio.h
#include linux/of_net.h
#include linux/pinctrl/consumer.h
@@ -275,7 +276,7 @@ static int macb_mii_probe(struct net_device *dev)
phydev = phy_find_first(bp-mii_bus);
if (!phydev) {
netdev_err(dev, no PHY found\n);
- return -1;
+ return -ENXIO;
}
pdata = dev_get_platdata(bp-pdev-dev);
@@ -314,6 +315,7 @@ static int macb_mii_probe(struct net_device *dev)
int macb_mii_init(struct macb *bp)
{
struct macb_platform_data *pdata;
+ struct device_node *np;
int err = -ENXIO, i;
/* Enable management port */
@@ -335,26 +337,52 @@ int macb_mii_init(struct macb *bp)
bp-mii_bus-parent = bp-dev-dev;
pdata = bp-pdev-dev.platform_data;
- if (pdata)
- bp-mii_bus-phy_mask = pdata-phy_mask;
-
bp-mii_bus-irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
if (!bp-mii_bus-irq) {
err = -ENOMEM;
goto err_out_free_mdiobus;
}
- for (i = 0; i PHY_MAX_ADDR; i++)
- bp-mii_bus-irq[i] = PHY_POLL;
-
dev_set_drvdata(bp-dev-dev, bp-mii_bus);
- if (mdiobus_register(bp-mii_bus))
+ np = bp-pdev-dev.of_node;
+ if (np) {
+ /* try dt phy registration */
+ err = of_mdiobus_register(bp-mii_bus, np);
+
+ /* fallback to standard phy registration if no phy were
+* found during dt phy registration
+*/
+ if (!err !phy_find_first(bp-mii_bus)) {
+ for (i = 0; i PHY_MAX_ADDR; i++) {
+ struct phy_device *phydev;
+
+ phydev = mdiobus_scan(bp-mii_bus, i);
+ if (IS_ERR(phydev)) {
+ err = PTR_ERR(phydev);
+ break;
+ }
+ }
+
+ if (err)
+ goto err_out_unregister_bus;
+ }
+ } else {
+ for (i = 0; i PHY_MAX_ADDR; i++)
+ bp-mii_bus-irq[i] = PHY_POLL;
+
+ if (pdata)
+ bp-mii_bus-phy_mask = pdata-phy_mask;
+
+ err = mdiobus_register(bp-mii_bus);
+ }
+
+ if (err)
goto err_out_free_mdio_irq;
- if (macb_mii_probe(bp-dev) != 0) {
+ err = macb_mii_probe(bp-dev);
+ if (err)
goto err_out_unregister_bus;
- }
return 0;
--
1.7.9.5
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[PATCH v3 2/2] ARM: at91/dt: define phy available on sama5d3 mother board
This patch describe the phy used on atmel sama5d3 mother board:
- phy address
- phy interrupt pin
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/sama5d3xmb.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi
b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 8a9e05d..dba739b 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -81,6 +81,14 @@
macb1: ethernet@f802c000 {
phy-mode = rmii;
+
+ #address-cells = 1;
+ #size-cells = 0;
+ phy0: ethernet-phy@1 {
+ interrupt-parent = pioE;
+ interrupts = 30 IRQ_TYPE_EDGE_FALLING;
+ reg = 1;
+ };
};
pinctrl@f200 {
--
1.7.9.5
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Re: [PATCH 0/2] net/cadence/macb: add support for dt phy definition
Hello Dave, On 26/08/2013 22:04, David Miller wrote: From: Boris BREZILLON b.brezil...@overkiz.com Date: Thu, 22 Aug 2013 17:56:20 +0200 This patch series adds support for ethernet phy definition using device tree. This may help in moving some at91 boards to dt (some of them define an interrupt pin). Tested on samad31ek. Series applied to net-next, thanks. Could you apply, the 3rd version of this series instead ? It fixes one bug when no phy is discovered and use the appropriate address for the phy dt node. Sorry for the inconvenience. Best Regards, Boris -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 0/2] net/cadence/macb: add support for dt phy definition
Hello David, Sorry, I forgot to add your email in the cc list. Do you want me to send you the whole series ? Best Regards, Boris On 27/08/2013 09:36, Boris BREZILLON wrote: Hello, This patch series adds support for ethernet phy definition using device tree. This may help in moving some at91 boards to dt (some of them define an interrupt pin). Tested on samad31ek. Best Regards, Boris Changes since v2: - fix wrong address of phy0 dt node Changes since v1: - fix wrong macb_mii_init return code when no PHY device is discovered Boris BREZILLON (2): net/cadence/macb: add support for dt phy definition ARM: at91/dt: define phy available on sama5d3 mother board arch/arm/boot/dts/sama5d3xmb.dtsi |8 ++ drivers/net/ethernet/cadence/macb.c | 48 +++ 2 files changed, 46 insertions(+), 10 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 1/3] pinctrl: add new generic pinconf config for deglitch filter
On 27/08/2013 09:42, Nicolas Ferre wrote: On 27/08/2013 08:16, boris brezillon : On 27/08/2013 05:55, Stephen Warren wrote: On 08/26/2013 11:01 AM, boris brezillon wrote: Hello Stephen, On 26/08/2013 18:50, Stephen Warren wrote: On 08/24/2013 03:35 PM, Boris BREZILLON wrote: Add a new parameter to support deglitch filter configuration. A deglitch filter works like a debounce filter but with a smaller delay (nanoseconds). Why not use the existing debounce property, just with a small delay specified. It seems like that's exactly what the property is for? That's one of the question I asked in my cover letter :-) Indeed the at91 deglitch filter delay is not configurable and is statically assigned to half a master clk cycle (if master clk = 133MHz - 8 ns). The debounce property argument is currently expressed in usecs. This will result in always selecting the debounce filter (which is also available on at91 SoCs) over the deglitch filter. Could we add a flag in the deglitch argument to specify the delay unit (nsecs or usecs) ? If the value is hard-coded in HW, why not use non-zero (or 1) to enable and zero to disable? Indeed at91 pins support both deglitch and debounce filter and I have to choose between the two given the argument value (in usec). Here's what I can do: if (arg = 1/2 * slowclock)/* debounce case */ /* choose debounce filter and configure the delay according to the given argument value */ else /* deglitch case */ /* choose deglitch filter */ Slow clock is running at 32KHz which gives a 30 usec clock cycle. I am not in favor for this kind of complicated heuristic. Deglitch and Debounce filters are different features in at91 (even if they pursuit the same goal). So I do prefer to let the user choose which feature is preferred for his application and add a different flag. (this kind of thing is why I'm not convinced that generic pinconf works so well... What if we need psecs in the future?) Should I keep the at91 native pinconf binding and add the missing flags to this binding (OUTPUT configuration flags) ? This was another question I asked in my cover letter: wether or not the generic pinconf binding should be used. The question is: how much this generic pinconf is... well... generic! And it is not a answer I can give. On the other hand, if the generic is not going to overcome the native pinctrl, I do not feel like switching to this at the cost of changing the whole dtsi/dts entries that we already have. So, it is more to Linus and Stephen to give us clues about this... Okay. I'll propose a new patch series adding native support for OUTPUT configuration of at91 pins (add OUTPUT_HIGH/LOW), and put this series in stand-by until a clear decision is made about generic pinconf. Thanks, Best Regards, Boris Bye, -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/2] net/cadence/macb: add support for dt phy definition
On 27/08/2013 11:07, Florian Fainelli wrote: Hello Boris, 2013/8/27 boris brezillon b.brezil...@overkiz.com: Hello Dave, On 26/08/2013 22:04, David Miller wrote: From: Boris BREZILLON b.brezil...@overkiz.com Date: Thu, 22 Aug 2013 17:56:20 +0200 This patch series adds support for ethernet phy definition using device tree. This may help in moving some at91 boards to dt (some of them define an interrupt pin). Tested on samad31ek. Series applied to net-next, thanks. Could you apply, the 3rd version of this series instead ? It fixes one bug when no phy is discovered and use the appropriate address for the phy dt node. Sorry for the inconvenience. You will probably have to resubmit an incremental patch, I have never seen David pick up another version of a patch once it has been pushed out: http://git.kernel.org/cgit/linux/kernel/git/davem/net-next.git/commit/?id=8c038e7e14b1c5f156745e3c4df0a3aa46173dd9 http://git.kernel.org/cgit/linux/kernel/git/davem/net-next.git/commit/?id=148cbb53ace32f584d208764c7f7e6aa8edb970c Okay, I will submit patches (based on net-next branch) to fix those bugs. Thanks. Best Regards, Boris -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: at91/dt: fix phy address to match the reg register
Fix phy0 address to match the reg porperty defined in phy0 node.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
Acked-by: Nicolas Ferre nicolas.fe...@atmel.com
---
arch/arm/boot/dts/sama5d3xmb.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi
b/arch/arm/boot/dts/sama5d3xmb.dtsi
index e9521d5..dba739b 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -84,7 +84,7 @@
#address-cells = 1;
#size-cells = 0;
- phy0: ethernet-phy@0 {
+ phy0: ethernet-phy@1 {
interrupt-parent = pioE;
interrupts = 30 IRQ_TYPE_EDGE_FALLING;
reg = 1;
--
1.7.9.5
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[PATCH] net/cadence/macb: fix invalid 0 return if no phy is discovered on mii init
Replace misleading -1 (-EPERM) by a more appropriate return code (-ENXIO)
in macb_mii_probe function.
Save macb_mii_probe return before branching to err_out_unregister to avoid
erronous 0 return.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
Acked-by: Nicolas Ferre nicolas.fe...@atmel.com
---
drivers/net/ethernet/cadence/macb.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/ethernet/cadence/macb.c
index fe06ab0..7660c45 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -276,7 +276,7 @@ static int macb_mii_probe(struct net_device *dev)
phydev = phy_find_first(bp-mii_bus);
if (!phydev) {
netdev_err(dev, no PHY found\n);
- return -1;
+ return -ENXIO;
}
pdata = dev_get_platdata(bp-pdev-dev);
@@ -379,9 +379,9 @@ int macb_mii_init(struct macb *bp)
if (err)
goto err_out_free_mdio_irq;
- if (macb_mii_probe(bp-dev) != 0) {
+ err = macb_mii_probe(bp-dev);
+ if (err)
goto err_out_unregister_bus;
- }
return 0;
--
1.7.9.5
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[PATCH v2] ARM: at91/dt: fix phy address in sama5xmb to match the reg property
Fix phy0 address to match the reg property defined in phy0 node.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
Acked-by: Nicolas Ferre nicolas.fe...@atmel.com
---
Changes since v1:
- better commit message
arch/arm/boot/dts/sama5d3xmb.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi
b/arch/arm/boot/dts/sama5d3xmb.dtsi
index e9521d5..dba739b 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -84,7 +84,7 @@
#address-cells = 1;
#size-cells = 0;
- phy0: ethernet-phy@0 {
+ phy0: ethernet-phy@1 {
interrupt-parent = pioE;
interrupts = 30 IRQ_TYPE_EDGE_FALLING;
reg = 1;
--
1.7.9.5
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Re: [PATCH v2] ARM: at91/dt: fix phy address in sama5xmb to match the reg property
Sorry for the noise, but the previous commit message was not clear enough.
On 27/08/2013 14:41, Boris BREZILLON wrote:
Fix phy0 address to match the reg property defined in phy0 node.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
Acked-by: Nicolas Ferre nicolas.fe...@atmel.com
---
Changes since v1:
- better commit message
arch/arm/boot/dts/sama5d3xmb.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi
b/arch/arm/boot/dts/sama5d3xmb.dtsi
index e9521d5..dba739b 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -84,7 +84,7 @@
#address-cells = 1;
#size-cells = 0;
- phy0: ethernet-phy@0 {
+ phy0: ethernet-phy@1 {
interrupt-parent = pioE;
interrupts = 30 IRQ_TYPE_EDGE_FALLING;
reg = 1;
--
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[PATCH] pinctrl: at91: fix get_pullup/down function return
In PIO_PUSR and PIO_PPDSR register if a given bit is set 1 this means the
pullup/down for this pin (pin is represented as a bit position) is
disabled.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/pinctrl/pinctrl-at91.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index b90a3a0..19afb9a 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -325,7 +325,7 @@ static void at91_mux_disable_interrupt(void __iomem *pio,
unsigned mask)
static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
{
- return (readl_relaxed(pio + PIO_PUSR) pin) 0x1;
+ return !((readl_relaxed(pio + PIO_PUSR) pin) 0x1);
}
static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
@@ -445,7 +445,7 @@ static void at91_mux_pio3_set_debounce(void __iomem *pio,
unsigned mask,
static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
{
- return (__raw_readl(pio + PIO_PPDSR) pin) 0x1;
+ return !((__raw_readl(pio + PIO_PPDSR) pin) 0x1);
}
static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool
is_on)
--
1.7.9.5
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[PATCH] ARM: at91/at91-pinctrl documentation: add missing sam9x5 compatible string
Add missing atmel,at91sam9x5-pinctrl compatible string to the documentation. Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com --- .../bindings/pinctrl/atmel,at91-pinctrl.txt|2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt index 648d60e..cf7c7bc 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt @@ -18,7 +18,7 @@ mode) this pin can work on and the 'config' configures various pad settings such as pull-up, multi drive, etc. Required properties for iomux controller: -- compatible: atmel,at91rm9200-pinctrl +- compatible: atmel,at91rm9200-pinctrl or atmel,at91sam9x5-pinctrl - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be configured in this periph mode. All the periph and bank need to be describe. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] pinctrl: at91: add support for OUTPUT config
Add support for pin output control through the pinctrl config:
- support enabling/disabling output on a given pin
- support output level setting (high or low)
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
.../bindings/pinctrl/atmel,at91-pinctrl.txt|2 ++
drivers/pinctrl/pinctrl-at91.c | 22
include/dt-bindings/pinctrl/at91.h |2 ++
3 files changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index cf7c7bc..5a22e0d 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -90,6 +90,8 @@ MULTIDRIVE(1 1): indicate this pin need to be
configured as multidrive.
DEGLITCH (1 2): indicate this pin need deglitch.
PULL_DOWN (1 3): indicate this pin need a pull down.
DIS_SCHMIT (1 4): indicate this pin need to disable schmit trigger.
+OUTPUT (1 5): indicate this pin need to be configured as an output.
+OUTPUT_VAL (0x1 6): output val (1 = high, 0 = low)
DEBOUNCE (1 16): indicate this pin need debounce.
DEBOUNCE_VAL (0x3fff 17): debounce val.
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 19afb9a..1578a0d 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -61,6 +61,9 @@ static int gpio_banks;
#define DEGLITCH (1 2)
#define PULL_DOWN (1 3)
#define DIS_SCHMIT (1 4)
+#define OUTPUT (1 5)
+#define OUTPUT_VAL_SHIFT 6
+#define OUTPUT_VAL (0x1 OUTPUT_VAL_SHIFT)
#define DEBOUNCE (1 16)
#define DEBOUNCE_VAL_SHIFT 17
#define DEBOUNCE_VAL (0x3fff DEBOUNCE_VAL_SHIFT)
@@ -333,6 +336,19 @@ static void at91_mux_set_pullup(void __iomem *pio,
unsigned mask, bool on)
writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
}
+static bool at91_mux_get_output(void __iomem *pio, unsigned pin, bool *val)
+{
+ *val = (readl_relaxed(pio + PIO_ODSR) pin) 0x1;
+ return (readl_relaxed(pio + PIO_OSR) pin) 0x1;
+}
+
+static void at91_mux_set_output(void __iomem *pio, unsigned mask, bool is_on,
+ bool val)
+{
+ writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
+ writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
+}
+
static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
{
return (readl_relaxed(pio + PIO_MDSR) pin) 0x1;
@@ -712,6 +728,7 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
void __iomem *pio;
unsigned pin;
int div;
+ bool out;
dev_dbg(info-dev, %s:%d, pin_id=%d, config=0x%lx, __func__,
__LINE__, pin_id, *config);
pio = pin_to_controller(info, pin_to_bank(pin_id));
@@ -732,6 +749,9 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
if (info-ops-get_schmitt_trig info-ops-get_schmitt_trig(pio,
pin))
*config |= DIS_SCHMIT;
+ if (at91_mux_get_output(pio, pin, out))
+ *config |= OUTPUT | (out OUTPUT_VAL_SHIFT);
+
return 0;
}
@@ -749,6 +769,8 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
if (config PULL_UP config PULL_DOWN)
return -EINVAL;
+ at91_mux_set_output(pio, mask, config OUTPUT,
+ (config OUTPUT_VAL) OUTPUT_VAL_SHIFT);
at91_mux_set_pullup(pio, mask, config PULL_UP);
at91_mux_set_multidrive(pio, mask, config MULTI_DRIVE);
if (info-ops-set_deglitch)
diff --git a/include/dt-bindings/pinctrl/at91.h
b/include/dt-bindings/pinctrl/at91.h
index d7988b4..9fd4d48 100644
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -15,6 +15,8 @@
#define AT91_PINCTRL_DEGLITCH (1 2)
#define AT91_PINCTRL_PULL_DOWN (1 3)
#define AT91_PINCTRL_DIS_SCHMIT(1 4)
+#define AT91_PINCTRL_OUTPUT(1 5)
+#define AT91_PINCTRL_OUTPUT_VAL(x) ((x 0x1) 6)
#define AT91_PINCTRL_DEBOUNCE (1 16)
#define AT91_PINCTRL_DEBOUNCE_VA(x)(x 17)
--
1.7.9.5
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Re: [PATCH] pinctrl: at91: add support for OUTPUT config
This was tested on sama5d31ek.
On 27/08/2013 16:51, Boris BREZILLON wrote:
Add support for pin output control through the pinctrl config:
- support enabling/disabling output on a given pin
- support output level setting (high or low)
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
.../bindings/pinctrl/atmel,at91-pinctrl.txt|2 ++
drivers/pinctrl/pinctrl-at91.c | 22
include/dt-bindings/pinctrl/at91.h |2 ++
3 files changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index cf7c7bc..5a22e0d 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -90,6 +90,8 @@ MULTIDRIVE(1 1): indicate this pin need to be
configured as multidrive.
DEGLITCH (1 2): indicate this pin need deglitch.
PULL_DOWN (1 3): indicate this pin need a pull down.
DIS_SCHMIT(1 4): indicate this pin need to disable schmit trigger.
+OUTPUT (1 5): indicate this pin need to be configured as an output.
+OUTPUT_VAL (0x1 6): output val (1 = high, 0 = low)
DEBOUNCE (1 16): indicate this pin need debounce.
DEBOUNCE_VAL (0x3fff 17): debounce val.
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 19afb9a..1578a0d 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -61,6 +61,9 @@ static int gpio_banks;
#define DEGLITCH (1 2)
#define PULL_DOWN (1 3)
#define DIS_SCHMIT(1 4)
+#define OUTPUT (1 5)
+#define OUTPUT_VAL_SHIFT 6
+#define OUTPUT_VAL (0x1 OUTPUT_VAL_SHIFT)
#define DEBOUNCE (1 16)
#define DEBOUNCE_VAL_SHIFT17
#define DEBOUNCE_VAL (0x3fff DEBOUNCE_VAL_SHIFT)
@@ -333,6 +336,19 @@ static void at91_mux_set_pullup(void __iomem *pio,
unsigned mask, bool on)
writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
}
+static bool at91_mux_get_output(void __iomem *pio, unsigned pin, bool *val)
+{
+ *val = (readl_relaxed(pio + PIO_ODSR) pin) 0x1;
+ return (readl_relaxed(pio + PIO_OSR) pin) 0x1;
+}
+
+static void at91_mux_set_output(void __iomem *pio, unsigned mask, bool is_on,
+ bool val)
+{
+ writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
+ writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
+}
+
static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
{
return (readl_relaxed(pio + PIO_MDSR) pin) 0x1;
@@ -712,6 +728,7 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
void __iomem *pio;
unsigned pin;
int div;
+ bool out;
dev_dbg(info-dev, %s:%d, pin_id=%d, config=0x%lx, __func__, __LINE__, pin_id, *config);
pio = pin_to_controller(info, pin_to_bank(pin_id));
@@ -732,6 +749,9 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
if (info-ops-get_schmitt_trig info-ops-get_schmitt_trig(pio,
pin))
*config |= DIS_SCHMIT;
+ if (at91_mux_get_output(pio, pin, out))
+ *config |= OUTPUT | (out OUTPUT_VAL_SHIFT);
+
return 0;
}
@@ -749,6 +769,8 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
if (config PULL_UP config PULL_DOWN)
return -EINVAL;
+ at91_mux_set_output(pio, mask, config OUTPUT,
+ (config OUTPUT_VAL) OUTPUT_VAL_SHIFT);
at91_mux_set_pullup(pio, mask, config PULL_UP);
at91_mux_set_multidrive(pio, mask, config MULTI_DRIVE);
if (info-ops-set_deglitch)
diff --git a/include/dt-bindings/pinctrl/at91.h
b/include/dt-bindings/pinctrl/at91.h
index d7988b4..9fd4d48 100644
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -15,6 +15,8 @@
#define AT91_PINCTRL_DEGLITCH (1 2)
#define AT91_PINCTRL_PULL_DOWN(1 3)
#define AT91_PINCTRL_DIS_SCHMIT (1 4)
+#define AT91_PINCTRL_OUTPUT(1 5)
+#define AT91_PINCTRL_OUTPUT_VAL(x) ((x 0x1) 6)
#define AT91_PINCTRL_DEBOUNCE (1 16)
#define AT91_PINCTRL_DEBOUNCE_VA(x) (x 17)
--
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Re: [PATCH 0/2] net/cadence/macb: add support for dt phy definition
On 27/08/2013 18:20, David Miller wrote: From: boris brezillon b.brezil...@overkiz.com Date: Tue, 27 Aug 2013 09:42:34 +0200 Could you apply, the 3rd version of this series instead ? There can never be an instead or reverting patches I've said I've applied already. If you want changes, you have to submit follow-on fixes. Hello David, I sent the incremental patches based on your net-next branch: https://lkml.org/lkml/2013/8/27/257 https://lkml.org/lkml/2013/8/27/259 Thanks. Best Regards, Boris -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] pinctrl: at91: add support for OUTPUT config
On 28/08/2013 09:31, Nicolas Ferre wrote:
On 27/08/2013 16:51, Boris BREZILLON :
Add support for pin output control through the pinctrl config:
- support enabling/disabling output on a given pin
- support output level setting (high or low)
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
.../bindings/pinctrl/atmel,at91-pinctrl.txt|2 ++
drivers/pinctrl/pinctrl-at91.c | 22
include/dt-bindings/pinctrl/at91.h |2 ++
3 files changed, 26 insertions(+)
diff --git
a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index cf7c7bc..5a22e0d 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -90,6 +90,8 @@ MULTIDRIVE(1 1): indicate this pin need to
be configured as multidrive.
DEGLITCH(1 2): indicate this pin need deglitch.
PULL_DOWN(1 3): indicate this pin need a pull down.
DIS_SCHMIT(1 4): indicate this pin need to disable schmit
trigger.
+OUTPUT(1 5): indicate this pin need to be configured as
an output.
+OUTPUT_VAL(0x1 6): output val (1 = high, 0 = low)
DEBOUNCE(1 16): indicate this pin need debounce.
DEBOUNCE_VAL(0x3fff 17): debounce val.
diff --git a/drivers/pinctrl/pinctrl-at91.c
b/drivers/pinctrl/pinctrl-at91.c
index 19afb9a..1578a0d 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -61,6 +61,9 @@ static int gpio_banks;
#define DEGLITCH(1 2)
#define PULL_DOWN(1 3)
#define DIS_SCHMIT(1 4)
+#define OUTPUT(1 5)
+#define OUTPUT_VAL_SHIFT6
+#define OUTPUT_VAL(0x1 OUTPUT_VAL_SHIFT)
#define DEBOUNCE(1 16)
#define DEBOUNCE_VAL_SHIFT17
#define DEBOUNCE_VAL(0x3fff DEBOUNCE_VAL_SHIFT)
@@ -333,6 +336,19 @@ static void at91_mux_set_pullup(void __iomem
*pio, unsigned mask, bool on)
writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
}
+static bool at91_mux_get_output(void __iomem *pio, unsigned pin,
bool *val)
+{
+*val = (readl_relaxed(pio + PIO_ODSR) pin) 0x1;
+return (readl_relaxed(pio + PIO_OSR) pin) 0x1;
+}
+
+static void at91_mux_set_output(void __iomem *pio, unsigned mask,
bool is_on,
+bool val)
+{
+writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
+writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
+}
+
static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned
pin)
{
return (readl_relaxed(pio + PIO_MDSR) pin) 0x1;
@@ -712,6 +728,7 @@ static int at91_pinconf_get(struct pinctrl_dev
*pctldev,
void __iomem *pio;
unsigned pin;
int div;
+bool out;
dev_dbg(info-dev, %s:%d, pin_id=%d, config=0x%lx, __func__,
__LINE__, pin_id, *config);
pio = pin_to_controller(info, pin_to_bank(pin_id));
@@ -732,6 +749,9 @@ static int at91_pinconf_get(struct pinctrl_dev
*pctldev,
if (info-ops-get_schmitt_trig
info-ops-get_schmitt_trig(pio, pin))
*config |= DIS_SCHMIT;
+if (at91_mux_get_output(pio, pin, out))
+*config |= OUTPUT | (out OUTPUT_VAL_SHIFT);
+
return 0;
}
@@ -749,6 +769,8 @@ static int at91_pinconf_set(struct pinctrl_dev
*pctldev,
if (config PULL_UP config PULL_DOWN)
return -EINVAL;
+at91_mux_set_output(pio, mask, config OUTPUT,
+(config OUTPUT_VAL) OUTPUT_VAL_SHIFT);
at91_mux_set_pullup(pio, mask, config PULL_UP);
at91_mux_set_multidrive(pio, mask, config MULTI_DRIVE);
if (info-ops-set_deglitch)
diff --git a/include/dt-bindings/pinctrl/at91.h
b/include/dt-bindings/pinctrl/at91.h
index d7988b4..9fd4d48 100644
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -15,6 +15,8 @@
#define AT91_PINCTRL_DEGLITCH(1 2)
#define AT91_PINCTRL_PULL_DOWN(1 3)
#define AT91_PINCTRL_DIS_SCHMIT(1 4)
+#define AT91_PINCTRL_OUTPUT(1 5)
+#define AT91_PINCTRL_OUTPUT_VAL(x)((x 0x1) 6)
Can you add this change to the documentation as well:
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
#define AT91_PINCTRL_DEBOUNCE(1 16)
#define AT91_PINCTRL_DEBOUNCE_VA(x)(x 17)
Oh, we have a nice typo here! ---^^
And moreover it would be good to add the mask as well.
Do you want me to fix this typo and add mask for DEBOUNCE
in a separate patch ?
Once the documentation added, you can stick my:
Acked-by: Nicolas Ferre nicolas.fe...@atmel.com
Thanks, bye,
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[PATCH 1/9] ARM: at91/dt: add rm9200 spi0 chip select pins definitions
Add spi0 cs pinctrl pins definitions.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/at91rm9200.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi
b/arch/arm/boot/dts/at91rm9200.dtsi
index f770655..69b76c7 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -486,6 +486,26 @@
AT91_PIOA 1
AT91_PERIPH_A AT91_PINCTRL_NONE/* PA1 periph A SPI0_MOSI pin */
AT91_PIOA 2
AT91_PERIPH_A AT91_PINCTRL_NONE; /* PA2 periph A SPI0_SPCK pin */
};
+
+ pinctrl_spi0_cs0: spi0_cs0-0 {
+ atmel,pins =
+ AT91_PIOA 3
AT91_PERIPH_A AT91_PINCTRL_NONE; /* PA3 periph A SPI0_NPCS0 pin */
+ };
+
+ pinctrl_spi0_cs1: spi0_cs1-0 {
+ atmel,pins =
+ AT91_PIOA 4
AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE;/* PA4 GPIO SPI0_NPCS1 pin */
+ };
+
+ pinctrl_spi0_cs2: spi0_cs2-0 {
+ atmel,pins =
+ AT91_PIOA 5
AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE;/* PA5 GPIO SPI0_NPCS2 pin */
+ };
+
+ pinctrl_spi0_cs3: spi0_cs3-0 {
+ atmel,pins =
+ AT91_PIOA 6
AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE;/* PA6 GPIO SPI0_NPCS3 pin */
+ };
};
pioA: gpio@f400 {
--
1.7.9.5
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[PATCH 2/9] ARM: at91/dt: add ethernet phy to at91rm9200ek board
Add ethernet phy node in at91rm9200ek.dts.
The reg register is not specified, as it may differ depending on the init
process of the board:
ADDR0/1 phy pins are connected to PA13/14 rm9200 pins. Which means the phy
will take its address from these pins during the reset process.
The macb driver will launch a full scan on the mdio bus to discover the phy
address.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/at91rm9200ek.dts |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts
b/arch/arm/boot/dts/at91rm9200ek.dts
index d2d72c3..37b0880 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -47,6 +47,11 @@
macb0: ethernet@fffbc000 {
phy-mode = rmii;
status = okay;
+
+ phy0: ethernet-phy {
+ interrupt-parent = pioC;
+ interrupts = 4 IRQ_TYPE_EDGE_FALLING;
+ };
};
usb1: gadget@fffb {
--
1.7.9.5
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[PATCH 3/9] ARM: at91/dt: add usb1 vbus and pullup pins
Add vbus and pullup pinctrl definitions.
Request the vbus and pullup pins in usb1 node.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/at91rm9200ek.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts
b/arch/arm/boot/dts/at91rm9200ek.dts
index 37b0880..76f3e87 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -29,6 +29,18 @@
ahb {
apb {
+ pinctrl@f400 {
+ usb1 {
+ pinctrl_usb1_vbus: usb1_vbus-0 {
+ atmel,pins = AT91_PIOD 4
AT91_PERIPH_GPIO AT91_PINCTRL_NONE;
+ };
+
+ pinctrl_usb1_pullup: usb1_pullup-0 {
+ atmel,pins = AT91_PIOD 5
AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE;
+ };
+ };
+ };
+
dbgu: serial@f200 {
status = okay;
};
@@ -56,6 +68,9 @@
usb1: gadget@fffb {
atmel,vbus-gpio = pioD 4 GPIO_ACTIVE_HIGH;
+ pinctrl-names = default;
+ pinctrl-0 = pinctrl_usb1_vbus
+pinctrl_usb1_pullup;
status = okay;
};
--
1.7.9.5
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[PATCH 4/9] ARM: at91/dt: add atmel,pullup-gpio to at91rm9200ek usb1 definition
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/at91rm9200ek.dts |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts
b/arch/arm/boot/dts/at91rm9200ek.dts
index 76f3e87..f2d6d79 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -68,6 +68,7 @@
usb1: gadget@fffb {
atmel,vbus-gpio = pioD 4 GPIO_ACTIVE_HIGH;
+ atmel,pullup-gpio = pioD 5 GPIO_ACTIVE_HIGH;
pinctrl-names = default;
pinctrl-0 = pinctrl_usb1_vbus
pinctrl_usb1_pullup;
--
1.7.9.5
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[PATCH 6/9] ARM: at91/dt: add spi0 support to at91rm9200ek board
Add spi0 cs3 switch pinctrl pin definitions: this pin is used to select
between mmc0 slot0 and spi dataflash connected to cs3.
Enable spi0 controller and define the mtd_dataflash connected to cs0.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/at91rm9200ek.dts | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts
b/arch/arm/boot/dts/at91rm9200ek.dts
index 2bad423..b3e7425 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -56,6 +56,13 @@
AT91_PIOB 22
AT91_PERIPH_GPIO (AT91_PINCTRL_OUTPUT | AT91_PINCTRL_OUTPUT_VAL(1));
};
};
+
+ spi0 {
+ pinctrl_spi0_cs3_switch:
spi0_cs3_switch-0 {
+ atmel,pins =
+ AT91_PIOB 22
AT91_PERIPH_GPIO (AT91_PINCTRL_OUTPUT | AT91_PINCTRL_OUTPUT_VAL(0));
+ };
+ };
};
dbgu: serial@f200 {
@@ -119,6 +126,19 @@
wp-gpios = pioA 17 GPIO_ACTIVE_HIGH;
};
};
+
+ spi0: spi@fffe {
+ pinctrl-0 = pinctrl_spi0 pinctrl_spi0_cs0;
+ cs-gpios = pioA 3 GPIO_ACTIVE_HIGH, 0,
+ 0, 0;
+ status = okay;
+
+ mtd_dataflash@0 {
+ compatible = atmel,at45,
atmel,dataflash;
+ spi-max-frequency = 1500;
+ reg = 0;
+ };
+ };
};
usb0: ohci@0030 {
--
1.7.9.5
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[PATCH 5/9] ARM: at91/dt: add mmc0 slot0 support to at91rm9200ek board
Add slot0 of mmc0 pinctrl pins definitions:
- detect pin
- write protect pin
- enable slot0 pin: this pin is connected to an external switch which
enable mmc0 slot0 or spi dataflash connected to cs3
The mmc0 device is not enabled, as it depends on the choosen functionnality
(spi cs3 or mmc0 slot0).
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/at91rm9200ek.dts | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts
b/arch/arm/boot/dts/at91rm9200ek.dts
index f2d6d79..2bad423 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -39,6 +39,23 @@
atmel,pins = AT91_PIOD 5
AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE;
};
};
+
+ mmc0 {
+ pinctrl_mmc0_slot0_detect:
mmc0_slot0_detect-0 {
+ atmel,pins =
+ AT91_PIOB 27
AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH;
+ };
+
+ pinctrl_mmc0_slot0_write_protect:
mmc0_slot0_write_protect-0 {
+ atmel,pins =
+ AT91_PIOA 17
AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP;
+ };
+
+ pinctrl_mmc0_slot0_switch:
mmc0_slot0_switch-0 {
+ atmel,pins =
+ AT91_PIOB 22
AT91_PERIPH_GPIO (AT91_PINCTRL_OUTPUT | AT91_PINCTRL_OUTPUT_VAL(1));
+ };
+ };
};
dbgu: serial@f200 {
@@ -84,6 +101,24 @@
reg = 0;
};
};
+
+ mmc0: mmc@fffb4000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-0 = pinctrl_mmc0_clk
+pinctrl_mmc0_slot0_cmd_dat0
+pinctrl_mmc0_slot0_dat1_3
+pinctrl_mmc0_slot0_detect
+pinctrl_mmc0_slot0_write_protect
+pinctrl_mmc0_slot0_switch;
+
+ slot0: slot@0 {
+ reg = 0;
+ bus-width = 4;
+ cd-gpios = pioB 27 GPIO_ACTIVE_HIGH;
+ wp-gpios = pioA 17 GPIO_ACTIVE_HIGH;
+ };
+ };
};
usb0: ohci@0030 {
--
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[PATCH 7/9] ARM: at91/dt: add i2c devices connected to at91rm9200ek board
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/at91rm9200ek.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts
b/arch/arm/boot/dts/at91rm9200ek.dts
index b3e7425..fd2601a 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -147,6 +147,18 @@
};
};
+ i2c@0 {
+ status = okay;
+
+ ics1523@26 {
+ reg = 0x26;
+ };
+
+ dac3550@4d {
+ reg = 0x4d;
+ };
+ };
+
leds {
compatible = gpio-leds;
--
1.7.9.5
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[PATCH 0/9] ARM: at91/dt: add missing devices to rm9200ek board
Hello, This patch series adds support for the remaining devices (or device options) not yet supported in dt. AFAICT there is no more infos/devices not converted to dt for this board, and we should be able to remove board-at91rm9200ek.c (when we decide to do it). This series was not tested (the dt compilation passed), could someone owning this board test it ? In order to test it, you need to apply these series first: https://lkml.org/lkml/2013/8/27/58 pinctrl: at91: add support for OUTPUT config Best Regards, Boris Boris BREZILLON (9): ARM: at91/dt: rm9200: add spi0 chip select pins definitions ARM: at91/dt: add ethernet phy to at91rm9200ek board ARM: at91/dt: add usb1 vbus and pullup pins ARM: at91/dt: add atmel,pullup-gpio to at91rm9200ek usb1 definition ARM: at91/dt: add mmc0 slot0 support to at91rm9200ek board ARM: at91/dt: add spi0 support to at91rm9200ek board ARM: at91/dt: add i2c devices connected to at91rm9200ek board ARM: at91/dt: add new at91rm9200ek_mmc board ARM: at91/dt: add new at91rm9200ek_dataflash board arch/arm/boot/dts/at91rm9200.dtsi| 20 ++ arch/arm/boot/dts/at91rm9200ek.dts | 88 ++ arch/arm/boot/dts/at91rm9200ek_dataflash.dts | 33 ++ arch/arm/boot/dts/at91rm9200ek_mmc.dts | 23 +++ 4 files changed, 164 insertions(+) create mode 100644 arch/arm/boot/dts/at91rm9200ek_dataflash.dts create mode 100644 arch/arm/boot/dts/at91rm9200ek_mmc.dts -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 8/9] ARM: at91/dt: add new at91rm9200ek_mmc board
Add a new at91rm9200ek_mmc board (based on at91rm9200ek board) which enables
mmc0/slot0.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/at91rm9200ek_mmc.dts | 23 +++
1 file changed, 23 insertions(+)
create mode 100644 arch/arm/boot/dts/at91rm9200ek_mmc.dts
diff --git a/arch/arm/boot/dts/at91rm9200ek_mmc.dts
b/arch/arm/boot/dts/at91rm9200ek_mmc.dts
new file mode 100644
index 000..c87a861
--- /dev/null
+++ b/arch/arm/boot/dts/at91rm9200ek_mmc.dts
@@ -0,0 +1,23 @@
+/*
+ * at91rm9200ek.dts - Device Tree file for Atmel AT91RM9200 evaluation kit with
+ *an MMC slot
+ *
+ * Copyright (C) 2013 Boris BREZILLON b.brezil...@overkiz.com
+ *
+ * Licensed under GPLv2 only
+ */
+/dts-v1/;
+#include at91rm9200ek.dts
+
+/ {
+ model = Atmel AT91RM9200 evaluation kit with MMC slot;
+ compatible = atmel,at91rm9200ek-mmc, atmel,at91rm9200ek,
atmel,at91rm9200;
+
+ ahb {
+ apb {
+ mmc0: mmc@fffb4000 {
+ status = okay;
+ };
+ };
+ };
+};
--
1.7.9.5
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[PATCH 9/9] ARM: at91/dt: add new at91rm9200ek_dataflash board
Add a new at91rm9200ek_dataflash board (based on at91rm9200ek board) which
enables dataflash connected to cs3 of spi0.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/at91rm9200ek_dataflash.dts | 33 ++
1 file changed, 33 insertions(+)
create mode 100644 arch/arm/boot/dts/at91rm9200ek_dataflash.dts
diff --git a/arch/arm/boot/dts/at91rm9200ek_dataflash.dts
b/arch/arm/boot/dts/at91rm9200ek_dataflash.dts
new file mode 100644
index 000..a43412e
--- /dev/null
+++ b/arch/arm/boot/dts/at91rm9200ek_dataflash.dts
@@ -0,0 +1,33 @@
+/*
+ * at91rm9200ek.dts - Device Tree file for Atmel AT91RM9200 evaluation kit with
+ *2 SPI dataflash
+ *
+ * Copyright (C) 2013 Boris BREZILLON b.brezil...@overkiz.com
+ *
+ * Licensed under GPLv2 only
+ */
+/dts-v1/;
+#include at91rm9200ek.dts
+
+/ {
+ model = Atmel AT91RM9200 evaluation kit with 2 SPI dataflash;
+ compatible = atmel,at91rm9200ek-dataflash, atmel,at91rm9200ek,
atmel,at91rm9200;
+
+ ahb {
+ apb {
+ spi0: spi@fffe {
+ pinctrl-0 = pinctrl_spi0 pinctrl_spi0_cs0
+pinctrl_spi0_cs3
+pinctrl_spi0_cs3_switch;
+ cs-gpios = pioA 3 GPIO_ACTIVE_HIGH, 0,
+ 0, pioA 6 GPIO_ACTIVE_HIGH;
+
+ mtd_dataflash@3 {
+ compatible = atmel,at45,
atmel,dataflash;
+ spi-max-frequency = 1500;
+ reg = 3;
+ };
+ };
+ };
+ };
+};
--
1.7.9.5
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Re: [RFC PATCH 3/3] ARM: at91/dt: move sama5 to generic pinconf
Hello Linus,
On 28/08/2013 14:28, Linus Walleij wrote:
On Sat, Aug 24, 2013 at 11:40 PM, Boris BREZILLON
b.brezil...@overkiz.com wrote:
Add generic pinconf definitions and reference appropriate configs in
atmel,pins properties.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
(...)
pinctrl@f200 {
#address-cells = 1;
#size-cells = 1;
- compatible = atmel,at91sam9x5-pinctrl,
atmel,at91rm9200-pinctrl, simple-bus;
+ compatible = atmel,at91sam9x5-pinctrl,
atmel,at91rm9200-pinctrl, generic-pinconf, simple-bus;
What kind of compatible string is that generic-pinconf?
There is no driver that can instantiate against this string but I'm not
100% sure about such things. Is there some other driver doing this?
Else I think it'd just be removed.
It did not exist before this patch series.
I thought it would be good idea to add a compatible string to tell if
the pinctrl subnodes support the generic-pinconf binding,
without modifying the current compatible strings:
if compatible string contains the generic-pinconf then the pinconf
definitions should be considered generic.
However, after discussing it with Stephen, Jean-Christophe and Nicolas,
I no longer think this is a good idea
(backward compatibility issues).
+ pcfg_none: pcfg_none {
+ bias-disable;
+ };
+
+ pcfg_pull_up: pcfg_pull_up {
+ bias-pull-up;
+ };
Nice.
+ pcfg_deglitch: pcfg_deglitch {
+ input-deglitch = 1;
+ };
+
+ pcfg_pull_up_deglitch: pcfg_pull_up_deglitch {
+ bias-pull-up;
+ input-deglitch = 1;
+ };
input-deglitch seems like a proposed generic binding but I haven't seen
these yet?
(It might be in my violently exploding INBOX though sorry in that case.)
This would need adding to
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
Plus changes to pinctrl core for handling.
This was added in the first patch of this series:
https://lkml.org/lkml/2013/8/24/99
BTW: this is really moving in the right direction!
Yours,
Linus Walleij
Thanks.
Best Regards,
Boris
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Re: [PATCH] pinctrl: at91: add support for OUTPUT config
On 28/08/2013 15:48, Linus Walleij wrote: On Wed, Aug 28, 2013 at 3:46 PM, Linus Walleij linus.wall...@linaro.org wrote: On Tue, Aug 27, 2013 at 4:51 PM, Boris BREZILLON b.brezil...@overkiz.com wrote: Add support for pin output control through the pinctrl config: - support enabling/disabling output on a given pin - support output level setting (high or low) Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com NAK. We already have this: * @PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument * 1 to indicate high level, argument 0 to indicate low level. It also has device tree bindings: output-low - set the pin to output mode with low level output-high - set the pin to output mode with high level Bah maybe I'm misunderstanding :-( So this is not part of the generic pin config series, but something stand-alone to augment the existing driver to do this? This is a proposal to add support for OUTPUT config using native at91 pinconf binding (not generic pinconf binding). I did this to get support for OUTPUT config quickly. The generic pinconf binding is still in discussion, and will be added as soon as at91 maintainers and pinctrl maintainers agree on how this should be done. So I just apply this patch right off then? I don't know, I think we should wait for Jean-Christophe approval. Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 00/19] ARM: at91: move to common clk framework
Hello Mike, Could you take a look at this patch series ? I'd like to have your opinion on some key points: - at91 clk dt bindings - in some clk_prepare (pll clks, main clk) callbacks I make use of wait_event to wait for an interrupt. Should I do it this way or instead use the cpu_relax function ? - some clks define clk_prepare but not clk_enable (enabling work is done in clk_prepare). Is it okay to leave this callback empty and rely on the default behaviour (enable count increment) ? - at91 clk implemetation in its whole Best Regards, Boris On 08/08/2013 06:53, Boris BREZILLON wrote: Hello, This patch series is the 3rd version of the new at91 clock implementation (using common clk framework). Most of the clock provided by the PMC (Power Management Controller) are implemented : - main clock (main oscillator) - pll clocks - master clock - programmable clocks - utmi clock - peripheral clocks - system clocks This implementation is only compatible with device tree definition. The goal is to define the whole clock tree in the device tree. Please feel free to comment the dt bindinds. This patch series is based on linux-next and has been tested on sama5d31ek board using device tree. It compiles for other SoCs and both with and but it has not been tested (Richard, I did not add your Tested-by because a lot of things have changed since v2). BTW could other people test it on other boards (I only have a kizbox and a sama5d31ek dev kit). Best Regards, Boris Changes since v2: - fix several bugs in clk implementations - drop non-dt boards support - split the series to ease review and tests: * 1 patch series for new clk implementations (this series) * 1 patch series to move each at91 SoC to common clk framework (coming soon) - modify dt-bindings (add atmel,clk- prefix to atmel specific properties) - add clk macros for dt-bindings - add pmc framework (helper function to access pmc registers) - add interrupt support to enable passive wait in clk_prepare functions Changes since v1: - fix bugs in pll, programmable and system clock implementations (wrong bit position). - add usb clock configuration support (ohci and udc drivers + clk_lookup for non dt boards) - rework of the system clock interfaces (no need to define a parent clock, system clock is a gate with no rate info) - change system, peripheral and programmable clk dt bindings (1 master node and multiple child nodes each defining a system/peripheral or prog clock) - fix bugs in sama5 dt definition Boris BREZILLON (19): ARM: at91: move at91_pmc.h to include/linux/clk/at91_pmc.h ARM: at91: add Kconfig options for common clk support clk: at91: add PMC base support clk: at91: add PMC macro file for dt definitions clk: at91: add PMC main clock clk: at91: add PMC pll clocks clk: at91: add pll id macros for pll dt bindings clk: at91: add PMC master clock clk: at91: add PMC system clocks ARM: at91/dt: add system clk id definitions in dt-bindings include dir clk: at91: add PMC peripheral clocks clk: at91: add peripheral clk macros for peripheral clk dt bindings clk: at91: add PMC programmable clocks clk: at91: add PMC utmi clock clk: at91: add PMC usb clock clk: at91: add PMC smd clock clk: at91: add PMC clk device tree binding doc. ARM: at91: move pit timer to common clk framework ARM: at91: add new compatible strings for pmc driver .../devicetree/bindings/clock/at91-clock.txt | 312 arch/arm/mach-at91/Kconfig | 44 ++ arch/arm/mach-at91/Kconfig.non_dt |6 + arch/arm/mach-at91/Makefile|2 +- arch/arm/mach-at91/at91rm9200.c|2 +- arch/arm/mach-at91/at91sam9260.c |2 +- arch/arm/mach-at91/at91sam9261.c |2 +- arch/arm/mach-at91/at91sam9263.c |2 +- arch/arm/mach-at91/at91sam926x_time.c | 14 +- arch/arm/mach-at91/at91sam9g45.c |2 +- arch/arm/mach-at91/at91sam9n12.c |2 +- arch/arm/mach-at91/at91sam9rl.c|2 +- arch/arm/mach-at91/at91sam9x5.c|2 +- arch/arm/mach-at91/clock.c |8 +- arch/arm/mach-at91/generic.h |3 +- arch/arm/mach-at91/pm.c|2 +- arch/arm/mach-at91/pm_slowclock.S |2 +- arch/arm/mach-at91/sama5d3.c |2 +- arch/arm/mach-at91/setup.c |8 +- drivers/clk/Makefile |1 + drivers/clk/at91/Makefile | 12 + drivers/clk/at91/clk-main.c| 171 +++ drivers/clk/at91/clk-master.c | 386 +++ drivers/clk/at91/clk-peripheral.c | 401
Re: [PATCH v4 2/5] mmc: atmel-mci: prepare clk before calling enable
Hello Chris,
Could you take this patch ?
It has been acked by Ludovic, and I need it in order to gracefully handle
at91's SoCs migration to common clk framework.
Thanks.
Best Regards,
Boris
On 18/07/2013 09:38, Boris BREZILLON wrote:
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
Acked-by: Ludovic Desroches ludovic.desroc...@atmel.com
---
drivers/mmc/host/atmel-mci.c | 34 +++---
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index bdb84da..69e438e 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -378,6 +378,8 @@ static int atmci_regs_show(struct seq_file *s, void *v)
{
struct atmel_mci*host = s-private;
u32 *buf;
+ int ret = 0;
+
buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
if (!buf)
@@ -388,12 +390,16 @@ static int atmci_regs_show(struct seq_file *s, void *v)
* not disabling interrupts, so IMR and SR may not be
* consistent.
*/
+ ret = clk_prepare_enable(host-mck);
+ if (ret)
+ goto out;
+
spin_lock_bh(host-lock);
- clk_enable(host-mck);
memcpy_fromio(buf, host-regs, ATMCI_REGS_SIZE);
- clk_disable(host-mck);
spin_unlock_bh(host-lock);
+ clk_disable_unprepare(host-mck);
+
seq_printf(s, MR:\t0x%08x%s%s ,
buf[ATMCI_MR / 4],
buf[ATMCI_MR / 4] ATMCI_MR_RDPROOF ? RDPROOF : ,
@@ -442,9 +448,10 @@ static int atmci_regs_show(struct seq_file *s, void *v)
val ATMCI_CFG_LSYNC ? LSYNC : );
}
+out:
kfree(buf);
- return 0;
+ return ret;
}
static int atmci_regs_open(struct inode *inode, struct file *file)
@@ -1262,6 +1269,7 @@ static void atmci_set_ios(struct mmc_host *mmc, struct
mmc_ios *ios)
struct atmel_mci_slot *slot = mmc_priv(mmc);
struct atmel_mci*host = slot-host;
unsigned inti;
+ boolunprepare_clk;
slot-sdc_reg = ~ATMCI_SDCBUS_MASK;
switch (ios-bus_width) {
@@ -1277,9 +1285,13 @@ static void atmci_set_ios(struct mmc_host *mmc, struct
mmc_ios *ios)
unsigned int clock_min = ~0U;
u32 clkdiv;
+ clk_prepare(host-mck);
+ unprepare_clk = true;
+
spin_lock_bh(host-lock);
if (!host-mode_reg) {
clk_enable(host-mck);
+ unprepare_clk = false;
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
if (host-caps.has_cfg_reg)
@@ -1347,6 +1359,8 @@ static void atmci_set_ios(struct mmc_host *mmc, struct
mmc_ios *ios)
} else {
bool any_slot_active = false;
+ unprepare_clk = false;
+
spin_lock_bh(host-lock);
slot-clock = 0;
for (i = 0; i ATMCI_MAX_NR_SLOTS; i++) {
@@ -1360,12 +1374,16 @@ static void atmci_set_ios(struct mmc_host *mmc, struct
mmc_ios *ios)
if (host-mode_reg) {
atmci_readl(host, ATMCI_MR);
clk_disable(host-mck);
+ unprepare_clk = true;
}
host-mode_reg = 0;
}
spin_unlock_bh(host-lock);
}
+ if (unprepare_clk)
+ clk_unprepare(host-mck);
+
switch (ios-power_mode) {
case MMC_POWER_UP:
set_bit(ATMCI_CARD_NEED_INIT, slot-flags);
@@ -2376,10 +2394,12 @@ static int __init atmci_probe(struct platform_device
*pdev)
if (!host-regs)
goto err_ioremap;
- clk_enable(host-mck);
+ ret = clk_prepare_enable(host-mck);
+ if (ret)
+ goto err_request_irq;
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
host-bus_hz = clk_get_rate(host-mck);
- clk_disable(host-mck);
+ clk_disable_unprepare(host-mck);
host-mapbase = regs-start;
@@ -2482,11 +2502,11 @@ static int __exit atmci_remove(struct platform_device *pdev)
atmci_cleanup_slot(host-slot[i], i);
}
- clk_enable(host-mck);
+ clk_prepare_enable(host-mck);
atmci_writel(host, ATMCI_IDR, ~0UL);
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
atmci_readl(host, ATMCI_SR);
- clk_disable(host-mck);
+ clk_disable_unprepare(host-mck);
if (host-dma.chan)
dma_release_channel(host-dma.chan);
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[RFC PATCH] phylib: mdio: handle register/unregister/register sequence
Hello, This patch is a proposal to support the register/unregister/register sequence on a given mdio bus. I use the register/unregister/register sequence to add a fallback when the of_mdiobus_register (this function calls mdiobus_register with phy_mask set to ~0) does not register any phy device (because the device tree does not define any phy). In this case I call mdiobus_unregister and then call mdiobus_register with a phy_mask set to 0 to trigger a full mdio bus scan. I'm not sure this is the right way to do it (this is why I added RFC in the subject). Could someone help me figuring out what I should use to implement my fallback ? 1) use the register/unregister/register sequence 2) reimplement the for (i = 0; i PHY_MAX_ADDR; i++) mdiobus_scan loop Thanks. Best Regards, Boris Boris BREZILLON (1): phylib: mdio: handle register/unregister/register sequence drivers/net/phy/mdio_bus.c |6 -- 1 file changed, 4 insertions(+), 2 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH] phylib: mdio: handle register/unregister/register sequence
The current implementation does not accept this sequence on a given mdio
bus: register/unregister/register.
The device core framework complain about already initialized kobject
struct:
kobject (df9e9848): tried to init an initialized object, something is
seriously wrong.
This patch replaces the device_register call with device_add in
mdiobus_register and move the device struct initialization in the
mdiobus_alloc_size function.
Thus the device struct is only initialized once.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/net/phy/mdio_bus.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
index dc92097..a256de3 100644
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -68,6 +68,8 @@ struct mii_bus *mdiobus_alloc_size(size_t size)
bus-priv = (void *)bus + aligned_size;
}
+ device_initialize(bus-dev);
+
return bus;
}
EXPORT_SYMBOL(mdiobus_alloc_size);
@@ -151,7 +153,7 @@ int mdiobus_register(struct mii_bus *bus)
bus-dev.groups = NULL;
dev_set_name(bus-dev, %s, bus-id);
- err = device_register(bus-dev);
+ err = device_add(bus-dev);
if (err) {
pr_err(mii_bus %s failed to register\n, bus-id);
return -EINVAL;
@@ -195,12 +197,12 @@ void mdiobus_unregister(struct mii_bus *bus)
BUG_ON(bus-state != MDIOBUS_REGISTERED);
bus-state = MDIOBUS_UNREGISTERED;
- device_del(bus-dev);
for (i = 0; i PHY_MAX_ADDR; i++) {
if (bus-phy_map[i])
device_unregister(bus-phy_map[i]-dev);
bus-phy_map[i] = NULL;
}
+ device_del(bus-dev);
}
EXPORT_SYMBOL(mdiobus_unregister);
--
1.7.9.5
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Re: [RFC PATCH] phylib: mdio: handle register/unregister/register sequence
Hello Florian,
Thanks for your answer.
On 22/08/2013 14:43, Florian Fainelli wrote:
Hello Boris,
2013/8/22 Boris BREZILLON b.brezil...@overkiz.com:
Hello,
This patch is a proposal to support the register/unregister/register
sequence on a given mdio bus.
I use the register/unregister/register sequence to add a fallback when the
of_mdiobus_register (this function calls mdiobus_register with phy_mask
set to ~0) does not register any phy device (because the device tree does
not define any phy).
In this case I call mdiobus_unregister and then call mdiobus_register with
a phy_mask set to 0 to trigger a full mdio bus scan.
I'm not sure this is the right way to do it (this is why I added RFC in the
subject).
Could someone help me figuring out what I should use to implement my fallback ?
1) use the register/unregister/register sequence
2) reimplement the for (i = 0; i PHY_MAX_ADDR; i++) mdiobus_scan loop
I think solution 2 is nicer, in that case, would it be enough in your
case to export a function called mdiobus_scan()? You could call at a
time you know PHY devices have a chance of having been probed?
mdiobus_scan is already exported:
struct phy_device *mdiobus_scan(struct mii_bus *bus, int addr);
This function scans the presence of a phy device at a given address.
What I need is a loop which scan all the possible address on the given
mdio bus:
struct phy_device *mdiobus_full_scan(struct mii_bus *bus)
{
int i;
for (i = 0; i PHY_MAX_ADDR; i++) {
if ((bus-phy_mask (1 i)) == 0) {
struct phy_device *phydev;
phydev = mdiobus_scan(bus, i);
if (IS_ERR(phydev)) {
err = PTR_ERR(phydev);
goto error;
}
}
}
return 0;
error:
while (--i = 0) {
if (bus-phy_map[i])
device_unregister(bus-phy_map[i]-dev);
}
}
EXPORT_SYMBOL(mdiobus_full_scan);
Since I am the only one who need this kind of functionnality right now,
I'm not sure
this is a good idea to export a new function.
This behaviour may be implemented in the of_mdiobus_register function:
when no dt phy node are found in the mdio bus dt node, we could launch a
full
scan.
What do you think ?
Best Regards,
Boris
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Re: [RFC PATCH] phylib: mdio: handle register/unregister/register sequence
On 22/08/2013 15:15, Florian Fainelli wrote:
2013/8/22 boris brezillon b.brezil...@overkiz.com:
Hello Florian,
Thanks for your answer.
On 22/08/2013 14:43, Florian Fainelli wrote:
Hello Boris,
2013/8/22 Boris BREZILLON b.brezil...@overkiz.com:
Hello,
This patch is a proposal to support the register/unregister/register
sequence on a given mdio bus.
I use the register/unregister/register sequence to add a fallback when
the
of_mdiobus_register (this function calls mdiobus_register with phy_mask
set to ~0) does not register any phy device (because the device tree does
not define any phy).
In this case I call mdiobus_unregister and then call mdiobus_register
with
a phy_mask set to 0 to trigger a full mdio bus scan.
I'm not sure this is the right way to do it (this is why I added RFC in
the
subject).
Could someone help me figuring out what I should use to implement my
fallback ?
1) use the register/unregister/register sequence
2) reimplement the for (i = 0; i PHY_MAX_ADDR; i++) mdiobus_scan loop
I think solution 2 is nicer, in that case, would it be enough in your
case to export a function called mdiobus_scan()? You could call at a
time you know PHY devices have a chance of having been probed?
mdiobus_scan is already exported:
struct phy_device *mdiobus_scan(struct mii_bus *bus, int addr);
This function scans the presence of a phy device at a given address.
What I need is a loop which scan all the possible address on the given
mdio bus:
struct phy_device *mdiobus_full_scan(struct mii_bus *bus)
{
int i;
for (i = 0; i PHY_MAX_ADDR; i++) {
if ((bus-phy_mask (1 i)) == 0) {
struct phy_device *phydev;
phydev = mdiobus_scan(bus, i);
if (IS_ERR(phydev)) {
err = PTR_ERR(phydev);
goto error;
}
}
}
return 0;
error:
while (--i = 0) {
if (bus-phy_map[i])
device_unregister(bus-phy_map[i]-dev);
}
}
EXPORT_SYMBOL(mdiobus_full_scan);
Since I am the only one who need this kind of functionnality right now, I'm
not sure
this is a good idea to export a new function.
A possible other use case for this full-scan is when you do not detect
a PHY connected to your MDIO bus, and that you did not register a
fixed PHY early enough for it to have been scanned by the fixed MDIO
bus emulation. In that case the driver may:
- scan hardware MDIO bus
- do not find any PHY, register a fixed PHY
- trigger a fixed MDIO bus full-rescan
- attach to the discovered fixed PHY
this is something currently done by the TI CPMAC driver in
drivers/net/ethernet/ti/cpmac.c (altough fixed_phy_add() is called
from platform code).
Okay, then we should consider this option.
This behaviour may be implemented in the of_mdiobus_register function:
when no dt phy node are found in the mdio bus dt node, we could launch a
full
scan.
What do you think ?
There is an existing kind of autoscan feature in
drivers/of/of_mdio.c, starting with the second foreach_child_node()
loop, so maybe that specific part could be exported and would achieve
what you are looking for? It relies on the Ethernet PHY nodes to be
attached to the MDIO bus node, but I assume this is what ultimately
happens in your case as well?
The second foreach_child_node loop only registers the dt phy nodes
which does not define any reg property (automatic address asssignement ?).
Indeed, what I need is a fallback when the device tree does not define
any phy
device (for old device tree backward compatibility).
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Re: [RFC PATCH] phylib: mdio: handle register/unregister/register sequence
On 22/08/2013 14:33, Boris BREZILLON wrote: Hello, This patch is a proposal to support the register/unregister/register sequence on a given mdio bus. I forgot to ask, if this limitation was made on purpose ? In other terms: no one should ever try to register, unregister and register again a given mii_bus structure. I use the register/unregister/register sequence to add a fallback when the of_mdiobus_register (this function calls mdiobus_register with phy_mask set to ~0) does not register any phy device (because the device tree does not define any phy). In this case I call mdiobus_unregister and then call mdiobus_register with a phy_mask set to 0 to trigger a full mdio bus scan. I'm not sure this is the right way to do it (this is why I added RFC in the subject). Could someone help me figuring out what I should use to implement my fallback ? 1) use the register/unregister/register sequence 2) reimplement the for (i = 0; i PHY_MAX_ADDR; i++) mdiobus_scan loop Thanks. Best Regards, Boris Boris BREZILLON (1): phylib: mdio: handle register/unregister/register sequence drivers/net/phy/mdio_bus.c |6 -- 1 file changed, 4 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH] phylib: mdio: handle register/unregister/register sequence
On 22/08/2013 17:27, Greg Kroah-Hartman wrote: On Thu, Aug 22, 2013 at 02:33:56PM +0200, Boris BREZILLON wrote: Hello, This patch is a proposal to support the register/unregister/register sequence on a given mdio bus. I use the register/unregister/register sequence to add a fallback when the of_mdiobus_register (this function calls mdiobus_register with phy_mask set to ~0) does not register any phy device (because the device tree does not define any phy). In this case I call mdiobus_unregister and then call mdiobus_register with a phy_mask set to 0 to trigger a full mdio bus scan. I'm not sure this is the right way to do it (this is why I added RFC in the subject). Could someone help me figuring out what I should use to implement my fallback ? 1) use the register/unregister/register sequence That will not work. Well, you might think it would work, but then things randomly start breaking later on. Try it with the KOBJECT_DELAYED_DESTROY build option in linux-next, and watch things go boom :) The rule is, you should never register a kobject/struct device that you have previously unregistered before, as you really don't know if unregistering has finished or not. Thanks for your answer. sorry, greg k-h -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/2] ARM: at91/dt: define phy available on sama5d3 mother board
This patch describe the phy used on atmel sama5d3 mother board:
- phy address
- phy interrupt pin
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/sama5d3xmb.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi
b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 8a9e05d..e9521d5 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -81,6 +81,14 @@
macb1: ethernet@f802c000 {
phy-mode = rmii;
+
+ #address-cells = 1;
+ #size-cells = 0;
+ phy0: ethernet-phy@0 {
+ interrupt-parent = pioE;
+ interrupts = 30 IRQ_TYPE_EDGE_FALLING;
+ reg = 1;
+ };
};
pinctrl@f200 {
--
1.7.9.5
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Re: [PATCH 1/2] net/cadence/macb: add support for dt phy definition
Hello Florian,
On 22/08/2013 17:57, Boris BREZILLON wrote:
The macb driver only handle PHY description through platform_data
(macb_platform_data).
Thus, when using dt you cannot define phy properties like phy address or
phy irq pin.
This patch makes use of the of_mdiobus_register to add support for
phy device definition using dt.
A fallback to the autoscan procedure is added in case there is no phy
devices defined in dt.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/net/ethernet/cadence/macb.c | 41 +--
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/ethernet/cadence/macb.c
index e866608..fe06ab0 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -27,6 +27,7 @@
#include linux/phy.h
#include linux/of.h
#include linux/of_device.h
+#include linux/of_mdio.h
#include linux/of_net.h
#include linux/pinctrl/consumer.h
@@ -314,6 +315,7 @@ static int macb_mii_probe(struct net_device *dev)
int macb_mii_init(struct macb *bp)
{
struct macb_platform_data *pdata;
+ struct device_node *np;
int err = -ENXIO, i;
/* Enable management port */
@@ -335,21 +337,46 @@ int macb_mii_init(struct macb *bp)
bp-mii_bus-parent = bp-dev-dev;
pdata = bp-pdev-dev.platform_data;
- if (pdata)
- bp-mii_bus-phy_mask = pdata-phy_mask;
-
bp-mii_bus-irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
if (!bp-mii_bus-irq) {
err = -ENOMEM;
goto err_out_free_mdiobus;
}
- for (i = 0; i PHY_MAX_ADDR; i++)
- bp-mii_bus-irq[i] = PHY_POLL;
-
dev_set_drvdata(bp-dev-dev, bp-mii_bus);
- if (mdiobus_register(bp-mii_bus))
+ np = bp-pdev-dev.of_node;
+ if (np) {
+ /* try dt phy registration */
+ err = of_mdiobus_register(bp-mii_bus, np);
+
+ /* fallback to standard phy registration if no phy were
+ found during dt phy registration */
+ if (!err !phy_find_first(bp-mii_bus)) {
+ for (i = 0; i PHY_MAX_ADDR; i++) {
+ struct phy_device *phydev;
+
+ phydev = mdiobus_scan(bp-mii_bus, i);
+ if (IS_ERR(phydev)) {
+ err = PTR_ERR(phydev);
+ break;
+ }
+ }
+
This is were I need the mdiobus_full_scan function.
+ if (err)
+ goto err_out_unregister_bus;
+ }
+ } else {
+ for (i = 0; i PHY_MAX_ADDR; i++)
+ bp-mii_bus-irq[i] = PHY_POLL;
+
+ if (pdata)
+ bp-mii_bus-phy_mask = pdata-phy_mask;
+
+ err = mdiobus_register(bp-mii_bus);
+ }
+
+ if (err)
goto err_out_free_mdio_irq;
if (macb_mii_probe(bp-dev) != 0) {
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[PATCH 0/2] net/cadence/macb: add support for dt phy definition
Hello, This patch series adds support for ethernet phy definition using device tree. This may help in moving some at91 boards to dt (some of them define an interrupt pin). Tested on samad31ek. Best Regards, Boris Boris BREZILLON (2): net/cadence/macb: add support for dt phy definition ARM: at91/dt: define phy available on sama5d3 mother board arch/arm/boot/dts/sama5d3xmb.dtsi |8 +++ drivers/net/ethernet/cadence/macb.c | 41 +-- 2 files changed, 42 insertions(+), 7 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 1/2] net/cadence/macb: add support for dt phy definition
The macb driver only handle PHY description through platform_data
(macb_platform_data).
Thus, when using dt you cannot define phy properties like phy address or
phy irq pin.
This patch makes use of the of_mdiobus_register to add support for
phy device definition using dt.
A fallback to the autoscan procedure is added in case there is no phy
devices defined in dt.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/net/ethernet/cadence/macb.c | 41 +--
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/ethernet/cadence/macb.c
index e866608..fe06ab0 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -27,6 +27,7 @@
#include linux/phy.h
#include linux/of.h
#include linux/of_device.h
+#include linux/of_mdio.h
#include linux/of_net.h
#include linux/pinctrl/consumer.h
@@ -314,6 +315,7 @@ static int macb_mii_probe(struct net_device *dev)
int macb_mii_init(struct macb *bp)
{
struct macb_platform_data *pdata;
+ struct device_node *np;
int err = -ENXIO, i;
/* Enable management port */
@@ -335,21 +337,46 @@ int macb_mii_init(struct macb *bp)
bp-mii_bus-parent = bp-dev-dev;
pdata = bp-pdev-dev.platform_data;
- if (pdata)
- bp-mii_bus-phy_mask = pdata-phy_mask;
-
bp-mii_bus-irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
if (!bp-mii_bus-irq) {
err = -ENOMEM;
goto err_out_free_mdiobus;
}
- for (i = 0; i PHY_MAX_ADDR; i++)
- bp-mii_bus-irq[i] = PHY_POLL;
-
dev_set_drvdata(bp-dev-dev, bp-mii_bus);
- if (mdiobus_register(bp-mii_bus))
+ np = bp-pdev-dev.of_node;
+ if (np) {
+ /* try dt phy registration */
+ err = of_mdiobus_register(bp-mii_bus, np);
+
+ /* fallback to standard phy registration if no phy were
+ found during dt phy registration */
+ if (!err !phy_find_first(bp-mii_bus)) {
+ for (i = 0; i PHY_MAX_ADDR; i++) {
+ struct phy_device *phydev;
+
+ phydev = mdiobus_scan(bp-mii_bus, i);
+ if (IS_ERR(phydev)) {
+ err = PTR_ERR(phydev);
+ break;
+ }
+ }
+
+ if (err)
+ goto err_out_unregister_bus;
+ }
+ } else {
+ for (i = 0; i PHY_MAX_ADDR; i++)
+ bp-mii_bus-irq[i] = PHY_POLL;
+
+ if (pdata)
+ bp-mii_bus-phy_mask = pdata-phy_mask;
+
+ err = mdiobus_register(bp-mii_bus);
+ }
+
+ if (err)
goto err_out_free_mdio_irq;
if (macb_mii_probe(bp-dev) != 0) {
--
1.7.9.5
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[PATCH 1/8] ARM: at91/tc/clocksource: replace clk_enable/disable with clk_prepare_enable/disable_unprepare.
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/clocksource/tcb_clksrc.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
index 8a61872..229c019 100644
--- a/drivers/clocksource/tcb_clksrc.c
+++ b/drivers/clocksource/tcb_clksrc.c
@@ -100,7 +100,7 @@ static void tc_mode(enum clock_event_mode m, struct
clock_event_device *d)
|| tcd-clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
- clk_disable(tcd-clk);
+ clk_disable_unprepare(tcd-clk);
}
switch (m) {
@@ -109,7 +109,7 @@ static void tc_mode(enum clock_event_mode m, struct
clock_event_device *d)
* of oneshot, we get lower overhead and improved accuracy.
*/
case CLOCK_EVT_MODE_PERIODIC:
- clk_enable(tcd-clk);
+ clk_prepare_enable(tcd-clk);
/* slow clock, count up to RC, then irq and restart */
__raw_writel(timer_clock
@@ -126,7 +126,7 @@ static void tc_mode(enum clock_event_mode m, struct
clock_event_device *d)
break;
case CLOCK_EVT_MODE_ONESHOT:
- clk_enable(tcd-clk);
+ clk_prepare_enable(tcd-clk);
/* slow clock, count up to RC, then irq and stop */
__raw_writel(timer_clock | ATMEL_TC_CPCSTOP
@@ -275,7 +275,7 @@ static int __init tcb_clksrc_init(void)
pdev = tc-pdev;
t0_clk = tc-clk[0];
- clk_enable(t0_clk);
+ clk_prepare_enable(t0_clk);
/* How fast will we be counting? Pick something over 5 MHz. */
rate = (u32) clk_get_rate(t0_clk);
@@ -313,7 +313,7 @@ static int __init tcb_clksrc_init(void)
/* tclib will give us three clocks no matter what the
* underlying platform supports.
*/
- clk_enable(tc-clk[1]);
+ clk_prepare_enable(tc-clk[1]);
/* setup both channel 0 1 */
tcb_setup_dual_chan(tc, best_divisor_idx);
}
--
1.7.9.5
--
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[PATCH 5/8] usb: gadget: at91_udc: prepare clk before calling enable
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to avoid common clk framework warnings. Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com --- drivers/usb/gadget/at91_udc.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c index 073b938..fce8e4e 100644 --- a/drivers/usb/gadget/at91_udc.c +++ b/drivers/usb/gadget/at91_udc.c @@ -870,8 +870,8 @@ static void clk_on(struct at91_udc *udc) if (udc-clocked) return; udc-clocked = 1; - clk_enable(udc-iclk); - clk_enable(udc-fclk); + clk_prepare_enable(udc-iclk); + clk_prepare_enable(udc-fclk); } static void clk_off(struct at91_udc *udc) @@ -880,8 +880,8 @@ static void clk_off(struct at91_udc *udc) return; udc-clocked = 0; udc-gadget.speed = USB_SPEED_UNKNOWN; - clk_disable(udc-fclk); - clk_disable(udc-iclk); + clk_disable_unprepare(udc-fclk); + clk_disable_unprepare(udc-iclk); } /* @@ -1782,12 +1782,14 @@ static int at91udc_probe(struct platform_device *pdev) } /* don't do anything until we have both gadget driver and VBUS */ - clk_enable(udc-iclk); + retval = clk_prepare_enable(udc-iclk); + if (retval) + goto fail1; at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS); at91_udp_write(udc, AT91_UDP_IDR, 0x); /* Clear all pending interrupts - UDP may be used by bootloader. */ at91_udp_write(udc, AT91_UDP_ICR, 0x); - clk_disable(udc-iclk); + clk_disable_unprepare(udc-iclk); /* request UDC and maybe VBUS irqs */ udc-udp_irq = platform_get_irq(pdev, 0); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 7/8] USB: ohci-at91: prepare clk before calling enable
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/usb/host/ohci-at91.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index a0cb44f..329d277 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -41,17 +41,17 @@ extern int usb_disabled(void);
static void at91_start_clock(void)
{
- clk_enable(hclk);
- clk_enable(iclk);
- clk_enable(fclk);
+ clk_prepare_enable(hclk);
+ clk_prepare_enable(iclk);
+ clk_prepare_enable(fclk);
clocked = 1;
}
static void at91_stop_clock(void)
{
- clk_disable(fclk);
- clk_disable(iclk);
- clk_disable(hclk);
+ clk_disable_unprepare(fclk);
+ clk_disable_unprepare(iclk);
+ clk_disable_unprepare(hclk);
clocked = 0;
}
--
1.7.9.5
--
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[PATCH 0/8] ARM: at91: prepare the move to common clk framework
Hello, This patch series was formerly part of the at91 common clk patch series. It prepares the move to common clk framework by replacing all the clk_enable and clk_disable calls by clk_prepare_unable and clk_disable_unprepare to avoid common clock framework warnings. This patch series was taken out of the at91 common clk patch series beacuse it does not rely on any other patches and have a low impact on the drivers (can be merge faster). Please tell me if I missed drivers using at91 PMC clks. Best Regards, Boris Changes since v1: - add clk_prepare_enable return check - fix a deadlock in atmel-mci (missing spin_unlock) - remove already applied patches (atmel-ssc and pwm-atmel-tcb) Boris BREZILLON (8): ARM: at91/tc/clocksource: replace clk_enable/disable with clk_prepare_enable/disable_unprepare. at_hdmac: prepare clk before calling enable mmc: atmel-mci: prepare clk before calling enable tty: atmel_serial: prepare clk before calling enable usb: gadget: at91_udc: prepare clk before calling enable ehci-atmel.c: prepare clk before calling enable USB: ohci-at91: prepare clk before calling enable at91/avr32/atmel_lcdfb: prepare clk before calling enable drivers/clocksource/tcb_clksrc.c | 10 - drivers/dma/at_hdmac.c| 17 +-- drivers/mmc/host/atmel-mci.c | 29 ++ drivers/tty/serial/atmel_serial.c | 41 - drivers/usb/gadget/at91_udc.c | 14 +++-- drivers/usb/host/ehci-atmel.c |8 drivers/usb/host/ohci-at91.c | 12 +-- drivers/video/atmel_lcdfb.c |8 8 files changed, 89 insertions(+), 50 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 4/8] tty: atmel_serial: prepare clk before calling enable
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/tty/serial/atmel_serial.c | 41 -
1 file changed, 31 insertions(+), 10 deletions(-)
diff --git a/drivers/tty/serial/atmel_serial.c
b/drivers/tty/serial/atmel_serial.c
index 3467462..691265f 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -1100,7 +1100,7 @@ static void atmel_serial_pm(struct uart_port *port,
unsigned int state,
* Enable the peripheral clock for this serial port.
* This is called on uart_open() or a resume event.
*/
- clk_enable(atmel_port-clk);
+ clk_prepare_enable(atmel_port-clk);
/* re-enable interrupts if we disabled some on suspend */
UART_PUT_IER(port, atmel_port-backup_imr);
@@ -1114,7 +1114,7 @@ static void atmel_serial_pm(struct uart_port *port,
unsigned int state,
* Disable the peripheral clock for this serial port.
* This is called on uart_close() or a suspend event.
*/
- clk_disable(atmel_port-clk);
+ clk_disable_unprepare(atmel_port-clk);
break;
default:
printk(KERN_ERR atmel_serial: unknown pm %d\n, state);
@@ -1458,9 +1458,10 @@ static void atmel_of_init_port(struct atmel_uart_port
*atmel_port,
/*
* Configure the port from the platform device resource info.
*/
-static void atmel_init_port(struct atmel_uart_port *atmel_port,
+static int atmel_init_port(struct atmel_uart_port *atmel_port,
struct platform_device *pdev)
{
+ int ret;
struct uart_port *port = atmel_port-uart;
struct atmel_uart_data *pdata = pdev-dev.platform_data;
@@ -1496,9 +1497,19 @@ static void atmel_init_port(struct atmel_uart_port
*atmel_port,
/* for console, the clock could already be configured */
if (!atmel_port-clk) {
atmel_port-clk = clk_get(pdev-dev, usart);
- clk_enable(atmel_port-clk);
+ if (IS_ERR(atmel_port-clk)) {
+ ret = PTR_ERR(atmel_port-clk);
+ atmel_port-clk = NULL;
+ return ret;
+ }
+ ret = clk_prepare_enable(atmel_port-clk);
+ if (ret) {
+ clk_put(atmel_port-clk);
+ atmel_port-clk = NULL;
+ return ret;
+ }
port-uartclk = clk_get_rate(atmel_port-clk);
- clk_disable(atmel_port-clk);
+ clk_disable_unprepare(atmel_port-clk);
/* only enable clock when USART is in use */
}
@@ -1511,6 +1522,8 @@ static void atmel_init_port(struct atmel_uart_port
*atmel_port,
} else {
atmel_port-tx_done_mask = ATMEL_US_TXRDY;
}
+
+ return 0;
}
struct platform_device *atmel_default_console_device; /* the serial console
device */
@@ -1601,6 +1614,7 @@ static void __init atmel_console_get_options(struct
uart_port *port, int *baud,
static int __init atmel_console_setup(struct console *co, char *options)
{
+ int ret;
struct uart_port *port = atmel_ports[co-index].uart;
int baud = 115200;
int bits = 8;
@@ -1612,7 +1626,9 @@ static int __init atmel_console_setup(struct console *co,
char *options)
return -ENODEV;
}
- clk_enable(atmel_ports[co-index].clk);
+ ret = clk_prepare_enable(atmel_ports[co-index].clk);
+ if (ret)
+ return ret;
UART_PUT_IDR(port, -1);
UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
@@ -1645,6 +1661,7 @@ static struct console atmel_console = {
*/
static int __init atmel_console_init(void)
{
+ int ret;
if (atmel_default_console_device) {
struct atmel_uart_data *pdata =
atmel_default_console_device-dev.platform_data;
@@ -1655,7 +1672,9 @@ static int __init atmel_console_init(void)
port-uart.line = id;
add_preferred_console(ATMEL_DEVICENAME, id, NULL);
- atmel_init_port(port, atmel_default_console_device);
+ ret = atmel_init_port(port, atmel_default_console_device);
+ if (ret)
+ return ret;
register_console(atmel_console);
}
@@ -1786,7 +1805,9 @@ static int atmel_serial_probe(struct platform_device
*pdev)
port-backup_imr = 0;
port-uart.line = ret;
- atmel_init_port(port, pdev);
+ ret = atmel_init_port(port, pdev);
+ if (ret)
+ goto err;
pinctrl = devm_pinctrl_get_select_default(pdev-dev);
if (IS_ERR(pinctrl)) {
@@ -1812,9 +1833,9
[PATCH 2/8] at_hdmac: prepare clk before calling enable
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to avoid common clk framework warnings. Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com --- drivers/dma/at_hdmac.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index e923cda..19a484a 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -1374,7 +1374,9 @@ static int __init at_dma_probe(struct platform_device *pdev) err = PTR_ERR(atdma-clk); goto err_clk; } - clk_enable(atdma-clk); + err = clk_prepare_enable(atdma-clk); + if (err) + goto err_clk_prepare; /* force dma off, just in case */ at_dma_off(atdma); @@ -1475,7 +1477,8 @@ err_pool_create: platform_set_drvdata(pdev, NULL); free_irq(platform_get_irq(pdev, 0), atdma); err_irq: - clk_disable(atdma-clk); + clk_disable_unprepare(atdma-clk); +err_clk_prepare: clk_put(atdma-clk); err_clk: iounmap(atdma-regs); @@ -1512,7 +1515,7 @@ static int at_dma_remove(struct platform_device *pdev) list_del(chan-device_node); } - clk_disable(atdma-clk); + clk_disable_unprepare(atdma-clk); clk_put(atdma-clk); iounmap(atdma-regs); @@ -1531,7 +1534,7 @@ static void at_dma_shutdown(struct platform_device *pdev) struct at_dma *atdma = platform_get_drvdata(pdev); at_dma_off(platform_get_drvdata(pdev)); - clk_disable(atdma-clk); + clk_disable_unprepare(atdma-clk); } static int at_dma_prepare(struct device *dev) @@ -1588,7 +1591,7 @@ static int at_dma_suspend_noirq(struct device *dev) /* disable DMA controller */ at_dma_off(atdma); - clk_disable(atdma-clk); + clk_disable_unprepare(atdma-clk); return 0; } @@ -1618,7 +1621,9 @@ static int at_dma_resume_noirq(struct device *dev) struct dma_chan *chan, *_chan; /* bring back DMA controller */ - clk_enable(atdma-clk); + err = clk_prepare_enable(atdma-clk); + if (err) + return err; dma_writel(atdma, EN, AT_DMA_ENABLE); /* clear any pending interrupt */ -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 3/8] mmc: atmel-mci: prepare clk before calling enable
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/mmc/host/atmel-mci.c | 29 -
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index e75774f..e3058a5 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -380,6 +380,8 @@ static int atmci_regs_show(struct seq_file *s, void *v)
{
struct atmel_mci*host = s-private;
u32 *buf;
+ int ret = 0;
+
buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
if (!buf)
@@ -391,9 +393,13 @@ static int atmci_regs_show(struct seq_file *s, void *v)
* consistent.
*/
spin_lock_bh(host-lock);
- clk_enable(host-mck);
+ ret = clk_prepare_enable(host-mck);
+ if (ret) {
+ spin_unlock_bh(host-lock);
+ goto out;
+ }
memcpy_fromio(buf, host-regs, ATMCI_REGS_SIZE);
- clk_disable(host-mck);
+ clk_disable_unprepare(host-mck);
spin_unlock_bh(host-lock);
seq_printf(s, MR:\t0x%08x%s%s ,
@@ -444,9 +450,10 @@ static int atmci_regs_show(struct seq_file *s, void *v)
val ATMCI_CFG_LSYNC ? LSYNC : );
}
+out:
kfree(buf);
- return 0;
+ return ret;
}
static int atmci_regs_open(struct inode *inode, struct file *file)
@@ -1281,7 +1288,7 @@ static void atmci_set_ios(struct mmc_host *mmc, struct
mmc_ios *ios)
spin_lock_bh(host-lock);
if (!host-mode_reg) {
- clk_enable(host-mck);
+ clk_prepare_enable(host-mck);
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
if (host-caps.has_cfg_reg)
@@ -1361,7 +1368,7 @@ static void atmci_set_ios(struct mmc_host *mmc, struct
mmc_ios *ios)
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
if (host-mode_reg) {
atmci_readl(host, ATMCI_MR);
- clk_disable(host-mck);
+ clk_disable_unprepare(host-mck);
}
host-mode_reg = 0;
}
@@ -2379,10 +2386,12 @@ static int __init atmci_probe(struct platform_device
*pdev)
if (!host-regs)
goto err_ioremap;
- clk_enable(host-mck);
+ ret = clk_prepare_enable(host-mck);
+ if (ret)
+ goto err_clk_prepare_enable;
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
host-bus_hz = clk_get_rate(host-mck);
- clk_disable(host-mck);
+ clk_disable_unprepare(host-mck);
host-mapbase = regs-start;
@@ -2463,6 +2472,8 @@ err_init_slot:
dma_release_channel(host-dma.chan);
free_irq(irq, host);
err_request_irq:
+ clk_unprepare(host-mck);
+err_clk_prepare_enable:
iounmap(host-regs);
err_ioremap:
clk_put(host-mck);
@@ -2487,11 +2498,11 @@ static int __exit atmci_remove(struct platform_device
*pdev)
atmci_cleanup_slot(host-slot[i], i);
}
- clk_enable(host-mck);
+ clk_prepare_enable(host-mck);
atmci_writel(host, ATMCI_IDR, ~0UL);
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
atmci_readl(host, ATMCI_SR);
- clk_disable(host-mck);
+ clk_disable_unprepare(host-mck);
if (host-dma.chan)
dma_release_channel(host-dma.chan);
--
1.7.9.5
--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH 6/8] ehci-atmel.c: prepare clk before calling enable
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/usb/host/ehci-atmel.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
index 6642009..015ce6e 100644
--- a/drivers/usb/host/ehci-atmel.c
+++ b/drivers/usb/host/ehci-atmel.c
@@ -37,15 +37,15 @@ static int clocked;
static void atmel_start_clock(void)
{
- clk_enable(iclk);
- clk_enable(fclk);
+ clk_prepare_enable(iclk);
+ clk_prepare_enable(fclk);
clocked = 1;
}
static void atmel_stop_clock(void)
{
- clk_disable(fclk);
- clk_disable(iclk);
+ clk_disable_unprepare(fclk);
+ clk_disable_unprepare(iclk);
clocked = 0;
}
--
1.7.9.5
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/8] at_hdmac: prepare clk before calling enable
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to avoid common clk framework warnings. Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com --- drivers/dma/at_hdmac.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index e923cda..19a484a 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -1374,7 +1374,9 @@ static int __init at_dma_probe(struct platform_device *pdev) err = PTR_ERR(atdma-clk); goto err_clk; } - clk_enable(atdma-clk); + err = clk_prepare_enable(atdma-clk); + if (err) + goto err_clk_prepare; /* force dma off, just in case */ at_dma_off(atdma); @@ -1475,7 +1477,8 @@ err_pool_create: platform_set_drvdata(pdev, NULL); free_irq(platform_get_irq(pdev, 0), atdma); err_irq: - clk_disable(atdma-clk); + clk_disable_unprepare(atdma-clk); +err_clk_prepare: clk_put(atdma-clk); err_clk: iounmap(atdma-regs); @@ -1512,7 +1515,7 @@ static int at_dma_remove(struct platform_device *pdev) list_del(chan-device_node); } - clk_disable(atdma-clk); + clk_disable_unprepare(atdma-clk); clk_put(atdma-clk); iounmap(atdma-regs); @@ -1531,7 +1534,7 @@ static void at_dma_shutdown(struct platform_device *pdev) struct at_dma *atdma = platform_get_drvdata(pdev); at_dma_off(platform_get_drvdata(pdev)); - clk_disable(atdma-clk); + clk_disable_unprepare(atdma-clk); } static int at_dma_prepare(struct device *dev) @@ -1588,7 +1591,7 @@ static int at_dma_suspend_noirq(struct device *dev) /* disable DMA controller */ at_dma_off(atdma); - clk_disable(atdma-clk); + clk_disable_unprepare(atdma-clk); return 0; } @@ -1618,7 +1621,9 @@ static int at_dma_resume_noirq(struct device *dev) struct dma_chan *chan, *_chan; /* bring back DMA controller */ - clk_enable(atdma-clk); + err = clk_prepare_enable(atdma-clk); + if (err) + return err; dma_writel(atdma, EN, AT_DMA_ENABLE); /* clear any pending interrupt */ -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 8/8] at91/avr32/atmel_lcdfb: prepare clk before calling enable
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/video/atmel_lcdfb.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 540909d..8525457 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -893,14 +893,14 @@ static int __init atmel_lcdfb_init_fbinfo(struct
atmel_lcdfb_info *sinfo)
static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
{
- clk_enable(sinfo-bus_clk);
- clk_enable(sinfo-lcdc_clk);
+ clk_prepare_enable(sinfo-bus_clk);
+ clk_prepare_enable(sinfo-lcdc_clk);
}
static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
{
- clk_disable(sinfo-bus_clk);
- clk_disable(sinfo-lcdc_clk);
+ clk_disable_unprepare(sinfo-bus_clk);
+ clk_disable_unprepare(sinfo-lcdc_clk);
}
--
1.7.9.5
--
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