Re: [PATCH RFC v8 02/21] of: Add vendor prefix for Himax Technologies Inc.
On Wed, Feb 04, 2015 at 10:02:53AM -0600, Rob Herring wrote: On Wed, Dec 31, 2014 at 2:23 AM, Liu Ying ying@freescale.com wrote: Signed-off-by: Liu Ying ying@freescale.com I don't know what the status is for the rest of the series, but I'm applying this and patch 3 so you don't have to keep sending them. Thank you, Rob. Regards, Liu Ying Rob --- v7-v8: * None. v6-v7: * None. v5-v6: * None. v4-v5: * None. v3-v4: * Fix an ordering issue to address Stefan Wahren's comment. v2-v3: * None. v1-v2: * None. Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 78efebb..f46adb2 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -67,6 +67,7 @@ gumstix Gumstix, Inc. gw Gateworks Corporation hannstar HannStar Display Corporation haoyu Haoyu Microelectronic Co. Ltd. +himax Himax Technologies, Inc. hisilicon Hisilicon Limited. hitHitachi Ltd. honeywell Honeywell -- 2.1.0 ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC v8 11/21] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
On Thu, Feb 05, 2015 at 11:10:04AM +0100, Philipp Zabel wrote: Am Mittwoch, den 31.12.2014, 16:23 +0800 schrieb Liu Ying: This patch adds device tree bindings for Synopsys DesignWare MIPI DSI host controller DRM bridge driver. Signed-off-by: Liu Ying ying@freescale.com --- v7-v8: * None. v6-v7: * None. v5-v6: * Add the #address-cells and #size-cells properties in the example 'ports' node. * Remove the useless input-port properties from the example port@0 and port@1 nodes. v4-v5: * None. v3-v4: * Newly introduced in v4. This is separated from the relevant driver patch in v3 to address Stefan Wahren's comment. .../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 73 ++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt diff --git a/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt new file mode 100644 index 000..f88a8d6 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt @@ -0,0 +1,73 @@ +Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller + +The controller is a digital core that implements all protocol functions +defined in the MIPI DSI specification, providing an interface between +the system and the MIPI DPHY, and allowing communication with a MIPI DSI +compliant display. + +Required properties: + - #address-cells: Should be 1. + - #size-cells: Should be 0. + - compatible: The compatible string should be fsl,imx6q-mipi-dsi for + i.MX6q/sdl SoCs. For other SoCs, please refer to their specific + device tree binding documentations. I think the compatible property should additionally contain snps,dw-mipi-dsi. Also I think other SoCs using the same IP core should eventually list their compatibles here, but that's for later. How about: + - compatible: The compatible string contain fsl,imx6q-mipi-dsi for + i.MX6q/sdl SoCs. For other SoCs, please refer to their specific + device tree binding documentations. A common compatible string + snps,dw-mipi-dsi should be appended for all SoCs. I'm not sure if snps,dw-mipi-dsi should be appended. Is it a compatible string that SoC specific drivers should actually use to bind a device? As Andy mentioned in [1], DW MIPI DSI embedded in RK618 is configured via I2C bus, while i.MX6Q/DL is configured via ARM bus... Another concern is that if users only specify snps,dw-mipi-dsi in their device tree sources and use a kernel which supports multiple platforms, say ARM multi v7 platforms, could several enabled SoC specific drivers be probed for a single DW MIPI DSI device? [1] http://lists.freedesktop.org/archives/dri-devel/2014-December/074344.html + - reg: Represent the physical address range of the controller. + - interrupts: Represent the controller's interrupt to the CPU(s). + - clocks, clock-names: Phandles to the controller pll reference and + core configuration clocks, as described in [1]. From the MIPI CSI-2 datasheets it looks like the D-PHY has a refclk and a cfg_clk input. So I suspect from the name of the core_cfg clock, that it actually represents two clock inputs, the cfg_clk wired to the D-PHY and a core clock wired to the MIPI DSI host controller. I am not sure if there are designs that control those clocks separately, but I think it'd be safer to split this into two clocks in the device tree. What MIPI CSI-2 datasheets do you refer to? I don't find the refclk and cfg_clk in the MIPI CSI chapter of the i.MX6DQ Reference Manual v2[2]. I think we need to know the design philosophy of DW MIPI DSI clock sources to settle down the documentation here. I've asked our internal MIPI DSI SoC owner for ideas. But, someone from Synopsys might be the right person, perhaps. [2] http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf?fasp=1WT_TYPE=Reference%20ManualsWT_VENDOR=FREESCALEWT_FILE_FORMAT=pdfWT_ASSET=DocumentationfileExt=.pdf Also I am not sure which input to the MIPI DSI host controller the core clock represents. The i.MX6DQ Reference Manual v2 calls the remaining clock inputs gated by mipi_core_cfg_clk_enable ac_clk_125m and ips_clk (I think the latter is the ABP clock driving the register bank, just called pclk in the MIPI CSI-2 documentation). The same MIPI CSI-2 documentation you mentioned above? I'm also puzzled about the clocks. Regards, Liu Ying regards Philipp -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 0/7] imx-drm: ipuv3-crtc: Implement mode_fixup
Hi, It looks that the below commit makes my Hannstar XGA LVDS panel stop working on the i.MX6DL SabreSD board. Any idea? commit eb10d6355532def3a74aaabd115e2373cca70b9d Author: Steve Longerbeam slongerb...@gmail.com Date: Thu Dec 18 18:00:24 2014 -0800 imx-drm: encoder prepare/mode_set must use adjusted mode The encoder -prepare() and -mode_set() methods need to use the hw adjusted mode, not the original mode. Signed-off-by: Steve Longerbeam steve_longerb...@mentor.com Signed-off-by: Philipp Zabel p.za...@pengutronix.de Regards, Liu Ying On Wed, Jan 07, 2015 at 07:27:28PM +0100, Philipp Zabel wrote: Am Donnerstag, den 18.12.2014, 18:00 -0800 schrieb Steve Longerbeam: This patchset implements -mode_fixup() in the imx ipuv3-crtc driver, using a new support function ipu_di_adjust_videomode(). This new function needs to be subsystem independent, so it accepts a video mode as a 'struct videomode'. Hence ipu-crtc -mode_fixup() needs another support function to convert a drm_display_mode to a videomode before passing the mode to ipu_di_adjust_videomode() for fixup. Also some related code cleanup: 'struct ipu_di_signal_cfg' should use 'struct videomode' for mode timings. Alright, I have applied the series with s/videomode_from_drm_display_mode/drm_display_mode_to_videomode/ thanks Philipp -- To unsubscribe from this list: send the line unsubscribe linux-fbdev in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC v8 11/21] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
Hi Philipp, On Wed, Feb 11, 2015 at 02:00:48PM +0100, Philipp Zabel wrote: Hi Liu, Am Mittwoch, den 11.02.2015, 15:21 +0800 schrieb Liu Ying: [...] Our internal MIPI DSI SoC owner gave me some feedbacks on the clock sources. According to him, the Synopsys DesignWare MIPI DSI host controller needs four clock sources from an application platform - pclk, refclk, cfg_clk and dpipclk. These clocks are mentioned in the DesignWare Cores MIPI DSI Host Controller Databook, 1.01a1.30a.pdf documentation. Quote some words from the documentation: pclk- APB clock signal. refclk - D-PHY reference clock used for Master-side serial clock generation in clock multiplying unit(PLL). cfg_clk - D-PHY Configuration clock used for the initialization of the PHY. It is also used for exiting ULPS state. dpipclk - Input Pixel clock signal. The below table reflects how does i.MX6Q/DL provide the pclk, refclk and cfg_clk for the DesignWare MIPI DSI host controller, according to the SoC owner. | Synopsys | i.MX6Q/DL MIPI DSI | | DesignWare || | documentation |clock | clock root | CCM_CCGR bits | |---|||--| | pclk | ips_clk |ipg_clk_root| mipi_core_cfg_clk_enable | |---|||--| |refclk | pll_refclk | video_27m_clk_root | mipi_core_cfg_clk_enable | |---|||--| |cfg_clk| cfg_clk | video_27m_clk_root | mipi_core_cfg_clk_enable | I think we should add a new clock IMX6QDL_CLK_MIPI_IPG as a shared clock gate clock. That would be necessary if the pclk clock rate mattered or would be set anywhere. I don't think the pclk clock rate matters a lot. It should be sufficient for the driver only to enable/disable the pclk for registers access, just like the way the pwm-imx driver uses the ipg clock. And, the clock-names property should exactly contain pclk, refclk and cfg_clk, right? My personal preference would be to drop the superfluous clk prefix if the resulting clock name is still clearly relatable to the official name. Existing clock naming for the pclk is a bit mixed - The snps,dw-apb-timer binding uses pclk, which seems to be quite common in other places, too. The snps,dw-apb-uart bindings use apb_pclk. snps,dw-hdmi-tx uses iahb and isfr without the clk suffix. How about pclk, ref and cfg? Looks good and clear enough. I'd like to use them. Thanks. BTW, regarding the compatible string topic, shall I keep my implementation unchanged and don't append the additional snps,dw-mipi-dsi as I shared my concerns about it before? Regards, Liu Ying regards Philipp -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC v8 11/21] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
On Wed, Feb 11, 2015 at 04:23:01PM +0100, Philipp Zabel wrote: Am Mittwoch, den 11.02.2015, 22:09 +0800 schrieb Liu Ying: BTW, regarding the compatible string topic, shall I keep my implementation unchanged and don't append the additional snps,dw-mipi-dsi as I shared my concerns about it before? Leave the implementation unchanged. Still, I'd like to see snps,dw-mipi-dsi appended to the mipi_dsi compatible property in Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt and in arch/arm/boot/dts/imx6qdl.dtsi. After all, Freescale's i.MX6 specific implementation is register compatible to Synopsys' design, isn't it? All right. Will do this in the next version. Regards, Liu Ying regards Philipp -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC v9 01/20] clk: divider: Correct parent clk round rate if no bestdiv is normally found
On Thu, Feb 12, 2015 at 10:33:56AM +0100, Sascha Hauer wrote:
On Thu, Feb 12, 2015 at 02:01:24PM +0800, Liu Ying wrote:
If no best divider is normally found, we will try to use the maximum
divider.
We should not set the parent clock rate to be 1Hz by force for being
rounded.
Instead, we should take the maximum divider as a base and calculate a
correct
parent clock rate for being rounded.
Please add an explanation why you think the current code is wrong and
what this actually fixes, maybe an example?
The MIPI DSI panel's pixel clock rate is 26.4MHz and it's derived from PLL5 on
the MX6DL SabreSD board.
These are the clock tree summaries with or without the patch applied:
1) With the patch applied:
pll5_bypass_src 112400 0 0
pll5 11 844800048 0 0
pll5_bypass 11 844800048 0 0
pll5_video 11 844800048 0 0
pll5_post_div 11 211200012 0 0
pll5_video_div 11 2112000120 0
ipu1_di0_pre_sel 11 211200012 0 0
ipu1_di0_pre 1126420 0
ipu1_di0_sel 112642 0 0
ipu1_di0 112642 0 0
2) Without the patch applied:
pll5_bypass_src 112400 0 0
pll5 11 64800 0 0
pll5_bypass 11 64800 0 0
pll5_video 11 64800 0 0
pll5_post_div 11 16200 0 0
pll5_video_div 1140500 0
ipu1_di0_pre_sel 114050 0 0
ipu1_di0_pre 1120250 0
ipu1_di0_sel 112025 0 0
ipu1_di0 112025 0 0
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index c0a842b..f641d4b 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -311,7 +311,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw,
unsigned long rate,
if (!bestdiv) {
bestdiv = _get_maxdiv(divider);
- *best_parent_rate = __clk_round_rate(__clk_get_parent(hw-clk),
1);
+ *best_parent_rate = __clk_round_rate(__clk_get_parent(hw-clk),
+ MULT_ROUND_UP(rate, bestdiv));
When getting into the if(!bestdiv) it means that the lowest possible
rate we can archieve is still higher than the target rate, so setting
the parent rate as low as possible seems sane to me. Why do you think
this is wrong? In which case this even makes a difference?
We still should take the little left chance to get a closest target clock
rate we want(26.4MHz, in the example case above), so it looks that the lowest
parent clock rate for being rounded should be MULT_ROUND_UP(rate, bestdiv)
instead of 1Hz.
Regards,
Liu Ying
Sascha
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Re: [PATCH RFC v9 01/20] clk: divider: Correct parent clk round rate if no bestdiv is normally found
On Thu, Feb 12, 2015 at 10:06:27PM +0800, Liu Ying wrote: On Thu, Feb 12, 2015 at 02:41:31PM +0100, Sascha Hauer wrote: On Thu, Feb 12, 2015 at 12:56:46PM +, Russell King - ARM Linux wrote: On Thu, Feb 12, 2015 at 01:24:05PM +0100, Sascha Hauer wrote: On Thu, Feb 12, 2015 at 06:39:45PM +0800, Liu Ying wrote: On Thu, Feb 12, 2015 at 10:33:56AM +0100, Sascha Hauer wrote: On Thu, Feb 12, 2015 at 02:01:24PM +0800, Liu Ying wrote: If no best divider is normally found, we will try to use the maximum divider. We should not set the parent clock rate to be 1Hz by force for being rounded. Instead, we should take the maximum divider as a base and calculate a correct parent clock rate for being rounded. Please add an explanation why you think the current code is wrong and what this actually fixes, maybe an example? The MIPI DSI panel's pixel clock rate is 26.4MHz and it's derived from PLL5 on the MX6DL SabreSD board. These are the clock tree summaries with or without the patch applied: 1) With the patch applied: pll5_bypass_src 112400 0 0 pll5 11 844800048 0 0 pll5_bypass 11 844800048 0 0 pll5_video 11 844800048 0 0 pll5_post_div 11 211200012 0 0 pll5_video_div 11 211200012 0 0 ipu1_di0_pre_sel 11 211200012 0 0 ipu1_di0_pre 11 26420 0 ipu1_di0_sel 11 2642 0 0 ipu1_di0 11 2642 0 0 2) Without the patch applied: pll5_bypass_src 112400 0 0 pll5 11 64800 0 0 pll5_bypass 11 64800 0 0 pll5_video 11 64800 0 0 pll5_post_div 11 16200 0 0 pll5_video_div 114050 0 0 ipu1_di0_pre_sel 11 4050 0 0 ipu1_di0_pre 11 20250 0 ipu1_di0_sel 11 2025 0 0 ipu1_di0 11 2025 0 0 This seems to be broken since: | commit b11d282dbea27db1788893115dfca8a7856bf205 | Author: Tomi Valkeinen tomi.valkei...@ti.com | Date: Thu Feb 13 12:03:59 2014 +0200 | | clk: divider: fix rate calculation for fractional rates This patch fixed a case when clk_set_rate(clk_round_rate(rate)) resulted in a lower frequency than clk_round_rate(rate) returned. Since then the MULT_ROUND_UP in clk_divider_bestdiv() is inconsistent to the rest of the divider. Maybe this should be a simple rate * i now, but I'm unsure what side effects this has. I think your patch only fixes the behaviour in your case by accident, it's not a correct fix for this issue. Well, it's defined that: new_rate = clk_round_rate(clk, rate); returns the rate which you would get if you did: clk_set_rate(clk, rate); new_rate = clk_get_rate(clk); The reasoning here is that clk_round_rate() gives you a way to query what rate you would get if you were to ask for the rate to be set, without effecting a change in the hardware. The idea that you should call clk_round_rate() first before clk_set_rate() and pass the returned rounded rate into clk_set_rate() is really idiotic given that. Please don't do it, and please remove code which does it, and in review comment on it. Thanks. Tomis patch is based on the assumption that clk_set_rate(clk_round_rate(rate)) is equal to clk_round_rate(rate). So when this assumption is wrong then it should simply be reverted. So Liu, could you test if reverting Tomis patch fixes your problem? Yes, I'll test tomorrow when I have access to my board. Tomi's patch cannot be reverted directly because of conflicts with the later patches. So, I revert all the clock divider driver patches on top of that. And, yes, after reverting Tomi's patch, I may get the correct 26.4MHz pixel clock rate. Regards, Liu Ying Regards, Liu Ying
Re: [PATCH RFC v9 09/20] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
On Thu, Feb 12, 2015 at 10:26:42AM +0100, Daniel Vetter wrote:
On Thu, Feb 12, 2015 at 02:01:32PM +0800, Liu Ying wrote:
Signed-off-by: Liu Ying ying@freescale.com
---
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git
repository.
v7-v8:
* None.
v6-v7:
* None.
v5-v6:
* Address the over 80 characters in one line warning reported by the
checkpatch.pl script.
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* None.
v1-v2:
* Thierry Reding suggested that the mipi_dsi_pixel_format_to_bpp() function
could be placed at the common DRM MIPI DSI driver.
This patch is newly added.
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..3662021 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -163,6 +163,20 @@ static inline struct mipi_dsi_device
*to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format
fmt)
Kerneldoc seems to be missing for this one.
I'll add it. Thanks for pointing out this.
Regards,
Liu Ying
-Daniel
+{
+ switch (fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ case MIPI_DSI_FMT_RGB666:
+ return 24;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ return 18;
+ case MIPI_DSI_FMT_RGB565:
+ return 16;
+ }
+ return -EINVAL;
+}
+
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node
*np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
--
2.1.0
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+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[PATCH RFC v9.5 09/20] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
Signed-off-by: Liu Ying ying@freescale.com
---
v9-v9.5:
* Add kernel-doc for the new helper function to address Daniel Vetter's
comment.
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7-v8:
* None.
v6-v7:
* None.
v5-v6:
* Address the over 80 characters in one line warning reported by the
checkpatch.pl script.
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* None.
v1-v2:
* Thierry Reding suggested that the mipi_dsi_pixel_format_to_bpp() function
could be placed at the common DRM MIPI DSI driver.
This patch is newly added.
include/drm/drm_mipi_dsi.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..cabc910 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -163,6 +163,28 @@ static inline struct mipi_dsi_device
*to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
+/**
+ * mipi_dsi_pixel_format_to_bpp() - get bits per pixel for a mipi dsi
+ *pixel format
+ * @fmt: mipi dsi pixel format
+ *
+ * Return: The bits per pixel value for the mipi dsi pixel format on success or
+ *a negative error code on failure.
+ */
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
+{
+ switch (fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ case MIPI_DSI_FMT_RGB666:
+ return 24;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ return 18;
+ case MIPI_DSI_FMT_RGB565:
+ return 16;
+ }
+ return -EINVAL;
+}
+
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node
*np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
--
2.1.0
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Re: [PATCH RFC v8 00/21] Add support for i.MX MIPI DSI DRM driver
Hi, This version has been submitted for a while. And, it looks there is no comments on this version. Can the maintainers consider to take this? Mike, any comments on patch 01/21? It's a clock driver change. Regards, Liu Ying On Wed, Dec 31, 2014 at 04:23:18PM +0800, Liu Ying wrote: Hi, This version mainly fixes the Kconfig for the Synopsys DesignWare MIPI DSI host controller bridge driver so that we may pass the allmodconfig for ARM. Also, this version contains a minor change for the Himax HX8369A panel driver to remove several unnecessary headers included. The i.MX MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a i.MX MIPI DSI specific DRM driver. Currently, the MIPI DSI drivers only support the burst with sync pulse mode. This series also includes a DRM panel driver for the Truly TFT480800-16-E panel which is driven by the Himax HX8369A driver IC. The driver IC data sheet could be found at [1]. As mentioned by the data sheet, the driver IC supports several interface modes. Currently, the DRM panel driver only supports the MIPI DSI video mode. New interface modes could be added later(perhaps, just like the way the DRM simple panel driver supports both MIPI DSI interface panels and simple(parallel) interface panels). The MIPI DSI feature is tested on i.MX6Q SabreSD board and i.MX6DL SabreSD board. The MIPI DSI display could be enabled directly on i.MX6Q SabreSD board after applying this series, because the 26.4MHz pixel clock the panel requires could be derived from the IPU HSP clock(264MHz) with an integer divider. On i.MX6DL SabreSD board, we need to manually disable the LVDS and HDMI displays in the device tree blob, since the i.MX6DL IPU HSP clock is 198MHz at present, which makes the pixel clock share the PLL5 video clock source with the LVDS and HDMI, thus, the panel cannot get the pixel clock rate it wants. Patch 01/21 is needed to get a precise pixel clock rate(26.4MHz) from the PLL5 video clock. If we don't have this patch, the pixel clock rate is about 20MHz, which causes a horitonal shift on the display image. This series can be applied on the drm-next branch. [1] http://www.allshore.com/pdf/Himax_HX8369-A.pdf Liu Ying (21): clk: divider: Correct parent clk round rate if no bestdiv is normally found of: Add vendor prefix for Himax Technologies Inc. of: Add vendor prefix for Truly Semiconductors Limited ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition ARM: imx6q: clk: Add the video_27m clock ARM: imx6q: clk: Change hdmi_isfr clock's parent to be video_27m clock ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gate ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver Documentation: dt-bindings: Add bindings for i.MX specific Synopsys DW MIPI DSI driver drm: imx: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for Himax HX8369A DRM panel driver drm: panel: Add support for Himax HX8369A MIPI DSI panel ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel .../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 73 ++ .../devicetree/bindings/drm/imx/mipi_dsi.txt | 78 ++ .../devicetree/bindings/panel/himax,hx8369a.txt| 39 + .../devicetree/bindings/vendor-prefixes.txt| 2 + arch/arm/boot/dts/imx6q.dtsi | 20 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 20 + arch/arm/boot/dts/imx6qdl.dtsi | 29 +- arch/arm/configs/imx_v6_v7_defconfig | 17 +- arch/arm/mach-imx/clk-imx6q.c | 7 +- drivers/clk/clk-divider.c | 3 +- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile| 1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 996 + drivers/gpu/drm/imx/Kconfig| 7 + drivers/gpu/drm/imx/Makefile | 1 + drivers/gpu/drm/imx/dw_mipi_dsi-imx.c | 230 + drivers/gpu/drm/panel/Kconfig | 5 + drivers/gpu/drm
Re: [PATCH RFC v8 00/21] Add support for i.MX MIPI DSI DRM driver
Correct Philipp's email address in the Cc list. Liu Ying On Mon, Feb 02, 2015 at 10:17:45AM +0800, Liu Ying wrote: Hi, This version has been submitted for a while. And, it looks there is no comments on this version. Can the maintainers consider to take this? Mike, any comments on patch 01/21? It's a clock driver change. Regards, Liu Ying On Wed, Dec 31, 2014 at 04:23:18PM +0800, Liu Ying wrote: Hi, This version mainly fixes the Kconfig for the Synopsys DesignWare MIPI DSI host controller bridge driver so that we may pass the allmodconfig for ARM. Also, this version contains a minor change for the Himax HX8369A panel driver to remove several unnecessary headers included. The i.MX MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a i.MX MIPI DSI specific DRM driver. Currently, the MIPI DSI drivers only support the burst with sync pulse mode. This series also includes a DRM panel driver for the Truly TFT480800-16-E panel which is driven by the Himax HX8369A driver IC. The driver IC data sheet could be found at [1]. As mentioned by the data sheet, the driver IC supports several interface modes. Currently, the DRM panel driver only supports the MIPI DSI video mode. New interface modes could be added later(perhaps, just like the way the DRM simple panel driver supports both MIPI DSI interface panels and simple(parallel) interface panels). The MIPI DSI feature is tested on i.MX6Q SabreSD board and i.MX6DL SabreSD board. The MIPI DSI display could be enabled directly on i.MX6Q SabreSD board after applying this series, because the 26.4MHz pixel clock the panel requires could be derived from the IPU HSP clock(264MHz) with an integer divider. On i.MX6DL SabreSD board, we need to manually disable the LVDS and HDMI displays in the device tree blob, since the i.MX6DL IPU HSP clock is 198MHz at present, which makes the pixel clock share the PLL5 video clock source with the LVDS and HDMI, thus, the panel cannot get the pixel clock rate it wants. Patch 01/21 is needed to get a precise pixel clock rate(26.4MHz) from the PLL5 video clock. If we don't have this patch, the pixel clock rate is about 20MHz, which causes a horitonal shift on the display image. This series can be applied on the drm-next branch. [1] http://www.allshore.com/pdf/Himax_HX8369-A.pdf Liu Ying (21): clk: divider: Correct parent clk round rate if no bestdiv is normally found of: Add vendor prefix for Himax Technologies Inc. of: Add vendor prefix for Truly Semiconductors Limited ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition ARM: imx6q: clk: Add the video_27m clock ARM: imx6q: clk: Change hdmi_isfr clock's parent to be video_27m clock ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gate ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver Documentation: dt-bindings: Add bindings for i.MX specific Synopsys DW MIPI DSI driver drm: imx: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for Himax HX8369A DRM panel driver drm: panel: Add support for Himax HX8369A MIPI DSI panel ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel .../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 73 ++ .../devicetree/bindings/drm/imx/mipi_dsi.txt | 78 ++ .../devicetree/bindings/panel/himax,hx8369a.txt| 39 + .../devicetree/bindings/vendor-prefixes.txt| 2 + arch/arm/boot/dts/imx6q.dtsi | 20 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 20 + arch/arm/boot/dts/imx6qdl.dtsi | 29 +- arch/arm/configs/imx_v6_v7_defconfig | 17 +- arch/arm/mach-imx/clk-imx6q.c | 7 +- drivers/clk/clk-divider.c | 3 +- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile| 1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 996 + drivers/gpu/drm/imx/Kconfig
Re: [PATCH RFC v7 16/21] drm: panel: Add support for Himax HX8369A MIPI DSI panel
Hi Daniel, On 01/05/2015 04:54 PM, Daniel Vetter wrote: On Tue, Dec 30, 2014 at 11:34:06AM +0800, Liu Ying wrote: This patch adds support for Himax HX8369A MIPI DSI panel. Reviewed-by: Andrzej Hajda a.ha...@samsung.com Signed-off-by: Liu Ying ying@freescale.com --- v6-v7: * Address Andrzej Hajda's following comments. * Simplify the return logic in hx8369a_dcs_write(). * Replace the macro hx8369a_dsi_init_helper() with a function array to improve the code quality. * Handle error cases during getting gpios in probe(). * Add 'Reviewed-by: Andrzej Hajda a.ha...@samsung.com'. If you only update one patch in a big series it's imo better to just resend that one to avoid spamming the mailing list with noise. Imo it also helps to keep the discussion all nicely grouped together. Thanks for your suggestion. I would try to make people happy about the way the series is submitted for review. In any case please give a short overview of what changed in the cover letter when resending the entire series so that people don't have to go through all the invidual patches. Yes, absolutely. I gave short overviews of what changed in the very beginning of the cover letters from v2 to v8 and I will do this in every necessary follow-up version. Regards, Liu Ying -Daniel -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v18 0/12] dw-hdmi: convert imx hdmi to bridge/dw_hdmi
with the allmodconfig configuration for the ARM architecture. Please fix this. drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c:243:1: error: ‘__mod_of__dw_hdmi_rockchip_dt_ids_device_table’ aliased to undefined symbol ‘dw_hdmi_rockchip_dt_ids’ scripts/Makefile.build:257: recipe for target 'drivers/gpu/drm/rockchip/dw_hdmi-rockchip.o' failed make[4]: *** [drivers/gpu/drm/rockchip/dw_hdmi-rockchip.o] Error 1 scripts/Makefile.build:402: recipe for target 'drivers/gpu/drm/rockchip' failed make[3]: *** [drivers/gpu/drm/rockchip] Error 2 scripts/Makefile.build:402: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:402: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:937: recipe for target 'drivers' failed make: *** [drivers] Error 2 Regards, Liu Ying -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC v8 11/21] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
Hi Philipp, On Fri, Feb 06, 2015 at 04:13:20PM +0800, Liu Ying wrote: On Thu, Feb 05, 2015 at 11:10:04AM +0100, Philipp Zabel wrote: Am Mittwoch, den 31.12.2014, 16:23 +0800 schrieb Liu Ying: This patch adds device tree bindings for Synopsys DesignWare MIPI DSI host controller DRM bridge driver. Signed-off-by: Liu Ying ying@freescale.com --- v7-v8: * None. v6-v7: * None. v5-v6: * Add the #address-cells and #size-cells properties in the example 'ports' node. * Remove the useless input-port properties from the example port@0 and port@1 nodes. v4-v5: * None. v3-v4: * Newly introduced in v4. This is separated from the relevant driver patch in v3 to address Stefan Wahren's comment. .../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 73 ++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt diff --git a/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt new file mode 100644 index 000..f88a8d6 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt @@ -0,0 +1,73 @@ +Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller + +The controller is a digital core that implements all protocol functions +defined in the MIPI DSI specification, providing an interface between +the system and the MIPI DPHY, and allowing communication with a MIPI DSI +compliant display. + +Required properties: + - #address-cells: Should be 1. + - #size-cells: Should be 0. + - compatible: The compatible string should be fsl,imx6q-mipi-dsi for + i.MX6q/sdl SoCs. For other SoCs, please refer to their specific + device tree binding documentations. I think the compatible property should additionally contain snps,dw-mipi-dsi. Also I think other SoCs using the same IP core should eventually list their compatibles here, but that's for later. How about: + - compatible: The compatible string contain fsl,imx6q-mipi-dsi for + i.MX6q/sdl SoCs. For other SoCs, please refer to their specific + device tree binding documentations. A common compatible string + snps,dw-mipi-dsi should be appended for all SoCs. I'm not sure if snps,dw-mipi-dsi should be appended. Is it a compatible string that SoC specific drivers should actually use to bind a device? As Andy mentioned in [1], DW MIPI DSI embedded in RK618 is configured via I2C bus, while i.MX6Q/DL is configured via ARM bus... Another concern is that if users only specify snps,dw-mipi-dsi in their device tree sources and use a kernel which supports multiple platforms, say ARM multi v7 platforms, could several enabled SoC specific drivers be probed for a single DW MIPI DSI device? [1] http://lists.freedesktop.org/archives/dri-devel/2014-December/074344.html + - reg: Represent the physical address range of the controller. + - interrupts: Represent the controller's interrupt to the CPU(s). + - clocks, clock-names: Phandles to the controller pll reference and + core configuration clocks, as described in [1]. From the MIPI CSI-2 datasheets it looks like the D-PHY has a refclk and a cfg_clk input. So I suspect from the name of the core_cfg clock, that it actually represents two clock inputs, the cfg_clk wired to the D-PHY and a core clock wired to the MIPI DSI host controller. I am not sure if there are designs that control those clocks separately, but I think it'd be safer to split this into two clocks in the device tree. Our internal MIPI DSI SoC owner gave me some feedbacks on the clock sources. According to him, the Synopsys DesignWare MIPI DSI host controller needs four clock sources from an application platform - pclk, refclk, cfg_clk and dpipclk. These clocks are mentioned in the DesignWare Cores MIPI DSI Host Controller Databook, 1.01a1.30a.pdf documentation. Quote some words from the documentation: pclk- APB clock signal. refclk - D-PHY reference clock used for Master-side serial clock generation in clock multiplying unit(PLL). cfg_clk - D-PHY Configuration clock used for the initialization of the PHY. It is also used for exiting ULPS state. dpipclk - Input Pixel clock signal. The below table reflects how does i.MX6Q/DL provide the pclk, refclk and cfg_clk for the DesignWare MIPI DSI host controller, according to the SoC owner. | Synopsys | i.MX6Q/DL MIPI DSI | | DesignWare|| | documentation |clock | clock root | CCM_CCGR bits
Re: [PATCH RFC v9 01/20] clk: divider: Correct parent clk round rate if no bestdiv is normally found
On Thu, Feb 12, 2015 at 02:41:31PM +0100, Sascha Hauer wrote: On Thu, Feb 12, 2015 at 12:56:46PM +, Russell King - ARM Linux wrote: On Thu, Feb 12, 2015 at 01:24:05PM +0100, Sascha Hauer wrote: On Thu, Feb 12, 2015 at 06:39:45PM +0800, Liu Ying wrote: On Thu, Feb 12, 2015 at 10:33:56AM +0100, Sascha Hauer wrote: On Thu, Feb 12, 2015 at 02:01:24PM +0800, Liu Ying wrote: If no best divider is normally found, we will try to use the maximum divider. We should not set the parent clock rate to be 1Hz by force for being rounded. Instead, we should take the maximum divider as a base and calculate a correct parent clock rate for being rounded. Please add an explanation why you think the current code is wrong and what this actually fixes, maybe an example? The MIPI DSI panel's pixel clock rate is 26.4MHz and it's derived from PLL5 on the MX6DL SabreSD board. These are the clock tree summaries with or without the patch applied: 1) With the patch applied: pll5_bypass_src 112400 0 0 pll5 11 844800048 0 0 pll5_bypass 11 844800048 0 0 pll5_video 11 844800048 0 0 pll5_post_div 11 211200012 0 0 pll5_video_div 11 211200012 0 0 ipu1_di0_pre_sel 11 211200012 0 0 ipu1_di0_pre 112642 0 0 ipu1_di0_sel 11 2642 0 0 ipu1_di0 11 2642 0 0 2) Without the patch applied: pll5_bypass_src 112400 0 0 pll5 11 64800 0 0 pll5_bypass 11 64800 0 0 pll5_video 11 64800 0 0 pll5_post_div 11 16200 0 0 pll5_video_div 114050 0 0 ipu1_di0_pre_sel 114050 0 0 ipu1_di0_pre 112025 0 0 ipu1_di0_sel 11 2025 0 0 ipu1_di0 11 2025 0 0 This seems to be broken since: | commit b11d282dbea27db1788893115dfca8a7856bf205 | Author: Tomi Valkeinen tomi.valkei...@ti.com | Date: Thu Feb 13 12:03:59 2014 +0200 | | clk: divider: fix rate calculation for fractional rates This patch fixed a case when clk_set_rate(clk_round_rate(rate)) resulted in a lower frequency than clk_round_rate(rate) returned. Since then the MULT_ROUND_UP in clk_divider_bestdiv() is inconsistent to the rest of the divider. Maybe this should be a simple rate * i now, but I'm unsure what side effects this has. I think your patch only fixes the behaviour in your case by accident, it's not a correct fix for this issue. Well, it's defined that: new_rate = clk_round_rate(clk, rate); returns the rate which you would get if you did: clk_set_rate(clk, rate); new_rate = clk_get_rate(clk); The reasoning here is that clk_round_rate() gives you a way to query what rate you would get if you were to ask for the rate to be set, without effecting a change in the hardware. The idea that you should call clk_round_rate() first before clk_set_rate() and pass the returned rounded rate into clk_set_rate() is really idiotic given that. Please don't do it, and please remove code which does it, and in review comment on it. Thanks. Tomis patch is based on the assumption that clk_set_rate(clk_round_rate(rate)) is equal to clk_round_rate(rate). So when this assumption is wrong then it should simply be reverted. So Liu, could you test if reverting Tomis patch fixes your problem? Yes, I'll test tomorrow when I have access to my board. Regards, Liu Ying Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord
[PATCH RFC v9 04/20] ARM: imx6q: clk: Change hdmi_isfr clock's parent to be video_27m clock
According to the table 33-1 in the i.MX6Q reference manual, the hdmi_isfr clock's parent should be the video_27m clock. The i.MX6DL reference manual has the same statement. This patch changes the hdmi_isfr clock's parent from the pll3_pfd1_540m clock to the video_27m clock. Suggested-by: Philipp Zabel p.za...@pengutronix.de Signed-off-by: Liu Ying ying@freescale.com --- v8-v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository. v7-v8: * None. v6-v7: * None. v5-v6: * None. v4-v5: * None. v3-v4: * None. v2-v3: * Newly introduced in v3. arch/arm/mach-imx/clk-imx6q.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 2b7beb8..0dbc79a 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -401,7 +401,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2(gpu2d_core, gpu2d_core_podf, base + 0x6c, 24); clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2(gpu3d_core, gpu3d_core_podf, base + 0x6c, 26); clk[IMX6QDL_CLK_HDMI_IAHB]= imx_clk_gate2(hdmi_iahb, ahb, base + 0x70, 0); - clk[IMX6QDL_CLK_HDMI_ISFR]= imx_clk_gate2(hdmi_isfr, pll3_pfd1_540m,base + 0x70, 4); + clk[IMX6QDL_CLK_HDMI_ISFR]= imx_clk_gate2(hdmi_isfr, video_27m, base + 0x70, 4); clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2(i2c1, ipg_per, base + 0x70, 6); clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2(i2c2, ipg_per, base + 0x70, 8); clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2(i2c3, ipg_per, base + 0x70, 10); -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v9 16/20] ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller
This patch adds support for MIPI DSI host controller.
Signed-off-by: Liu Ying ying@freescale.com
---
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
* To address Philipp's comment, mention that a common compatible string
snps,dw-mipi-dsi should be appended.
* To address Philipp's comment, add a new required clock pclk and clean up
clock-names.
v7-v8:
* None.
v6-v7:
* None.
v5-v6:
* None.
v3-v4:
* None.
v2-v3:
* As suggested by Phillip Zabel, change the clocks and the clock-names
properties to use the pllref and core_cfg clocks only.
v1-v2:
* None.
arch/arm/boot/dts/imx6qdl.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 55aced8..0a4d7f7 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1020,7 +1020,14 @@
mipi_dsi: mipi@021e {
#address-cells = 1;
#size-cells = 0;
+ compatible = fsl,imx6q-mipi-dsi,
snps,dw-mipi-dsi;
reg = 0x021e 0x4000;
+ interrupts = 0 102 IRQ_TYPE_LEVEL_HIGH;
+ gpr = gpr;
+ clocks = clks IMX6QDL_CLK_MIPI_CORE_CFG,
+clks IMX6QDL_CLK_MIPI_CORE_CFG,
+clks IMX6QDL_CLK_MIPI_IPG;
+ clock-names = ref, cfg, pclk;
status = disabled;
ports {
--
2.1.0
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v9 20/20] ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel
This patch adds support for Himax HX8369A panel. The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm menuconfig and manually choose to build in the Himax HX8369A panel driver * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying ying@freescale.com --- v8-v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository. v7-v8: * None. v6-v7: * None. v5-v6: * None. v4-v5: * None. v3-v4: * None. v2-v3: * None. v1-v2: * Add the HIMAX prefix in the Kconfig name. arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 9e650e8f..52d70a1 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -197,6 +197,7 @@ CONFIG_SOC_CAMERA_OV2640=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_HIMAX_HX8369A=y CONFIG_DRM_IMX=y CONFIG_DRM_IMX_FB_HELPER=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v9 18/20] ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging
The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying ying@freescale.com --- v8-v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository, so the patch content is different from v8. v7-v8: * None. v6-v7: * None. v5-v6: * None. v4-v5: * None. v3-v4: * None. v2-v3: * None. v1-v2: * None. arch/arm/configs/imx_v6_v7_defconfig | 21 + 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 7c2075a..ec4b255 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -54,7 +54,6 @@ CONFIG_ARM_IMX6Q_CPUFREQ=y CONFIG_VFP=y CONFIG_NEON=y CONFIG_BINFMT_MISC=m -CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_PM_TEST_SUSPEND=y CONFIG_NET=y @@ -163,13 +162,13 @@ CONFIG_SPI_IMX=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_MC9S08DZ60=y CONFIG_GPIO_STMPE=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_IMX=y CONFIG_SENSORS_GPIO_FAN=y CONFIG_THERMAL=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_IMX=y CONFIG_WATCHDOG=y CONFIG_IMX2_WDT=y CONFIG_MFD_DA9052_I2C=y @@ -198,7 +197,12 @@ CONFIG_SOC_CAMERA_OV2640=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_FB_HELPER=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_HDMI=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y @@ -257,13 +261,6 @@ CONFIG_IMX_SDMA=y CONFIG_MXS_DMA=y CONFIG_FSL_EDMA=y CONFIG_STAGING=y -CONFIG_DRM_IMX=y -CONFIG_DRM_IMX_FB_HELPER=y -CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -CONFIG_DRM_IMX_TVE=y -CONFIG_DRM_IMX_LDB=y -CONFIG_DRM_IMX_IPUV3=y -CONFIG_DRM_IMX_HDMI=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_PWM=y CONFIG_PWM_IMX=y -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v9 19/20] ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller
This patch adds support for MIPI DSI host controller. The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm menuconfig and manually choose to build in the MIPI DSI host controller driver * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying ying@freescale.com --- v8-v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository. v7-v8: * None. v6-v7: * None. v5-v6: * None. v4-v5: * None. v3-v4: * None. v2-v3: * None. v1-v2: * None. arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index ec4b255..9e650e8f 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -203,6 +203,7 @@ CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_MIPI_DSI=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v9 09/20] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
Signed-off-by: Liu Ying ying@freescale.com
---
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7-v8:
* None.
v6-v7:
* None.
v5-v6:
* Address the over 80 characters in one line warning reported by the
checkpatch.pl script.
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* None.
v1-v2:
* Thierry Reding suggested that the mipi_dsi_pixel_format_to_bpp() function
could be placed at the common DRM MIPI DSI driver.
This patch is newly added.
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..3662021 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -163,6 +163,20 @@ static inline struct mipi_dsi_device
*to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
+{
+ switch (fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ case MIPI_DSI_FMT_RGB666:
+ return 24;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ return 18;
+ case MIPI_DSI_FMT_RGB565:
+ return 16;
+ }
+ return -EINVAL;
+}
+
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node
*np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
--
2.1.0
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[PATCH RFC v9 12/20] Documentation: dt-bindings: Add bindings for i.MX specific Synopsys DW MIPI DSI driver
This patch adds device tree bindings for i.MX specific Synopsys DW MIPI DSI
driver.
Signed-off-by: Liu Ying ying@freescale.com
---
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
* To address Philipp's comment, mention that a common compatible string
snps,dw-mipi-dsi should be appended.
* To address Philipp's comment, add a new required clock pclk and clean up
clock-names.
v7-v8:
* None.
v6-v7:
* None.
v5-v6:
* Add the #address-cells and #size-cells properties in the example 'ports'
node.
* Remove the useless pllref_gate clock from the required clocks, clock-names
property.
v4-v5:
* None.
v3-v4:
* Newly introduced in v4. This is separated from the relevant driver patch
in v3 to address Stefan Wahren's comment.
.../devicetree/bindings/drm/imx/mipi_dsi.txt | 81 ++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
diff --git a/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
new file mode 100644
index 000..4bd8451
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
@@ -0,0 +1,81 @@
+i.MX specific Device-Tree bindings for Synopsys DesignWare MIPI DSI host
controller
+
+MIPI DSI host controller
+
+
+The MIPI DSI host controller is a Synopsys DesignWare IP.
+The common device tree documentation for this controller can be found
+at [1].
+
+Required properties:
+ - #address-cells: Should be 1.
+ - #size-cells: Should be 0.
+ - compatible: The first compatible string should be fsl,imx6q-mipi-dsi
+ for i.MX6q/sdl SoCs. And, a common compatible string snps,dw-mipi-dsi
+ should be appended.
+ - reg: Physical base address of the controller and length of memory
+ mapped region.
+ - interrupts: The controller's interrupt number to the CPU(s).
+ - gpr: Should be gpr.
+ The phandle points to the iomuxc-gpr region containing the
+ multiplexer control register for the controller.
+ - clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref), configuration clock(cfg) and APB clock(pclk), as described
+ in [2] and [3].
+
+Required sub-nodes:
+ - ports: This node may contain up to four port nodes with endpoint
+ definitions as defined in [4], corresponding to the four inputs to
+ the controller multiplexer.
+ - A node to represent a DSI peripheral as described in [5].
+
+[1] Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt.
+[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[3] Documentation/devicetree/bindings/clock/imx6q-clock.txt
+[4] Documentation/devicetree/bindings/media/video-interfaces.txt
+[5] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr@020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi@021e {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,imx6q-mipi-dsi, snps,dw-mipi-dsi;
+ reg = 0x021e 0x4000;
+ interrupts = 0 102 IRQ_TYPE_LEVEL_HIGH;
+ gpr = gpr;
+ clocks = clks IMX6QDL_CLK_MIPI_CORE_CFG,
+clks IMX6QDL_CLK_MIPI_CORE_CFG,
+clks IMX6QDL_CLK_MIPI_IPG;
+ clock-names = ref, cfg, pclk;
+
+ ports {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ port@0 {
+ reg = 0;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = ipu1_di0_mipi;
+ };
+ };
+
+ port@1 {
+ reg = 1;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = ipu1_di1_mipi;
+ };
+ };
+ };
+
+ panel {
+ compatible = truly,tft480800-16-e-dsi;
+ reg = 0;
+ /* ... */
+ };
+ };
--
2.1.0
--
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[PATCH RFC v9 06/20] ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the hsi_tx_sel clock's output and the video_27m clock's output. The MIPI DSI host controller embedded in the i.MX6q/sdl SoCs uses the video_27m clock to generate PLL reference clock and MIPI core configuration clock. In order to gate/ungate the two MIPI DSI host controller relevant clocks, this patch adds the mipi_core_cfg clock as a shared clock gate. Suggested-by: Philipp Zabel p.za...@pengutronix.de Signed-off-by: Liu Ying ying@freescale.com --- v8-v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository. v7-v8: * None. v6-v7: * None. v5-v6: * Add two spaces in the clock driver to eliminate two errors reported by the checkpatch.pl script. v4-v5: * None. v3-v4: * None. v2-v3: * Newly introduced in v3. arch/arm/mach-imx/clk-imx6q.c | 1 + include/dt-bindings/clock/imx6qdl-clock.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 049e922..cbdbe2a 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -418,6 +418,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2(ldb_di1, ldb_di1_podf, base + 0x74, 14); clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2(ipu2_di1, ipu2_di1_sel, base + 0x74, 10); clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared(hsi_tx, hsi_tx_podf, base + 0x74, 16, share_count_mipi_core_cfg); + clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared(mipi_core_cfg, video_27m, base + 0x74, 16, share_count_mipi_core_cfg); if (cpu_is_imx6dl()) /* * The multiplexer and divider of the imx6q clock gpu2d get diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index 25625bf..dbc828c 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -249,6 +249,7 @@ #define IMX6QDL_PLL7_BYPASS236 #define IMX6QDL_CLK_GPT_3M 237 #define IMX6QDL_CLK_VIDEO_27M 238 -#define IMX6QDL_CLK_END239 +#define IMX6QDL_CLK_MIPI_CORE_CFG 239 +#define IMX6QDL_CLK_END240 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v9 05/20] ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gate
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg'
clock, according to the i.MX6q/sdl reference manuals. This clock is
actually the gate for several clocks, including the hsi_tx_sel clock's
output and the video_27m clock's output. So, this patch changes the
hsi_tx clock to be a shared clock gate.
Suggested-by: Philipp Zabel p.za...@pengutronix.de
Signed-off-by: Liu Ying ying@freescale.com
---
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7-v8:
* None.
v6-v7:
* None.
v5-v6:
* None.
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* Newly introduced in v3.
arch/arm/mach-imx/clk-imx6q.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 0dbc79a..049e922 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -119,6 +119,7 @@ static unsigned int share_count_asrc;
static unsigned int share_count_ssi1;
static unsigned int share_count_ssi2;
static unsigned int share_count_ssi3;
+static unsigned int share_count_mipi_core_cfg;
static void __init imx6q_clocks_init(struct device_node *ccm_node)
{
@@ -416,7 +417,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2(ldb_di0,
ldb_di0_podf, base + 0x74, 12);
clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2(ldb_di1,
ldb_di1_podf, base + 0x74, 14);
clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2(ipu2_di1,
ipu2_di1_sel, base + 0x74, 10);
- clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2(hsi_tx,
hsi_tx_podf, base + 0x74, 16);
+ clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared(hsi_tx,
hsi_tx_podf, base + 0x74, 16, share_count_mipi_core_cfg);
if (cpu_is_imx6dl())
/*
* The multiplexer and divider of the imx6q clock gpu2d get
--
2.1.0
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[PATCH RFC v9 10/20] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.
Signed-off-by: Liu Ying ying@freescale.com
---
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
* To address Philipp's comment, mention that a common compatible string
snps,dw-mipi-dsi should be appended for all SoCs.
* To address Philipp's comment, add a new required clock pclk and clean up
clock-names.
v7-v8:
* None.
v6-v7:
* None.
v5-v6:
* Add the #address-cells and #size-cells properties in the example 'ports'
node.
* Remove the useless input-port properties from the example port@0 and port@1
nodes.
v4-v5:
* None.
v3-v4:
* Newly introduced in v4. This is separated from the relevant driver patch
in v3 to address Stefan Wahren's comment.
.../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 76 ++
1 file changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
diff --git a/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
new file mode 100644
index 000..bb87466
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,76 @@
+Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller
+
+The controller is a digital core that implements all protocol functions
+defined in the MIPI DSI specification, providing an interface between
+the system and the MIPI DPHY, and allowing communication with a MIPI DSI
+compliant display.
+
+Required properties:
+ - #address-cells: Should be 1.
+ - #size-cells: Should be 0.
+ - compatible: The first compatible string should be fsl,imx6q-mipi-dsi
+ for i.MX6q/sdl SoCs. For other SoCs, please refer to their specific
+ device tree binding documentations. A common compatible string
+ snps,dw-mipi-dsi should be appended for all SoCs.
+ - reg: Represent the physical address range of the controller.
+ - interrupts: Represent the controller's interrupt to the CPU(s).
+ - clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref), configuration clock(cfg) and APB clock(pclk), as
+ described in [1].
+
+For more required properties, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+Required sub-nodes:
+ - A node to represent a DSI peripheral as described in [2].
+
+For more required sub-nodes, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr@020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi@021e {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,imx6q-mipi-dsi, snps,dw-mipi-dsi;
+ reg = 0x021e 0x4000;
+ interrupts = 0 102 IRQ_TYPE_LEVEL_HIGH;
+ gpr = gpr;
+ clocks = clks IMX6QDL_CLK_MIPI_CORE_CFG,
+clks IMX6QDL_CLK_MIPI_CORE_CFG,
+clks IMX6QDL_CLK_MIPI_IPG;
+ clock-names = ref, cfg, pclk;
+
+ ports {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ port@0 {
+ reg = 0;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = ipu1_di0_mipi;
+ };
+ };
+
+ port@1 {
+ reg = 1;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = ipu1_di1_mipi;
+ };
+ };
+ };
+
+ panel {
+ compatible = truly,tft480800-16-e-dsi;
+ reg = 0;
+ /* ... */
+ };
+ };
--
2.1.0
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[PATCH RFC v9 08/20] ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node
The MIPI DSI node contains some ports which represent possible DRM CRTCs
it can connect with. Each port has a 'reg' property embedded. This
property will be wrongly interpretted by the MIPI DSI bus driver, because
the driver will take each subnode which contains a 'reg' property as a
DSI peripheral device. This patch moves the existing MIPI DSI ports into
a new 'ports' node so that the MIPI DSI bus driver may distinguish its
DSI peripheral device(s) from the existing ports.
Acked-by: Philipp Zabel p.za...@pengutronix.de
Signed-off-by: Liu Ying ying@freescale.com
---
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7-v8:
* None.
v5-v6:
* None.
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* Add Philipp's Ack.
v1-v2:
* Newly added, as suggested by Thierry Reding.
arch/arm/boot/dts/imx6q.dtsi | 20 +++-
arch/arm/boot/dts/imx6qdl.dtsi | 23 ++-
2 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 85f72e6..e152e6e 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -292,19 +292,21 @@
};
mipi_dsi {
- port@2 {
- reg = 2;
+ ports {
+ port@2 {
+ reg = 2;
- mipi_mux_2: endpoint {
- remote-endpoint = ipu2_di0_mipi;
+ mipi_mux_2: endpoint {
+ remote-endpoint = ipu2_di0_mipi;
+ };
};
- };
- port@3 {
- reg = 3;
+ port@3 {
+ reg = 3;
- mipi_mux_3: endpoint {
- remote-endpoint = ipu2_di1_mipi;
+ mipi_mux_3: endpoint {
+ remote-endpoint = ipu2_di1_mipi;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 2109d07..55aced8 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1023,19 +1023,24 @@
reg = 0x021e 0x4000;
status = disabled;
- port@0 {
- reg = 0;
+ ports {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ port@0 {
+ reg = 0;
- mipi_mux_0: endpoint {
- remote-endpoint =
ipu1_di0_mipi;
+ mipi_mux_0: endpoint {
+ remote-endpoint =
ipu1_di0_mipi;
+ };
};
- };
- port@1 {
- reg = 1;
+ port@1 {
+ reg = 1;
- mipi_mux_1: endpoint {
- remote-endpoint =
ipu1_di1_mipi;
+ mipi_mux_1: endpoint {
+ remote-endpoint =
ipu1_di1_mipi;
+ };
};
};
};
--
2.1.0
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[PATCH RFC v9 01/20] clk: divider: Correct parent clk round rate if no bestdiv is normally found
If no best divider is normally found, we will try to use the maximum divider.
We should not set the parent clock rate to be 1Hz by force for being rounded.
Instead, we should take the maximum divider as a base and calculate a correct
parent clock rate for being rounded.
Signed-off-by: Liu Ying ying@freescale.com
---
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7-v8:
* None.
v6-v7:
* None.
v5-v6:
* None.
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* None.
v1-v2:
* None.
drivers/clk/clk-divider.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index c0a842b..f641d4b 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -311,7 +311,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned
long rate,
if (!bestdiv) {
bestdiv = _get_maxdiv(divider);
- *best_parent_rate = __clk_round_rate(__clk_get_parent(hw-clk),
1);
+ *best_parent_rate = __clk_round_rate(__clk_get_parent(hw-clk),
+ MULT_ROUND_UP(rate, bestdiv));
}
return bestdiv;
--
2.1.0
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[PATCH RFC v9 14/20] Documentation: dt-bindings: Add bindings for Himax HX8369A DRM panel driver
This patch adds device tree bindings for Himax HX8369A DRM panel driver.
Signed-off-by: Liu Ying ying@freescale.com
---
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7-v8:
* None.
v6-v7:
* None.
v5-v6:
* None.
v4-v5:
* Merge the bs[3:0]-gpios properties into one property - bs-gpios.
This addresses Andrzej Hajda's comment.
v3-v4:
* Newly introduced in v4. This is separated from the relevant driver patch
in v3 to address Stefan Wahren's comment.
.../devicetree/bindings/panel/himax,hx8369a.txt| 39 ++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/himax,hx8369a.txt
diff --git a/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
b/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
new file mode 100644
index 000..3a44b70
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
@@ -0,0 +1,39 @@
+Himax HX8369A WVGA 16.7M color TFT single chip driver with internal GRAM
+
+Himax HX8369A is a WVGA resolution driving controller.
+It is designed to provide a single chip solution that combines a source
+driver and power supply circuits to drive a TFT dot matrix LCD with
+480RGBx864 dots at the maximum.
+
+The HX8369A supports several interface modes, including MPU MIPI DBI Type
+A/B mode, MIPI DPI/DBI Type C mode, MIPI DSI video mode, MIPI DSI command
+mode and MDDI mode. The interface mode is selected by the external hardware
+pins BS[3:0].
+
+Currently, only the MIPI DSI video mode is supported.
+
+Required properties:
+ - compatible: should be a panel's compatible string
+ - reg: the virtual channel number of a DSI peripheral, as described in [1]
+ - reset-gpios: a GPIO spec for the reset pin, as described in [2]
+
+Optional properties:
+ - vdd1-supply: I/O and interface power supply
+ - vdd2-supply: analog power supply
+ - vdd3-supply: logic power supply
+ - dsi-vcc-supply: DSI and MDDI power supply
+ - vpp-supply: OTP programming voltage
+ - bs-gpios: a GPIO spec for the pins BS[3:0], as described in [2]
+
+[1] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+[2] Documentation/devicetree/bindings/gpio/gpio.txt
+
+Example:
+ panel {
+ compatible = truly,tft480800-16-e-dsi;
+ reg = 0;
+ pinctrl-names = default;
+ pinctrl-0 = pinctrl_mipi_panel;
+ reset-gpios = gpio6 11 GPIO_ACTIVE_LOW;
+ bs-gpios = 0, 0, gpio6 14 GPIO_ACTIVE_HIGH, 0;
+ };
--
2.1.0
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[PATCH RFC v9 00/20] Add support for i.MX MIPI DSI DRM driver
Hi, This version mainly addresses the comments from Philipp Zabel on v8. The comments include a. A common compatible string snps,dw-mipi-dsi should be appended to all SoCs' MIPI DSI device tree documentations and nodes. b. Clean up the common clocks needed by the Synopsys DesignWare MIPI DSI host controller. This version also drops two documentation patches in v8 for adding Himax and Truly vendor prefixes since Rob Herring has taken them. The i.MX MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a i.MX MIPI DSI specific DRM driver. Currently, the MIPI DSI drivers only support the burst with sync pulse mode. This series also includes a DRM panel driver for the Truly TFT480800-16-E panel which is driven by the Himax HX8369A driver IC. The driver IC data sheet could be found at [1]. As mentioned by the data sheet, the driver IC supports several interface modes. Currently, the DRM panel driver only supports the MIPI DSI video mode. New interface modes could be added later(perhaps, just like the way the DRM simple panel driver supports both MIPI DSI interface panels and simple(parallel) interface panels). The MIPI DSI feature is tested on i.MX6Q SabreSD board and i.MX6DL SabreSD board. The MIPI DSI display could be enabled directly on i.MX6Q SabreSD board after applying this series, because the 26.4MHz pixel clock the panel requires could be derived from the IPU HSP clock(264MHz) with an integer divider. On i.MX6DL SabreSD board, we need to manually disable the LVDS and HDMI displays in the device tree blob, since the i.MX6DL IPU HSP clock is 198MHz at present, which makes the pixel clock share the PLL5 video clock source with the LVDS and HDMI, thus, the panel cannot get the pixel clock rate it wants. Patch 01/20 is needed to get a precise pixel clock rate(26.4MHz) from the PLL5 video clock. If we don't have this patch, the pixel clock rate is about 20MHz, which causes a horitonal shift on the display image. This series can be applied on the imx-drm/next branch of Philipp Zabel's open git repository. [1] http://www.allshore.com/pdf/Himax_HX8369-A.pdf Liu Ying (20): clk: divider: Correct parent clk round rate if no bestdiv is normally found ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition ARM: imx6q: clk: Add the video_27m clock ARM: imx6q: clk: Change hdmi_isfr clock's parent to be video_27m clock ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gate ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate ARM: imx6q: clk: Add support for mipi_ipg clock as a shared clock gate ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver Documentation: dt-bindings: Add bindings for i.MX specific Synopsys DW MIPI DSI driver drm: imx: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for Himax HX8369A DRM panel driver drm: panel: Add support for Himax HX8369A MIPI DSI panel ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel .../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 76 ++ .../devicetree/bindings/drm/imx/mipi_dsi.txt | 81 ++ .../devicetree/bindings/panel/himax,hx8369a.txt| 39 + arch/arm/boot/dts/imx6q.dtsi | 20 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 20 + arch/arm/boot/dts/imx6qdl.dtsi | 30 +- arch/arm/configs/imx_v6_v7_defconfig | 23 +- arch/arm/mach-imx/clk-imx6q.c |8 +- drivers/clk/clk-divider.c |3 +- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1006 drivers/gpu/drm/imx/Kconfig|7 + drivers/gpu/drm/imx/Makefile |1 + drivers/gpu/drm/imx/dw_mipi_dsi-imx.c | 230 + drivers/gpu/drm/panel/Kconfig |5 + drivers/gpu/drm/panel/Makefile |1 + drivers/gpu/drm/panel/panel-himax-hx8369a.c| 610 include/drm/bridge/dw_mipi_dsi.h | 27 + include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock
[PATCH RFC v9 03/20] ARM: imx6q: clk: Add the video_27m clock
This patch supports the video_27m clock which is a fixed factor
clock of the pll3_pfd1_540m clock.
Signed-off-by: Liu Ying ying@freescale.com
---
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7-v8:
* None.
v6-v7:
* None.
v5-v6:
* None.
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* None.
v1-v2:
* None.
arch/arm/mach-imx/clk-imx6q.c | 1 +
include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 2daef61..2b7beb8 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -246,6 +246,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor(pll3_60m,
pll3_usb_otg, 1, 8);
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor(twd, arm,
1, 2);
clk[IMX6QDL_CLK_GPT_3M]= imx_clk_fixed_factor(gpt_3m,osc,
1, 8);
+ clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor(video_27m,
pll3_pfd1_540m, 1, 20);
if (cpu_is_imx6dl()) {
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor(gpu2d_axi,
mmdc_ch0_axi_podf, 1, 1);
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor(gpu3d_axi,
mmdc_ch0_axi_podf, 1, 1);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h
b/include/dt-bindings/clock/imx6qdl-clock.h
index b690cdb..25625bf 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -248,6 +248,7 @@
#define IMX6QDL_PLL6_BYPASS235
#define IMX6QDL_PLL7_BYPASS236
#define IMX6QDL_CLK_GPT_3M 237
-#define IMX6QDL_CLK_END238
+#define IMX6QDL_CLK_VIDEO_27M 238
+#define IMX6QDL_CLK_END239
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.1.0
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[PATCH RFC v9 13/20] drm: imx: Support Synopsys DesignWare MIPI DSI host controller
This patch adds support for Synopsys DesignWare MIPI DSI host controller
which is embedded in the i.MX6q/sdl SoCs.
Signed-off-by: Liu Ying ying@freescale.com
---
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
* Add driver copyright for 2015.
v7-v8:
* None.
v6-v7:
* None.
v5-v6:
* Make the checkpatch.pl script be happier.
v4-v5:
* None.
v3-v4:
* Move the relevant dt-bindings to a separate patch to address Stefan
Wahren's comment.
v2-v3:
* To address Andy Yan's comments, move the common Synopsys DesignWare MIPI DSI
host controller logic into it's drm/bridge driver and leave the i.MX specific
logic only.
v1-v2:
* Address almost all comments from Thierry Reding and Russell.
* Update the DT documentation to remove the display-timings node in the panel
node.
* Update the DT documentation to state that the nodes which represent the
possible
DRM CRTCs the controller may connect with should be placed in the node
ports.
* Remove the flag 'enabled' from the struct imx_mipi_dsi.
* Move the format_to_bpp() function in v1 to the common DRM MIPI DSI driver.
* Improve the way we wait for check status for DPHY and command packet
transfer.
* Improve the DPMS support for the encoder.
* Split the functions of -host_attach() and -mode_valid() clearly as
suggested by
Thierry Reding.
* Improve the logics in imx_mipi_dsi_dcs_long_write().
* Enable/disable the pllref_clk and pllref_gate_clk at the component
binding/unbinding
stages to help remove the flag 'enabled'.
* Update the module license to be GPL.
* Other minor changes, such as coding style issues and macro naming issues.
drivers/gpu/drm/imx/Kconfig | 7 ++
drivers/gpu/drm/imx/Makefile | 1 +
drivers/gpu/drm/imx/dw_mipi_dsi-imx.c | 230 ++
3 files changed, 238 insertions(+)
create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx.c
diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 33cdddf..7faeb49 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -53,3 +53,10 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
Choose this if you want to use HDMI on i.MX6.
+
+config DRM_IMX_MIPI_DSI
+ tristate Freescale i.MX DRM MIPI DSI
+ select DRM_DW_MIPI_DSI
+ depends on DRM_IMX
+ help
+ Choose this if you want to use MIPI DSI on i.MX6.
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index f3ecd89..93919b4 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
imx-ipuv3-crtc-objs := ipuv3-crtc.o ipuv3-plane.o
obj-$(CONFIG_DRM_IMX_IPUV3)+= imx-ipuv3-crtc.o
obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX_MIPI_DSI) += dw_mipi_dsi-imx.o
diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx.c
b/drivers/gpu/drm/imx/dw_mipi_dsi-imx.c
new file mode 100644
index 000..5e6f62d
--- /dev/null
+++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx.c
@@ -0,0 +1,230 @@
+/*
+ * i.MX drm driver - MIPI DSI Host Controller
+ *
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/component.h
+#include linux/mfd/syscon.h
+#include linux/mfd/syscon/imx6q-iomuxc-gpr.h
+#include linux/module.h
+#include linux/of_device.h
+#include linux/regmap.h
+#include linux/videodev2.h
+#include drm/bridge/dw_mipi_dsi.h
+#include drm/drm_crtc_helper.h
+#include drm/drm_mipi_dsi.h
+
+#include imx-drm.h
+
+#define DRIVER_NAMEimx-mipi-dsi
+
+struct imx_mipi_dsi {
+ struct drm_encoder encoder;
+ struct device *dev;
+ struct regmap *regmap;
+};
+
+static inline struct imx_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
+{
+ return container_of(enc, struct imx_mipi_dsi, encoder);
+}
+
+static void imx_mipi_dsi_set_ipu_di_mux(struct imx_mipi_dsi *dsi, int ipu_di)
+{
+ regmap_update_bits(dsi-regmap, IOMUXC_GPR3,
+ IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
+ ipu_di IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT);
+}
+
+static struct drm_encoder_funcs imx_mipi_dsi_encoder_funcs = {
+ .destroy = imx_drm_encoder_destroy,
+};
+
+static bool imx_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true
[PATCH RFC v9 02/20] ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition
This patch adds a macro to define the GPR3 MIPI muxing control register field shift bits. Signed-off-by: Liu Ying ying@freescale.com --- v8-v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository. v7-v8: * None. v6-v7: * None. v5-v6: * None. v4-v5: * None. v3-v4: * None. v2-v3: * None. v1-v2: * None. include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index c877cad..d16f4c8 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -207,6 +207,7 @@ #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 6) #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 6) #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 6) +#define IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT 4 #define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 4) -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v9 11/20] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver
This patch adds Synopsys DesignWare MIPI DSI host controller driver support. Currently, the driver supports the burst with sync pulses mode only. Signed-off-by: Liu Ying ying@freescale.com --- v8-v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository and adapt to bridge API change as the dw-hdmi driver did. * To address Philipp's comment, add a new required clock pclk and clean up clock-names. * Add driver copyright for 2015. v7-v8: * Fix the driver's Kconfig so that we may pass the allmodconfig for ARM. v6-v7: * None. v5-v6: * Make the checkpatch.pl script be happier. v4-v5: * Remove 'dsi-panel = NULL;' in dw_mipi_dsi_host_detach() to address Andrzej Hajda's comment. v3-v4: * Move the relevant dt-bindings to a separate patch to address Stefan Wahren's comment. v2-v3: * Newly introduced in v3 to address Andy Yan's comment. This is based on the i.MX MIPI DSI driver in v2. To make the Synopsys DesignWare MIPI DSI host controller driver less platform-dependant, this patch places it at the drm/bridge directory as a DRM bridge driver. drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1006 ++ include/drm/bridge/dw_mipi_dsi.h | 27 + 4 files changed, 1044 insertions(+) create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index f38bbcd..de151f2 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -3,6 +3,16 @@ config DRM_DW_HDMI depends on DRM select DRM_KMS_HELPER +config DRM_DW_MIPI_DSI + tristate Synopsys DesignWare MIPI DSI host controller bridge + depends on DRM + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + help + Choose this if you want to use the Synopsys DesignWare MIPI DSI host + controller bridge. + config DRM_PTN3460 tristate PTN3460 DP/LVDS bridge depends on DRM diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index d8a8cfd..5f8e9b3 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -2,3 +2,4 @@ ccflags-y := -Iinclude/drm obj-$(CONFIG_DRM_PTN3460) += ptn3460.o obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw_mipi_dsi.o diff --git a/drivers/gpu/drm/bridge/dw_mipi_dsi.c b/drivers/gpu/drm/bridge/dw_mipi_dsi.c new file mode 100644 index 000..0ff241e --- /dev/null +++ b/drivers/gpu/drm/bridge/dw_mipi_dsi.c @@ -0,0 +1,1006 @@ +/* + * Synopsys DesignWare(DW) MIPI DSI Host Controller + * + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include linux/clk.h +#include linux/math64.h +#include linux/module.h +#include drm/bridge/dw_mipi_dsi.h +#include drm/drm_crtc_helper.h +#include drm/drm_mipi_dsi.h +#include drm/drm_panel.h +#include video/mipi_display.h + +#define DSI_VERSION0x00 + +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) 0xff) 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) 0xff) 0) + +#define DSI_DPI_CFG0x0c +#define EN18_LOOSELY BIT(10) +#define COLORM_ACTIVE_LOW BIT(9) +#define SHUTD_ACTIVE_LOW BIT(8) +#define HSYNC_ACTIVE_LOW BIT(7) +#define VSYNC_ACTIVE_LOW BIT(6) +#define DATAEN_ACTIVE_LOW BIT(5) +#define DPI_COLOR_CODING_16BIT_1 (0x0 2) +#define DPI_COLOR_CODING_16BIT_2 (0x1 2) +#define DPI_COLOR_CODING_16BIT_3 (0x2 2) +#define DPI_COLOR_CODING_18BIT_1 (0x3 2) +#define DPI_COLOR_CODING_18BIT_2 (0x4 2) +#define DPI_COLOR_CODING_24BIT (0x5 2) +#define DPI_VID(vid) (((vid) 0x3) 0) + +#define DSI_DBI_CFG0x10 +#define DSI_DBIS_CMDSIZE 0x14 + +#define DSI_PCKHDL_CFG 0x18 +#define GEN_VID_RX(vid)(((vid) 0x3) 5) +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTN_RX
[PATCH RFC v9 07/20] ARM: imx6q: clk: Add support for mipi_ipg clock as a shared clock gate
The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the ipg clock's output. The MIPI DSI host controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk - the APB clock signal . In order to gate/ungate the ipg clock, this patch adds a new shared clock gate named as mipi_ipg. Signed-off-by: Liu Ying ying@freescale.com --- v8-v9: * Newly introduced in v9. arch/arm/mach-imx/clk-imx6q.c | 1 + include/dt-bindings/clock/imx6qdl-clock.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index cbdbe2a..909828d 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -419,6 +419,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2(ipu2_di1, ipu2_di1_sel, base + 0x74, 10); clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared(hsi_tx, hsi_tx_podf, base + 0x74, 16, share_count_mipi_core_cfg); clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared(mipi_core_cfg, video_27m, base + 0x74, 16, share_count_mipi_core_cfg); + clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared(mipi_ipg, ipg, base + 0x74, 16, share_count_mipi_core_cfg); if (cpu_is_imx6dl()) /* * The multiplexer and divider of the imx6q clock gpu2d get diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index dbc828c..8780868 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -250,6 +250,7 @@ #define IMX6QDL_CLK_GPT_3M 237 #define IMX6QDL_CLK_VIDEO_27M 238 #define IMX6QDL_CLK_MIPI_CORE_CFG 239 -#define IMX6QDL_CLK_END240 +#define IMX6QDL_CLK_MIPI_IPG 240 +#define IMX6QDL_CLK_END241 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v9 17/20] ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel
The TRULY TFT480800-16-E panel is driven by the Himax HX8369A driver IC.
The driver IC supports several display/control interface modes, including
the MIPI DSI video mode and command mode.
Signed-off-by: Liu Ying ying@freescale.com
---
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7-v8:
* None.
v6-v7:
* None.
v5-v6:
* None.
v4-v5:
* Replace the bs[3:0]-gpios properties with the bs-gpios property.
This addresses Andrzej Hajda's comment.
v3-v4:
* None.
v2-v3:
* None.
v1-v2:
* To address Thierry Reding's comments, remove several unnecessary
properties as they can be implied by the compatible string.
* Fix the compatible string.
* Remove the display-timings node from the panel node as it can be
implied by the compatible string as well.
* Remove the status property as it is unneeded.
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index f1cd214..9ff4ba5 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -480,6 +480,13 @@
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
;
};
+
+ pinctrl_mipi_panel: mipipanelgrp {
+ fsl,pins =
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
+ ;
+ };
};
gpio_leds {
@@ -516,6 +523,19 @@
};
};
+mipi_dsi {
+ status = okay;
+
+ panel {
+ compatible = truly,tft480800-16-e-dsi;
+ reg = 0;
+ pinctrl-names = default;
+ pinctrl-0 = pinctrl_mipi_panel;
+ reset-gpios = gpio6 11 GPIO_ACTIVE_LOW;
+ bs-gpios = 0, 0, gpio6 14 GPIO_ACTIVE_HIGH, 0;
+ };
+};
+
pcie {
pinctrl-names = default;
pinctrl-0 = pinctrl_pcie;
--
2.1.0
--
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[PATCH RFC v9 15/20] drm: panel: Add support for Himax HX8369A MIPI DSI panel
This patch adds support for Himax HX8369A MIPI DSI panel.
Reviewed-by: Andrzej Hajda a.ha...@samsung.com
Signed-off-by: Liu Ying ying@freescale.com
---
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
* Add driver copyright for 2015.
v7-v8:
* Remove several unnecessary headers included in the driver.
v6-v7:
* Address Andrzej Hajda's following comments.
* Simplify the return logic in hx8369a_dcs_write().
* Replace the macro hx8369a_dsi_init_helper() with a function array to improve
the code quality.
* Handle error cases during getting gpios in probe().
* Add 'Reviewed-by: Andrzej Hajda a.ha...@samsung.com'.
v5-v6:
* Make the checkpatch.pl script be happier.
* Do not set the dsi channel number to be zero in probe(), because the MIPI DSI
bus driver would set it.
v4-v5:
* Address Andrzej Hajda's comments.
* Get the bs-gpios property instead of the bs[3:0]-gpios properties.
* Implement error propagation for panel register configurations.
* Other minor changes to improve the code quality.
v3-v4:
* Move the relevant dt-bindings to a separate patch to address Stefan
Wahren's comment.
v2-v3:
* Sort the included header files alphabetically.
v1-v2:
* Address almost all comments from Thierry Reding.
* Remove several DT properties as they can be implied by the compatible string.
* Add the HIMAX/himax prefixes to the driver's Kconfig name and driver name.
* Move the driver's Makefile entry place to sort the entries alphabetically.
* Reuse several standard DCS functions instead of inventing wheels.
* Move the panel resetting and power logics to the driver probe/remove stages.
This may simplify panel prepare/unprepare hooks. The power consumption should
not change a lot at DPMS since the panel enters sleep mode at that time.
* Add the module author.
* Other minor changes, such as coding style issues.
drivers/gpu/drm/panel/Kconfig | 5 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-himax-hx8369a.c | 610
3 files changed, 616 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-himax-hx8369a.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index d845837..cd6fbb7 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -17,6 +17,11 @@ config DRM_PANEL_SIMPLE
that it can be automatically turned off when the panel goes into a
low power state.
+config DRM_PANEL_HIMAX_HX8369A
+ tristate Himax HX8369A panel
+ depends on OF
+ select DRM_MIPI_DSI
+
config DRM_PANEL_LD9040
tristate LD9040 RGB/SPI panel
depends on OF SPI
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 4b2a043..d5dbe06 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
+obj-$(CONFIG_DRM_PANEL_HIMAX_HX8369A) += panel-himax-hx8369a.o
obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
diff --git a/drivers/gpu/drm/panel/panel-himax-hx8369a.c
b/drivers/gpu/drm/panel/panel-himax-hx8369a.c
new file mode 100644
index 000..649e395
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-himax-hx8369a.c
@@ -0,0 +1,610 @@
+/*
+ * Himax HX8369A panel driver.
+ *
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This driver is based on Samsung s6e8aa0 panel driver.
+ */
+
+#include drm/drmP.h
+#include drm/drm_mipi_dsi.h
+#include drm/drm_panel.h
+
+#include linux/gpio/consumer.h
+#include linux/of_device.h
+#include linux/regulator/consumer.h
+
+#define WRDISBV0x51
+#define WRCTRLD0x53
+#define WRCABC 0x55
+#define SETPOWER 0xb1
+#define SETDISP0xb2
+#define SETCYC 0xb4
+#define SETVCOM0xb6
+#define SETEXTC0xb9
+#define SETMIPI0xba
+#define SETPANEL 0xcc
+#define SETGIP 0xd5
+#define SETGAMMA 0xe0
+
+#define HX8369A_MIN_BRIGHTNESS 0x00
+#define HX8369A_MAX_BRIGHTNESS 0xff
+
+enum hx8369a_mpu_interface {
+ HX8369A_DBI_TYPE_A_8BIT,
+ HX8369A_DBI_TYPE_A_9BIT,
+ HX8369A_DBI_TYPE_A_16BIT,
+ HX8369A_DBI_TYPE_A_18BIT,
+ HX8369A_DBI_TYPE_B_8BIT,
+ HX8369A_DBI_TYPE_B_9BIT,
+ HX8369A_DBI_TYPE_B_16BIT,
+ HX8369A_DBI_TYPE_B_18BIT,
+ HX8369A_DSI_CMD_MODE,
+ HX8369A_DBI_TYPE_B_24BIT,
+ HX8369A_DSI_VIDEO_MODE,
+ HX8369A_MDDI,
+ HX8369A_DPI_DBI_TYPE_C_OPT1,
+ HX8369A_DPI_DBI_TYPE_C_OPT2,
+ HX8369A_DPI_DBI_TYPE_C_OPT3
+};
+
+enum
Re: [PATCH] ARM: imx_v6_v7_defconfig: Select CONFIG_FB_MXS
2015-01-08 7:35 GMT+08:00 Fabio Estevam feste...@gmail.com: From: Fabio Estevam fabio.este...@freescale.com CONFIG_FB_MXS is the LCD driver for mx6solo-lite and mx6solox. Enable it by default. I'm not sure if it is suitable to enable CONFIG_FB_MXS by default. At least, I have no strong objections. I am considering to add a LCDIF CRTC driver to the imx-drm framework so that we may use the existing LDB drm driver to support the mx6solox LVDS interface. I see the i915 and omap2 fb drivers depend on !DRM_: grep DRM_ drivers/video/fbdev/ -nr drivers/video/fbdev/omap2/omapfb/Kconfig:3:depends on FB OMAP2_DSS !DRM_OMAP drivers/video/fbdev/Kconfig:1197: depends on !DRM_I915 So, similarly, we'll probably have two LCDIF drivers and make the DRM one enabled by default - finally, CONFIG_FB_MXS is disabled. Another concern is the compatibility. Since both the framebuffer driver and the imx-drm driver would export the framebuffer interface to the user space, we'd better to keep the interface behavior the same. Maybe, this is not a big problem, because we need to keep the compatibility anyway... Regards, Liu Ying Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 9575af8..1f36977 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -203,6 +203,7 @@ CONFIG_DRM_PANEL_SIMPLE=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y +CONFIG_FB_MXS=y CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_GPIO=y CONFIG_FRAMEBUFFER_CONSOLE=y -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ -- Best Regards, Liu Ying -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3] video: mxsfb: Make sure axi clock is enabled when accessing registers
The LCDIF engines embedded in i.MX6sl and i.MX6sx SoCs need the axi clock
as the engine's system clock. The clock should be enabled when accessing
LCDIF registers, otherwise the kernel would hang up. We should also keep
the clock enabled when the engine is being active to scan out frames from
memory. This patch makes sure the axi clock is enabled when accessing
registers so that the kernel hang up issue can be fixed.
Reported-by: Peter Chen peter.c...@freescale.com
Tested-by: Peter Chen peter.c...@freescale.com
Cc: sta...@vger.kernel.org # 3.19+
Signed-off-by: Liu Ying ying@freescale.com
---
v2-v3:
* To address Tomi's comment, improve the commit message only.
v1-v2:
* Add 'Tested-by: Peter Chen peter.c...@freescale.com' tag.
* Add 'Cc: sta...@vger.kernel.org # 3.19+' tag.
drivers/video/fbdev/mxsfb.c | 70 -
1 file changed, 56 insertions(+), 14 deletions(-)
diff --git a/drivers/video/fbdev/mxsfb.c b/drivers/video/fbdev/mxsfb.c
index f8ac4a4..a8cf3b2 100644
--- a/drivers/video/fbdev/mxsfb.c
+++ b/drivers/video/fbdev/mxsfb.c
@@ -316,6 +316,18 @@ static int mxsfb_check_var(struct fb_var_screeninfo *var,
return 0;
}
+static inline void mxsfb_enable_axi_clk(struct mxsfb_info *host)
+{
+ if (host-clk_axi)
+ clk_prepare_enable(host-clk_axi);
+}
+
+static inline void mxsfb_disable_axi_clk(struct mxsfb_info *host)
+{
+ if (host-clk_axi)
+ clk_disable_unprepare(host-clk_axi);
+}
+
static void mxsfb_enable_controller(struct fb_info *fb_info)
{
struct mxsfb_info *host = to_imxfb_host(fb_info);
@@ -333,14 +345,13 @@ static void mxsfb_enable_controller(struct fb_info
*fb_info)
}
}
- if (host-clk_axi)
- clk_prepare_enable(host-clk_axi);
-
if (host-clk_disp_axi)
clk_prepare_enable(host-clk_disp_axi);
clk_prepare_enable(host-clk);
clk_set_rate(host-clk, PICOS2KHZ(fb_info-var.pixclock) * 1000U);
+ mxsfb_enable_axi_clk(host);
+
/* if it was disabled, re-enable the mode again */
writel(CTRL_DOTCLK_MODE, host-base + LCDC_CTRL + REG_SET);
@@ -380,11 +391,11 @@ static void mxsfb_disable_controller(struct fb_info
*fb_info)
reg = readl(host-base + LCDC_VDCTRL4);
writel(reg ~VDCTRL4_SYNC_SIGNALS_ON, host-base + LCDC_VDCTRL4);
+ mxsfb_disable_axi_clk(host);
+
clk_disable_unprepare(host-clk);
if (host-clk_disp_axi)
clk_disable_unprepare(host-clk_disp_axi);
- if (host-clk_axi)
- clk_disable_unprepare(host-clk_axi);
host-enabled = 0;
@@ -421,6 +432,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
mxsfb_disable_controller(fb_info);
}
+ mxsfb_enable_axi_clk(host);
+
/* clear the FIFOs */
writel(CTRL1_FIFO_CLEAR, host-base + LCDC_CTRL1 + REG_SET);
@@ -438,6 +451,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
ctrl |= CTRL_SET_WORD_LENGTH(3);
switch (host-ld_intf_width) {
case STMLCDIF_8BIT:
+ mxsfb_disable_axi_clk(host);
dev_err(host-pdev-dev,
Unsupported LCD bus width mapping\n);
return -EINVAL;
@@ -451,6 +465,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
writel(CTRL1_SET_BYTE_PACKAGING(0x7), host-base + LCDC_CTRL1);
break;
default:
+ mxsfb_disable_axi_clk(host);
dev_err(host-pdev-dev, Unhandled color depth of %u\n,
fb_info-var.bits_per_pixel);
return -EINVAL;
@@ -504,6 +519,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
fb_info-fix.line_length * fb_info-var.yoffset,
host-base + host-devdata-next_buf);
+ mxsfb_disable_axi_clk(host);
+
if (reenable)
mxsfb_enable_controller(fb_info);
@@ -582,10 +599,16 @@ static int mxsfb_pan_display(struct fb_var_screeninfo
*var,
offset = fb_info-fix.line_length * var-yoffset;
+ if (!host-enabled)
+ mxsfb_enable_axi_clk(host);
+
/* update on next VSYNC */
writel(fb_info-fix.smem_start + offset,
host-base + host-devdata-next_buf);
+ if (!host-enabled)
+ mxsfb_disable_axi_clk(host);
+
return 0;
}
@@ -608,13 +631,17 @@ static int mxsfb_restore_mode(struct mxsfb_info *host,
unsigned line_count;
unsigned period;
unsigned long pa, fbsize;
- int bits_per_pixel, ofs;
+ int bits_per_pixel, ofs, ret = 0;
u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
+ mxsfb_enable_axi_clk(host);
+
/* Only restore the mode when the controller is running */
ctrl = readl(host-base + LCDC_CTRL
Re: [PATCH v2] video: mxsfb: Make sure axi clock is enabled when accessing registers
On Tue, Mar 10, 2015 at 02:02:37PM +0200, Tomi Valkeinen wrote:
On 04/03/15 09:06, Liu Ying wrote:
The LCDIF engines embedded in i.MX6sl and i.MX6sx SoCs need the axi clock
as the engine's system clock. The clock should be enabled when accessing
LCDIF registers, otherwise the kernel would hang up. We should also keep
the clock being enabled when the engine is being active to scan out frames
The text above is a bit confusing. Maybe just ... also keep the clock
enabled when...
Okay.
from memory. This patch makes sure the axi clock is enabled when accessing
registers so that the kernel hang up issue can be fixed.
Reported-by: Peter Chen peter.c...@freescale.com
Tested-by: Peter Chen peter.c...@freescale.com
Cc: sta...@vger.kernel.org # 3.19+
Signed-off-by: Liu Ying ying@freescale.com
---
v1-v2:
* Add 'Tested-by: Peter Chen peter.c...@freescale.com' tag.
* Add 'Cc: sta...@vger.kernel.org # 3.19+' tag.
drivers/video/fbdev/mxsfb.c | 70
-
1 file changed, 56 insertions(+), 14 deletions(-)
diff --git a/drivers/video/fbdev/mxsfb.c b/drivers/video/fbdev/mxsfb.c
index f8ac4a4..a8cf3b2 100644
--- a/drivers/video/fbdev/mxsfb.c
+++ b/drivers/video/fbdev/mxsfb.c
@@ -316,6 +316,18 @@ static int mxsfb_check_var(struct fb_var_screeninfo
*var,
return 0;
}
+static inline void mxsfb_enable_axi_clk(struct mxsfb_info *host)
+{
+ if (host-clk_axi)
+ clk_prepare_enable(host-clk_axi);
+}
+
+static inline void mxsfb_disable_axi_clk(struct mxsfb_info *host)
+{
+ if (host-clk_axi)
+ clk_disable_unprepare(host-clk_axi);
+}
+
static void mxsfb_enable_controller(struct fb_info *fb_info)
{
struct mxsfb_info *host = to_imxfb_host(fb_info);
@@ -333,14 +345,13 @@ static void mxsfb_enable_controller(struct fb_info
*fb_info)
}
}
- if (host-clk_axi)
- clk_prepare_enable(host-clk_axi);
-
if (host-clk_disp_axi)
clk_prepare_enable(host-clk_disp_axi);
clk_prepare_enable(host-clk);
clk_set_rate(host-clk, PICOS2KHZ(fb_info-var.pixclock) * 1000U);
+ mxsfb_enable_axi_clk(host);
+
Is there some reason to move the clk enable to a different place here?
Moving it to here reflects better that we need to enable it when accessing the
registers.
Another reason is weak, perhaps. We've got an unannounced new SoC(not yet get
upstreamed). It has a LCDIF embedded. The pixel clock(host-clk) and the axi
clock are derived from a same clock gate. And, the clock gate is defined with
the flag CLK_SET_RATE_GATE, which means it must be gated across rate change.
So, we need to move it beneath clk_set_rate() for the pixel clock sooner or
later.
/* if it was disabled, re-enable the mode again */
writel(CTRL_DOTCLK_MODE, host-base + LCDC_CTRL + REG_SET);
@@ -380,11 +391,11 @@ static void mxsfb_disable_controller(struct fb_info
*fb_info)
reg = readl(host-base + LCDC_VDCTRL4);
writel(reg ~VDCTRL4_SYNC_SIGNALS_ON, host-base + LCDC_VDCTRL4);
+ mxsfb_disable_axi_clk(host);
+
clk_disable_unprepare(host-clk);
if (host-clk_disp_axi)
clk_disable_unprepare(host-clk_disp_axi);
- if (host-clk_axi)
- clk_disable_unprepare(host-clk_axi);
And same here for disable.
This is to make sure the clock disable order is exactly reversed, comparing to
the clock enable order.
host-enabled = 0;
@@ -421,6 +432,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
mxsfb_disable_controller(fb_info);
}
+ mxsfb_enable_axi_clk(host);
+
/* clear the FIFOs */
writel(CTRL1_FIFO_CLEAR, host-base + LCDC_CTRL1 + REG_SET);
@@ -438,6 +451,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
ctrl |= CTRL_SET_WORD_LENGTH(3);
switch (host-ld_intf_width) {
case STMLCDIF_8BIT:
+ mxsfb_disable_axi_clk(host);
dev_err(host-pdev-dev,
Unsupported LCD bus width mapping\n);
return -EINVAL;
@@ -451,6 +465,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
writel(CTRL1_SET_BYTE_PACKAGING(0x7), host-base + LCDC_CTRL1);
break;
default:
+ mxsfb_disable_axi_clk(host);
dev_err(host-pdev-dev, Unhandled color depth of %u\n,
fb_info-var.bits_per_pixel);
return -EINVAL;
@@ -504,6 +519,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
fb_info-fix.line_length * fb_info-var.yoffset,
host-base + host-devdata-next_buf);
+ mxsfb_disable_axi_clk(host);
+
if (reenable)
mxsfb_enable_controller(fb_info);
@@ -582,10 +599,16 @@ static int mxsfb_pan_display(struct
[PATCH v2] video: mxsfb: Make sure axi clock is enabled when accessing registers
The LCDIF engines embedded in i.MX6sl and i.MX6sx SoCs need the axi clock
as the engine's system clock. The clock should be enabled when accessing
LCDIF registers, otherwise the kernel would hang up. We should also keep
the clock being enabled when the engine is being active to scan out frames
from memory. This patch makes sure the axi clock is enabled when accessing
registers so that the kernel hang up issue can be fixed.
Reported-by: Peter Chen peter.c...@freescale.com
Tested-by: Peter Chen peter.c...@freescale.com
Cc: sta...@vger.kernel.org # 3.19+
Signed-off-by: Liu Ying ying@freescale.com
---
v1-v2:
* Add 'Tested-by: Peter Chen peter.c...@freescale.com' tag.
* Add 'Cc: sta...@vger.kernel.org # 3.19+' tag.
drivers/video/fbdev/mxsfb.c | 70 -
1 file changed, 56 insertions(+), 14 deletions(-)
diff --git a/drivers/video/fbdev/mxsfb.c b/drivers/video/fbdev/mxsfb.c
index f8ac4a4..a8cf3b2 100644
--- a/drivers/video/fbdev/mxsfb.c
+++ b/drivers/video/fbdev/mxsfb.c
@@ -316,6 +316,18 @@ static int mxsfb_check_var(struct fb_var_screeninfo *var,
return 0;
}
+static inline void mxsfb_enable_axi_clk(struct mxsfb_info *host)
+{
+ if (host-clk_axi)
+ clk_prepare_enable(host-clk_axi);
+}
+
+static inline void mxsfb_disable_axi_clk(struct mxsfb_info *host)
+{
+ if (host-clk_axi)
+ clk_disable_unprepare(host-clk_axi);
+}
+
static void mxsfb_enable_controller(struct fb_info *fb_info)
{
struct mxsfb_info *host = to_imxfb_host(fb_info);
@@ -333,14 +345,13 @@ static void mxsfb_enable_controller(struct fb_info
*fb_info)
}
}
- if (host-clk_axi)
- clk_prepare_enable(host-clk_axi);
-
if (host-clk_disp_axi)
clk_prepare_enable(host-clk_disp_axi);
clk_prepare_enable(host-clk);
clk_set_rate(host-clk, PICOS2KHZ(fb_info-var.pixclock) * 1000U);
+ mxsfb_enable_axi_clk(host);
+
/* if it was disabled, re-enable the mode again */
writel(CTRL_DOTCLK_MODE, host-base + LCDC_CTRL + REG_SET);
@@ -380,11 +391,11 @@ static void mxsfb_disable_controller(struct fb_info
*fb_info)
reg = readl(host-base + LCDC_VDCTRL4);
writel(reg ~VDCTRL4_SYNC_SIGNALS_ON, host-base + LCDC_VDCTRL4);
+ mxsfb_disable_axi_clk(host);
+
clk_disable_unprepare(host-clk);
if (host-clk_disp_axi)
clk_disable_unprepare(host-clk_disp_axi);
- if (host-clk_axi)
- clk_disable_unprepare(host-clk_axi);
host-enabled = 0;
@@ -421,6 +432,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
mxsfb_disable_controller(fb_info);
}
+ mxsfb_enable_axi_clk(host);
+
/* clear the FIFOs */
writel(CTRL1_FIFO_CLEAR, host-base + LCDC_CTRL1 + REG_SET);
@@ -438,6 +451,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
ctrl |= CTRL_SET_WORD_LENGTH(3);
switch (host-ld_intf_width) {
case STMLCDIF_8BIT:
+ mxsfb_disable_axi_clk(host);
dev_err(host-pdev-dev,
Unsupported LCD bus width mapping\n);
return -EINVAL;
@@ -451,6 +465,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
writel(CTRL1_SET_BYTE_PACKAGING(0x7), host-base + LCDC_CTRL1);
break;
default:
+ mxsfb_disable_axi_clk(host);
dev_err(host-pdev-dev, Unhandled color depth of %u\n,
fb_info-var.bits_per_pixel);
return -EINVAL;
@@ -504,6 +519,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
fb_info-fix.line_length * fb_info-var.yoffset,
host-base + host-devdata-next_buf);
+ mxsfb_disable_axi_clk(host);
+
if (reenable)
mxsfb_enable_controller(fb_info);
@@ -582,10 +599,16 @@ static int mxsfb_pan_display(struct fb_var_screeninfo
*var,
offset = fb_info-fix.line_length * var-yoffset;
+ if (!host-enabled)
+ mxsfb_enable_axi_clk(host);
+
/* update on next VSYNC */
writel(fb_info-fix.smem_start + offset,
host-base + host-devdata-next_buf);
+ if (!host-enabled)
+ mxsfb_disable_axi_clk(host);
+
return 0;
}
@@ -608,13 +631,17 @@ static int mxsfb_restore_mode(struct mxsfb_info *host,
unsigned line_count;
unsigned period;
unsigned long pa, fbsize;
- int bits_per_pixel, ofs;
+ int bits_per_pixel, ofs, ret = 0;
u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
+ mxsfb_enable_axi_clk(host);
+
/* Only restore the mode when the controller is running */
ctrl = readl(host-base + LCDC_CTRL);
- if (!(ctrl CTRL_RUN))
- return -EINVAL
[PATCH] video: mxsfb: Make sure axi clock is enabled when accessing registers
The LCDIF engines embedded in i.MX6sl and i.MX6sx SoCs need the axi clock
as the engine's system clock. The clock should be enabled when accessing
LCDIF registers, otherwise the kernel would hang up. We should also keep
the clock being enabled when the engine is being active to scan out frames
from memory. This patch makes sure the axi clock is enabled when accessing
registers so that the kernel hang up issue can be fixed.
Reported-by: Peter Chen peter.c...@freescale.com
Signed-off-by: Liu Ying ying@freescale.com
---
drivers/video/fbdev/mxsfb.c | 70 -
1 file changed, 56 insertions(+), 14 deletions(-)
diff --git a/drivers/video/fbdev/mxsfb.c b/drivers/video/fbdev/mxsfb.c
index f8ac4a4..a8cf3b2 100644
--- a/drivers/video/fbdev/mxsfb.c
+++ b/drivers/video/fbdev/mxsfb.c
@@ -316,6 +316,18 @@ static int mxsfb_check_var(struct fb_var_screeninfo *var,
return 0;
}
+static inline void mxsfb_enable_axi_clk(struct mxsfb_info *host)
+{
+ if (host-clk_axi)
+ clk_prepare_enable(host-clk_axi);
+}
+
+static inline void mxsfb_disable_axi_clk(struct mxsfb_info *host)
+{
+ if (host-clk_axi)
+ clk_disable_unprepare(host-clk_axi);
+}
+
static void mxsfb_enable_controller(struct fb_info *fb_info)
{
struct mxsfb_info *host = to_imxfb_host(fb_info);
@@ -333,14 +345,13 @@ static void mxsfb_enable_controller(struct fb_info
*fb_info)
}
}
- if (host-clk_axi)
- clk_prepare_enable(host-clk_axi);
-
if (host-clk_disp_axi)
clk_prepare_enable(host-clk_disp_axi);
clk_prepare_enable(host-clk);
clk_set_rate(host-clk, PICOS2KHZ(fb_info-var.pixclock) * 1000U);
+ mxsfb_enable_axi_clk(host);
+
/* if it was disabled, re-enable the mode again */
writel(CTRL_DOTCLK_MODE, host-base + LCDC_CTRL + REG_SET);
@@ -380,11 +391,11 @@ static void mxsfb_disable_controller(struct fb_info
*fb_info)
reg = readl(host-base + LCDC_VDCTRL4);
writel(reg ~VDCTRL4_SYNC_SIGNALS_ON, host-base + LCDC_VDCTRL4);
+ mxsfb_disable_axi_clk(host);
+
clk_disable_unprepare(host-clk);
if (host-clk_disp_axi)
clk_disable_unprepare(host-clk_disp_axi);
- if (host-clk_axi)
- clk_disable_unprepare(host-clk_axi);
host-enabled = 0;
@@ -421,6 +432,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
mxsfb_disable_controller(fb_info);
}
+ mxsfb_enable_axi_clk(host);
+
/* clear the FIFOs */
writel(CTRL1_FIFO_CLEAR, host-base + LCDC_CTRL1 + REG_SET);
@@ -438,6 +451,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
ctrl |= CTRL_SET_WORD_LENGTH(3);
switch (host-ld_intf_width) {
case STMLCDIF_8BIT:
+ mxsfb_disable_axi_clk(host);
dev_err(host-pdev-dev,
Unsupported LCD bus width mapping\n);
return -EINVAL;
@@ -451,6 +465,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
writel(CTRL1_SET_BYTE_PACKAGING(0x7), host-base + LCDC_CTRL1);
break;
default:
+ mxsfb_disable_axi_clk(host);
dev_err(host-pdev-dev, Unhandled color depth of %u\n,
fb_info-var.bits_per_pixel);
return -EINVAL;
@@ -504,6 +519,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
fb_info-fix.line_length * fb_info-var.yoffset,
host-base + host-devdata-next_buf);
+ mxsfb_disable_axi_clk(host);
+
if (reenable)
mxsfb_enable_controller(fb_info);
@@ -582,10 +599,16 @@ static int mxsfb_pan_display(struct fb_var_screeninfo
*var,
offset = fb_info-fix.line_length * var-yoffset;
+ if (!host-enabled)
+ mxsfb_enable_axi_clk(host);
+
/* update on next VSYNC */
writel(fb_info-fix.smem_start + offset,
host-base + host-devdata-next_buf);
+ if (!host-enabled)
+ mxsfb_disable_axi_clk(host);
+
return 0;
}
@@ -608,13 +631,17 @@ static int mxsfb_restore_mode(struct mxsfb_info *host,
unsigned line_count;
unsigned period;
unsigned long pa, fbsize;
- int bits_per_pixel, ofs;
+ int bits_per_pixel, ofs, ret = 0;
u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
+ mxsfb_enable_axi_clk(host);
+
/* Only restore the mode when the controller is running */
ctrl = readl(host-base + LCDC_CTRL);
- if (!(ctrl CTRL_RUN))
- return -EINVAL;
+ if (!(ctrl CTRL_RUN)) {
+ ret = -EINVAL;
+ goto err;
+ }
vdctrl0 = readl(host-base + LCDC_VDCTRL0);
vdctrl2 = readl(host-base + LCDC_VDCTRL2
Re: [PATCH RFC v9 09/20] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
Hi Thierry, 2015-03-03 19:07 GMT+08:00 Philipp Zabel p.za...@pengutronix.de: Hi, Am Donnerstag, den 12.02.2015, 14:01 +0800 schrieb Liu Ying: Signed-off-by: Liu Ying ying@freescale.com --- v8-v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository. I can't test this myself for lack of hardware, but I see no further issues with patches 09 - 13 except for the use of imx_drm_encoder_get_mux_id. I'll either rebase my patches that remove it or fix it up when applying. Thierry, may I take these patches through imx-drm, or would you rather I waited for you to pick up the drm/dsi and drm/bridge patches? Gentle ping. What's your opinion on the patches Philipp mentioned? Regards, Liu Ying regards Philipp ___ dri-devel mailing list dri-de...@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel -- Best Regards, Liu Ying -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2] video: mxsfb: Make sure axi clock is enabled when accessing registers
2015-03-20 19:26 GMT+08:00 Tomi Valkeinen tomi.valkei...@ti.com: On 11/03/15 05:03, Liu Ying wrote: Why do you check for host-enabled here, but not elsewhere? We need this check here to make sure the axi clock reference count is no greater than 1. Looking at the context of mxsfb_set_par(), mxsfb_restore_mode() and Why is that? The clock framework handles ref counting for you. All the driver needs to take care of is to call as many times disable as it calls enable. Okay. I'll remove the check and send another version. Regards, Liu Ying Tomi -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4] video: mxsfb: Make sure axi clock is enabled when accessing registers
The LCDIF engines embedded in i.MX6sl and i.MX6sx SoCs need the axi clock
as the engine's system clock. The clock should be enabled when accessing
LCDIF registers, otherwise the kernel would hang up. We should also keep
the clock enabled when the engine is being active to scan out frames from
memory. This patch makes sure the axi clock is enabled when accessing
registers so that the kernel hang up issue can be fixed.
Reported-by: Peter Chen peter.c...@freescale.com
Tested-by: Peter Chen peter.c...@freescale.com
Cc: sta...@vger.kernel.org # 3.19+
Signed-off-by: Liu Ying ying@freescale.com
---
v3-v4:
* To address Tomi's comment, enable/disable the axi clock in
mxsfb_pan_display() directly instead of checking the host-enabled flag.
v2-v3:
* To address Tomi's comment, improve the commit message only.
v1-v2:
* Add 'Tested-by: Peter Chen peter.c...@freescale.com' tag.
* Add 'Cc: sta...@vger.kernel.org # 3.19+' tag.
drivers/video/fbdev/mxsfb.c | 68 +++--
1 file changed, 54 insertions(+), 14 deletions(-)
diff --git a/drivers/video/fbdev/mxsfb.c b/drivers/video/fbdev/mxsfb.c
index f8ac4a4..0f64165 100644
--- a/drivers/video/fbdev/mxsfb.c
+++ b/drivers/video/fbdev/mxsfb.c
@@ -316,6 +316,18 @@ static int mxsfb_check_var(struct fb_var_screeninfo *var,
return 0;
}
+static inline void mxsfb_enable_axi_clk(struct mxsfb_info *host)
+{
+ if (host-clk_axi)
+ clk_prepare_enable(host-clk_axi);
+}
+
+static inline void mxsfb_disable_axi_clk(struct mxsfb_info *host)
+{
+ if (host-clk_axi)
+ clk_disable_unprepare(host-clk_axi);
+}
+
static void mxsfb_enable_controller(struct fb_info *fb_info)
{
struct mxsfb_info *host = to_imxfb_host(fb_info);
@@ -333,14 +345,13 @@ static void mxsfb_enable_controller(struct fb_info
*fb_info)
}
}
- if (host-clk_axi)
- clk_prepare_enable(host-clk_axi);
-
if (host-clk_disp_axi)
clk_prepare_enable(host-clk_disp_axi);
clk_prepare_enable(host-clk);
clk_set_rate(host-clk, PICOS2KHZ(fb_info-var.pixclock) * 1000U);
+ mxsfb_enable_axi_clk(host);
+
/* if it was disabled, re-enable the mode again */
writel(CTRL_DOTCLK_MODE, host-base + LCDC_CTRL + REG_SET);
@@ -380,11 +391,11 @@ static void mxsfb_disable_controller(struct fb_info
*fb_info)
reg = readl(host-base + LCDC_VDCTRL4);
writel(reg ~VDCTRL4_SYNC_SIGNALS_ON, host-base + LCDC_VDCTRL4);
+ mxsfb_disable_axi_clk(host);
+
clk_disable_unprepare(host-clk);
if (host-clk_disp_axi)
clk_disable_unprepare(host-clk_disp_axi);
- if (host-clk_axi)
- clk_disable_unprepare(host-clk_axi);
host-enabled = 0;
@@ -421,6 +432,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
mxsfb_disable_controller(fb_info);
}
+ mxsfb_enable_axi_clk(host);
+
/* clear the FIFOs */
writel(CTRL1_FIFO_CLEAR, host-base + LCDC_CTRL1 + REG_SET);
@@ -438,6 +451,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
ctrl |= CTRL_SET_WORD_LENGTH(3);
switch (host-ld_intf_width) {
case STMLCDIF_8BIT:
+ mxsfb_disable_axi_clk(host);
dev_err(host-pdev-dev,
Unsupported LCD bus width mapping\n);
return -EINVAL;
@@ -451,6 +465,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
writel(CTRL1_SET_BYTE_PACKAGING(0x7), host-base + LCDC_CTRL1);
break;
default:
+ mxsfb_disable_axi_clk(host);
dev_err(host-pdev-dev, Unhandled color depth of %u\n,
fb_info-var.bits_per_pixel);
return -EINVAL;
@@ -504,6 +519,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
fb_info-fix.line_length * fb_info-var.yoffset,
host-base + host-devdata-next_buf);
+ mxsfb_disable_axi_clk(host);
+
if (reenable)
mxsfb_enable_controller(fb_info);
@@ -582,10 +599,14 @@ static int mxsfb_pan_display(struct fb_var_screeninfo
*var,
offset = fb_info-fix.line_length * var-yoffset;
+ mxsfb_enable_axi_clk(host);
+
/* update on next VSYNC */
writel(fb_info-fix.smem_start + offset,
host-base + host-devdata-next_buf);
+ mxsfb_disable_axi_clk(host);
+
return 0;
}
@@ -608,13 +629,17 @@ static int mxsfb_restore_mode(struct mxsfb_info *host,
unsigned line_count;
unsigned period;
unsigned long pa, fbsize;
- int bits_per_pixel, ofs;
+ int bits_per_pixel, ofs, ret = 0;
u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
+ mxsfb_enable_axi_clk(host);
+
/* Only restore the mode when
Re: [PATCH RFC v9.5 09/20] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
2015-05-12 21:36 GMT+08:00 Thierry Reding thierry.red...@gmail.com: On Fri, Feb 13, 2015 at 01:25:19PM +0800, Liu Ying wrote: Signed-off-by: Liu Ying ying@freescale.com This could use a commit message. Describe for example why this is useful or when to use it. Ok, I'll add it in the next version. --- v9-v9.5: * Add kernel-doc for the new helper function to address Daniel Vetter's comment. v8-v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository. v7-v8: * None. v6-v7: * None. v5-v6: * Address the over 80 characters in one line warning reported by the checkpatch.pl script. v4-v5: * None. v3-v4: * None. v2-v3: * None. v1-v2: * Thierry Reding suggested that the mipi_dsi_pixel_format_to_bpp() function could be placed at the common DRM MIPI DSI driver. This patch is newly added. include/drm/drm_mipi_dsi.h | 22 ++ 1 file changed, 22 insertions(+) diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index f1d8d0d..cabc910 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -163,6 +163,28 @@ static inline struct mipi_dsi_device *to_mipi_dsi_device(struct device *dev) return container_of(dev, struct mipi_dsi_device, dev); } +/** + * mipi_dsi_pixel_format_to_bpp() - get bits per pixel for a mipi dsi + *pixel format + * @fmt: mipi dsi pixel format + * + * Return: The bits per pixel value for the mipi dsi pixel format on success or + *a negative error code on failure. + */ s/mipi dsi/MIPI DSI/, please. Ok. Thanks, Liu Ying Thierry ___ dri-devel mailing list dri-de...@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel -- Best Regards, Liu Ying -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9.5.1 09/20] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
This patch adds a helper to get bits per pixel value of MIPI DSI pixel format.
The helper takes a parameter in the type 'enum mipi_dsi_pixel_format' and
returns it's bits per pixel value if the parameter is valid, otherwise, it
returns -EINVAL. The helper makes users' life easier to do the conversion
from a specific MIPI DSI pixel format to it's bits per pixel value.
Signed-off-by: Liu Ying ying@freescale.com
---
v9.5-v9.5.1:
* To address Thierry Reding's comments, add a commit message to describe why
the helper is useful and when to use it and fix typo in kernel-doc from
'mipi dsi' to 'MIPI DSI'.
v9-v9.5:
* Add kernel-doc for the new helper function to address Daniel Vetter's
comment.
v8-v9:
* Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository.
v7-v8:
* None.
v6-v7:
* None.
v5-v6:
* Address the over 80 characters in one line warning reported by the
checkpatch.pl script.
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* None.
v1-v2:
* Thierry Reding suggested that the mipi_dsi_pixel_format_to_bpp() function
could be placed at the common DRM MIPI DSI driver.
This patch is newly added.
include/drm/drm_mipi_dsi.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..186b15b 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -163,6 +163,28 @@ static inline struct mipi_dsi_device
*to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
+/**
+ * mipi_dsi_pixel_format_to_bpp() - get bits per pixel for a MIPI DSI
+ *pixel format
+ * @fmt: MIPI DSI pixel format
+ *
+ * Return: The bits per pixel value for the MIPI DSI pixel format on success or
+ *a negative error code on failure.
+ */
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
+{
+ switch (fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ case MIPI_DSI_FMT_RGB666:
+ return 24;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ return 18;
+ case MIPI_DSI_FMT_RGB565:
+ return 16;
+ }
+ return -EINVAL;
+}
+
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node
*np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
--
1.9.1
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Re: [PATCH 2/2] drm/imx: Remove the primary plane created by create_primary_plane()
On Mon, Nov 16, 2015 at 05:00:21PM +0100, Daniel Vetter wrote:
> On Wed, Nov 04, 2015 at 06:15:58PM +0800, Liu Ying wrote:
> > Since we are using ipu_plane_init() to add one primary plane for each
> > IPU CRTC, it's unnecessary to create the safe one by using the helper
> > create_primary_plane().
> >
> > Furthermore, the safe one is attached to crtc->primary, which actually
> > carries a framebuffer(crtc->primary->fb) created by the fbdev helper to
> > build up the fbcon. Instead, the one created by ipu_plane_init() is
> > dangling, but it is the one actually does ipu_plane_mode_set() for the
> > fbcon. This may causes the mismatch bewteen ipu_plane->enabled(true) and
> > ipu_plane->base.fb(NULL). Thus, it brings a NULL pointer dereference
> > issue in ipu_plane_mode_set() when we try to additionally touch the
> > IDMAC channel of the ipu_plane. This issue could be reproduced by
> > running the drm modetest with command line 'modetest -P 19:1024x768@XR24'
> > on the i.MX6Q SabreSD platform(single LVDS display). This patch binds
> > the plane created by ipu_plane_init() with crtc->primary and removes the
> > safe one to address this issue.
> >
> > Signed-off-by: Liu Ying <ying@freescale.com>
> > ---
> > drivers/gpu/drm/imx/imx-drm-core.c | 3 ++-
> > drivers/gpu/drm/imx/ipuv3-crtc.c | 6 ++
> > 2 files changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/imx/imx-drm-core.c
> > b/drivers/gpu/drm/imx/imx-drm-core.c
> > index 6faa735..08eceeb 100644
> > --- a/drivers/gpu/drm/imx/imx-drm-core.c
> > +++ b/drivers/gpu/drm/imx/imx-drm-core.c
> > @@ -373,7 +373,8 @@ int imx_drm_add_crtc(struct drm_device *drm, struct
> > drm_crtc *crtc,
> > drm_crtc_helper_add(crtc,
> > imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs);
> >
> > - drm_crtc_init(drm, crtc,
> > + /* The related primary plane will be created in ipu_plane_init(). */
> > + drm_crtc_init_with_planes(drm, crtc, NULL, NULL,
> > imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs);
> >
> > return 0;
> > diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c
> > b/drivers/gpu/drm/imx/ipuv3-crtc.c
> > index 8d68697..d27143f 100644
> > --- a/drivers/gpu/drm/imx/ipuv3-crtc.c
> > +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
> > @@ -343,6 +343,11 @@ err_out:
> > return ret;
> > }
> >
> > +static inline void ipu_crtc_set_primary_plane(struct ipu_crtc *ipu_crtc)
> > +{
> > + ipu_crtc->base.primary = _crtc->plane[0]->base;
>
> This is quite a hack. Better would be to reorg the code so that when you
> call drm_crtc_init_with_planes the primary plane has been created already.
> -Daniel
Thanks for your comments.
Philipp has generated a patch[1] to address this.
I acked it conditionally.
[1] http://www.spinics.net/lists/dri-devel/msg93700.html
Regards,
Liu Ying
>
> > +}
> > +
> > static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
> > struct ipu_client_platformdata *pdata, struct drm_device *drm)
> > {
> > @@ -380,6 +385,7 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
> > ret);
> > goto err_remove_crtc;
> > }
> > + ipu_crtc_set_primary_plane(ipu_crtc);
> >
> > /* If this crtc is using the DP, add an overlay plane */
> > if (pdata->dp >= 0 && pdata->dma[1] > 0) {
> > --
> > 2.5.0
> >
> > ___
> > dri-devel mailing list
> > dri-de...@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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Re: [PATCH 1/2] drm/imx: ipuv3-crtc: Return error if ipu_plane_init() fails for primary plane
On Fri, Nov 06, 2015 at 11:05:54AM +0100, Philipp Zabel wrote:
> Hi Liu,
>
> Am Mittwoch, den 04.11.2015, 18:15 +0800 schrieb Liu Ying:
> > For primary plane initialization failure cases, ipu_plane_init() may return
> > a pointer encoded by ERR_PTR(). So, we should bailout instead of use that
> > pointer blindly.
> >
> > Signed-off-by: Liu Ying <ying@freescale.com>
> > ---
> > drivers/gpu/drm/imx/ipuv3-crtc.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c
> > b/drivers/gpu/drm/imx/ipuv3-crtc.c
> > index 7bc8301..8d68697 100644
> > --- a/drivers/gpu/drm/imx/ipuv3-crtc.c
> > +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
> > @@ -370,6 +370,10 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
> > id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
> > ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev, ipu,
> > pdata->dma[0], dp, BIT(id), true);
> > + if (IS_ERR(ipu_crtc->plane[0])) {
> > + ret = PTR_ERR(ipu_crtc->plane[0]);
> > + goto err_put_resources;
>
> That should be "goto err_remove_crtc;"
Ah, yes, you're right. I'll fix this.
BTW, there is nothing to free the ipu_plane allocated in ipu_plane_init() in
case something goes wrong after ipu_plane_init(). Of course, we may fix this
with another patch.
Thanks,
Liu Ying
>
> regards
> Philipp
>
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Re: [PATCH 2/2] drm/imx: Remove the primary plane created by create_primary_plane()
On Fri, Nov 06, 2015 at 11:05:48AM +0100, Philipp Zabel wrote: > Am Mittwoch, den 04.11.2015, 18:15 +0800 schrieb Liu Ying: > > Since we are using ipu_plane_init() to add one primary plane for each > > IPU CRTC, it's unnecessary to create the safe one by using the helper > > create_primary_plane(). > > > > Furthermore, the safe one is attached to crtc->primary, which actually > > carries a framebuffer(crtc->primary->fb) created by the fbdev helper to > > build up the fbcon. Instead, the one created by ipu_plane_init() is > > dangling, but it is the one actually does ipu_plane_mode_set() for the > > fbcon. This may causes the mismatch bewteen ipu_plane->enabled(true) and > > ipu_plane->base.fb(NULL). Thus, it brings a NULL pointer dereference > > issue in ipu_plane_mode_set() when we try to additionally touch the > > IDMAC channel of the ipu_plane. This issue could be reproduced by > > running the drm modetest with command line 'modetest -P 19:1024x768@XR24' > > on the i.MX6Q SabreSD platform(single LVDS display). This patch binds > > the plane created by ipu_plane_init() with crtc->primary and removes the > > safe one to address this issue. > > > > Signed-off-by: Liu Ying <ying@freescale.com> > > --- > > drivers/gpu/drm/imx/imx-drm-core.c | 3 ++- > > drivers/gpu/drm/imx/ipuv3-crtc.c | 6 ++ > > 2 files changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/imx/imx-drm-core.c > > b/drivers/gpu/drm/imx/imx-drm-core.c > > index 6faa735..08eceeb 100644 > > --- a/drivers/gpu/drm/imx/imx-drm-core.c > > +++ b/drivers/gpu/drm/imx/imx-drm-core.c > > @@ -373,7 +373,8 @@ int imx_drm_add_crtc(struct drm_device *drm, struct > > drm_crtc *crtc, > > drm_crtc_helper_add(crtc, > > imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs); > > > > - drm_crtc_init(drm, crtc, > > + /* The related primary plane will be created in ipu_plane_init(). */ > > + drm_crtc_init_with_planes(drm, crtc, NULL, NULL, > > imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs); > > We rather should generate the plane first and add the primary_plane > parameter to imx_drm_add_crtc than calling drm_crtc_init_with_planes > without planes. Yes, that is the regular way. I thought about that, though I took the easy approach here. The question is that we currently generate the crtc pipe number in imx_drm_add_crtc() first, and then pass it to ipu_plane_init(). Do you think it would be good to add OF alias id for IPU, pass the id to ipu_crtc_init() via struct ipu_soc and determine the pipe number in ipu_crtc_init() by using the IPU id and pdata->di? This way, ipu_plane_init() may know the pipe number in the first place. Or, any other suggestions? Regards, Liu Ying > > regards > Philipp > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2] drm/imx: ipuv3-crtc: Return error if ipu_plane_init() fails for primary plane
For primary plane initialization failure cases, ipu_plane_init() may return
a pointer encoded by ERR_PTR(). So, we should bailout instead of using that
pointer blindly.
Signed-off-by: Liu Ying <ying@freescale.com>
---
v1->v2:
* Trivial commit message fix.
* Rebase onto Phillip's patch[1].
[1] http://www.spinics.net/lists/dri-devel/msg93700.html
drivers/gpu/drm/imx/ipuv3-crtc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c
index 872183a..35a77e5 100644
--- a/drivers/gpu/drm/imx/ipuv3-crtc.c
+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
@@ -361,6 +361,10 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
dp = IPU_DP_FLOW_SYNC_BG;
ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
DRM_PLANE_TYPE_PRIMARY);
+ if (IS_ERR(ipu_crtc->plane[0])) {
+ ret = PTR_ERR(ipu_crtc->plane[0]);
+ goto err_put_resources;
+ }
ret = imx_drm_add_crtc(drm, _crtc->base, _crtc->imx_crtc,
_crtc->plane[0]->base, _crtc_helper_funcs,
--
2.5.0
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[PATCH 2/2] drm/imx: Remove the primary plane created by create_primary_plane()
Since we are using ipu_plane_init() to add one primary plane for each
IPU CRTC, it's unnecessary to create the safe one by using the helper
create_primary_plane().
Furthermore, the safe one is attached to crtc->primary, which actually
carries a framebuffer(crtc->primary->fb) created by the fbdev helper to
build up the fbcon. Instead, the one created by ipu_plane_init() is
dangling, but it is the one actually does ipu_plane_mode_set() for the
fbcon. This may causes the mismatch bewteen ipu_plane->enabled(true) and
ipu_plane->base.fb(NULL). Thus, it brings a NULL pointer dereference
issue in ipu_plane_mode_set() when we try to additionally touch the
IDMAC channel of the ipu_plane. This issue could be reproduced by
running the drm modetest with command line 'modetest -P 19:1024x768@XR24'
on the i.MX6Q SabreSD platform(single LVDS display). This patch binds
the plane created by ipu_plane_init() with crtc->primary and removes the
safe one to address this issue.
Signed-off-by: Liu Ying <ying@freescale.com>
---
drivers/gpu/drm/imx/imx-drm-core.c | 3 ++-
drivers/gpu/drm/imx/ipuv3-crtc.c | 6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c
b/drivers/gpu/drm/imx/imx-drm-core.c
index 6faa735..08eceeb 100644
--- a/drivers/gpu/drm/imx/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/imx-drm-core.c
@@ -373,7 +373,8 @@ int imx_drm_add_crtc(struct drm_device *drm, struct
drm_crtc *crtc,
drm_crtc_helper_add(crtc,
imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs);
- drm_crtc_init(drm, crtc,
+ /* The related primary plane will be created in ipu_plane_init(). */
+ drm_crtc_init_with_planes(drm, crtc, NULL, NULL,
imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs);
return 0;
diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c
index 8d68697..d27143f 100644
--- a/drivers/gpu/drm/imx/ipuv3-crtc.c
+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
@@ -343,6 +343,11 @@ err_out:
return ret;
}
+static inline void ipu_crtc_set_primary_plane(struct ipu_crtc *ipu_crtc)
+{
+ ipu_crtc->base.primary = _crtc->plane[0]->base;
+}
+
static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
@@ -380,6 +385,7 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
ret);
goto err_remove_crtc;
}
+ ipu_crtc_set_primary_plane(ipu_crtc);
/* If this crtc is using the DP, add an overlay plane */
if (pdata->dp >= 0 && pdata->dma[1] > 0) {
--
2.5.0
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[PATCH 1/2] drm/imx: ipuv3-crtc: Return error if ipu_plane_init() fails for primary plane
For primary plane initialization failure cases, ipu_plane_init() may return
a pointer encoded by ERR_PTR(). So, we should bailout instead of use that
pointer blindly.
Signed-off-by: Liu Ying <ying@freescale.com>
---
drivers/gpu/drm/imx/ipuv3-crtc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c
index 7bc8301..8d68697 100644
--- a/drivers/gpu/drm/imx/ipuv3-crtc.c
+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
@@ -370,6 +370,10 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev, ipu,
pdata->dma[0], dp, BIT(id), true);
+ if (IS_ERR(ipu_crtc->plane[0])) {
+ ret = PTR_ERR(ipu_crtc->plane[0]);
+ goto err_put_resources;
+ }
ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
if (ret) {
dev_err(ipu_crtc->dev, "getting plane 0 resources failed with
%d.\n",
--
2.5.0
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[PATCH] drvres: Improve grp->id setting logics in devres_open_group()
Instead of setting grp->id directly with a temporary value and then changing it if a certain condition meets, we may check the condition first and then decide which value should be set to grp->id. This may save two lines of code and potentially reduces a writing operation. Signed-off-by: Liu Ying --- drivers/base/devres.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/base/devres.c b/drivers/base/devres.c index c8a53d1..39e1856 100644 --- a/drivers/base/devres.c +++ b/drivers/base/devres.c @@ -544,9 +544,7 @@ void * devres_open_group(struct device *dev, void *id, gfp_t gfp) INIT_LIST_HEAD(>node[1].entry); set_node_dbginfo(>node[0], "grp<", 0); set_node_dbginfo(>node[1], "grp>", 0); - grp->id = grp; - if (id) - grp->id = id; + grp->id = id ? id : grp; spin_lock_irqsave(>devres_lock, flags); add_dr(dev, >node[0]); -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2] devres: Improve grp->id setting logics in devres_open_group()
Instead of setting grp->id directly with a temporary value and then changing it if a certain condition meets, we may check the condition first and then decide which value should be set to grp->id. This may save two lines of code and potentially reduces a writing operation. Signed-off-by: Liu Ying --- v1->v2: * Fix a typo in the commit head line. drivers/base/devres.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/base/devres.c b/drivers/base/devres.c index c8a53d1..39e1856 100644 --- a/drivers/base/devres.c +++ b/drivers/base/devres.c @@ -544,9 +544,7 @@ void * devres_open_group(struct device *dev, void *id, gfp_t gfp) INIT_LIST_HEAD(>node[1].entry); set_node_dbginfo(>node[0], "grp<", 0); set_node_dbginfo(>node[1], "grp>", 0); - grp->id = grp; - if (id) - grp->id = id; + grp->id = id ? id : grp; spin_lock_irqsave(>devres_lock, flags); add_dr(dev, >node[0]); -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v18 0/12] dw-hdmi: convert imx hdmi to bridge/dw_hdmi
. Please fix this. drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c:243:1: error: ‘__mod_of__dw_hdmi_rockchip_dt_ids_device_table’ aliased to undefined symbol ‘dw_hdmi_rockchip_dt_ids’ scripts/Makefile.build:257: recipe for target 'drivers/gpu/drm/rockchip/dw_hdmi-rockchip.o' failed make[4]: *** [drivers/gpu/drm/rockchip/dw_hdmi-rockchip.o] Error 1 scripts/Makefile.build:402: recipe for target 'drivers/gpu/drm/rockchip' failed make[3]: *** [drivers/gpu/drm/rockchip] Error 2 scripts/Makefile.build:402: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:402: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:937: recipe for target 'drivers' failed make: *** [drivers] Error 2 Regards, Liu Ying -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: imx_v6_v7_defconfig: Select CONFIG_FB_MXS
2015-01-08 7:35 GMT+08:00 Fabio Estevam : > From: Fabio Estevam > > CONFIG_FB_MXS is the LCD driver for mx6solo-lite and mx6solox. > > Enable it by default. I'm not sure if it is suitable to enable CONFIG_FB_MXS by default. At least, I have no strong objections. I am considering to add a LCDIF CRTC driver to the imx-drm framework so that we may use the existing LDB drm driver to support the mx6solox LVDS interface. I see the i915 and omap2 fb drivers depend on !DRM_: grep DRM_ drivers/video/fbdev/ -nr drivers/video/fbdev/omap2/omapfb/Kconfig:3:depends on FB && OMAP2_DSS && !DRM_OMAP drivers/video/fbdev/Kconfig:1197: depends on !DRM_I915 So, similarly, we'll probably have two LCDIF drivers and make the DRM one enabled by default - finally, CONFIG_FB_MXS is disabled. Another concern is the compatibility. Since both the framebuffer driver and the imx-drm driver would export the framebuffer interface to the user space, we'd better to keep the interface behavior the same. Maybe, this is not a big problem, because we need to keep the compatibility anyway... Regards, Liu Ying > > Signed-off-by: Fabio Estevam > --- > arch/arm/configs/imx_v6_v7_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/configs/imx_v6_v7_defconfig > b/arch/arm/configs/imx_v6_v7_defconfig > index 9575af8..1f36977 100644 > --- a/arch/arm/configs/imx_v6_v7_defconfig > +++ b/arch/arm/configs/imx_v6_v7_defconfig > @@ -203,6 +203,7 @@ CONFIG_DRM_PANEL_SIMPLE=y > CONFIG_LCD_CLASS_DEVICE=y > CONFIG_LCD_L4F00242T03=y > CONFIG_LCD_PLATFORM=y > +CONFIG_FB_MXS=y > CONFIG_BACKLIGHT_PWM=y > CONFIG_BACKLIGHT_GPIO=y > CONFIG_FRAMEBUFFER_CONSOLE=y > -- > 1.9.1 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ -- Best Regards, Liu Ying -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 09/15] drm: imx: Add MIPI DSI host controller driver
Hi Thierry, Sorry for the late response. I tried to address almost all your comments locally first. More feedback below. On 12/10/2014 09:16 PM, Thierry Reding wrote: On Wed, Dec 10, 2014 at 04:37:22PM +0800, Liu Ying wrote: This patch adds i.MX MIPI DSI host controller driver support. Currently, the driver supports the burst with sync pulses mode only. Signed-off-by: Liu Ying --- .../devicetree/bindings/drm/imx/mipi_dsi.txt | 81 ++ drivers/gpu/drm/imx/Kconfig|6 + drivers/gpu/drm/imx/Makefile |1 + drivers/gpu/drm/imx/imx-mipi-dsi.c | 1017 4 files changed, 1105 insertions(+) create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt create mode 100644 drivers/gpu/drm/imx/imx-mipi-dsi.c diff --git a/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt new file mode 100644 index 000..3d07fd7 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt @@ -0,0 +1,81 @@ +Device-Tree bindings for MIPI DSI host controller + +MIPI DSI host controller + + +The MIPI DSI host controller is a Synopsys DesignWare IP. +It is a digital core that implements all protocol functions defined +in the MIPI DSI specification, providing an interface between the +system and the MIPI DPHY, and allowing communication with a MIPI DSI +compliant display. + +Required properties: + - #address-cells : Should be <1>. + - #size-cells : Should be <0>. + - compatible : Should be "fsl,imx6q-mipi-dsi" for i.MX6q/sdl SoCs. + - reg : Physical base address of the controller and length of memory + mapped region. + - interrupts : The controller's interrupt number to the CPU(s). + - gpr : Should be <>. + The phandle points to the iomuxc-gpr region containing the + multiplexer control register for the controller. Side-note: Shouldn't this really be a pinmux, then? No. The muxing is inside the i.MX SoC. There is a DT binding documentation for the system controller node(gpr) at [1]. And, for i.MX DT sources, there are several existing use cases in which the gpr node is referred by other nodes. [1] Documentation/devicetree/bindings/mfd/syscon.txt. + - clocks, clock-names : Phandles to the controller pllref, pllref_gate + and core_cfg clocks, as described in [1] and [2]. + - panel@0 : A panel node which contains a display-timings child node as + defined in [3]. There's no need for these to be named panel@*. They could be bridges for example. And no, they shouldn't contain a display-timings child node either. Panels should have a proper driver and the driver being device specific it should have the timings embedded. Ok, I'll move the timing to the panel driver. + - port@[0-4] : Up to four port nodes with endpoint definitions as defined + in [4], corresponding to the four inputs to the controller multiplexer. + Note that each port node should contain the input-port property to + distinguish it from the panel node, as described in [5]. [4] says that you can group all port nodes under a ports parent node. I think this is really what you want to do here to make it clear that the ports aren't part of the DSI host binding part of the device. Accepted. diff --git a/drivers/gpu/drm/imx/imx-mipi-dsi.c b/drivers/gpu/drm/imx/imx-mipi-dsi.c [...] +/* + * i.MX drm driver - MIPI DSI Host Controller + * + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include Don't you want the more generic linux/math64.h here? I'll use linux/math64.h. +#include +#include +#include I don't see any of the functions defined in that header used here. I'll remove this. +#include +#include +#include +#include +#include + +#include "imx-drm.h" + +#define DRIVER_NAME"imx-mipi-dsi" + +#defineDSI_VERSION 0x00 + +#defineDSI_PWR_UP 0x04 +#defineRESET 0 +#definePOWERUP BIT(0) + +#defineDSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) &am
Re: [PATCH RFC 10/15] drm: panel: Add support for Himax HX8369A MIPI DSI panel
On 12/10/2014 10:03 PM, Thierry Reding wrote:
On Wed, Dec 10, 2014 at 04:37:23PM +0800, Liu Ying wrote:
This patch adds support for Himax HX8369A MIPI DSI panel.
Signed-off-by: Liu Ying
---
.../devicetree/bindings/panel/himax,hx8369a.txt| 86 +++
drivers/gpu/drm/panel/Kconfig | 6 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-hx8369a.c | 627 +
4 files changed, 720 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/himax,hx8369a.txt
create mode 100644 drivers/gpu/drm/panel/panel-hx8369a.c
diff --git a/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
b/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
new file mode 100644
index 000..6fe251e
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
@@ -0,0 +1,86 @@
+Himax HX8369A WVGA 16.7M color TFT single chip driver with internal GRAM
+
+Himax HX8369A is a WVGA resolution driving controller.
+It is designed to provide a single chip solution that combines a source
+driver and power supply circuits to drive a TFT dot matrix LCD with
+480RGBx864 dots at the maximum.
+
+The HX8369A supports several interface modes, including MPU MIPI DBI Type
+A/B mode, MIPI DPI/DBI Type C mode, MIPI DSI video mode, MIPI DSI command
+mode and MDDI mode. The interface mode is selected by the external hardware
+pins BS[3:0].
+
+Currently, only the MIPI DSI video mode is supported.
+
+Required properties:
+ - compatible: "himax,hx8369a-dsi"
+ - reg: the virtual channel number of a DSI peripheral
+ - reset-gpios: a GPIO spec for the reset pin
+ - data-lanes: the data lane number of a DSI peripheral
This is implied by the compatible already.
Accepted.
+ - display-timings: timings for the connected panel as described by [1]
Also implied by the compatible value.
Accepted.
+ - bs: the interface mode number described by the following table
+--
+ | DBI_TYPE_A_8BIT | 0 |
+ | DBI_TYPE_A_9BIT | 1 |
+ | DBI_TYPE_A_16BIT| 2 |
+ | DBI_TYPE_A_18BIT| 3 |
+ | DBI_TYPE_B_8BIT | 4 |
+ | DBI_TYPE_B_9BIT | 5 |
+ | DBI_TYPE_B_16BIT| 6 |
+ | DBI_TYPE_B_18BIT| 7 |
+ | DSI_CMD_MODE| 8 |
+ | DBI_TYPE_B_24BIT| 9 |
+ | DSI_VIDEO_MODE | 10 |
+ | MDDI| 11 |
+ | DPI_DBI_TYPE_C_OPT1 | 12 |
+ | DPI_DBI_TYPE_C_OPT2 | 13 |
+ | DPI_DBI_TYPE_C_OPT3 | 14 |
+--
Can this not be inferred by the driver? If it's a DSI driver can't it
select between DSI_VIDEO_MODE or DSI_CMD_MODE based on its capabilities?
That is, if the panel driver can setup command mode, shouldn't it be
using command mode in that case? And use DSI_VIDEO_MODE otherwise?
I may remove this property.
But, I choose not to add any logic in the host and slave drivers to
handle the interface mode selection at present, since I only support
the DSI_VIDEO_MODE now. Is this acceptable?
+Optional properties:
+ - power-on-delay: delay after turning regulators on [ms]
+ - reset-delay: delay after reset sequence [ms]
Surely these are constant for this panel?
Accepted.
+ - panel-width-mm: physical panel width [mm]
+ - panel-height-mm: physical panel height [mm]
These are also implied by compatible.
Accepted.
+Example:
+ panel@0 {
+ compatible = "himax,hx8369a-dsi";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_mipi_panel>;
+ reset-gpios = < 11 GPIO_ACTIVE_LOW>;
+ reset-delay = <120>;
+ bs2-gpios = < 14 GPIO_ACTIVE_HIGH>;
+ data-lanes = <2>;
+ panel-width-mm = <45>;
+ panel-height-mm = <76>;
+ bs = <10>;
+ status = "okay";
status = "okay" is the default, so it probably shouldn't be in this
example.
Accepted.
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 024e98e..f1a5b58 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -40,4 +40,10 @@ config DRM_PANEL_SHARP_LQ101R1SX01
To compile this driver as a module, choose M here: the module
will be called panel-sharp-lq101r1sx01.
+config DRM_PANEL_HX8369A
+ tristate "HX8369A panel"
+ depends on OF
+ select DRM_MIPI_DSI
+ select VIDEOMODE_HELPERS
+
This should be sorted alphabetically. I think it would also be a good
idea to use a HIMAX prefix here, just to reduce the potential for name
clashes.
Accepted.
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 4b2a043..d6768ca 100644
--- a/drivers/gpu/drm/panel/Ma
Re: [PATCH RFC 09/15] drm: imx: Add MIPI DSI host controller driver
Hi Russell,
On 12/17/2014 06:40 PM, Russell King - ARM Linux wrote:
On Wed, Dec 17, 2014 at 05:44:33PM +0800, Liu Ying wrote:
Hi Thierry,
Sorry for the late response.
I tried to address almost all your comments locally first.
More feedback below.
On 12/10/2014 09:16 PM, Thierry Reding wrote:
On Wed, Dec 10, 2014 at 04:37:22PM +0800, Liu Ying wrote:
+static int check_status(struct imx_mipi_dsi *dsi, u32 reg, u32 status,
+ int timeout, bool to_set)
+{
+ u32 val;
+ bool out = false;
+
+ val = dsi_read(dsi, reg);
+ for (;;) {
+ out = to_set ? (val & status) : !(val & status);
+ if (out)
+ break;
+
+ if (!timeout--)
+ return -EFAULT;
+
+ msleep(1);
+ val = dsi_read(dsi, reg);
+ }
+ return 0;
+}
You should probably use a properly timed loop here. msleep() isn't
guaranteed to return after exactly one millisecond, so your timeout is
never going to be accurate. Something like the following would be better
in my opinion:
timeout = jiffies + msecs_to_jiffies(timeout);
while (time_before(jiffies, timeout)) {
...
}
Also timeout should be unsigned long in that case.
Accepted.
Actually, that's a bad example: what we want to do is to assess success
after we wait, before we decide that something has failed. In other
words, we don't want to wait, and decide that we failed without first
checking for success.
In any case, returning -EFAULT is not sane: EFAULT doesn't mean "fault"
it means "Bad address", and it is returned to userspace to mean that
userspace passed the kernel a bad address. That definition does /not/
fit what's going on here.
timeout = jiffies + msecs_to_jiffies(timeout);
do {
val = dsi_read(dsi, reg);
out = to_set ? (val & status) : !(val & status);
if (out)
break;
if (time_is_after_jiffies(timeout))
time_is_after_jiffies(a) is defined as time_before(jiffies, a).
So, this line should be changed to
if (time_after(jiffies, timeout))
Right?
return -ETIMEDOUT;
msleep(1);
} while (1);
return 0;
would be better: we only fail immediately after we have checked whether
we succeeded, and we also do the first check immediately.
Does this one look better? I use cpu_relax() instead of msleep(1).
expire = jiffies + msecs_to_jiffies(timeout);
for (;;) {
val = dsi_read(dsi, reg);
out = to_set ? (val & status) : !(val & status);
if (out)
break;
if (time_after(jiffies, expire))
return -ETIMEDOUT;
cpu_relax();
}
return 0;
Regards,
Liu Ying
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[PATCH RFC v2 00/14] Add support for i.MX MIPI DSI DRM driver
Hi, This series addressed almost all comments from Thierry Redding and Russell on v1. This series adds support for i.MX MIPI DSI DRM driver. Currently, the MIPI DSI driver only supports the burst with sync pulse mode. This series also includes a DRM panel driver for the Truly TFT480800-16-E panel which is driven by the Himax HX8369A driver IC. The driver IC data sheet could be found at [1]. As mentioned by the data sheet, the driver IC supports several interface modes. Currently, the DRM panel driver only supports the MIPI DSI video mode. New interface modes could be added later(perhaps, just like the way the DRM simple panel driver supports both MIPI DSI interface panels and simple(parallel) interface panels). The MIPI DSI feature is tested on i.MX6Q SabreSD board and i.MX6DL SabreSD board. The MIPI DSI display could be enabled directly on i.MX6Q SabreSD board after applying this series, because the 26.4MHz pixel clock the panel requires could be derived from the IPU HSP clock(264MHz) with an integer divider. On i.MX6DL SabreSD board, we need to manually disable the LVDS and HDMI displays in the device tree blob, since the i.MX6DL IPU HSP clock is 198MHz at present, which makes the pixel clock share the PLL5 video clock source with the LVDS and HDMI, thus, the panel cannot get the pixel clock rate it wants. Patch 01/15 is needed to get a precise pixel clock rate(26.4MHz) from the PLL5 video clock. If we don't have this patch, the pixel clock rate is about 20MHz, which causes a horitonal shift on the display image. This series can be applied on the drm-next branch. [1] http://www.allshore.com/pdf/Himax_HX8369-A.pdf Liu Ying (14): clk: divider: Correct parent clk round rate if no bestdiv is normally found of: Add vendor prefix for Himax Technologies Inc. of: Add vendor prefix for Truly Semiconductors Limited ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition ARM: imx6q: clk: Add the video_27m clock ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format drm: imx: Add MIPI DSI host controller driver drm: panel: Add support for Himax HX8369A MIPI DSI panel ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel .../devicetree/bindings/drm/imx/mipi_dsi.txt | 78 ++ .../devicetree/bindings/panel/himax,hx8369a.txt| 41 + .../devicetree/bindings/vendor-prefixes.txt|2 + arch/arm/boot/dts/imx6q.dtsi | 20 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 20 + arch/arm/boot/dts/imx6qdl.dtsi | 30 +- arch/arm/configs/imx_v6_v7_defconfig | 17 +- arch/arm/mach-imx/clk-imx6q.c |1 + drivers/clk/clk-divider.c |3 +- drivers/gpu/drm/imx/Kconfig|6 + drivers/gpu/drm/imx/Makefile |1 + drivers/gpu/drm/imx/imx-mipi-dsi.c | 1056 drivers/gpu/drm/panel/Kconfig |5 + drivers/gpu/drm/panel/Makefile |1 + drivers/gpu/drm/panel/panel-himax-hx8369a.c| 573 +++ include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/imx6qdl-clock.h |3 +- include/linux/mfd/syscon/imx6q-iomuxc-gpr.h|1 + 18 files changed, 1844 insertions(+), 28 deletions(-) create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt create mode 100644 Documentation/devicetree/bindings/panel/himax,hx8369a.txt create mode 100644 drivers/gpu/drm/imx/imx-mipi-dsi.c create mode 100644 drivers/gpu/drm/panel/panel-himax-hx8369a.c -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v2 10/14] ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller
This patch adds support for MIPI DSI host controller.
Signed-off-by: Liu Ying
---
v1->v2:
* None.
arch/arm/boot/dts/imx6qdl.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 96bf2a0..bfc39fd 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1006,7 +1006,14 @@
mipi_dsi: mipi@021e {
#address-cells = <1>;
#size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi";
reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <>;
+ clocks = < IMX6QDL_CLK_VIDEO_27M>,
+< IMX6QDL_CLK_HSI_TX>,
+< IMX6QDL_CLK_HSI_TX>;
+ clock-names = "pllref", "pllref_gate",
"core_cfg";
status = "disabled";
ports {
--
2.1.0
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[PATCH RFC v2 08/14] drm: imx: Add MIPI DSI host controller driver
This patch adds i.MX MIPI DSI host controller driver support.
Currently, the driver supports the burst with sync pulses mode only.
Signed-off-by: Liu Ying
---
v1->v2:
* Address almost all comments from Thierry Reding and Russell.
* Update the DT documentation to remove the display-timings node in the panel
node.
* Update the DT documentation to state that the nodes which represent the
possible
DRM CRTCs the controller may connect with should be placed in the node
"ports".
* Remove the flag 'enabled' from the struct imx_mipi_dsi.
* Move the format_to_bpp() function in v1 to the common DRM MIPI DSI driver.
* Improve the way we wait for check status for DPHY and command packet
transfer.
* Improve the DPMS support for the encoder.
* Split the functions of ->host_attach() and ->mode_valid() clearly as
suggested by
Thierry Reding.
* Improve the logics in imx_mipi_dsi_dcs_long_write().
* Enable/disable the pllref_clk and pllref_gate_clk at the component
binding/unbinding
stages to help remove the flag 'enabled'.
* Update the module license to be "GPL".
* Other minor changes, such as coding style issues and macro naming issues.
.../devicetree/bindings/drm/imx/mipi_dsi.txt | 78 ++
drivers/gpu/drm/imx/Kconfig|6 +
drivers/gpu/drm/imx/Makefile |1 +
drivers/gpu/drm/imx/imx-mipi-dsi.c | 1056
4 files changed, 1141 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
create mode 100644 drivers/gpu/drm/imx/imx-mipi-dsi.c
diff --git a/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
new file mode 100644
index 000..892ed62
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
@@ -0,0 +1,78 @@
+Device-Tree bindings for MIPI DSI host controller
+
+MIPI DSI host controller
+
+
+The MIPI DSI host controller is a Synopsys DesignWare IP.
+It is a digital core that implements all protocol functions defined
+in the MIPI DSI specification, providing an interface between the
+system and the MIPI DPHY, and allowing communication with a MIPI DSI
+compliant display.
+
+Required properties:
+ - #address-cells: Should be <1>.
+ - #size-cells: Should be <0>.
+ - compatible: Should be "fsl,imx6q-mipi-dsi" for i.MX6q/sdl SoCs.
+ - reg: Physical base address of the controller and length of memory
+ mapped region.
+ - interrupts: The controller's interrupt number to the CPU(s).
+ - gpr: Should be <>.
+ The phandle points to the iomuxc-gpr region containing the
+ multiplexer control register for the controller.
+ - clocks, clock-names: Phandles to the controller pllref, pllref_gate
+ and core_cfg clocks, as described in [1] and [2].
+
+Required sub-nodes:
+ - ports: This node may contain up to four port nodes with endpoint
+ definitions as defined in [3], corresponding to the four inputs to
+ the controller multiplexer.
+ - A node to represent a DSI peripheral as described in [4].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/imx6q-clock.txt
+[3] Documentation/devicetree/bindings/media/video-interfaces.txt
+[4] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr@020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi@021e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi";
+ reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <>;
+ clocks = < IMX6QDL_CLK_VIDEO_27M>,
+< IMX6QDL_CLK_HSI_TX>,
+< IMX6QDL_CLK_HSI_TX>;
+ clock-names = "pllref", "pllref_gate", "core_cfg";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ input-port;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <_di0_mipi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ input-port;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <_di1_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ /* ... */
+ };
+ }
[PATCH RFC v2 04/14] ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition
This patch adds a macro to define the GPR3 MIPI muxing control register field shift bits. Signed-off-by: Liu Ying --- v1->v2: * None. include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index ff44374..3b0bed4 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -207,6 +207,7 @@ #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6) #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6) #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6) +#define IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT 4 #define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4) -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v2 07/14] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
Signed-off-by: Liu Ying
---
v1->v2:
* Thierry Reding suggested that the mipi_dsi_pixel_format_to_bpp() function
could be placed at the common DRM MIPI DSI driver.
This patch is newly added.
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..0f5210c 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -163,6 +163,20 @@ static inline struct mipi_dsi_device
*to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format
format)
+{
+ switch (format) {
+ case MIPI_DSI_FMT_RGB888:
+ case MIPI_DSI_FMT_RGB666:
+ return 24;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ return 18;
+ case MIPI_DSI_FMT_RGB565:
+ return 16;
+ }
+ return -EINVAL;
+}
+
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node
*np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
--
2.1.0
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[PATCH RFC v2 05/14] ARM: imx6q: clk: Add the video_27m clock
This patch supports the video_27m clock which is a fixed factor
clock of the pll3_pfd1_540m clock.
Signed-off-by: Liu Ying
---
v1->v2:
* None.
arch/arm/mach-imx/clk-imx6q.c | 1 +
include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4e79da7..9470df3 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -246,6 +246,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m",
"pll3_usb_otg", 1, 8);
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm",
1, 2);
clk[IMX6QDL_CLK_GPT_3M]= imx_clk_fixed_factor("gpt_3m","osc",
1, 8);
+ clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m",
"pll3_pfd1_540m", 1, 20);
if (cpu_is_imx6dl()) {
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi",
"mmdc_ch0_axi_podf", 1, 1);
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi",
"mmdc_ch0_axi_podf", 1, 1);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h
b/include/dt-bindings/clock/imx6qdl-clock.h
index b690cdb..25625bf 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -248,6 +248,7 @@
#define IMX6QDL_PLL6_BYPASS235
#define IMX6QDL_PLL7_BYPASS236
#define IMX6QDL_CLK_GPT_3M 237
-#define IMX6QDL_CLK_END238
+#define IMX6QDL_CLK_VIDEO_27M 238
+#define IMX6QDL_CLK_END239
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.1.0
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[PATCH RFC v2 14/14] ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel
This patch adds support for Himax HX8369A panel. The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm menuconfig and manually choose to build in the Himax HX8369A panel driver * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying --- v1->v2: * Add the HIMAX prefix in the Kconfig name. arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 3e0e589..27db91b 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -192,6 +192,7 @@ CONFIG_SOC_CAMERA_OV2640=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_HIMAX_HX8369A=y CONFIG_DRM_IMX=y CONFIG_DRM_IMX_FB_HELPER=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v2 13/14] ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller
This patch adds support for MIPI DSI host controller. The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm menuconfig and manually choose to build in the MIPI DSI host controller driver * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying --- v1->v2: * None. arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 0dbd0c3..3e0e589 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -199,6 +199,7 @@ CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_IPUV3=y CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_MIPI_DSI=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v2 12/14] ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging
The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying --- v1->v2: * None. arch/arm/configs/imx_v6_v7_defconfig | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 6790f1b..0dbd0c3 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -192,7 +192,13 @@ CONFIG_SOC_CAMERA_OV2640=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_FB_HELPER=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_IPUV3=y +CONFIG_DRM_IMX_HDMI=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y @@ -249,13 +255,6 @@ CONFIG_IMX_SDMA=y CONFIG_MXS_DMA=y CONFIG_FSL_EDMA=y CONFIG_STAGING=y -CONFIG_DRM_IMX=y -CONFIG_DRM_IMX_FB_HELPER=y -CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -CONFIG_DRM_IMX_TVE=y -CONFIG_DRM_IMX_LDB=y -CONFIG_DRM_IMX_IPUV3=y -CONFIG_DRM_IMX_HDMI=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_PWM=y CONFIG_PWM_IMX=y -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v2 06/14] ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node
The MIPI DSI node contains some ports which represent possible DRM CRTCs
it can connect with. Each port has a 'reg' property embedded. This
property will be wrongly interpretted by the MIPI DSI bus driver, because
the driver will take each subnode which contains a 'reg' property as a
DSI peripheral device. This patch moves the existing MIPI DSI ports into
a new 'ports' node so that the MIPI DSI bus driver may distinguish its
DSI peripheral device(s) from the existing ports.
Signed-off-by: Liu Ying
---
v1->v2:
* Newly added, as suggested by Thierry Reding.
arch/arm/boot/dts/imx6q.dtsi | 20 +++-
arch/arm/boot/dts/imx6qdl.dtsi | 23 ++-
2 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e9f3646..9c0990b 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -292,19 +292,21 @@
};
_dsi {
- port@2 {
- reg = <2>;
+ ports {
+ port@2 {
+ reg = <2>;
- mipi_mux_2: endpoint {
- remote-endpoint = <_di0_mipi>;
+ mipi_mux_2: endpoint {
+ remote-endpoint = <_di0_mipi>;
+ };
};
- };
- port@3 {
- reg = <3>;
+ port@3 {
+ reg = <3>;
- mipi_mux_3: endpoint {
- remote-endpoint = <_di1_mipi>;
+ mipi_mux_3: endpoint {
+ remote-endpoint = <_di1_mipi>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9596ed5..96bf2a0 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1009,19 +1009,24 @@
reg = <0x021e 0x4000>;
status = "disabled";
- port@0 {
- reg = <0>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
- mipi_mux_0: endpoint {
- remote-endpoint =
<_di0_mipi>;
+ mipi_mux_0: endpoint {
+ remote-endpoint =
<_di0_mipi>;
+ };
};
- };
- port@1 {
- reg = <1>;
+ port@1 {
+ reg = <1>;
- mipi_mux_1: endpoint {
- remote-endpoint =
<_di1_mipi>;
+ mipi_mux_1: endpoint {
+ remote-endpoint =
<_di1_mipi>;
+ };
};
};
};
--
2.1.0
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[PATCH RFC v2 09/14] drm: panel: Add support for Himax HX8369A MIPI DSI panel
This patch adds support for Himax HX8369A MIPI DSI panel.
Signed-off-by: Liu Ying
---
v1->v2:
* Address almost all comments from Thierry Reding.
* Remove several DT properties as they can be implied by the compatible string.
* Add the HIMAX/himax prefixes to the driver's Kconfig name and driver name.
* Move the driver's Makefile entry place to sort the entries alphabetically.
* Reuse several standard DCS functions instead of inventing wheels.
* Move the panel resetting and power logics to the driver probe/remove stages.
This may simplify panel prepare/unprepare hooks. The power consumption should
not change a lot at DPMS since the panel enters sleep mode at that time.
* Add the module author.
* Other minor changes, such as coding style issues.
.../devicetree/bindings/panel/himax,hx8369a.txt| 41 ++
drivers/gpu/drm/panel/Kconfig | 5 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-himax-hx8369a.c| 573 +
4 files changed, 620 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/himax,hx8369a.txt
create mode 100644 drivers/gpu/drm/panel/panel-himax-hx8369a.c
diff --git a/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
b/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
new file mode 100644
index 000..36a2f11
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
@@ -0,0 +1,41 @@
+Himax HX8369A WVGA 16.7M color TFT single chip driver with internal GRAM
+
+Himax HX8369A is a WVGA resolution driving controller.
+It is designed to provide a single chip solution that combines a source
+driver and power supply circuits to drive a TFT dot matrix LCD with
+480RGBx864 dots at the maximum.
+
+The HX8369A supports several interface modes, including MPU MIPI DBI Type
+A/B mode, MIPI DPI/DBI Type C mode, MIPI DSI video mode, MIPI DSI command
+mode and MDDI mode. The interface mode is selected by the external hardware
+pins BS[3:0].
+
+Currently, only the MIPI DSI video mode is supported.
+
+Required properties:
+ - compatible: should be a panel's compatible string
+ - reg: the virtual channel number of a DSI peripheral as described in [1]
+ - reset-gpios: a GPIO spec for the reset pin
+
+Optional properties:
+ - vdd1-supply: I/O and interface power supply
+ - vdd2-supply: analog power supply
+ - vdd3-supply: logic power supply
+ - dsi-vcc-supply: DSI and MDDI power supply
+ - vpp-supply: OTP programming voltage
+ - bs0-gpios: a GPIO spec for the pin BS0
+ - bs1-gpios: a GPIO spec for the pin BS1
+ - bs2-gpios: a GPIO spec for the pin BS2
+ - bs3-gpios: a GPIO spec for the pin BS3
+
+[1] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+
+Example:
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_mipi_panel>;
+ reset-gpios = < 11 GPIO_ACTIVE_LOW>;
+ bs2-gpios = < 14 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 024e98e..81b0bf0 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -16,6 +16,11 @@ config DRM_PANEL_SIMPLE
that it can be automatically turned off when the panel goes into a
low power state.
+config DRM_PANEL_HIMAX_HX8369A
+ tristate "Himax HX8369A panel"
+ depends on OF
+ select DRM_MIPI_DSI
+
config DRM_PANEL_LD9040
tristate "LD9040 RGB/SPI panel"
depends on OF && SPI
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 4b2a043..d5dbe06 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
+obj-$(CONFIG_DRM_PANEL_HIMAX_HX8369A) += panel-himax-hx8369a.o
obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
diff --git a/drivers/gpu/drm/panel/panel-himax-hx8369a.c
b/drivers/gpu/drm/panel/panel-himax-hx8369a.c
new file mode 100644
index 000..ae783f2
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-himax-hx8369a.c
@@ -0,0 +1,573 @@
+/*
+ * Himax HX8369A panel driver.
+ *
+ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This driver is based on Samsung s6e8aa0 panel driver.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#define WRDISBV0x51
+#define WRCTRLD0x53
+#define WRCABC 0x55
+#defi
[PATCH RFC v2 11/14] ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel
The TRULY TFT480800-16-E panel is driven by the Himax HX8369A driver IC.
The driver IC supports several display/control interface modes, including
the MIPI DSI video mode and command mode.
Signed-off-by: Liu Ying
---
v1->v2:
* To address Thierry Reding's comments, remove several unnecessary
properties as they can be implied by the compatible string.
* Fix the compatible string.
* Remove the display-timings node from the panel node as it can be
implied by the compatible string as well.
* Remove the status property as it is unneeded.
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index baf2f00..658bde9 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -482,6 +482,13 @@
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
+
+ pinctrl_mipi_panel: mipipanelgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
+ >;
+ };
};
gpio_leds {
@@ -518,6 +525,19 @@
};
};
+_dsi {
+ status = "okay";
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_mipi_panel>;
+ reset-gpios = < 11 GPIO_ACTIVE_LOW>;
+ bs2-gpios = < 14 GPIO_ACTIVE_HIGH>;
+ };
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pcie>;
--
2.1.0
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[PATCH RFC v2 01/14] clk: divider: Correct parent clk round rate if no bestdiv is normally found
If no best divider is normally found, we will try to use the maximum divider.
We should not set the parent clock rate to be 1Hz by force for being rounded.
Instead, we should take the maximum divider as a base and calculate a correct
parent clock rate for being rounded.
Signed-off-by: Liu Ying
---
v1->v2:
* None.
drivers/clk/clk-divider.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index c0a842b..f641d4b 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -311,7 +311,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned
long rate,
if (!bestdiv) {
bestdiv = _get_maxdiv(divider);
- *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
1);
+ *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
+ MULT_ROUND_UP(rate, bestdiv));
}
return bestdiv;
--
2.1.0
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[PATCH RFC v2 03/14] of: Add vendor prefix for Truly Semiconductors Limited
Signed-off-by: Liu Ying --- v1->v2: * None. Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 3cee528..8257f3a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -158,6 +158,7 @@ tlm Trusted Logic Mobility toradexToradex AG toshibaToshiba Corporation toumaz Toumaz +truly Truly Semiconductors Limited usiUniversal Scientific Industrial Co., Ltd. v3 V3 Semiconductor variscite Variscite Ltd. -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC v2 02/14] of: Add vendor prefix for Himax Technologies Inc.
Signed-off-by: Liu Ying --- v1->v2: * None. Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 78efebb..3cee528 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -69,6 +69,7 @@ hannstar HannStar Display Corporation haoyu Haoyu Microelectronic Co. Ltd. hisilicon Hisilicon Limited. hitHitachi Ltd. +himax Himax Technologies, Inc. honeywell Honeywell hp Hewlett Packard i2se I2SE GmbH -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC v2 05/14] ARM: imx6q: clk: Add the video_27m clock
Hi Philipp,
On 12/18/2014 06:31 PM, Philipp Zabel wrote:
Am Donnerstag, den 18.12.2014, 15:11 +0800 schrieb Liu Ying:
This patch supports the video_27m clock which is a fixed factor
clock of the pll3_pfd1_540m clock.
Signed-off-by: Liu Ying
---
v1->v2:
* None.
arch/arm/mach-imx/clk-imx6q.c | 1 +
include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4e79da7..9470df3 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -246,6 +246,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m",
"pll3_usb_otg", 1, 8);
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm",
1, 2);
clk[IMX6QDL_CLK_GPT_3M]= imx_clk_fixed_factor("gpt_3m","osc",
1, 8);
+ clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m",
"pll3_pfd1_540m", 1, 20);
The HDMI TX isfr clock input is sourced from video_27m, too, according
to Table 33-1 "HDMI clocks".
I think the parent of clk[IMX6QDL_CLK_HDMI_ISFR] should be changed from
"pll3_pfd1_540m" to "video_27m", then.
I'll add a new patch in the next version to change the hdmi_isfr
clock's parent.
Thanks,
Liu Ying
regards
Philipp
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Re: [PATCH RFC v2 06/14] ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node
Hi Philipp, On 12/18/2014 06:33 PM, Philipp Zabel wrote: Am Donnerstag, den 18.12.2014, 15:11 +0800 schrieb Liu Ying: The MIPI DSI node contains some ports which represent possible DRM CRTCs it can connect with. Each port has a 'reg' property embedded. This property will be wrongly interpretted by the MIPI DSI bus driver, because the driver will take each subnode which contains a 'reg' property as a DSI peripheral device. This patch moves the existing MIPI DSI ports into a new 'ports' node so that the MIPI DSI bus driver may distinguish its DSI peripheral device(s) from the existing ports. Signed-off-by: Liu Ying Acked-by: Philipp Zabel Thanks. I'll add your ack for this one in the next version. Regards, Liu Ying regards Philipp -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC v2 08/14] drm: imx: Add MIPI DSI host controller driver
On 12/18/2014 07:39 PM, Philipp Zabel wrote:
Am Donnerstag, den 18.12.2014, 15:11 +0800 schrieb Liu Ying:
This patch adds i.MX MIPI DSI host controller driver support.
Currently, the driver supports the burst with sync pulses mode only.
Signed-off-by: Liu Ying
---
v1->v2:
* Address almost all comments from Thierry Reding and Russell.
* Update the DT documentation to remove the display-timings node in the panel
node.
* Update the DT documentation to state that the nodes which represent the
possible
DRM CRTCs the controller may connect with should be placed in the node
"ports".
* Remove the flag 'enabled' from the struct imx_mipi_dsi.
* Move the format_to_bpp() function in v1 to the common DRM MIPI DSI driver.
* Improve the way we wait for check status for DPHY and command packet
transfer.
* Improve the DPMS support for the encoder.
* Split the functions of ->host_attach() and ->mode_valid() clearly as
suggested by
Thierry Reding.
* Improve the logics in imx_mipi_dsi_dcs_long_write().
* Enable/disable the pllref_clk and pllref_gate_clk at the component
binding/unbinding
stages to help remove the flag 'enabled'.
* Update the module license to be "GPL".
* Other minor changes, such as coding style issues and macro naming issues.
.../devicetree/bindings/drm/imx/mipi_dsi.txt | 78 ++
drivers/gpu/drm/imx/Kconfig|6 +
drivers/gpu/drm/imx/Makefile |1 +
drivers/gpu/drm/imx/imx-mipi-dsi.c | 1056
4 files changed, 1141 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
create mode 100644 drivers/gpu/drm/imx/imx-mipi-dsi.c
diff --git a/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
new file mode 100644
index 000..892ed62
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
@@ -0,0 +1,78 @@
+Device-Tree bindings for MIPI DSI host controller
+
+MIPI DSI host controller
+
+
+The MIPI DSI host controller is a Synopsys DesignWare IP.
+It is a digital core that implements all protocol functions defined
+in the MIPI DSI specification, providing an interface between the
+system and the MIPI DPHY, and allowing communication with a MIPI DSI
+compliant display.
+
+Required properties:
+ - #address-cells: Should be <1>.
+ - #size-cells: Should be <0>.
+ - compatible: Should be "fsl,imx6q-mipi-dsi" for i.MX6q/sdl SoCs.
If this is a Synopsys DesignWare IP core as the HDMI TX, I think the
compatible should reflect that. How about a second compatible
"snps,dw-mipi-dsi"?
Ok, I'll add this second compatible string.
+ - reg: Physical base address of the controller and length of memory
+ mapped region.
+ - interrupts: The controller's interrupt number to the CPU(s).
+ - gpr: Should be <>.
+ The phandle points to the iomuxc-gpr region containing the
+ multiplexer control register for the controller.
+ - clocks, clock-names: Phandles to the controller pllref, pllref_gate
+ and core_cfg clocks, as described in [1] and [2].
+
+Required sub-nodes:
+ - ports: This node may contain up to four port nodes with endpoint
+ definitions as defined in [3], corresponding to the four inputs to
+ the controller multiplexer.
+ - A node to represent a DSI peripheral as described in [4].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/imx6q-clock.txt
+[3] Documentation/devicetree/bindings/media/video-interfaces.txt
+[4] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr@020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi@021e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi";
+ reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <>;
+ clocks = < IMX6QDL_CLK_VIDEO_27M>,
+< IMX6QDL_CLK_HSI_TX>,
+< IMX6QDL_CLK_HSI_TX>;
+ clock-names = "pllref", "pllref_gate", "core_cfg";
Not sure about this. Are those names from the Synopsys documentation?
No, I don't think it's from there.
According to Table 41-1 in the i.MX6Q Reference Manual, this module has
6 clock inputs:
- ac_clk_125m (from ahb_clk_root)
- pixel_clk (from axi_clk_root)
- cfg_clk and pll_refclk (from video_27m)
- ips_clk and ipg_clk_s (from ipg_clk_root)
The CCM chapter says that of these, "ac_clk_125m", "cfg_clk", ips_clk",
and "pll_refclk" are gated by a single bit called
"mipi_core_cfg_clk_enable&
Re: [PATCH RFC v2 00/14] Add support for i.MX MIPI DSI DRM driver
Hi Andy, On 12/19/2014 02:33 PM, Andy Yan wrote: Hi Liu Ying: I foud Rockchip RK618 (a mfd function device with mipi dsi，lvds transmitter、HDMI TX、and audio codec，and controlled by the SOC from i2c ) have the same register layout with your i.MX MIPI DSI，which means RK618 MIPI DSI also have the Synopsys compatible DSI IP。So Would you please make this drives more platform independent？ I may try to place the Synopsys DesignWare MIPI DSI driver in the drm/bridge directory and make it as less platform-dependant as possible. I have no access to the Rockchip RK618 chip and it's reference menu. You probably may add the Rockchip part support later. Regards, Liu Ying At 2014-12-18 15:11:22, "Liu Ying" wrote: Hi, This series addressed almost all comments from Thierry Redding and Russell on v1. This series adds support for i.MX MIPI DSI DRM driver. Currently, the MIPI DSI driver only supports the burst with sync pulse mode. This series also includes a DRM panel driver for the Truly TFT480800-16-E panel which is driven by the Himax HX8369A driver IC. The driver IC data sheet could be found at [1]. As mentioned by the data sheet, the driver IC supports several interface modes. Currently, the DRM panel driver only supports the MIPI DSI video mode. New interface modes could be added later(perhaps, just like the way the DRM simple panel driver supports both MIPI DSI interface panels and simple(parallel) interface panels). The MIPI DSI feature is tested on i.MX6Q SabreSD board and i.MX6DL SabreSD board. The MIPI DSI display could be enabled directly on i.MX6Q SabreSD board after applying this series, because the 26.4MHz pixel clock the panel requires could be derived from the IPU HSP clock(264MHz) with an integer divider. On i.MX6DL SabreSD board, we need to manually disable the LVDS and HDMI displays in the device tree blob, since the i.MX6DL IPU HSP clock is 198MHz at present, which makes the pixel clock share the PLL5 video clock source with the LVDS and HDMI, thus, the panel cannot get the pixel clock rate it wants. Patch 01/15 is needed to get a precise pixel clock rate(26.4MHz) from the PLL5 video clock. If we don't have this patch, the pixel clock rate is about 20MHz, which causes a horitonal shift on the display image. This series can be applied on the drm-next branch. [1] http://www.allshore.com/pdf/Himax_HX8369-A.pdf Liu Ying (14): clk: divider: Correct parent clk round rate if no bestdiv is normally found of: Add vendor prefix for Himax Technologies Inc. of: Add vendor prefix for Truly Semiconductors Limited ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition ARM: imx6q: clk: Add the video_27m clock ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format drm: imx: Add MIPI DSI host controller driver drm: panel: Add support for Himax HX8369A MIPI DSI panel ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel .../devicetree/bindings/drm/imx/mipi_dsi.txt | 78 ++ .../devicetree/bindings/panel/himax,hx8369a.txt| 41 + .../devicetree/bindings/vendor-prefixes.txt|2 + arch/arm/boot/dts/imx6q.dtsi | 20 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 20 + arch/arm/boot/dts/imx6qdl.dtsi | 30 +- arch/arm/configs/imx_v6_v7_defconfig | 17 +- arch/arm/mach-imx/clk-imx6q.c |1 + drivers/clk/clk-divider.c |3 +- drivers/gpu/drm/imx/Kconfig|6 + drivers/gpu/drm/imx/Makefile |1 + drivers/gpu/drm/imx/imx-mipi-dsi.c | 1056 drivers/gpu/drm/panel/Kconfig |5 + drivers/gpu/drm/panel/Makefile |1 + drivers/gpu/drm/panel/panel-himax-hx8369a.c| 573 +++ include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/imx6qdl-clock.h |3 +- include/linux/mfd/syscon/imx6q-iomuxc-gpr.h|1 + 18 files changed, 1844 insertions(+), 28 deletions(-) create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt create mode 100644 Documentation/devicetree/bindings/panel/himax,hx8369a.txt create mode 100644 drivers/gpu/drm/imx/imx-mipi-dsi.c create mode 100644 drivers/gpu/drm/panel/panel-himax-hx8369a.c -- 2.1.0 ___ dri-devel mailing list dri-de...@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel -- To unsubscribe from this list: send the line "un
[PATCH RFC 03/15] of: Add vendor prefix for Truly Semiconductors Limited
Signed-off-by: Liu Ying --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 3cee528..8257f3a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -158,6 +158,7 @@ tlm Trusted Logic Mobility toradexToradex AG toshibaToshiba Corporation toumaz Toumaz +truly Truly Semiconductors Limited usiUniversal Scientific Industrial Co., Ltd. v3 V3 Semiconductor variscite Variscite Ltd. -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC 01/15] clk: divider: Correct parent clk round rate if no bestdiv is normally found
If no best divider is normally found, we will try to use the maximum divider.
We should not set the parent clock rate to be 1Hz by force for being rounded.
Instead, we should take the maximum divider as a base and calculate a correct
parent clock rate for being rounded.
Signed-off-by: Liu Ying
---
drivers/clk/clk-divider.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index c0a842b..f641d4b 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -311,7 +311,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned
long rate,
if (!bestdiv) {
bestdiv = _get_maxdiv(divider);
- *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
1);
+ *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
+ MULT_ROUND_UP(rate, bestdiv));
}
return bestdiv;
--
2.1.0
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[PATCH RFC 08/15] ARM: imx6q: clk: Add the video_27m clock
This patch supports the video_27m clock which is a fixed factor
clock of the pll3_pfd1_540m clock.
Signed-off-by: Liu Ying
---
arch/arm/mach-imx/clk-imx6q.c | 1 +
include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4e79da7..9470df3 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -246,6 +246,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m",
"pll3_usb_otg", 1, 8);
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm",
1, 2);
clk[IMX6QDL_CLK_GPT_3M]= imx_clk_fixed_factor("gpt_3m","osc",
1, 8);
+ clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m",
"pll3_pfd1_540m", 1, 20);
if (cpu_is_imx6dl()) {
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi",
"mmdc_ch0_axi_podf", 1, 1);
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi",
"mmdc_ch0_axi_podf", 1, 1);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h
b/include/dt-bindings/clock/imx6qdl-clock.h
index b690cdb..25625bf 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -248,6 +248,7 @@
#define IMX6QDL_PLL6_BYPASS235
#define IMX6QDL_PLL7_BYPASS236
#define IMX6QDL_CLK_GPT_3M 237
-#define IMX6QDL_CLK_END238
+#define IMX6QDL_CLK_VIDEO_27M 238
+#define IMX6QDL_CLK_END239
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.1.0
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[PATCH RFC 15/15] ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel
This patch adds support for Himax HX8369A panel. The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm menuconfig and manually choose to build in the Himax HX8369A panel driver * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 3e0e589..01b2b89 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -192,6 +192,7 @@ CONFIG_SOC_CAMERA_OV2640=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_HX8369A=y CONFIG_DRM_IMX=y CONFIG_DRM_IMX_FB_HELPER=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC 00/15] Add support for i.MX MIPI DSI DRM driver
Hi, This series adds support for i.MX MIPI DSI DRM driver. Currently, the MIPI DSI driver only supports the burst with sync pulse mode. This series also includes a DRM panel driver for the Truly TFT480800-16-E panel which is driven by the Himax HX8369A driver IC. The driver IC data sheet could be found at [1]. As mentioned by the data sheet, the driver IC supports several interface modes. Currently, the DRM panel driver only supports the MIPI DSI video mode. New interface modes could be added later(perhaps, just like the way the DRM simple panel driver supports both MIPI DSI interface panels and simple(parallel) interface panels). The MIPI DSI feature is tested on i.MX6Q SabreSD board and i.MX6DL SabreSD board. The MIPI DSI display could be enabled directly on i.MX6Q SabreSD board after applying this series, because the 26.4MHz pixel clock the panel requires could be derived from the IPU HSP clock(264MHz) with an integer divider. On i.MX6DL SabreSD board, we need to manually disable the LVDS and HDMI displays in the device tree blob, since the i.MX6DL IPU HSP clock is 198MHz at present, which makes the pixel clock share the PLL5 video clock source with the LVDS and HDMI, thus, the panel cannot get the pixel clock rate it wants. Patch 01/15 is needed to get a precise pixel clock rate(26.4MHz) from the PLL5 video clock. If we don't have this patch, the pixel clock rate is about 20MHz, which causes a horitonal shift on the display image. This series can be applied on the drm-next branch. [1] http://www.allshore.com/pdf/Himax_HX8369-A.pdf Liu Ying (15): clk: divider: Correct parent clk round rate if no bestdiv is normally found of: Add vendor prefix for Himax Technologies Inc. of: Add vendor prefix for Truly Semiconductors Limited drm/dsi: Do not add DSI devices for the child nodes with input-port property ARM: dts: imx6qdl: Add input-port property to MIPI DSI node's CTRC child nodes ARM: dts: imx6q: Add MIPI DSI remote end points for IPU2 DI0/1 end points ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition ARM: imx6q: clk: Add the video_27m clock drm: imx: Add MIPI DSI host controller driver drm: panel: Add support for Himax HX8369A MIPI DSI panel ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel .../devicetree/bindings/drm/imx/mipi_dsi.txt | 81 ++ .../devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt |4 + .../devicetree/bindings/panel/himax,hx8369a.txt| 86 ++ .../devicetree/bindings/vendor-prefixes.txt|2 + arch/arm/boot/dts/imx6q.dtsi |4 + arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 41 + arch/arm/boot/dts/imx6qdl.dtsi |9 + arch/arm/configs/imx_v6_v7_defconfig | 17 +- arch/arm/mach-imx/clk-imx6q.c |1 + drivers/clk/clk-divider.c |3 +- drivers/gpu/drm/drm_mipi_dsi.c |5 +- drivers/gpu/drm/imx/Kconfig|6 + drivers/gpu/drm/imx/Makefile |1 + drivers/gpu/drm/imx/imx-mipi-dsi.c | 1017 drivers/gpu/drm/panel/Kconfig |6 + drivers/gpu/drm/panel/Makefile |1 + drivers/gpu/drm/panel/panel-hx8369a.c | 627 include/dt-bindings/clock/imx6qdl-clock.h |3 +- include/linux/mfd/syscon/imx6q-iomuxc-gpr.h|1 + 19 files changed, 1903 insertions(+), 12 deletions(-) create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt create mode 100644 Documentation/devicetree/bindings/panel/himax,hx8369a.txt create mode 100644 drivers/gpu/drm/imx/imx-mipi-dsi.c create mode 100644 drivers/gpu/drm/panel/panel-hx8369a.c -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC 05/15] ARM: dts: imx6qdl: Add input-port property to MIPI DSI node's CTRC child nodes
To phase out the MIPI DSI's child nodes which present DRM CRTCs from the
child nodes which represent MIPI DSI peripherals, we need to add input-port
property to the child nodes to be phased out.
Signed-off-by: Liu Ying
---
arch/arm/boot/dts/imx6q.dtsi | 2 ++
arch/arm/boot/dts/imx6qdl.dtsi | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e9f3646..e6a6d90 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -294,6 +294,7 @@
_dsi {
port@2 {
reg = <2>;
+ input-port;
mipi_mux_2: endpoint {
remote-endpoint = <_di0_mipi>;
@@ -302,6 +303,7 @@
port@3 {
reg = <3>;
+ input-port;
mipi_mux_3: endpoint {
remote-endpoint = <_di1_mipi>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9596ed5..5d92ad7 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1011,6 +1011,7 @@
port@0 {
reg = <0>;
+ input-port;
mipi_mux_0: endpoint {
remote-endpoint =
<_di0_mipi>;
@@ -1019,6 +1020,7 @@
port@1 {
reg = <1>;
+ input-port;
mipi_mux_1: endpoint {
remote-endpoint =
<_di1_mipi>;
--
2.1.0
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[PATCH RFC 14/15] ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller
This patch adds support for MIPI DSI host controller. The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm menuconfig and manually choose to build in the MIPI DSI host controller driver * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 0dbd0c3..3e0e589 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -199,6 +199,7 @@ CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_IPUV3=y CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_MIPI_DSI=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC 11/15] ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller
This patch adds support for MIPI DSI host controller.
Signed-off-by: Liu Ying
---
arch/arm/boot/dts/imx6qdl.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 5d92ad7..4769767 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1006,7 +1006,14 @@
mipi_dsi: mipi@021e {
#address-cells = <1>;
#size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi";
reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <>;
+ clocks = < IMX6QDL_CLK_VIDEO_27M>,
+< IMX6QDL_CLK_HSI_TX>,
+< IMX6QDL_CLK_HSI_TX>;
+ clock-names = "pllref", "pllref_gate",
"core_cfg";
status = "disabled";
port@0 {
--
2.1.0
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[PATCH RFC 02/15] of: Add vendor prefix for Himax Technologies Inc.
Signed-off-by: Liu Ying --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 78efebb..3cee528 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -69,6 +69,7 @@ hannstar HannStar Display Corporation haoyu Haoyu Microelectronic Co. Ltd. hisilicon Hisilicon Limited. hitHitachi Ltd. +himax Himax Technologies, Inc. honeywell Honeywell hp Hewlett Packard i2se I2SE GmbH -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC 04/15] drm/dsi: Do not add DSI devices for the child nodes with input-port property
The MIPI DSI bus driver would try to add a DSI device for a host's every
child node which contains the reg property. Unfortunately, the existing
i.MX6Q/SDL MIPI DSI host device tree node's child nodes contain the reg
property, but the child nodes are ports pointing to dedicated CRTCs.
So, this patch phases out the child nodes with input-port property before
adding DSI devices for them and updates the MIPI DSI bus OF binding
documentation.
Signed-off-by: Liu Ying
---
Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt | 4
drivers/gpu/drm/drm_mipi_dsi.c | 5 +++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
b/Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
index 973c272..1a1d3c1 100644
--- a/Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+++ b/Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
@@ -36,6 +36,10 @@ Peripherals are represented as child nodes of the DSI host's
node. Properties
described here apply to all DSI peripherals, but individual bindings may want
to define additional, device-specific properties.
+Please, do not add the input-port property to the child nodes which represent
+peripherals. Otherwise, the peripherals would be omitted by the MIPI DSI bus
+driver.
+
Required properties:
- reg: The virtual channel number of a DSI peripheral. Must be in the range
from 0 to 3.
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index c0644bb..9adacfe 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -176,8 +176,9 @@ int mipi_dsi_host_register(struct mipi_dsi_host *host)
struct device_node *node;
for_each_available_child_of_node(host->dev->of_node, node) {
- /* skip nodes without reg property */
- if (!of_find_property(node, "reg", NULL))
+ /* skip nodes without reg property or with input-port property
*/
+ if (!of_find_property(node, "reg", NULL) ||
+of_find_property(node, "input-port", NULL))
continue;
of_mipi_dsi_device_add(host, node);
}
--
2.1.0
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[PATCH RFC 10/15] drm: panel: Add support for Himax HX8369A MIPI DSI panel
This patch adds support for Himax HX8369A MIPI DSI panel.
Signed-off-by: Liu Ying
---
.../devicetree/bindings/panel/himax,hx8369a.txt| 86 +++
drivers/gpu/drm/panel/Kconfig | 6 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-hx8369a.c | 627 +
4 files changed, 720 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/himax,hx8369a.txt
create mode 100644 drivers/gpu/drm/panel/panel-hx8369a.c
diff --git a/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
b/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
new file mode 100644
index 000..6fe251e
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
@@ -0,0 +1,86 @@
+Himax HX8369A WVGA 16.7M color TFT single chip driver with internal GRAM
+
+Himax HX8369A is a WVGA resolution driving controller.
+It is designed to provide a single chip solution that combines a source
+driver and power supply circuits to drive a TFT dot matrix LCD with
+480RGBx864 dots at the maximum.
+
+The HX8369A supports several interface modes, including MPU MIPI DBI Type
+A/B mode, MIPI DPI/DBI Type C mode, MIPI DSI video mode, MIPI DSI command
+mode and MDDI mode. The interface mode is selected by the external hardware
+pins BS[3:0].
+
+Currently, only the MIPI DSI video mode is supported.
+
+Required properties:
+ - compatible: "himax,hx8369a-dsi"
+ - reg: the virtual channel number of a DSI peripheral
+ - reset-gpios: a GPIO spec for the reset pin
+ - data-lanes: the data lane number of a DSI peripheral
+ - display-timings: timings for the connected panel as described by [1]
+ - bs: the interface mode number described by the following table
+--
+ | DBI_TYPE_A_8BIT | 0 |
+ | DBI_TYPE_A_9BIT | 1 |
+ | DBI_TYPE_A_16BIT| 2 |
+ | DBI_TYPE_A_18BIT| 3 |
+ | DBI_TYPE_B_8BIT | 4 |
+ | DBI_TYPE_B_9BIT | 5 |
+ | DBI_TYPE_B_16BIT| 6 |
+ | DBI_TYPE_B_18BIT| 7 |
+ | DSI_CMD_MODE| 8 |
+ | DBI_TYPE_B_24BIT| 9 |
+ | DSI_VIDEO_MODE | 10 |
+ | MDDI| 11 |
+ | DPI_DBI_TYPE_C_OPT1 | 12 |
+ | DPI_DBI_TYPE_C_OPT2 | 13 |
+ | DPI_DBI_TYPE_C_OPT3 | 14 |
+--
+
+Optional properties:
+ - power-on-delay: delay after turning regulators on [ms]
+ - reset-delay: delay after reset sequence [ms]
+ - vdd1-supply: I/O and interface power supply
+ - vdd2-supply: analog power supply
+ - vdd3-supply: logic power supply
+ - dsi-vcc-supply: DSI and MDDI power supply
+ - vpp-supply: OTP programming voltage
+ - bs0-gpios: a GPIO spec for the pin BS0
+ - bs1-gpios: a GPIO spec for the pin BS1
+ - bs2-gpios: a GPIO spec for the pin BS2
+ - bs3-gpios: a GPIO spec for the pin BS3
+ - panel-width-mm: physical panel width [mm]
+ - panel-height-mm: physical panel height [mm]
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+
+Example:
+ panel@0 {
+ compatible = "himax,hx8369a-dsi";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_mipi_panel>;
+ reset-gpios = < 11 GPIO_ACTIVE_LOW>;
+ reset-delay = <120>;
+ bs2-gpios = < 14 GPIO_ACTIVE_HIGH>;
+ data-lanes = <2>;
+ panel-width-mm = <45>;
+ panel-height-mm = <76>;
+ bs = <10>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <>;
+ timing1: truly-tft480800-16-e {
+ clock-frequency = <2640>;
+ hactive = <480>;
+ vactive = <800>;
+ hfront-porch = <8>;
+ hback-porch = <8>;
+ hsync-len = <8>;
+ vfront-porch = <6>;
+ vback-porch = <6>;
+ vsync-len = <6>;
+ };
+ };
+};
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 024e98e..f1a5b58 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -40,4 +40,10 @@ config DRM_PANEL_SHARP_LQ101R1SX01
To compile this driver as a module, choose M here: the module
will be called panel-sharp-lq101r1sx01.
+config DRM_PANEL_HX8369A
+ tristate "HX8369A panel"
+ depends on OF
+ select DRM_MIPI_DSI
+ select VIDEOMODE_HELPERS
+
endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 4b2a043..d6768ca 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/M
[PATCH RFC 07/15] ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition
This patch adds a macro to define the GPR3 MIPI muxing control register field shift bits. Signed-off-by: Liu Ying --- include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index ff44374..3b0bed4 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -207,6 +207,7 @@ #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6) #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6) #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6) +#define IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT 4 #define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4) -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RFC 06/15] ARM: dts: imx6q: Add MIPI DSI remote end points for IPU2 DI0/1 end points
This patch adds MIPI DSI remote end points for IPU2 DI0/1 end points.
Signed-off-by: Liu Ying
---
arch/arm/boot/dts/imx6q.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e6a6d90..82507e7 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -185,6 +185,7 @@
};
ipu2_di0_mipi: endpoint@2 {
+ remote-endpoint = <_mux_2>;
};
ipu2_di0_lvds0: endpoint@3 {
@@ -206,6 +207,7 @@
};
ipu2_di1_mipi: endpoint@2 {
+ remote-endpoint = <_mux_3>;
};
ipu2_di1_lvds0: endpoint@3 {
--
2.1.0
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[PATCH RFC 12/15] ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel
The TRULY TFT480800-16-E panel is driven by the Himax HX8369A driver IC.
The driver IC supports several display/control interface modes, including
the MIPI DSI video mode and command mode.
Signed-off-by: Liu Ying
---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 41 ++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index baf2f00..483aa5f 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -482,6 +482,13 @@
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
+
+ pinctrl_mipi_panel: mipipanelgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
+ >;
+ };
};
gpio_leds {
@@ -518,6 +525,40 @@
};
};
+_dsi {
+ status = "okay";
+
+ panel@0 {
+ compatible = "himax,hx8369a-dsi";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_mipi_panel>;
+ reset-gpios = < 11 GPIO_ACTIVE_LOW>;
+ reset-delay = <120>;
+ bs2-gpios = < 14 GPIO_ACTIVE_HIGH>;
+ data-lanes = <2>;
+ panel-width-mm = <45>;
+ panel-height-mm = <76>;
+ bs = <10>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <>;
+ timing1: truly-tft480800-16-e {
+ clock-frequency = <2640>;
+ hactive = <480>;
+ vactive = <800>;
+ hfront-porch = <8>;
+ hback-porch = <8>;
+ hsync-len = <8>;
+ vfront-porch = <6>;
+ vback-porch = <6>;
+ vsync-len = <6>;
+ };
+ };
+ };
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pcie>;
--
2.1.0
--
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[PATCH RFC 09/15] drm: imx: Add MIPI DSI host controller driver
This patch adds i.MX MIPI DSI host controller driver support.
Currently, the driver supports the burst with sync pulses mode only.
Signed-off-by: Liu Ying
---
.../devicetree/bindings/drm/imx/mipi_dsi.txt | 81 ++
drivers/gpu/drm/imx/Kconfig|6 +
drivers/gpu/drm/imx/Makefile |1 +
drivers/gpu/drm/imx/imx-mipi-dsi.c | 1017
4 files changed, 1105 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
create mode 100644 drivers/gpu/drm/imx/imx-mipi-dsi.c
diff --git a/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
new file mode 100644
index 000..3d07fd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
@@ -0,0 +1,81 @@
+Device-Tree bindings for MIPI DSI host controller
+
+MIPI DSI host controller
+
+
+The MIPI DSI host controller is a Synopsys DesignWare IP.
+It is a digital core that implements all protocol functions defined
+in the MIPI DSI specification, providing an interface between the
+system and the MIPI DPHY, and allowing communication with a MIPI DSI
+compliant display.
+
+Required properties:
+ - #address-cells : Should be <1>.
+ - #size-cells : Should be <0>.
+ - compatible : Should be "fsl,imx6q-mipi-dsi" for i.MX6q/sdl SoCs.
+ - reg : Physical base address of the controller and length of memory
+ mapped region.
+ - interrupts : The controller's interrupt number to the CPU(s).
+ - gpr : Should be <>.
+ The phandle points to the iomuxc-gpr region containing the
+ multiplexer control register for the controller.
+ - clocks, clock-names : Phandles to the controller pllref, pllref_gate
+ and core_cfg clocks, as described in [1] and [2].
+ - panel@0 : A panel node which contains a display-timings child node as
+ defined in [3].
+ - port@[0-4] : Up to four port nodes with endpoint definitions as defined
+ in [4], corresponding to the four inputs to the controller multiplexer.
+ Note that each port node should contain the input-port property to
+ distinguish it from the panel node, as described in [5].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/imx6q-clock.txt
+[3] Documentation/devicetree/bindings/video/display-timing.txt
+[4] Documentation/devicetree/bindings/media/video-interfaces.txt
+[5] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr@020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi@021e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi";
+ reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <>;
+ clocks = < IMX6QDL_CLK_VIDEO_27M>,
+< IMX6QDL_CLK_HSI_TX>,
+< IMX6QDL_CLK_HSI_TX>;
+ clock-names = "pllref", "pllref_gate", "core_cfg";
+
+ port@0 {
+ reg = <0>;
+ input-port;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <_di0_mipi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ input-port;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <_di1_mipi>;
+ };
+ };
+
+ panel@0 {
+ compatible = "himax,hx8369a-dsi";
+ reg = <0>;
+ /* ... */
+
+ display-timings {
+ /* ... */
+ };
+ };
+ };
diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 82fb758..03f04fb 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -51,3 +51,9 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
Choose this if you want to use HDMI on i.MX6.
+
+config DRM_IMX_MIPI_DSI
+ tristate "Freescale i.MX DRM MIPI DSI"
+ depends on DRM_IMX && MFD_SYSCON
+ help
+ Choose this if you want to use MIPI DSI on i.MX6.
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 582c438..4571d52 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
imx-ipuv3-crtc-objs := ipuv3-crtc.o ipuv3-plane.o
obj-$(CONFIG_DRM_IMX_IPUV3)+= imx-ipuv3-crtc.o
obj-$(CONFIG_DRM_IMX_HDMI) +=
[PATCH RFC 13/15] ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging
The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying --- arch/arm/configs/imx_v6_v7_defconfig | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 6790f1b..0dbd0c3 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -192,7 +192,13 @@ CONFIG_SOC_CAMERA_OV2640=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_FB_HELPER=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_IPUV3=y +CONFIG_DRM_IMX_HDMI=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y @@ -249,13 +255,6 @@ CONFIG_IMX_SDMA=y CONFIG_MXS_DMA=y CONFIG_FSL_EDMA=y CONFIG_STAGING=y -CONFIG_DRM_IMX=y -CONFIG_DRM_IMX_FB_HELPER=y -CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -CONFIG_DRM_IMX_TVE=y -CONFIG_DRM_IMX_LDB=y -CONFIG_DRM_IMX_IPUV3=y -CONFIG_DRM_IMX_HDMI=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_PWM=y CONFIG_PWM_IMX=y -- 2.1.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 04/15] drm/dsi: Do not add DSI devices for the child nodes with input-port property
Hi Thierry, On 12/10/2014 08:21 PM, Thierry Reding wrote: On Wed, Dec 10, 2014 at 04:37:17PM +0800, Liu Ying wrote: The MIPI DSI bus driver would try to add a DSI device for a host's every child node which contains the reg property. Unfortunately, the existing i.MX6Q/SDL MIPI DSI host device tree node's child nodes contain the reg There aren't any existing nodes for the DSI host on i.MX. This patch series adds support for them. There are existing nodes for the DSI host node. Please find them in arch/arm/boot/dts/imx6qdl.dtsi and arch/arm/boot/dts/imx6q.dts. The DSI host node contains two child nodes for i.MX6DL and another two for i.MX6Q. Each child node has a reg property embedded. property, but the child nodes are ports pointing to dedicated CRTCs. So, this patch phases out the child nodes with input-port property before adding DSI devices for them and updates the MIPI DSI bus OF binding documentation. Signed-off-by: Liu Ying --- Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt | 4 drivers/gpu/drm/drm_mipi_dsi.c | 5 +++-- 2 files changed, 7 insertions(+), 2 deletions(-) Sorry, but NAK. There's no need for this special-case. I'll go into more detail in response to patch 09/15. Thanks for reviewing the patches. Any idea how to handle the special case? The existing child nodes for the DSI host node do have the reg properties embedded. Regards, Liu Ying Thierry -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 04/15] drm/dsi: Do not add DSI devices for the child nodes with input-port property
Hi Thierry, On 12/11/2014 10:52 AM, Liu Ying wrote: Hi Thierry, On 12/10/2014 08:21 PM, Thierry Reding wrote: On Wed, Dec 10, 2014 at 04:37:17PM +0800, Liu Ying wrote: The MIPI DSI bus driver would try to add a DSI device for a host's every child node which contains the reg property. Unfortunately, the existing i.MX6Q/SDL MIPI DSI host device tree node's child nodes contain the reg There aren't any existing nodes for the DSI host on i.MX. This patch series adds support for them. There are existing nodes for the DSI host node. Please find them in arch/arm/boot/dts/imx6qdl.dtsi and arch/arm/boot/dts/imx6q.dts. The DSI host node contains two child nodes for i.MX6DL and another two for i.MX6Q. Each child node has a reg property embedded. property, but the child nodes are ports pointing to dedicated CRTCs. So, this patch phases out the child nodes with input-port property before adding DSI devices for them and updates the MIPI DSI bus OF binding documentation. Signed-off-by: Liu Ying --- Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt | 4 drivers/gpu/drm/drm_mipi_dsi.c | 5 +++-- 2 files changed, 7 insertions(+), 2 deletions(-) Sorry, but NAK. There's no need for this special-case. I'll go into more detail in response to patch 09/15. Thanks for reviewing the patches. Any idea how to handle the special case? The existing child nodes for the DSI host node do have the reg properties embedded. I see your suggestions on this topic in the comments for patch 09/15. I will try to move the existing child nodes into a parent port node. Liu Ying Thierry ___ dri-devel mailing list dri-de...@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC v9 09/20] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
Hi Thierry, 2015-03-03 19:07 GMT+08:00 Philipp Zabel : > Hi, > > Am Donnerstag, den 12.02.2015, 14:01 +0800 schrieb Liu Ying: >> Signed-off-by: Liu Ying >> --- >> v8->v9: >> * Rebase onto the imx-drm/next branch of Philipp Zabel's open git >> repository. > > I can't test this myself for lack of hardware, but I see no further > issues with patches 09 - 13 except for the use of > imx_drm_encoder_get_mux_id. I'll either rebase my patches that remove it > or fix it up when applying. > > Thierry, may I take these patches through imx-drm, or would you rather I > waited for you to pick up the drm/dsi and drm/bridge patches? Gentle ping. What's your opinion on the patches Philipp mentioned? Regards, Liu Ying > > regards > Philipp > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel -- Best Regards, Liu Ying -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2] video: mxsfb: Make sure axi clock is enabled when accessing registers
2015-03-20 19:26 GMT+08:00 Tomi Valkeinen : > On 11/03/15 05:03, Liu Ying wrote: > >>> Why do you check for host->enabled here, but not elsewhere? >> >> We need this check here to make sure the axi clock reference count is no >> greater >> than 1. Looking at the context of mxsfb_set_par(), mxsfb_restore_mode() and > > Why is that? The clock framework handles ref counting for you. All the > driver needs to take care of is to call as many times disable as it > calls enable. Okay. I'll remove the check and send another version. Regards, Liu Ying > > Tomi > > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4] video: mxsfb: Make sure axi clock is enabled when accessing registers
The LCDIF engines embedded in i.MX6sl and i.MX6sx SoCs need the axi clock
as the engine's system clock. The clock should be enabled when accessing
LCDIF registers, otherwise the kernel would hang up. We should also keep
the clock enabled when the engine is being active to scan out frames from
memory. This patch makes sure the axi clock is enabled when accessing
registers so that the kernel hang up issue can be fixed.
Reported-by: Peter Chen
Tested-by: Peter Chen
Cc: # 3.19+
Signed-off-by: Liu Ying
---
v3->v4:
* To address Tomi's comment, enable/disable the axi clock in
mxsfb_pan_display() directly instead of checking the host->enabled flag.
v2->v3:
* To address Tomi's comment, improve the commit message only.
v1->v2:
* Add 'Tested-by: Peter Chen ' tag.
* Add 'Cc: # 3.19+' tag.
drivers/video/fbdev/mxsfb.c | 68 +++--
1 file changed, 54 insertions(+), 14 deletions(-)
diff --git a/drivers/video/fbdev/mxsfb.c b/drivers/video/fbdev/mxsfb.c
index f8ac4a4..0f64165 100644
--- a/drivers/video/fbdev/mxsfb.c
+++ b/drivers/video/fbdev/mxsfb.c
@@ -316,6 +316,18 @@ static int mxsfb_check_var(struct fb_var_screeninfo *var,
return 0;
}
+static inline void mxsfb_enable_axi_clk(struct mxsfb_info *host)
+{
+ if (host->clk_axi)
+ clk_prepare_enable(host->clk_axi);
+}
+
+static inline void mxsfb_disable_axi_clk(struct mxsfb_info *host)
+{
+ if (host->clk_axi)
+ clk_disable_unprepare(host->clk_axi);
+}
+
static void mxsfb_enable_controller(struct fb_info *fb_info)
{
struct mxsfb_info *host = to_imxfb_host(fb_info);
@@ -333,14 +345,13 @@ static void mxsfb_enable_controller(struct fb_info
*fb_info)
}
}
- if (host->clk_axi)
- clk_prepare_enable(host->clk_axi);
-
if (host->clk_disp_axi)
clk_prepare_enable(host->clk_disp_axi);
clk_prepare_enable(host->clk);
clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
+ mxsfb_enable_axi_clk(host);
+
/* if it was disabled, re-enable the mode again */
writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
@@ -380,11 +391,11 @@ static void mxsfb_disable_controller(struct fb_info
*fb_info)
reg = readl(host->base + LCDC_VDCTRL4);
writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
+ mxsfb_disable_axi_clk(host);
+
clk_disable_unprepare(host->clk);
if (host->clk_disp_axi)
clk_disable_unprepare(host->clk_disp_axi);
- if (host->clk_axi)
- clk_disable_unprepare(host->clk_axi);
host->enabled = 0;
@@ -421,6 +432,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
mxsfb_disable_controller(fb_info);
}
+ mxsfb_enable_axi_clk(host);
+
/* clear the FIFOs */
writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
@@ -438,6 +451,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
ctrl |= CTRL_SET_WORD_LENGTH(3);
switch (host->ld_intf_width) {
case STMLCDIF_8BIT:
+ mxsfb_disable_axi_clk(host);
dev_err(>pdev->dev,
"Unsupported LCD bus width mapping\n");
return -EINVAL;
@@ -451,6 +465,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
break;
default:
+ mxsfb_disable_axi_clk(host);
dev_err(>pdev->dev, "Unhandled color depth of %u\n",
fb_info->var.bits_per_pixel);
return -EINVAL;
@@ -504,6 +519,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
fb_info->fix.line_length * fb_info->var.yoffset,
host->base + host->devdata->next_buf);
+ mxsfb_disable_axi_clk(host);
+
if (reenable)
mxsfb_enable_controller(fb_info);
@@ -582,10 +599,14 @@ static int mxsfb_pan_display(struct fb_var_screeninfo
*var,
offset = fb_info->fix.line_length * var->yoffset;
+ mxsfb_enable_axi_clk(host);
+
/* update on next VSYNC */
writel(fb_info->fix.smem_start + offset,
host->base + host->devdata->next_buf);
+ mxsfb_disable_axi_clk(host);
+
return 0;
}
@@ -608,13 +629,17 @@ static int mxsfb_restore_mode(struct mxsfb_info *host,
unsigned line_count;
unsigned period;
unsigned long pa, fbsize;
- int bits_per_pixel, ofs;
+ int bits_per_pixel, ofs, ret = 0;
u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
+ mxsfb_enable_axi_cl
[PATCH v3] video: mxsfb: Make sure axi clock is enabled when accessing registers
The LCDIF engines embedded in i.MX6sl and i.MX6sx SoCs need the axi clock
as the engine's system clock. The clock should be enabled when accessing
LCDIF registers, otherwise the kernel would hang up. We should also keep
the clock enabled when the engine is being active to scan out frames from
memory. This patch makes sure the axi clock is enabled when accessing
registers so that the kernel hang up issue can be fixed.
Reported-by: Peter Chen
Tested-by: Peter Chen
Cc: # 3.19+
Signed-off-by: Liu Ying
---
v2->v3:
* To address Tomi's comment, improve the commit message only.
v1->v2:
* Add 'Tested-by: Peter Chen ' tag.
* Add 'Cc: # 3.19+' tag.
drivers/video/fbdev/mxsfb.c | 70 -
1 file changed, 56 insertions(+), 14 deletions(-)
diff --git a/drivers/video/fbdev/mxsfb.c b/drivers/video/fbdev/mxsfb.c
index f8ac4a4..a8cf3b2 100644
--- a/drivers/video/fbdev/mxsfb.c
+++ b/drivers/video/fbdev/mxsfb.c
@@ -316,6 +316,18 @@ static int mxsfb_check_var(struct fb_var_screeninfo *var,
return 0;
}
+static inline void mxsfb_enable_axi_clk(struct mxsfb_info *host)
+{
+ if (host->clk_axi)
+ clk_prepare_enable(host->clk_axi);
+}
+
+static inline void mxsfb_disable_axi_clk(struct mxsfb_info *host)
+{
+ if (host->clk_axi)
+ clk_disable_unprepare(host->clk_axi);
+}
+
static void mxsfb_enable_controller(struct fb_info *fb_info)
{
struct mxsfb_info *host = to_imxfb_host(fb_info);
@@ -333,14 +345,13 @@ static void mxsfb_enable_controller(struct fb_info
*fb_info)
}
}
- if (host->clk_axi)
- clk_prepare_enable(host->clk_axi);
-
if (host->clk_disp_axi)
clk_prepare_enable(host->clk_disp_axi);
clk_prepare_enable(host->clk);
clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
+ mxsfb_enable_axi_clk(host);
+
/* if it was disabled, re-enable the mode again */
writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
@@ -380,11 +391,11 @@ static void mxsfb_disable_controller(struct fb_info
*fb_info)
reg = readl(host->base + LCDC_VDCTRL4);
writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
+ mxsfb_disable_axi_clk(host);
+
clk_disable_unprepare(host->clk);
if (host->clk_disp_axi)
clk_disable_unprepare(host->clk_disp_axi);
- if (host->clk_axi)
- clk_disable_unprepare(host->clk_axi);
host->enabled = 0;
@@ -421,6 +432,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
mxsfb_disable_controller(fb_info);
}
+ mxsfb_enable_axi_clk(host);
+
/* clear the FIFOs */
writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
@@ -438,6 +451,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
ctrl |= CTRL_SET_WORD_LENGTH(3);
switch (host->ld_intf_width) {
case STMLCDIF_8BIT:
+ mxsfb_disable_axi_clk(host);
dev_err(>pdev->dev,
"Unsupported LCD bus width mapping\n");
return -EINVAL;
@@ -451,6 +465,7 @@ static int mxsfb_set_par(struct fb_info *fb_info)
writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
break;
default:
+ mxsfb_disable_axi_clk(host);
dev_err(>pdev->dev, "Unhandled color depth of %u\n",
fb_info->var.bits_per_pixel);
return -EINVAL;
@@ -504,6 +519,8 @@ static int mxsfb_set_par(struct fb_info *fb_info)
fb_info->fix.line_length * fb_info->var.yoffset,
host->base + host->devdata->next_buf);
+ mxsfb_disable_axi_clk(host);
+
if (reenable)
mxsfb_enable_controller(fb_info);
@@ -582,10 +599,16 @@ static int mxsfb_pan_display(struct fb_var_screeninfo
*var,
offset = fb_info->fix.line_length * var->yoffset;
+ if (!host->enabled)
+ mxsfb_enable_axi_clk(host);
+
/* update on next VSYNC */
writel(fb_info->fix.smem_start + offset,
host->base + host->devdata->next_buf);
+ if (!host->enabled)
+ mxsfb_disable_axi_clk(host);
+
return 0;
}
@@ -608,13 +631,17 @@ static int mxsfb_restore_mode(struct mxsfb_info *host,
unsigned line_count;
unsigned period;
unsigned long pa, fbsize;
- int bits_per_pixel, ofs;
+ int bits_per_pixel, ofs, ret = 0;
u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
+ mxsfb_enable_axi_clk(host);
+
/* Only restore the mode when the controller
