Re: [PATCH v2 2/2] s5p-fimc: Add support for alpha component configuration
On 11/28/2011 12:42 PM, Hans Verkuil wrote: > On Friday 25 November 2011 16:39:32 Sylwester Nawrocki wrote: >> On Exynos SoCs the FIMC IP allows to configure globally the alpha >> component of all pixels for V4L2_PIX_FMT_RGB32, V4L2_PIX_FMT_RGB555 >> and V4L2_PIX_FMT_RGB444 image formats. This patch adds a v4l2 control >> in order to let the applications control the alpha component value. >> >> The alpha value range depends on the pixel format, for RGB32 it's >> 0..255 (8-bits), for RGB555 - 0..1 (1-bit) and for RGB444 - 0..15 >> (4-bits). The v4l2 control range is always 0..255 and the alpha >> component data width is determined by currently set format on the >> V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE buffer queue. The applications >> need to match the alpha channel data width and the pixel format >> since the driver will ignore the alpha component bits that are not >> applicable to the configured pixel format. > > Will the driver ignore the least significant bits or the most significant > bits? Most significant bits will be ignored, i.e. depending on fourcc the valid alpha bits are: V4L2_PIX_FMT_RGB555 - [0] V4L2_PIX_FMT_RGB444 - [3:0] V4L2_PIX_FMT_RGB32 - [7:0] -- Regards, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/2] s5p-fimc: Add support for alpha component configuration
On Friday 25 November 2011 16:39:32 Sylwester Nawrocki wrote:
> On Exynos SoCs the FIMC IP allows to configure globally the alpha
> component of all pixels for V4L2_PIX_FMT_RGB32, V4L2_PIX_FMT_RGB555
> and V4L2_PIX_FMT_RGB444 image formats. This patch adds a v4l2 control
> in order to let the applications control the alpha component value.
>
> The alpha value range depends on the pixel format, for RGB32 it's
> 0..255 (8-bits), for RGB555 - 0..1 (1-bit) and for RGB444 - 0..15
> (4-bits). The v4l2 control range is always 0..255 and the alpha
> component data width is determined by currently set format on the
> V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE buffer queue. The applications
> need to match the alpha channel data width and the pixel format
> since the driver will ignore the alpha component bits that are not
> applicable to the configured pixel format.
Will the driver ignore the least significant bits or the most significant
bits?
Regards,
Hans
>
> A new entry is added in the variant description data structure
> so an additional control is created only where really supported
> by the hardware.
>
> Signed-off-by: Sylwester Nawrocki
> Signed-off-by: Kyungmin Park
> ---
> drivers/media/video/s5p-fimc/fimc-capture.c |4 ++
> drivers/media/video/s5p-fimc/fimc-core.c| 49
> ++--- drivers/media/video/s5p-fimc/fimc-core.h|
> 13 ++-
> drivers/media/video/s5p-fimc/fimc-reg.c | 53
> +-- drivers/media/video/s5p-fimc/regs-fimc.h|
> 5 +++
> 5 files changed, 105 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/media/video/s5p-fimc/fimc-capture.c
> b/drivers/media/video/s5p-fimc/fimc-capture.c index 82d9ab6..70176e5
> 100644
> --- a/drivers/media/video/s5p-fimc/fimc-capture.c
> +++ b/drivers/media/video/s5p-fimc/fimc-capture.c
> @@ -63,6 +63,8 @@ static int fimc_init_capture(struct fimc_dev *fimc)
> fimc_hw_set_effect(ctx, false);
> fimc_hw_set_output_path(ctx);
> fimc_hw_set_out_dma(ctx);
> + if (fimc->variant->has_alpha)
> + fimc_hw_set_rgb_alpha(ctx);
> clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
> }
> spin_unlock_irqrestore(&fimc->slock, flags);
> @@ -154,6 +156,8 @@ int fimc_capture_config_update(struct fimc_ctx *ctx)
> fimc_hw_set_rotation(ctx);
> fimc_prepare_dma_offset(ctx, &ctx->d_frame);
> fimc_hw_set_out_dma(ctx);
> + if (fimc->variant->has_alpha)
> + fimc_hw_set_rgb_alpha(ctx);
> clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
> }
> spin_unlock(&ctx->slock);
> diff --git a/drivers/media/video/s5p-fimc/fimc-core.c
> b/drivers/media/video/s5p-fimc/fimc-core.c index 567e9ea..5fe9aeb 100644
> --- a/drivers/media/video/s5p-fimc/fimc-core.c
> +++ b/drivers/media/video/s5p-fimc/fimc-core.c
> @@ -52,13 +52,29 @@ static struct fimc_fmt fimc_formats[] = {
> .colplanes = 1,
> .flags = FMT_FLAGS_M2M,
> }, {
> - .name = "XRGB-8-8-8-8, 32 bpp",
> + .name = "ARGB, 32 bpp",
> .fourcc = V4L2_PIX_FMT_RGB32,
> .depth = { 32 },
> .color = S5P_FIMC_RGB888,
> .memplanes = 1,
> .colplanes = 1,
> - .flags = FMT_FLAGS_M2M,
> + .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
> + }, {
> + .name = "ARGB1555",
> + .fourcc = V4L2_PIX_FMT_RGB555,
> + .depth = { 16 },
> + .color = S5P_FIMC_RGB555,
> + .memplanes = 1,
> + .colplanes = 1,
> + .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
> + }, {
> + .name = "ARGB",
> + .fourcc = V4L2_PIX_FMT_RGB444,
> + .depth = { 16 },
> + .color = S5P_FIMC_RGB444,
> + .memplanes = 1,
> + .colplanes = 1,
> + .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
> }, {
> .name = "YUV 4:2:2 packed, YCbYCr",
> .fourcc = V4L2_PIX_FMT_YUYV,
> @@ -652,8 +668,11 @@ static void fimc_dma_run(void *priv)
> if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
> fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
>
> - if (ctx->state & FIMC_PARAMS)
> + if (ctx->state & FIMC_PARAMS) {
> fimc_hw_set_out_dma(ctx);
> + if (fimc->variant->has_alpha)
> + fimc_hw_set_rgb_alpha(ctx);
> + }
>
> fimc_activate_capture(ctx);
>
> @@ -790,6 +809,11 @@ static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
> ctx->rotation = ctrl->val;
> break;
>
> + case V4L2_CID_ALPHA_COMPONENT:
> +
[PATCH v2 2/2] s5p-fimc: Add support for alpha component configuration
On Exynos SoCs the FIMC IP allows to configure globally the alpha
component of all pixels for V4L2_PIX_FMT_RGB32, V4L2_PIX_FMT_RGB555
and V4L2_PIX_FMT_RGB444 image formats. This patch adds a v4l2 control
in order to let the applications control the alpha component value.
The alpha value range depends on the pixel format, for RGB32 it's
0..255 (8-bits), for RGB555 - 0..1 (1-bit) and for RGB444 - 0..15
(4-bits). The v4l2 control range is always 0..255 and the alpha
component data width is determined by currently set format on the
V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE buffer queue. The applications
need to match the alpha channel data width and the pixel format
since the driver will ignore the alpha component bits that are not
applicable to the configured pixel format.
A new entry is added in the variant description data structure
so an additional control is created only where really supported
by the hardware.
Signed-off-by: Sylwester Nawrocki
Signed-off-by: Kyungmin Park
---
drivers/media/video/s5p-fimc/fimc-capture.c |4 ++
drivers/media/video/s5p-fimc/fimc-core.c| 49 ++---
drivers/media/video/s5p-fimc/fimc-core.h| 13 ++-
drivers/media/video/s5p-fimc/fimc-reg.c | 53 +--
drivers/media/video/s5p-fimc/regs-fimc.h|5 +++
5 files changed, 105 insertions(+), 19 deletions(-)
diff --git a/drivers/media/video/s5p-fimc/fimc-capture.c
b/drivers/media/video/s5p-fimc/fimc-capture.c
index 82d9ab6..70176e5 100644
--- a/drivers/media/video/s5p-fimc/fimc-capture.c
+++ b/drivers/media/video/s5p-fimc/fimc-capture.c
@@ -63,6 +63,8 @@ static int fimc_init_capture(struct fimc_dev *fimc)
fimc_hw_set_effect(ctx, false);
fimc_hw_set_output_path(ctx);
fimc_hw_set_out_dma(ctx);
+ if (fimc->variant->has_alpha)
+ fimc_hw_set_rgb_alpha(ctx);
clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
}
spin_unlock_irqrestore(&fimc->slock, flags);
@@ -154,6 +156,8 @@ int fimc_capture_config_update(struct fimc_ctx *ctx)
fimc_hw_set_rotation(ctx);
fimc_prepare_dma_offset(ctx, &ctx->d_frame);
fimc_hw_set_out_dma(ctx);
+ if (fimc->variant->has_alpha)
+ fimc_hw_set_rgb_alpha(ctx);
clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
}
spin_unlock(&ctx->slock);
diff --git a/drivers/media/video/s5p-fimc/fimc-core.c
b/drivers/media/video/s5p-fimc/fimc-core.c
index 567e9ea..5fe9aeb 100644
--- a/drivers/media/video/s5p-fimc/fimc-core.c
+++ b/drivers/media/video/s5p-fimc/fimc-core.c
@@ -52,13 +52,29 @@ static struct fimc_fmt fimc_formats[] = {
.colplanes = 1,
.flags = FMT_FLAGS_M2M,
}, {
- .name = "XRGB-8-8-8-8, 32 bpp",
+ .name = "ARGB, 32 bpp",
.fourcc = V4L2_PIX_FMT_RGB32,
.depth = { 32 },
.color = S5P_FIMC_RGB888,
.memplanes = 1,
.colplanes = 1,
- .flags = FMT_FLAGS_M2M,
+ .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
+ }, {
+ .name = "ARGB1555",
+ .fourcc = V4L2_PIX_FMT_RGB555,
+ .depth = { 16 },
+ .color = S5P_FIMC_RGB555,
+ .memplanes = 1,
+ .colplanes = 1,
+ .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
+ }, {
+ .name = "ARGB",
+ .fourcc = V4L2_PIX_FMT_RGB444,
+ .depth = { 16 },
+ .color = S5P_FIMC_RGB444,
+ .memplanes = 1,
+ .colplanes = 1,
+ .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
}, {
.name = "YUV 4:2:2 packed, YCbYCr",
.fourcc = V4L2_PIX_FMT_YUYV,
@@ -652,8 +668,11 @@ static void fimc_dma_run(void *priv)
if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
- if (ctx->state & FIMC_PARAMS)
+ if (ctx->state & FIMC_PARAMS) {
fimc_hw_set_out_dma(ctx);
+ if (fimc->variant->has_alpha)
+ fimc_hw_set_rgb_alpha(ctx);
+ }
fimc_activate_capture(ctx);
@@ -790,6 +809,11 @@ static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
ctx->rotation = ctrl->val;
break;
+ case V4L2_CID_ALPHA_COMPONENT:
+ spin_lock_irqsave(&ctx->slock, flags);
+ ctx->d_frame.alpha = ctrl->val;
+ break;
+
default:
v4l2_err(fimc->v4l2_dev, "Invalid control: 0x%X\n", ctrl->id);
return -EINVAL;
@@ -806
