Re: [PATCH v2 5/8] arm64: dts: mediatek: Add Video Encoder for MT8173

2015-12-15 Thread tiffany lin 
Hi Matthias,

On Mon, 2015-12-14 at 19:18 +0100, Matthias Brugger wrote:
> On Friday 11 Dec 2015 17:55:40 Tiffany Lin wrote:
> > Add video encoder node for MT8173
> > 
> > Signed-off-by: Tiffany Lin 
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8173.dtsi |   47
> > ++ 1 file changed, 47 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index b8c8ff0..a6b0fcf 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -545,6 +545,53 @@
> > #clock-cells = <1>;
> > };
> > 
> > +   larb3: larb@18001000 {
> > +   compatible = "mediatek,mt8173-smi-larb";
> > +   reg = <0 0x18001000 0 0x1000>;
> > +   mediatek,smi = <_common>;
> > +   power-domains = < MT8173_POWER_DOMAIN_VENC>;
> > +   clocks = < CLK_VENC_CKE1>,
> > +< CLK_VENC_CKE0>;
> > +   clock-names = "apb", "smi";
> > +   };
> > +
> > +   vcodec_enc: vcodec@18002000 {
> > +   compatible = "mediatek,mt8173-vcodec-enc";
> > +   reg = <0 0x18002000 0 0x1000>,  /* VENC_SYS */
> > + <0 0x19002000 0 0x1000>;  /* VENC_LT_SYS */
> > +   interrupts = ,
> > +;
> > +   larb = <>,
> > +  <>;
> 
> should be mediatek,larb or just larb for all instances of the larb's.
> See my other email about the bindings.
> 
Yes, it should be mediatek,larb.
We will fix this and mediatek,vpu in next version.

best regards,
Tiffany

> Regards,
> Matthias
> 
> > +   iommus = < M4U_LARB3_ID M4U_PORT_VENC_RCPU>,
> > +< M4U_LARB3_ID M4U_PORT_VENC_REC>,
> > +< M4U_LARB3_ID M4U_PORT_VENC_BSDMA>,
> > +< M4U_LARB3_ID M4U_PORT_VENC_SV_COMV>,
> > +< M4U_LARB3_ID M4U_PORT_VENC_RD_COMV>,
> > +< M4U_LARB3_ID M4U_PORT_VENC_CUR_LUMA>,
> > +< M4U_LARB3_ID M4U_PORT_VENC_CUR_CHROMA>,
> > +< M4U_LARB3_ID M4U_PORT_VENC_REF_LUMA>,
> > +< M4U_LARB3_ID M4U_PORT_VENC_REF_CHROMA>,
> > +< M4U_LARB3_ID M4U_PORT_VENC_NBM_RDMA>,
> > +< M4U_LARB3_ID M4U_PORT_VENC_NBM_WDMA>,
> > +< M4U_LARB5_ID M4U_PORT_VENC_RCPU_SET2>,
> > +< M4U_LARB5_ID 
> > M4U_PORT_VENC_REC_FRM_SET2>,
> > +< M4U_LARB5_ID M4U_PORT_VENC_BSDMA_SET2>,
> > +< M4U_LARB5_ID 
> > M4U_PORT_VENC_SV_COMA_SET2>,
> > +< M4U_LARB5_ID 
> > M4U_PORT_VENC_RD_COMA_SET2>,
> > +< M4U_LARB5_ID 
> > M4U_PORT_VENC_CUR_LUMA_SET2>,
> > +< M4U_LARB5_ID 
> > M4U_PORT_VENC_CUR_CHROMA_SET2>,
> > +< M4U_LARB5_ID 
> > M4U_PORT_VENC_REF_LUMA_SET2>,
> > +< M4U_LARB5_ID 
> > M4U_PORT_VENC_REC_CHROMA_SET2>;
> > +   vpu = <>;
> > +   clocks = < CLK_APMIXED_VENCPLL>,
> > +< CLK_TOP_VENC_LT_SEL>,
> > +< CLK_TOP_VCODECPLL_370P5>;
> > +   clock-names = "vencpll",
> > + "venc_lt_sel",
> > + "vcodecpll_370p5_ck";
> > +   };
> > +
> > vencltsys: clock-controller@1900 {
> > compatible = "mediatek,mt8173-vencltsys", "syscon";
> > reg = <0 0x1900 0 0x1000>;
> 


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Re: [PATCH v2 5/8] arm64: dts: mediatek: Add Video Encoder for MT8173

2015-12-14 Thread Matthias Brugger 
On Friday 11 Dec 2015 17:55:40 Tiffany Lin wrote:
> Add video encoder node for MT8173
> 
> Signed-off-by: Tiffany Lin 
> ---
>  arch/arm64/boot/dts/mediatek/mt8173.dtsi |   47
> ++ 1 file changed, 47 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index b8c8ff0..a6b0fcf 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -545,6 +545,53 @@
>   #clock-cells = <1>;
>   };
> 
> + larb3: larb@18001000 {
> + compatible = "mediatek,mt8173-smi-larb";
> + reg = <0 0x18001000 0 0x1000>;
> + mediatek,smi = <_common>;
> + power-domains = < MT8173_POWER_DOMAIN_VENC>;
> + clocks = < CLK_VENC_CKE1>,
> +  < CLK_VENC_CKE0>;
> + clock-names = "apb", "smi";
> + };
> +
> + vcodec_enc: vcodec@18002000 {
> + compatible = "mediatek,mt8173-vcodec-enc";
> + reg = <0 0x18002000 0 0x1000>,  /* VENC_SYS */
> +   <0 0x19002000 0 0x1000>;  /* VENC_LT_SYS */
> + interrupts = ,
> +  ;
> + larb = <>,
> +<>;

should be mediatek,larb or just larb for all instances of the larb's.
See my other email about the bindings.

Regards,
Matthias

> + iommus = < M4U_LARB3_ID M4U_PORT_VENC_RCPU>,
> +  < M4U_LARB3_ID M4U_PORT_VENC_REC>,
> +  < M4U_LARB3_ID M4U_PORT_VENC_BSDMA>,
> +  < M4U_LARB3_ID M4U_PORT_VENC_SV_COMV>,
> +  < M4U_LARB3_ID M4U_PORT_VENC_RD_COMV>,
> +  < M4U_LARB3_ID M4U_PORT_VENC_CUR_LUMA>,
> +  < M4U_LARB3_ID M4U_PORT_VENC_CUR_CHROMA>,
> +  < M4U_LARB3_ID M4U_PORT_VENC_REF_LUMA>,
> +  < M4U_LARB3_ID M4U_PORT_VENC_REF_CHROMA>,
> +  < M4U_LARB3_ID M4U_PORT_VENC_NBM_RDMA>,
> +  < M4U_LARB3_ID M4U_PORT_VENC_NBM_WDMA>,
> +  < M4U_LARB5_ID M4U_PORT_VENC_RCPU_SET2>,
> +  < M4U_LARB5_ID 
> M4U_PORT_VENC_REC_FRM_SET2>,
> +  < M4U_LARB5_ID M4U_PORT_VENC_BSDMA_SET2>,
> +  < M4U_LARB5_ID 
> M4U_PORT_VENC_SV_COMA_SET2>,
> +  < M4U_LARB5_ID 
> M4U_PORT_VENC_RD_COMA_SET2>,
> +  < M4U_LARB5_ID 
> M4U_PORT_VENC_CUR_LUMA_SET2>,
> +  < M4U_LARB5_ID 
> M4U_PORT_VENC_CUR_CHROMA_SET2>,
> +  < M4U_LARB5_ID 
> M4U_PORT_VENC_REF_LUMA_SET2>,
> +  < M4U_LARB5_ID 
> M4U_PORT_VENC_REC_CHROMA_SET2>;
> + vpu = <>;
> + clocks = < CLK_APMIXED_VENCPLL>,
> +  < CLK_TOP_VENC_LT_SEL>,
> +  < CLK_TOP_VCODECPLL_370P5>;
> + clock-names = "vencpll",
> +   "venc_lt_sel",
> +   "vcodecpll_370p5_ck";
> + };
> +
>   vencltsys: clock-controller@1900 {
>   compatible = "mediatek,mt8173-vencltsys", "syscon";
>   reg = <0 0x1900 0 0x1000>;

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[PATCH v2 5/8] arm64: dts: mediatek: Add Video Encoder for MT8173

2015-12-11 Thread Tiffany Lin 
Add video encoder node for MT8173

Signed-off-by: Tiffany Lin 
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi |   47 ++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index b8c8ff0..a6b0fcf 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -545,6 +545,53 @@
#clock-cells = <1>;
};
 
+   larb3: larb@18001000 {
+   compatible = "mediatek,mt8173-smi-larb";
+   reg = <0 0x18001000 0 0x1000>;
+   mediatek,smi = <_common>;
+   power-domains = < MT8173_POWER_DOMAIN_VENC>;
+   clocks = < CLK_VENC_CKE1>,
+< CLK_VENC_CKE0>;
+   clock-names = "apb", "smi";
+   };
+
+   vcodec_enc: vcodec@18002000 {
+   compatible = "mediatek,mt8173-vcodec-enc";
+   reg = <0 0x18002000 0 0x1000>,  /* VENC_SYS */
+ <0 0x19002000 0 0x1000>;  /* VENC_LT_SYS */
+   interrupts = ,
+;
+   larb = <>,
+  <>;
+   iommus = < M4U_LARB3_ID M4U_PORT_VENC_RCPU>,
+< M4U_LARB3_ID M4U_PORT_VENC_REC>,
+< M4U_LARB3_ID M4U_PORT_VENC_BSDMA>,
+< M4U_LARB3_ID M4U_PORT_VENC_SV_COMV>,
+< M4U_LARB3_ID M4U_PORT_VENC_RD_COMV>,
+< M4U_LARB3_ID M4U_PORT_VENC_CUR_LUMA>,
+< M4U_LARB3_ID M4U_PORT_VENC_CUR_CHROMA>,
+< M4U_LARB3_ID M4U_PORT_VENC_REF_LUMA>,
+< M4U_LARB3_ID M4U_PORT_VENC_REF_CHROMA>,
+< M4U_LARB3_ID M4U_PORT_VENC_NBM_RDMA>,
+< M4U_LARB3_ID M4U_PORT_VENC_NBM_WDMA>,
+< M4U_LARB5_ID M4U_PORT_VENC_RCPU_SET2>,
+< M4U_LARB5_ID 
M4U_PORT_VENC_REC_FRM_SET2>,
+< M4U_LARB5_ID M4U_PORT_VENC_BSDMA_SET2>,
+< M4U_LARB5_ID 
M4U_PORT_VENC_SV_COMA_SET2>,
+< M4U_LARB5_ID 
M4U_PORT_VENC_RD_COMA_SET2>,
+< M4U_LARB5_ID 
M4U_PORT_VENC_CUR_LUMA_SET2>,
+< M4U_LARB5_ID 
M4U_PORT_VENC_CUR_CHROMA_SET2>,
+< M4U_LARB5_ID 
M4U_PORT_VENC_REF_LUMA_SET2>,
+< M4U_LARB5_ID 
M4U_PORT_VENC_REC_CHROMA_SET2>;
+   vpu = <>;
+   clocks = < CLK_APMIXED_VENCPLL>,
+< CLK_TOP_VENC_LT_SEL>,
+< CLK_TOP_VCODECPLL_370P5>;
+   clock-names = "vencpll",
+ "venc_lt_sel",
+ "vcodecpll_370p5_ck";
+   };
+
vencltsys: clock-controller@1900 {
compatible = "mediatek,mt8173-vencltsys", "syscon";
reg = <0 0x1900 0 0x1000>;
-- 
1.7.9.5

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