RE: [RFC/PATCH v7 2/5] MFC: Add MFC 5.1 driver to plat-s5p
Kamil Debski wrote:
This patch adds platform support for Multi Format Codec 5.1.
MFC 5.1 is capable of handling a range of video codecs and this driver
provides V4L2 interface for video decoding.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-s5pv310/clock.c | 28 -
arch/arm/mach-s5pv310/include/mach/map.h|2 +
arch/arm/mach-s5pv310/include/mach/regs-clock.h |3 +
arch/arm/plat-s5p/Kconfig |5 ++
arch/arm/plat-s5p/Makefile |2 +-
arch/arm/plat-s5p/dev-mfc.c | 49
+++
arch/arm/plat-samsung/include/plat/devs.h |1 +
7 files changed, 88 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/plat-s5p/dev-mfc.c
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index f142b8c..d28fa6f 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -523,6 +523,11 @@ static struct clk init_clocks_off[] = {
.enable = s5pv310_clk_ip_lcd1_ctrl,
.ctrlbit= (1 0),
}, {
+ .name = mfc,
+ .id = -1,
+ .enable = s5pv310_clk_ip_mfc_ctrl,
Where is s5pv310_clk_ip_mfc_ctrl in your patch or mainline?
Please make sure that your patch can be applied into current maintainer's
tree before submitting.
+ .ctrlbit= (1 0),
+ }, {
.name = hsmmc,
.id = 0,
.parent = clk_aclk_133.clk,
@@ -734,6 +739,18 @@ static struct clksrc_sources clkset_group = {
.nr_sources = ARRAY_SIZE(clkset_group_list),
};
+static struct clk *clkset_group1_list[] = {
What group1? We can know it is used for MFC now, but if there is in just
clock.c, can't do it.
+ [0] = clk_mout_mpll.clk,
+ [1] = clk_sclk_apll.clk,
+ [2] = clk_mout_epll.clk,
+ [3] = clk_sclk_vpll.clk,
As you know, above sources are not connected to one same MUX, so should be
separated.
+};
+
+static struct clksrc_sources clkset_group1 = {
+ .sources= clkset_group1_list,
+ .nr_sources = ARRAY_SIZE(clkset_group1_list),
+};
+
static struct clk *clkset_mout_g2d0_list[] = {
[0] = clk_mout_mpll.clk,
[1] = clk_sclk_apll.clk,
@@ -1076,7 +1093,16 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit= (1 16),
},
.reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8
},
- }
+ }, {
+ .clk= {
+ .name = sclk_mfc,
+ .id = -1,
+ },
+ .sources = clkset_group1,
+ .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
+ .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
+ },
+
};
/* Clock initialization code */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-
s5pv310/include/mach/map.h
index 0db3a47..576ba55 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -29,6 +29,7 @@
#define S5PV310_PA_FIMC1 0x1181
#define S5PV310_PA_FIMC2 0x1182
#define S5PV310_PA_FIMC3 0x1183
+#define S5PV310_PA_MFC 0x1340
#define S5PV310_PA_I2S0 0x0383
#define S5PV310_PA_I2S1 0xE310
#define S5PV310_PA_I2S2 0xE2A0
@@ -129,6 +130,7 @@
#define S5P_PA_FIMC1 S5PV310_PA_FIMC1
#define S5P_PA_FIMC2 S5PV310_PA_FIMC2
#define S5P_PA_FIMC3 S5PV310_PA_FIMC3
+#define S5P_PA_MFC S5PV310_PA_MFC
#define S5P_PA_ONENAND S5PC210_PA_ONENAND
#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
#define S5P_PA_SDRAM S5PV310_PA_SDRAM
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
b/arch/arm/mach-
s5pv310/include/mach/regs-clock.h
index 9ef5f0c..f6b8181 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -176,4 +176,7 @@
#define S5P_EPLL_CON S5P_EPLL_CON0
+/* MFC related */
+#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
+#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528)
#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 4166964..ea9032e 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -5,6 +5,11 @@
#
# Licensed under GPLv2
+config S5P_DEV_MFC
+ bool
+ help
+ Compile in platform device definitions for MFC
+
[RFC/PATCH v7 2/5] MFC: Add MFC 5.1 driver to plat-s5p
This patch adds platform support for Multi Format Codec 5.1.
MFC 5.1 is capable of handling a range of video codecs and this driver
provides V4L2 interface for video decoding.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-s5pv310/clock.c | 28 -
arch/arm/mach-s5pv310/include/mach/map.h|2 +
arch/arm/mach-s5pv310/include/mach/regs-clock.h |3 +
arch/arm/plat-s5p/Kconfig |5 ++
arch/arm/plat-s5p/Makefile |2 +-
arch/arm/plat-s5p/dev-mfc.c | 49 +++
arch/arm/plat-samsung/include/plat/devs.h |1 +
7 files changed, 88 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/plat-s5p/dev-mfc.c
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index f142b8c..d28fa6f 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -523,6 +523,11 @@ static struct clk init_clocks_off[] = {
.enable = s5pv310_clk_ip_lcd1_ctrl,
.ctrlbit= (1 0),
}, {
+ .name = mfc,
+ .id = -1,
+ .enable = s5pv310_clk_ip_mfc_ctrl,
+ .ctrlbit= (1 0),
+ }, {
.name = hsmmc,
.id = 0,
.parent = clk_aclk_133.clk,
@@ -734,6 +739,18 @@ static struct clksrc_sources clkset_group = {
.nr_sources = ARRAY_SIZE(clkset_group_list),
};
+static struct clk *clkset_group1_list[] = {
+ [0] = clk_mout_mpll.clk,
+ [1] = clk_sclk_apll.clk,
+ [2] = clk_mout_epll.clk,
+ [3] = clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources clkset_group1 = {
+ .sources= clkset_group1_list,
+ .nr_sources = ARRAY_SIZE(clkset_group1_list),
+};
+
static struct clk *clkset_mout_g2d0_list[] = {
[0] = clk_mout_mpll.clk,
[1] = clk_sclk_apll.clk,
@@ -1076,7 +1093,16 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit= (1 16),
},
.reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
- }
+ }, {
+ .clk= {
+ .name = sclk_mfc,
+ .id = -1,
+ },
+ .sources = clkset_group1,
+ .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
+ .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
+ },
+
};
/* Clock initialization code */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h
b/arch/arm/mach-s5pv310/include/mach/map.h
index 0db3a47..576ba55 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -29,6 +29,7 @@
#define S5PV310_PA_FIMC1 0x1181
#define S5PV310_PA_FIMC2 0x1182
#define S5PV310_PA_FIMC3 0x1183
+#define S5PV310_PA_MFC 0x1340
#define S5PV310_PA_I2S00x0383
#define S5PV310_PA_I2S10xE310
#define S5PV310_PA_I2S20xE2A0
@@ -129,6 +130,7 @@
#define S5P_PA_FIMC1 S5PV310_PA_FIMC1
#define S5P_PA_FIMC2 S5PV310_PA_FIMC2
#define S5P_PA_FIMC3 S5PV310_PA_FIMC3
+#define S5P_PA_MFC S5PV310_PA_MFC
#define S5P_PA_ONENAND S5PC210_PA_ONENAND
#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
#define S5P_PA_SDRAM S5PV310_PA_SDRAM
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
index 9ef5f0c..f6b8181 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -176,4 +176,7 @@
#define S5P_EPLL_CON S5P_EPLL_CON0
+/* MFC related */
+#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
+#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528)
#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 4166964..ea9032e 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -5,6 +5,11 @@
#
# Licensed under GPLv2
+config S5P_DEV_MFC
+ bool
+ help
+ Compile in platform device definitions for MFC
+
config PLAT_S5P
bool
depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 ||
ARCH_S5PV210 || ARCH_S5PV310)
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index cfcd1db..54e330d 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -24,7 +24,7 @@ obj-$(CONFIG_SUSPEND) += pm.o
obj-$(CONFIG_SUSPEND) += irq-pm.o
#
