Re: Connecting ADV76xx to CSI via SFMC
Hi Jean-Michel, Am Montag, den 24.11.2014, 16:19 +0100 schrieb Jean-Michel Hautbois: Hi, I am working on using the CSI bus of i.MX6 with a adv7611 chip. I started to work with Steve Longerbeam's tree, and here is the current tree I am using : https://github.com/Vodalys/linux-2.6-imx/tree/mx6-camera-staging-v2-vbx This is a WiP tree, and not intended to be complete right now. But at least, it should be possible to get a picture. I will try to be as complete and synthetic as possible... Right now, I am configuring the ADV7611 in 16-Bit SDR ITU-R BT.656 4:2:2 Mode 0 (Table 73 in Appendix C of the Reference Manual). ITU-R BT.656 only specifies 8-bit (or 10-bit) streams, the 16-bit BT.656 SDR/DDR modes with two values on the bus at the same time are somewhat nonstandard. As far as I can tell, this mode should correspond to the CSI's BT.1120 SDR mode (Figure 37-20 in MX6DQ Reference Manual v1), so I'd expect CSI_SENS_CONF to be configured as DATA_WIDTH=1 (8-bit components), SENS_DATA_FORMAT=1 (YUV422), SENS_PRCTL=5 (progressive BT.1120 SDR). regards Philipp -- To unsubscribe from this list: send the line unsubscribe linux-media in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Connecting ADV76xx to CSI via SFMC
Hi Philipp,
Thanks for answering.
2014-11-25 9:16 GMT+01:00 Philipp Zabel p.za...@pengutronix.de:
Hi Jean-Michel,
Am Montag, den 24.11.2014, 16:19 +0100 schrieb Jean-Michel Hautbois:
Hi,
I am working on using the CSI bus of i.MX6 with a adv7611 chip.
I started to work with Steve Longerbeam's tree, and here is the
current tree I am using :
https://github.com/Vodalys/linux-2.6-imx/tree/mx6-camera-staging-v2-vbx
This is a WiP tree, and not intended to be complete right now.
But at least, it should be possible to get a picture.
I will try to be as complete and synthetic as possible...
Right now, I am configuring the ADV7611 in 16-Bit SDR ITU-R BT.656
4:2:2 Mode 0 (Table 73 in Appendix C of the Reference Manual).
ITU-R BT.656 only specifies 8-bit (or 10-bit) streams, the 16-bit BT.656
SDR/DDR modes with two values on the bus at the same time are somewhat
nonstandard. As far as I can tell, this mode should correspond to the
CSI's BT.1120 SDR mode (Figure 37-20 in MX6DQ Reference Manual v1), so
I'd expect CSI_SENS_CONF to be configured as DATA_WIDTH=1 (8-bit
components), SENS_DATA_FORMAT=1 (YUV422), SENS_PRCTL=5 (progressive
BT.1120 SDR).
OK, so I tested in a brutal way :
diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c
index 293262d..ff48819 100644
--- a/drivers/gpu/ipu-v3/ipu-csi.c
+++ b/drivers/gpu/ipu-v3/ipu-csi.c
@@ -342,10 +342,16 @@ static void fill_csi_bus_cfg(struct
ipu_csi_bus_config *csicfg,
break;
case V4L2_MBUS_BT656:
csicfg-ext_vsync = 0;
- if (V4L2_FIELD_HAS_BOTH(mbus_fmt-field))
- csicfg-clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
+ if (mbus_fmt-code == V4L2_MBUS_FMT_YUYV8_2X8)
+ if (V4L2_FIELD_HAS_BOTH(mbus_fmt-field))
+ csicfg-clk_mode =
IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR;
+ else
+ csicfg-clk_mode =
IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR;
else
- csicfg-clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
+ if (V4L2_FIELD_HAS_BOTH(mbus_fmt-field))
+ csicfg-clk_mode =
IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
+ else
+ csicfg-clk_mode =
IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
break;
case V4L2_MBUS_CSI2:
And before launching capture, I configure manually register 0x3 of
ADV7611 in order to have the SDR 4:2:2 mode I want.
It works better, but still have a little issue :
I am expecting : 0x23 0x72 0x23 0xd4 ...
I am getting : 0x23 0xc8 0x23 0x50
If I take binary values :
0x72 = 01110010b
0xc8 = 11001000b = 0x72 2
0xd4 = 11010100
0x50 = 0101 = 0xd4 2
In my DT, I have specified :
csi0: endpoint@0 {
reg = 0;
bus-width = 16;
data-shift = 4; /* Lines 19:4 used */
};
pinctrl_ipu1_csi0: ipu1_csi0grp {
fsl,pins =
MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x8000
MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x8000
MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x8000
MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x8000
MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x8000
MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x8000
MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x8000
MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x8000
MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x8000
MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x8000
MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x8000
MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x8000
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x8000
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x8000
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x8000
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x8000
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x8000
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x8000
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x8000
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x8000
/* Clock and Data only : BT.656 mode */
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x8000
/*MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x8000
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x8000
MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x8000*/
;
};
Can it be linked to the data-shift ?
Thanks again.
Regards,
JM
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Connecting ADV76xx to CSI via SFMC
Hi, I am working on using the CSI bus of i.MX6 with a adv7611 chip. I started to work with Steve Longerbeam's tree, and here is the current tree I am using : https://github.com/Vodalys/linux-2.6-imx/tree/mx6-camera-staging-v2-vbx This is a WiP tree, and not intended to be complete right now. But at least, it should be possible to get a picture. I will try to be as complete and synthetic as possible... Right now, I am configuring the ADV7611 in 16-Bit SDR ITU-R BT.656 4:2:2 Mode 0 (Table 73 in Appendix C of the Reference Manual). This means that I have pins [15:8] = [Y7..Y0] and [7:0]=[Cb7,Cr7..Cb0,Cr0]. On my board, thanks to a FPGA, pin 15 is connected to MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 and pin 0 to MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04. In the source code, I am asking for a 4:2:2 YUYV packed format. Then, when starting the board, I am doing the following : $ v4l2-ctl -d2 --set-fmt-video=width=1280,height=720,pixelformat=YUYV,field=none,bytesperline=2560 -i3 $ v4l2-ctl -d2 --set-dv-bt-timings index=4 -i3 $ [ 69.360256] adv7611 1-004c: -Chip status- [ 69.365652] adv7611 1-004c: Chip power: on [ 69.370446] adv7611 1-004c: EDID enabled port A: No, B: No, C: No, D: No [ 69.378110] adv7611 1-004c: CEC: disabled [ 69.382132] adv7611 1-004c: -Signal status- [ 69.387722] adv7611 1-004c: Cable detected (+5V power) port A: No, B: No, C: No, D: No [ 69.396344] adv7611 1-004c: TMDS signal detected: false [ 69.402245] adv7611 1-004c: TMDS signal locked: false [ 69.408015] adv7611 1-004c: SSPD locked: true [ 69.413047] adv7611 1-004c: STDI locked: false [ 69.417529] adv7611 1-004c: CP locked: true [ 69.422402] adv7611 1-004c: CP free run: on [ 69.429013] adv7611 1-004c: Prim-mode = 0x5, video std = 0x13, v_freq = 0x1 [ 69.436022] adv7611 1-004c: -Video Timings- [ 69.441594] adv7611 1-004c: STDI: not locked [ 69.449212] adv7611 1-004c: No video detected [ 69.453587] adv7611 1-004c: Configured format: 1280x720p50 (1980x750) [ 69.460066] adv7611 1-004c: horizontal: fp = 440, +sync = 40, bp = 220 [ 69.466637] adv7611 1-004c: vertical: fp = 5, +sync = 5, bp = 20 [ 69.472653] adv7611 1-004c: pixelclock: 7425 [ 69.477300] adv7611 1-004c: flags (0x0): [ 69.481233] adv7611 1-004c: standards (0x1): CEA [ 69.490112] adv7604 1-0020: -Chip status- I keep the ADV7611 running in Free mode, which produces a blue frame, with Y=0x23 and Cr=0x72, Cb=0xD4. Now, I try to capture a frame : $ v4l2-ctl -d2 --stream-mmap --stream-to x.raw --stream-count=1 I don't get anything, and here is the dmesg : [ 187.191644] imx-ipuv3 240.ipu: CSI_SENS_CONF = 0x4920 [ 187.191849] imx-ipuv3 240.ipu: CSI_ACT_FRM_SIZE = 0x02CF04FF [ 187.200454] ipu_cpmem_set_image: resolution: 1280x720 stride: 2560 [ 187.200472] ipu_ch_param_write_field 0 125 13 [ 187.200486] ipu_ch_param_write_field 0 138 12 [ 187.200498] ipu_ch_param_write_field 1 102 14 [ 187.200510] ipu_ch_param_write_field 0 107 3 [ 187.200521] ipu_ch_param_write_field 1 85 4 [ 187.200532] ipu_ch_param_write_field 1 78 7 [ 187.200543] ipu_ch_param_write_field 1 0 29 [ 187.200554] ipu_ch_param_write_field 1 29 29 [ 187.200566] ipu_ch_param_write_field 1 78 7 [ 187.200586] ipu_ch_param_write_field 1 93 2 [ 187.201077] mx6-camera-encoder: Enable CSI [ 187.205206] imx-ipuv3 240.ipu: ch 0 word 0 - E0001800 000B3C9F [ 187.205226] imx-ipuv3 240.ipu: ch 0 word 1 - 09E6 013D4000 0103C000 00027FC0 [ 187.205240] ipu_ch_param_read_field 1 85 4 [ 187.205254] imx-ipuv3 240.ipu: PFS 0x8, [ 187.205265] ipu_ch_param_read_field 0 107 3 [ 187.205278] imx-ipuv3 240.ipu: BPP 0x3, [ 187.205289] ipu_ch_param_read_field 1 78 7 [ 187.205302] imx-ipuv3 240.ipu: NPB 0xf [ 187.205313] ipu_ch_param_read_field 0 125 13 [ 187.205326] imx-ipuv3 240.ipu: FW 1279, [ 187.205337] ipu_ch_param_read_field 0 138 12 [ 187.205350] imx-ipuv3 240.ipu: FH 719, [ 187.205361] ipu_ch_param_read_field 1 0 29 [ 187.205374] imx-ipuv3 240.ipu: EBA0 0x4f30 [ 187.205385] ipu_ch_param_read_field 1 29 29 [ 187.205398] imx-ipuv3 240.ipu: EBA1 0x4f50 [ 187.205409] ipu_ch_param_read_field 1 102 14 [ 187.205422] imx-ipuv3 240.ipu: Stride 2559 [ 187.205433] ipu_ch_param_read_field 0 113 1 [ 187.205445] imx-ipuv3 240.ipu: scan_order 0 [ 187.205456] ipu_ch_param_read_field 1 128 14 [ 187.205469] imx-ipuv3 240.ipu: uv_stride 0 [ 187.205480] ipu_ch_param_read_field 0 46 22 [ 187.205492] imx-ipuv3 240.ipu: u_offset 0x0 [ 187.205541] ipu_ch_param_read_field 0 68 22 [ 187.205557] imx-ipuv3 240.ipu: v_offset 0x0 [ 187.205568] ipu_ch_param_read_field 1 116 3 [ 187.205581] imx-ipuv3 240.ipu: Width0 0+1, [ 187.205592] ipu_ch_param_read_field 1 119 3 [ 187.205604] imx-ipuv3 240.ipu: Width1 0+1, [ 187.205615] ipu_ch_param_read_field 1 122 3 [
