Re: FYI - Frankencamera is open source, runs on Linux

2009-09-06 Thread Eino-Ville Talvala



Have you seen this post on N95 camera using linux by Stanford Team -
http://news.cnet.com/8301-17938_105-10345557-1.html

Is this running on OMAP?--



The board in the youtube video looks a lot like the omap3evm, so I 
guess it's safe to say it's omap3 based.


regards,

Koen

I'm one of the graduate students at Stanford working on this project.

Yes, we're using an OMAP3 EVM (needed the camera interface pins) 
connected to a small custom daughtercard that interfaces to an Elphel 
10338 camera tile, with an Aptina MT9P031 on it.  Plus a bunch of other 
off-the-shelf hardware, but the OMAP3 is at the heart of it.


Eino-Ville (Eddy) Talvala
Graduate Research Assistant
Stanford University
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[PATCH]Optimize the delay in MMC power sequence

2009-09-06 Thread Madhusudhan Chikkature
commit 004a049bbab47d382a741d8e8fc6a1b9b44b36ac
Author: Madhu madhu...@ti.com
Date:   Sun Sep 6 13:18:21 2009 -0400

Replace the 100mS delay in the MMC power sequence with an appropriate delay
based on the measurements taken for VDDS stability on SDP with T2 power IC.
The delay in the power down sequence is not needed since it is taken care in
the power up sequence.

Signed-off-by: Madhusudhan Chikkature madhu...@ti.com

diff --git a/arch/arm/mach-omap2/mmc-twl4030.c 
b/arch/arm/mach-omap2/mmc-twl4030.c
index 3c04c2f..6a9be61 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -237,30 +237,27 @@ static int twl_mmc1_set_power(struct device *dev, int
slot, int power_on,
reg = ~OMAP2_PBIASLITEPWRDNZ0;
omap_ctrl_writel(reg, control_pbias_offset);

-   ret = mmc_regulator_set_ocr(c-vcc, vdd);
-
-   /* 100ms delay required for PBIAS configuration */
-   msleep(100);
reg = omap_ctrl_readl(control_pbias_offset);
-   reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
if ((1  vdd) = MMC_VDD_165_195)
reg = ~OMAP2_PBIASLITEVMODE0;
else
reg |= OMAP2_PBIASLITEVMODE0;
omap_ctrl_writel(reg, control_pbias_offset);
+
+   ret = mmc_regulator_set_ocr(c-vcc, vdd);
+
+   /* 400uS required for VDDS to stable */
+   udelay(400);
+
+   reg = omap_ctrl_readl(control_pbias_offset);
+   reg |= OMAP2_PBIASLITEPWRDNZ0;
+   omap_ctrl_writel(reg, control_pbias_offset);
} else {
reg = omap_ctrl_readl(control_pbias_offset);
reg = ~OMAP2_PBIASLITEPWRDNZ0;
omap_ctrl_writel(reg, control_pbias_offset);

ret = mmc_regulator_set_ocr(c-vcc, 0);
-
-   /* 100ms delay required for PBIAS configuration */
-   msleep(100);
-   reg = omap_ctrl_readl(control_pbias_offset);
-   reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
-   OMAP2_PBIASLITEVMODE0);
-   omap_ctrl_writel(reg, control_pbias_offset);
}

return ret;


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