[PATCH 0/4] ARM: dts: omap5: Cleanup and updates for DT files
uevm is the official board supported for OMAP5 soc in the mainline. This series renames the board dts file for OMAP5 accordingly and cleans up the same. Also a few additional device DT entry updates are done. This is on top of the below branch git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.11/dts Boot tested on omap5-uevm after pulling in the data from below place git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux.git HWMOD DATA: for_3.11/omap5_data_files CLOCK DATA: out_of_tree/omap5_clk_data Dan Murphy (1): ARM: dts: omap5-uevm: Add LED support for uEVM blue LED Roger Quadros (1): ARM: dts: omap5-uevm: Add USB Host support Sourav Poddar (1): ARM: dts: omap5-uevm: Add uart pinctrl data Sricharan R (1): ARM: dts: omap5: Rename omap5-evm to omap5-uevm arch/arm/boot/dts/Makefile |2 +- arch/arm/boot/dts/omap5-evm.dts | 261 --- arch/arm/boot/dts/omap5-uevm.dts | 319 ++ arch/arm/boot/dts/omap5.dtsi | 30 4 files changed, 350 insertions(+), 262 deletions(-) delete mode 100644 arch/arm/boot/dts/omap5-evm.dts create mode 100644 arch/arm/boot/dts/omap5-uevm.dts -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/4] ARM: dts: omap5-uevm: Add uart pinctrl data
From: Sourav Poddar sourav.pod...@ti.com
Booting omap5 uevm results in the following error
did not get pins for uart error: -19
This happens because omap5 uevm dts file is not adapted to use uart through
pinctrl
framework. Populating uart pinctrl data to get rid of the error.
Cc: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
[Sricharan R r.sricha...@ti.com: Replaced constants with preprocessor macros]
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/omap5-uevm.dts | 41 ++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index a2aed5b..e545e64 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -192,6 +192,32 @@
0x196 (PIN_OUTPUT | MUX_MODE6) /*
uart3_cts_rctx.gpio5_153 OUTPUT | MODE6 */
;
};
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins =
+ 0x60 (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts
MODE0 */
+ 0x62 (PIN_INPUT_PULLUP | MUX_MODE0) /*
uart1_tx.uart1_cts INPUT | PULLUP | MODE0 */
+ 0x64 (PIN_INPUT_PULLUP | MUX_MODE0) /*
uart1_rx.uart1_rts INPUT | PULLUP | MODE0 */
+ 0x66 (PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts
MODE0 */
+ ;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins =
+ 0x19a (PIN_OUTPUT | MUX_MODE0) /*
uart3_rts_irsd.uart3_tx_irtx MODE0 */
+ 0x19c (PIN_INPUT_PULLUP | MUX_MODE0) /*
uart3_rx_irrx.uart3_usbb3_hsic INPUT | PULLUP | MODE0 */
+ ;
+ };
+
+ uart5_pins: pinmux_uart5_pins {
+ pinctrl-single,pins =
+ 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /*
uart5_rx.uart5_rx INPUT | PULLUP | MODE0 */
+ 0x172 (PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx
MODE0 */
+ 0x174 (PIN_INPUT_PULLUP | MUX_MODE0) /*
uart5_cts.uart5_rts INPUT | PULLUP | MODE0 */
+ 0x176 (PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts
MODE0 */
+ ;
+ };
+
};
omap5_pmx_wkup {
@@ -276,3 +302,18 @@
pinctrl-names = default;
pinctrl-0 = mcspi4_pins;
};
+
+uart1 {
+pinctrl-names = default;
+pinctrl-0 = uart1_pins;
+};
+
+uart3 {
+pinctrl-names = default;
+pinctrl-0 = uart3_pins;
+};
+
+uart5 {
+pinctrl-names = default;
+pinctrl-0 = uart5_pins;
+};
--
1.7.9.5
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[PATCH 3/4] ARM: dts: omap5-uevm: Add LED support for uEVM blue LED
From: Dan Murphy dmur...@ti.com
Add support for blue LED 1 off of GPIO 153.
Make the LED a heartbeat LED
Configure the MUX for GPIO output.
Cc: Dan Murphy dmur...@ti.com
Signed-off-by: Dan Murphy dmur...@ti.com
[Sricharan R r.sricha...@ti.com: Replaced constants with preprocessor macros]
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/omap5-uevm.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index cf862df..a2aed5b 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -66,6 +66,16 @@
device = hsusb2_phy;
clock-frequency = 1920; /* 19.2 MHz */
};
+
+ leds {
+ compatible = gpio-leds;
+ led@1 {
+ label = omap5:blue:usr1;
+ gpios = gpio5 25 GPIO_ACTIVE_HIGH; /* gpio5_153 D1
LED */
+ linux,default-trigger = heartbeat;
+ default-state = off;
+ };
+ };
};
omap5_pmx_core {
@@ -77,6 +87,7 @@
mcbsp1_pins
mcbsp2_pins
usbhost_pins
+ led_gpio_pins
;
twl6040_pins: pinmux_twl6040_pins {
@@ -175,6 +186,12 @@
0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 OUTPUT | MODE
6 ETH_NRESET */
;
};
+
+ led_gpio_pins: pinmux_led_gpio_pins {
+ pinctrl-single,pins =
+ 0x196 (PIN_OUTPUT | MUX_MODE6) /*
uart3_cts_rctx.gpio5_153 OUTPUT | MODE6 */
+ ;
+ };
};
omap5_pmx_wkup {
--
1.7.9.5
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[PATCH 2/4] ARM: dts: omap5-uevm: Add USB Host support
From: Roger Quadros rog...@ti.com
Provide the RESET regulators for the USB PHYs, the USB Host
port modes and the PHY devices.
Also provide pin multiplexer information for the USB host
pins.
Cc: Roger Quadros rog...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
[Sricharan R r.sricha...@ti.com: Replaced constants with preprocessor macros]
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/omap5-uevm.dts | 77 ++
arch/arm/boot/dts/omap5.dtsi | 30 +++
2 files changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 843a001..cf862df 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -25,6 +25,47 @@
regulator-max-microvolt = 300;
};
+ /* HS USB Port 2 RESET */
+ hsusb2_reset: hsusb2_reset_reg {
+ compatible = regulator-fixed;
+ regulator-name = hsusb2_reset;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ gpio = gpio3 16 GPIO_ACTIVE_HIGH; /* gpio3_80 HUB_NRESET */
+ startup-delay-us = 7;
+ enable-active-high;
+ };
+
+ /* HS USB Host PHY on PORT 2 */
+ hsusb2_phy: hsusb2_phy {
+ compatible = usb-nop-xceiv;
+ reset-supply = hsusb2_reset;
+ };
+
+ /* HS USB Port 3 RESET */
+ hsusb3_reset: hsusb3_reset_reg {
+ compatible = regulator-fixed;
+ regulator-name = hsusb3_reset;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ gpio = gpio3 15 GPIO_ACTIVE_HIGH; /* gpio3_79 ETH_NRESET */
+ startup-delay-us = 7;
+ enable-active-high;
+ };
+
+ /* HS USB Host PHY on PORT 3 */
+ hsusb3_phy: hsusb3_phy {
+ compatible = usb-nop-xceiv;
+ reset-supply = hsusb3_reset;
+ };
+
+ /* hsusb2_phy is clocked by FREF_CLK1 i.e. auxclk1 */
+ clock_alias {
+ clock-name = auxclk1_ck;
+ clock-alias = main_clk;
+ device = hsusb2_phy;
+ clock-frequency = 1920; /* 19.2 MHz */
+ };
};
omap5_pmx_core {
@@ -35,6 +76,7 @@
dmic_pins
mcbsp1_pins
mcbsp2_pins
+ usbhost_pins
;
twl6040_pins: pinmux_twl6040_pins {
@@ -120,6 +162,32 @@
0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */
;
};
+
+ usbhost_pins: pinmux_usbhost_pins {
+ pinctrl-single,pins =
+ 0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe INPUT
| MODE 0 */
+ 0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data INPUT |
MODE 0 */
+
+ 0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe
INPUT | MODE 0 */
+ 0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data INPUT
| MODE 0 */
+
+ 0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 OUTPUT | MODE
6 HUB_NRESET */
+ 0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 OUTPUT | MODE
6 ETH_NRESET */
+ ;
+ };
+};
+
+omap5_pmx_wkup {
+ pinctrl-names = default;
+ pinctrl-0 =
+ usbhost_wkup_pins
+ ;
+
+ usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
+ pinctrl-single,pins =
+ 0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out OUTPUT |
MODE 7 for USB hub clk */
+ ;
+ };
};
mmc1 {
@@ -164,6 +232,15 @@
status = disabled;
};
+usbhshost {
+ port2-mode = ehci-hsic;
+ port3-mode = ehci-hsic;
+};
+
+usbhsehci {
+ phys = 0 hsusb2_phy hsusb3_phy;
+};
+
mcspi1 {
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 1e84db8..67d6e1f 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -666,5 +666,35 @@
ctrl-module = omap_control_usb;
};
};
+
+ usbhstll: usbhstll@4a062000 {
+ compatible = ti,usbhs-tll;
+ reg = 0x4a062000 0x1000;
+ interrupts = 0 78 IRQ_TYPE_LEVEL_HIGH;
+ ti,hwmods = usb_tll_hs;
+ };
+
+ usbhshost: usbhshost@4a064000 {
+ compatible = ti,usbhs-host;
+ reg = 0x4a064000 0x800;
+ ti,hwmods = usb_host_hs;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+
+ usbhsohci: ohci@4a064800 {
+ compatible = ti,ohci-omap3,
[PATCH 1/4] ARM: dts: omap5: Rename omap5-evm to omap5-uevm
The uevm is the official board supported for the OMAP5 soc
in mainline. The uevm has an OMAP5432 with a DDR3 memory.
Renaming the board dts file and adding the following cleanups.
* There are no devices connected on I2C 2,3,4 buses. So remove
the pinmux data for the same.
* DDR3 memory is used in the uevm. Neither DVFS or temperature
polling is supported with DDR3. So remove the DDR3 device and
emif nodes.
* Keypad is not supported on uevm. So remove the device node.
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/Makefile |2 +-
arch/arm/boot/dts/omap5-evm.dts | 261 --
arch/arm/boot/dts/omap5-uevm.dts | 184 +++
3 files changed, 185 insertions(+), 262 deletions(-)
delete mode 100644 arch/arm/boot/dts/omap5-evm.dts
create mode 100644 arch/arm/boot/dts/omap5-uevm.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f0895c5..13b86bf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -149,7 +149,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap4-panda-es.dtb \
omap4-var-som.dtb \
omap4-sdp.dtb \
- omap5-evm.dtb \
+ omap5-uevm.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
am335x-bone.dtb
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
deleted file mode 100644
index 22e9ee8..000
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/dts-v1/;
-
-#include omap5.dtsi
-#include samsung_k3pe0e000b.dtsi
-
-/ {
- model = TI OMAP5 EVM board;
- compatible = ti,omap5-evm, ti,omap5;
-
- memory {
- device_type = memory;
- reg = 0x8000 0x7F00; /* 2032 MB */
- };
-
- vmmcsd_fixed: fixedregulator-mmcsd {
- compatible = regulator-fixed;
- regulator-name = vmmcsd_fixed;
- regulator-min-microvolt = 300;
- regulator-max-microvolt = 300;
- };
-
-};
-
-omap5_pmx_core {
- pinctrl-names = default;
- pinctrl-0 =
- twl6040_pins
- mcpdm_pins
- dmic_pins
- mcbsp1_pins
- mcbsp2_pins
- ;
-
- twl6040_pins: pinmux_twl6040_pins {
- pinctrl-single,pins =
- 0x18a (PIN_OUTPUT | MUX_MODE6) /*
perslimbus2_clock.gpio5_145 */
- ;
- };
-
- mcpdm_pins: pinmux_mcpdm_pins {
- pinctrl-single,pins =
- 0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
abe_clks.abe_clks */
- 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
abemcpdm_ul_data.abemcpdm_ul_data */
- 0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
abemcpdm_dl_data.abemcpdm_dl_data */
- 0x160 (PIN_INPUT_PULLUP | MUX_MODE0)/*
abemcpdm_frame.abemcpdm_frame */
- 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
abemcpdm_lb_clk.abemcpdm_lb_clk */
- ;
- };
-
- dmic_pins: pinmux_dmic_pins {
- pinctrl-single,pins =
- 0x144 (PIN_INPUT | MUX_MODE0) /*
abedmic_din1.abedmic_din1 */
- 0x146 (PIN_INPUT | MUX_MODE0) /*
abedmic_din2.abedmic_din2 */
- 0x148 (PIN_INPUT | MUX_MODE0) /*
abedmic_din3.abedmic_din3 */
- 0x14a (PIN_OUTPUT | MUX_MODE0) /*
abedmic_clk1.abedmic_clk1 */
- ;
- };
-
- mcbsp1_pins: pinmux_mcbsp1_pins {
- pinctrl-single,pins =
- 0x14c (PIN_INPUT | MUX_MODE1) /*
abedmic_clk2.abemcbsp1_fsx */
- 0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /*
abedmic_clk3.abemcbsp1_dx */
- 0x150 (PIN_INPUT | MUX_MODE1) /*
abeslimbus1_clock.abemcbsp1_clkx */
- 0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1) /*
abeslimbus1_data.abemcbsp1_dr */
- ;
- };
-
- mcbsp2_pins: pinmux_mcbsp2_pins {
- pinctrl-single,pins =
- 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
abemcbsp2_dr.abemcbsp2_dr */
- 0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /*
abemcbsp2_dx.abemcbsp2_dx */
- 0x158 (PIN_INPUT | MUX_MODE0) /*
abemcbsp2_fsx.abemcbsp2_fsx */
- 0x15a (PIN_INPUT | MUX_MODE0) /*
abemcbsp2_clkx.abemcbsp2_clkx */
- ;
- };
-
- i2c1_pins: pinmux_i2c1_pins {
-
Re: [PATCH 1/4] ARM: dts: omap5: Rename omap5-evm to omap5-uevm
On Wednesday 05 June 2013 12:16 PM, Sricharan R wrote:
The uevm is the official board supported for the OMAP5 soc
in mainline. The uevm has an OMAP5432 with a DDR3 memory.
Renaming the board dts file and adding the following cleanups.
* There are no devices connected on I2C 2,3,4 buses. So remove
the pinmux data for the same.
* DDR3 memory is used in the uevm. Neither DVFS or temperature
polling is supported with DDR3. So remove the DDR3 device and
emif nodes.
* Keypad is not supported on uevm. So remove the device node.
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/Makefile |2 +-
arch/arm/boot/dts/omap5-evm.dts | 261
--
arch/arm/boot/dts/omap5-uevm.dts | 184 +++
3 files changed, 185 insertions(+), 262 deletions(-)
delete mode 100644 arch/arm/boot/dts/omap5-evm.dts
create mode 100644 arch/arm/boot/dts/omap5-uevm.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f0895c5..13b86bf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -149,7 +149,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap4-panda-es.dtb \
omap4-var-som.dtb \
omap4-sdp.dtb \
- omap5-evm.dtb \
+ omap5-uevm.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
am335x-bone.dtb
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
deleted file mode 100644
index 22e9ee8..000
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/dts-v1/;
-
-#include omap5.dtsi
-#include samsung_k3pe0e000b.dtsi
-
-/ {
- model = TI OMAP5 EVM board;
- compatible = ti,omap5-evm, ti,omap5;
-
- memory {
- device_type = memory;
- reg = 0x8000 0x7F00; /* 2032 MB */
- };
-
- vmmcsd_fixed: fixedregulator-mmcsd {
- compatible = regulator-fixed;
- regulator-name = vmmcsd_fixed;
- regulator-min-microvolt = 300;
- regulator-max-microvolt = 300;
- };
-
-};
-
-omap5_pmx_core {
- pinctrl-names = default;
- pinctrl-0 =
- twl6040_pins
- mcpdm_pins
- dmic_pins
- mcbsp1_pins
- mcbsp2_pins
- ;
-
- twl6040_pins: pinmux_twl6040_pins {
- pinctrl-single,pins =
- 0x18a (PIN_OUTPUT | MUX_MODE6) /*
perslimbus2_clock.gpio5_145 */
- ;
- };
-
- mcpdm_pins: pinmux_mcpdm_pins {
- pinctrl-single,pins =
- 0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
abe_clks.abe_clks */
- 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
abemcpdm_ul_data.abemcpdm_ul_data */
- 0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
abemcpdm_dl_data.abemcpdm_dl_data */
- 0x160 (PIN_INPUT_PULLUP | MUX_MODE0)/*
abemcpdm_frame.abemcpdm_frame */
- 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
abemcpdm_lb_clk.abemcpdm_lb_clk */
- ;
- };
-
- dmic_pins: pinmux_dmic_pins {
- pinctrl-single,pins =
- 0x144 (PIN_INPUT | MUX_MODE0) /*
abedmic_din1.abedmic_din1 */
- 0x146 (PIN_INPUT | MUX_MODE0) /*
abedmic_din2.abedmic_din2 */
- 0x148 (PIN_INPUT | MUX_MODE0) /*
abedmic_din3.abedmic_din3 */
- 0x14a (PIN_OUTPUT | MUX_MODE0) /*
abedmic_clk1.abedmic_clk1 */
- ;
- };
-
- mcbsp1_pins: pinmux_mcbsp1_pins {
- pinctrl-single,pins =
- 0x14c (PIN_INPUT | MUX_MODE1) /*
abedmic_clk2.abemcbsp1_fsx */
- 0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /*
abedmic_clk3.abemcbsp1_dx */
- 0x150 (PIN_INPUT | MUX_MODE1) /*
abeslimbus1_clock.abemcbsp1_clkx */
- 0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1) /*
abeslimbus1_data.abemcbsp1_dr */
- ;
- };
-
- mcbsp2_pins: pinmux_mcbsp2_pins {
- pinctrl-single,pins =
- 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
abemcbsp2_dr.abemcbsp2_dr */
- 0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /*
abemcbsp2_dx.abemcbsp2_dx */
- 0x158 (PIN_INPUT | MUX_MODE0) /*
abemcbsp2_fsx.abemcbsp2_fsx */
- 0x15a (PIN_INPUT | MUX_MODE0) /*
abemcbsp2_clkx.abemcbsp2_clkx */
- ;
-
[PATCH 1/4] ARM: dts: omap5: Rename omap5-evm to omap5-uevm
The uevm is the official board supported for the OMAP5 soc
in mainline. The uevm has an OMAP5432 with a DDR3 memory.
Renaming the board dts file and adding the following cleanups.
* There are no devices connected on I2C 2,3,4 buses. So remove
the pinmux data for the same.
* DDR3 memory is used in the uevm. Neither DVFS or temperature
polling is supported with DDR3. So remove the DDR3 device and
emif nodes.
* Keypad is not supported on uevm. So remove the device node.
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/Makefile |2 +-
.../arm/boot/dts/{omap5-evm.dts = omap5-uevm.dts} | 83 +---
2 files changed, 4 insertions(+), 81 deletions(-)
rename arch/arm/boot/dts/{omap5-evm.dts = omap5-uevm.dts} (73%)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f0895c5..13b86bf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -149,7 +149,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap4-panda-es.dtb \
omap4-var-som.dtb \
omap4-sdp.dtb \
- omap5-evm.dtb \
+ omap5-uevm.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
am335x-bone.dtb
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-uevm.dts
similarity index 73%
rename from arch/arm/boot/dts/omap5-evm.dts
rename to arch/arm/boot/dts/omap5-uevm.dts
index 22e9ee8..843a001 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -8,11 +8,10 @@
/dts-v1/;
#include omap5.dtsi
-#include samsung_k3pe0e000b.dtsi
/ {
- model = TI OMAP5 EVM board;
- compatible = ti,omap5-evm, ti,omap5;
+ model = TI OMAP5 uEVM board;
+ compatible = ti,omap5-uevm, ti,omap5;
memory {
device_type = memory;
@@ -88,27 +87,6 @@
;
};
- i2c2_pins: pinmux_i2c2_pins {
- pinctrl-single,pins =
- 0x178 (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
- 0x17a (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
- ;
- };
-
- i2c3_pins: pinmux_i2c3_pins {
- pinctrl-single,pins =
- 0x13a (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
- 0x13c (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
- ;
- };
-
- i2c4_pins: pinmux_i2c4_pins {
- pinctrl-single,pins =
- 0xb8 (PIN_INPUT | MUX_MODE0)/* i2c4_scl */
- 0xba (PIN_INPUT | MUX_MODE0)/* i2c4_sda */
- ;
- };
-
i2c5_pins: pinmux_i2c5_pins {
pinctrl-single,pins =
0x184 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */
@@ -175,39 +153,6 @@
clock-frequency = 40;
};
-i2c2 {
- pinctrl-names = default;
- pinctrl-0 = i2c2_pins;
-
- clock-frequency = 40;
-
- /* Pressure Sensor */
- bmp085@77 {
- compatible = bosch,bmp085;
- reg = 0x77;
- };
-};
-
-i2c3 {
- pinctrl-names = default;
- pinctrl-0 = i2c3_pins;
-
- clock-frequency = 40;
-};
-
-i2c4 {
- pinctrl-names = default;
- pinctrl-0 = i2c4_pins;
-
- clock-frequency = 40;
-
- /* Temperature Sensor */
- tmp102@48{
- compatible = ti,tmp102;
- reg = 0x48;
- };
-};
-
i2c5 {
pinctrl-names = default;
pinctrl-0 = i2c5_pins;
@@ -215,32 +160,10 @@
clock-frequency = 40;
};
-keypad {
- keypad,num-rows = 8;
- keypad,num-columns = 8;
- linux,keymap = 0x02020073 /* VOLUP */
- 0x02030072 /* VOLDOWM */
- 0x020400e7 /* SEND */
- 0x02050066 /* HOME */
- 0x0206006b /* END */
- 0x020700d9;/* SEARCH */
- linux,input-no-autorepeat;
-};
-
mcbsp3 {
status = disabled;
};
-emif1 {
- cs1-used;
- device-handle = samsung_K3PE0E000B;
-};
-
-emif2 {
- cs1-used;
- device-handle = samsung_K3PE0E000B;
-};
-
mcspi1 {
};
--
1.7.9.5
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Re: [PATCH 3/3] ARM: DTS: TWL4030: fix mux and wakeup for SYS_NIRQ line
On 06/04/2013 12:19 AM, Kevin Hilman wrote:
Florian Vaussard florian.vauss...@epfl.ch writes:
Hello Kevin,
On 06/01/2013 12:45 AM, Kevin Hilman wrote:
On most OMAP3 platforms, the twl4030 IRQ line is connected to the
SYS_NIRQ line on OMAP. Therefore, configure the defaults for the
SYS_NIRQ pin in the twl4030 DTS file.
Boards that hook up the twl4030 differently can easily override this
in their board-specific DTS file.
This allows RTC wake from off-mode to work again on OMAP3-based
platforms with twl4030. Tested on 3530/Beagle, 3730/Beagle-xM,
3530/Overo, 3730/Overo-STORM.
Signed-off-by: Kevin Hilman khil...@linaro.org
---
arch/arm/boot/dts/twl4030.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index b3034da..c7fe9f6 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -13,6 +13,8 @@
compatible = ti,twl4030;
interrupt-controller;
#interrupt-cells = 1;
+ pinctrl-names = default;
+ pinctrl-0 = twl4030_pins;
rtc {
compatible = ti,twl4030-rtc;
@@ -92,3 +94,18 @@
#pwm-cells = 2;
};
};
+
+omap3_pmx_core {
Here you are making the TWL4030 to explicitly depend on OMAP3. Could
this chip be used by another target? If the case, I would put this
piece of code in the files including twl4030. Otherwise it's ok here.
I talked this over with Tony before posting. In theorry, it could be
used on other platforms. In practice, it's only used on OMAP. We can
easily move this to board files if needed later, but thought it would be
simpler to put it here. I'll let Benoit decide.
Ok, so I am fine with your approach. If need arises later, we can have
a .dtsi file in-between to make the glue layer and avoid duplication inside
board files.
Regards,
Florian
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Re: [PATCH 2/4] ARM: dts: omap5-uevm: Add USB Host support
Hello,
Some very minor comments.
On 06/05/2013 08:46 AM, Sricharan R wrote:
From: Roger Quadros rog...@ti.com
Provide the RESET regulators for the USB PHYs, the USB Host
port modes and the PHY devices.
Also provide pin multiplexer information for the USB host
pins.
Cc: Roger Quadros rog...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
[Sricharan R r.sricha...@ti.com: Replaced constants with preprocessor macros]
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/omap5-uevm.dts | 77 ++
arch/arm/boot/dts/omap5.dtsi | 30 +++
2 files changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 843a001..cf862df 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -25,6 +25,47 @@
regulator-max-microvolt = 300;
};
+ /* HS USB Port 2 RESET */
+ hsusb2_reset: hsusb2_reset_reg {
+ compatible = regulator-fixed;
+ regulator-name = hsusb2_reset;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ gpio = gpio3 16 GPIO_ACTIVE_HIGH; /* gpio3_80 HUB_NRESET */
+ startup-delay-us = 7;
+ enable-active-high;
+ };
+
+ /* HS USB Host PHY on PORT 2 */
+ hsusb2_phy: hsusb2_phy {
+ compatible = usb-nop-xceiv;
+ reset-supply = hsusb2_reset;
+ };
+
+ /* HS USB Port 3 RESET */
+ hsusb3_reset: hsusb3_reset_reg {
+ compatible = regulator-fixed;
+ regulator-name = hsusb3_reset;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ gpio = gpio3 15 GPIO_ACTIVE_HIGH; /* gpio3_79 ETH_NRESET */
+ startup-delay-us = 7;
+ enable-active-high;
+ };
+
+ /* HS USB Host PHY on PORT 3 */
+ hsusb3_phy: hsusb3_phy {
+ compatible = usb-nop-xceiv;
+ reset-supply = hsusb3_reset;
+ };
+
+ /* hsusb2_phy is clocked by FREF_CLK1 i.e. auxclk1 */
+ clock_alias {
+ clock-name = auxclk1_ck;
+ clock-alias = main_clk;
+ device = hsusb2_phy;
+ clock-frequency = 1920; /* 19.2 MHz */
+ };
};
omap5_pmx_core {
@@ -35,6 +76,7 @@
dmic_pins
mcbsp1_pins
mcbsp2_pins
+ usbhost_pins
;
twl6040_pins: pinmux_twl6040_pins {
@@ -120,6 +162,32 @@
0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */
;
};
+
+ usbhost_pins: pinmux_usbhost_pins {
+ pinctrl-single,pins =
+ 0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe INPUT
| MODE 0 */
+ 0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data INPUT |
MODE 0 */
Comments are redundant with the constants, so maybe you can leave this
part out.
Same for a few others below.
+
+ 0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe
INPUT | MODE 0 */
+ 0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data INPUT
| MODE 0 */
+
+ 0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 OUTPUT | MODE
6 HUB_NRESET */
+ 0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 OUTPUT | MODE
6 ETH_NRESET */
+ ;
+ };
+};
+
+omap5_pmx_wkup {
+ pinctrl-names = default;
+ pinctrl-0 =
+ usbhost_wkup_pins
+ ;
+
+ usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
+ pinctrl-single,pins =
+ 0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out OUTPUT |
MODE 7 for USB hub clk */
Mismatch between constants and comments, which mode should it be?
+ ;
+ };
};
mmc1 {
@@ -164,6 +232,15 @@
status = disabled;
};
+usbhshost {
+ port2-mode = ehci-hsic;
+ port3-mode = ehci-hsic;
+};
+
+usbhsehci {
+ phys = 0 hsusb2_phy hsusb3_phy;
+};
+
mcspi1 {
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 1e84db8..67d6e1f 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -666,5 +666,35 @@
ctrl-module = omap_control_usb;
};
};
+
+ usbhstll: usbhstll@4a062000 {
+ compatible = ti,usbhs-tll;
+ reg = 0x4a062000 0x1000;
+ interrupts = 0 78 IRQ_TYPE_LEVEL_HIGH;
I guess that here you can replace '0' with GIC_SPI.
+ ti,hwmods = usb_tll_hs;
+ };
+
+ usbhshost: usbhshost@4a064000 {
+ compatible = ti,usbhs-host;
+
Re: [PATCH v2] OMAP: AES: Don't idle/start AES device between Encrypt operations
On Tue, May 28, 2013 at 07:02:55PM -0500, Joel A Fernandes wrote: Calling runtime PM API for every block causes serious perf hit to crypto operations that are done on a long buffer. As crypto is performed on a page boundary, encrypting large buffers can cause a series of crypto operations divided by page. The runtime PM API is also called those many times. We call runtime_pm_get_sync only at beginning on the session (cra_init) and runtime_pm_put at the end. This result in upto a 50% speedup as below. This doesn't make the driver to keep the system awake as runtime get/put is only called during a crypto session which completes usually quickly. Before: root@beagleboard:~# time -v openssl speed -evp aes-128-cbc Doing aes-128-cbc for 3s on 16 size blocks: 13310 aes-128-cbc's in 0.01s Doing aes-128-cbc for 3s on 64 size blocks: 13040 aes-128-cbc's in 0.04s Doing aes-128-cbc for 3s on 256 size blocks: 9134 aes-128-cbc's in 0.03s Doing aes-128-cbc for 3s on 1024 size blocks: 8939 aes-128-cbc's in 0.01s Doing aes-128-cbc for 3s on 8192 size blocks: 4299 aes-128-cbc's in 0.00s After: root@beagleboard:~# time -v openssl speed -evp aes-128-cbc Doing aes-128-cbc for 3s on 16 size blocks: 18911 aes-128-cbc's in 0.02s Doing aes-128-cbc for 3s on 64 size blocks: 18878 aes-128-cbc's in 0.02s Doing aes-128-cbc for 3s on 256 size blocks: 11878 aes-128-cbc's in 0.10s Doing aes-128-cbc for 3s on 1024 size blocks: 11538 aes-128-cbc's in 0.05s Doing aes-128-cbc for 3s on 8192 size blocks: 4857 aes-128-cbc's in 0.03s While at it, also drop enter and exit pr_debugs, in related code. tracers can be used for that. Tested on a Beaglebone (AM335x SoC) board. v3 changes: Refreshed patch on kernel v3.10-rc3 Signed-off-by: Joel A Fernandes joelag...@ti.com Patch applied. Thanks! -- Email: Herbert Xu herb...@gondor.apana.org.au Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 1/9] ARM: davinci: move private EDMA API to arm/common
Hi Russell,
On 3/6/2013 9:45 PM, Matt Porter wrote:
Move mach-davinci/dma.c to common/edma.c so it can be used
by OMAP (specifically AM33xx) as well.
Signed-off-by: Matt Porter mpor...@ti.com
Acked-by: Sekhar Nori nsek...@ti.com
Can you please ack this movement of davinci private EDMA implementation
to arch/arm/common? I would like to take this patch through davinci tree
for v3.11.
Thanks,
Sekhar
---
arch/arm/Kconfig |1 +
arch/arm/common/Kconfig|3 +
arch/arm/common/Makefile |1 +
arch/arm/{mach-davinci/dma.c = common/edma.c} |2 +-
arch/arm/mach-davinci/Makefile |2 +-
arch/arm/mach-davinci/board-tnetv107x-evm.c|2 +-
arch/arm/mach-davinci/davinci.h|2 +-
arch/arm/mach-davinci/devices-tnetv107x.c |2 +-
arch/arm/mach-davinci/devices.c|6 +-
arch/arm/mach-davinci/dm355.c |2 +-
arch/arm/mach-davinci/dm365.c |2 +-
arch/arm/mach-davinci/dm644x.c |2 +-
arch/arm/mach-davinci/dm646x.c |2 +-
arch/arm/mach-davinci/include/mach/da8xx.h |2 +-
drivers/dma/edma.c |2 +-
drivers/mmc/host/davinci_mmc.c |1 +
include/linux/mfd/davinci_voicecodec.h |3 +-
.../mach = include/linux/platform_data}/edma.h| 89
+---
include/linux/platform_data/spi-davinci.h |2 +-
sound/soc/davinci/davinci-evm.c|1 +
sound/soc/davinci/davinci-pcm.c|1 +
sound/soc/davinci/davinci-pcm.h|2 +-
sound/soc/davinci/davinci-sffsdr.c |5 +-
23 files changed, 33 insertions(+), 104 deletions(-)
rename arch/arm/{mach-davinci/dma.c = common/edma.c} (99%)
rename {arch/arm/mach-davinci/include/mach =
include/linux/platform_data}/edma.h (59%)
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RE: [PATCH 11/11] i2c: omap: enhance pinctrl support
On Fri, May 31, 2013 at 20:25:38, Strashko, Grygorii wrote:
On 05/31/2013 01:13 PM, Hebbar Gururaja wrote:
Amend the I2C omap pin controller to optionally take a pin control
handle and set the state of the pins to:
- default on boot, resume and before performing an i2c transfer
- idle after initial default, after resume default, and after each
i2c xfer
- sleep on suspend()
By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.
Note:
A .suspend .resume callback is added which simply puts the pins to sleep
state upon suspend are moved to default idle state upon resume.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
(Changes based on i2c-nomadik.c)
Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Wolfram Sang w...@the-dreams.de
Cc: linux-omap@vger.kernel.org
Cc: linux-...@vger.kernel.org
---
:100644 100644 e02f9e3... 588ba28... M drivers/i2c/busses/i2c-omap.c
drivers/i2c/busses/i2c-omap.c | 112
++---
1 file changed, 105 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e02f9e3..588ba28 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -214,7 +214,11 @@ struct omap_i2c_dev {
u16 westate;
u16 errata;
- struct pinctrl *pins;
+ /* Three pin states - default, idle sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_default;
+ struct pinctrl_state*pins_idle;
+ struct pinctrl_state*pins_sleep;
};
static const u8 reg_map_ip_v1[] = {
@@ -641,6 +645,11 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num)
if (IS_ERR_VALUE(r))
goto out;
The current HWMOD framework configures PINs to enable state before
enabling the device and
switch PINs to idle state after disabling the device. Why here its done
in different order?
AFAIK, in case of DT boot, oh-mux will be NULL. So hwmod will not change
Any pins.
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(dev-pins_default))
+ if (pinctrl_select_state(dev-pinctrl, dev-pins_default))
+ dev_err(dev-dev, could not set default pins\n);
+
r = omap_i2c_wait_for_bb(dev);
if (r 0)
goto out;
@@ -664,7 +673,13 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num)
out:
pm_runtime_mark_last_busy(dev-dev);
+
pm_runtime_put_autosuspend(dev-dev);
+ /* Optionally let pins go into idle state */
+ if (!IS_ERR(dev-pins_idle))
+ if (pinctrl_select_state(dev-pinctrl, dev-pins_idle))
+ dev_err(dev-dev, could not set pins to idle state\n);
+
return r;
}
@@ -1123,14 +1138,47 @@ omap_i2c_probe(struct platform_device *pdev)
dev-set_mpu_wkup_lat = pdata-set_mpu_wkup_lat;
}
- dev-pins = devm_pinctrl_get_select_default(pdev-dev);
- if (IS_ERR(dev-pins)) {
- if (PTR_ERR(dev-pins) == -EPROBE_DEFER)
+ dev-pinctrl = devm_pinctrl_get(pdev-dev);
May be struct device -pins-p can be used instead of dev-pinctrl?
+ if (!IS_ERR(dev-pinctrl)) {
+ dev-pins_default = pinctrl_lookup_state(dev-pinctrl,
+PINCTRL_STATE_DEFAULT);
+ if (IS_ERR(dev-pins_default))
+ dev_dbg(pdev-dev, could not get default pinstate\n);
+ else
+ if (pinctrl_select_state(dev-pinctrl,
+dev-pins_default))
+ dev_err(pdev-dev,
+ could not set default pinstate\n);
Don't need to set Default pin state
Default pins state is applied by DD framework automatically before
device probing
and stored in struct device -pins-default_state
Correct.
+
+ dev-pins_idle = pinctrl_lookup_state(dev-pinctrl,
+ PINCTRL_STATE_IDLE);
+ if (IS_ERR(dev-pins_idle))
+ dev_dbg(pdev-dev, could not get idle pinstate\n);
+ else
+ /* If possible, let's idle until the first transfer */
+ if
RE: [PATCH 11/11] i2c: omap: enhance pinctrl support
On Fri, May 31, 2013 at 23:04:59, Kevin Hilman wrote: Hebbar Gururaja gururaja.heb...@ti.com writes: Amend the I2C omap pin controller to optionally take a pin control handle and set the state of the pins to: - default on boot, resume and before performing an i2c transfer - idle after initial default, after resume default, and after each i2c xfer - sleep on suspend() By optionally putting the pins into sleep state in the suspend callback we can accomplish two things. - One is to minimize current leakage from pins and thus save power, - second, we can prevent the IP from driving pins output in an uncontrolled manner, which may happen if the power domain drops the domain regulator. Note: A .suspend .resume callback is added which simply puts the pins to sleep state upon suspend are moved to default idle state upon resume. If any of the above pin states are missing in dt, a warning message about the missing state is displayed. If certain pin-states are not available, to remove this warning message pass respective state name with null phandler. (Changes based on i2c-nomadik.c) Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com Cc: Tony Lindgren t...@atomide.com Cc: Wolfram Sang w...@the-dreams.de Cc: linux-omap@vger.kernel.org Cc: linux-...@vger.kernel.org [...] @@ -664,7 +673,13 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) out: pm_runtime_mark_last_busy(dev-dev); + pm_runtime_put_autosuspend(dev-dev); + /* Optionally let pins go into idle state */ + if (!IS_ERR(dev-pins_idle)) + if (pinctrl_select_state(dev-pinctrl, dev-pins_idle)) + dev_err(dev-dev, could not set pins to idle state\n); This is wrong. You're changing the muxing before the device actually goes idle. Anything you want to happen when the device actually idles for real has to be in runtime PM callbacks. Looking below, I see it's already in the callbacks, so why is it here also? Just to be double sure. Seems it is unwanted. [...] @@ -1300,6 +1348,10 @@ static int omap_i2c_runtime_suspend(struct device *dev) omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG); } + if (!IS_ERR(_dev-pins_idle)) + if (pinctrl_select_state(_dev-pinctrl, _dev-pins_idle)) + dev_err(dev, could not set pins to idle state\n); + return 0; } Kevin Regards, Gururaja -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/4] ARM: dts: omap5-uevm: Add USB Host support
Hi,
On Wednesday 05 June 2013 01:29 PM, Florian Vaussard wrote:
Hello,
Some very minor comments.
On 06/05/2013 08:46 AM, Sricharan R wrote:
From: Roger Quadros rog...@ti.com
Provide the RESET regulators for the USB PHYs, the USB Host
port modes and the PHY devices.
Also provide pin multiplexer information for the USB host
pins.
Cc: Roger Quadros rog...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
[Sricharan R r.sricha...@ti.com: Replaced constants with preprocessor
macros]
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/omap5-uevm.dts | 77
++
arch/arm/boot/dts/omap5.dtsi | 30 +++
2 files changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/omap5-uevm.dts
b/arch/arm/boot/dts/omap5-uevm.dts
index 843a001..cf862df 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -25,6 +25,47 @@
regulator-max-microvolt = 300;
};
+/* HS USB Port 2 RESET */
+hsusb2_reset: hsusb2_reset_reg {
+compatible = regulator-fixed;
+regulator-name = hsusb2_reset;
+regulator-min-microvolt = 330;
+regulator-max-microvolt = 330;
+gpio = gpio3 16 GPIO_ACTIVE_HIGH; /* gpio3_80 HUB_NRESET */
+startup-delay-us = 7;
+enable-active-high;
+};
+
+/* HS USB Host PHY on PORT 2 */
+hsusb2_phy: hsusb2_phy {
+compatible = usb-nop-xceiv;
+reset-supply = hsusb2_reset;
+};
+
+/* HS USB Port 3 RESET */
+hsusb3_reset: hsusb3_reset_reg {
+compatible = regulator-fixed;
+regulator-name = hsusb3_reset;
+regulator-min-microvolt = 330;
+regulator-max-microvolt = 330;
+gpio = gpio3 15 GPIO_ACTIVE_HIGH; /* gpio3_79 ETH_NRESET */
+startup-delay-us = 7;
+enable-active-high;
+};
+
+/* HS USB Host PHY on PORT 3 */
+hsusb3_phy: hsusb3_phy {
+compatible = usb-nop-xceiv;
+reset-supply = hsusb3_reset;
+};
+
+/* hsusb2_phy is clocked by FREF_CLK1 i.e. auxclk1 */
+clock_alias {
+clock-name = auxclk1_ck;
+clock-alias = main_clk;
+device = hsusb2_phy;
+clock-frequency = 1920; /* 19.2 MHz */
+};
};
omap5_pmx_core {
@@ -35,6 +76,7 @@
dmic_pins
mcbsp1_pins
mcbsp2_pins
+usbhost_pins
;
twl6040_pins: pinmux_twl6040_pins {
@@ -120,6 +162,32 @@
0x16c (PIN_INPUT | MUX_MODE1)/* mcspi2_cs */
;
};
+
+usbhost_pins: pinmux_usbhost_pins {
+pinctrl-single,pins =
+0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe INPUT | MODE
0 */
+0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data INPUT | MODE 0
*/
Comments are redundant with the constants, so maybe you can leave this part
out.
Same for a few others below.
Ok, I agree here for attributes like pulls, i/o etc, comments are now not
required.
But comment is still good to describe just the mux mode functionality ?
One module will use different pins, like data, clk, gpios, etc. Just MUX_MODEX
does not
complete it..
+
+0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe INPUT | MODE
0 */
+0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data INPUT | MODE 0
*/
+
+0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 OUTPUT | MODE 6
HUB_NRESET */
+0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 OUTPUT | MODE 6
ETH_NRESET */
+;
+};
+};
+
+omap5_pmx_wkup {
+pinctrl-names = default;
+pinctrl-0 =
+usbhost_wkup_pins
+;
+
+usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
+pinctrl-single,pins =
+0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out OUTPUT | MODE 7
for USB hub clk */
Mismatch between constants and comments, which mode should it be?
MODE 0. I see safe mode for 7. Comment should be corrected.
+;
+};
};
mmc1 {
@@ -164,6 +232,15 @@
status = disabled;
};
+usbhshost {
+port2-mode = ehci-hsic;
+port3-mode = ehci-hsic;
+};
+
+usbhsehci {
+phys = 0 hsusb2_phy hsusb3_phy;
+};
+
mcspi1 {
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 1e84db8..67d6e1f 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -666,5 +666,35 @@
ctrl-module = omap_control_usb;
};
};
+
+usbhstll: usbhstll@4a062000 {
+compatible = ti,usbhs-tll;
+reg = 0x4a062000 0x1000;
+interrupts = 0 78 IRQ_TYPE_LEVEL_HIGH;
I guess that here you can replace '0' with GIC_SPI.
Thanks. Will replace here and below.
Regards,
Sricharan
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Re: [PATCH v2 0/2] USB: PHY: Improve PHY selection logic
On 06/04/2013 11:26 PM, Felipe Balbi wrote: Hi, On Tue, Jun 04, 2013 at 10:16:50AM +0300, Roger Quadros wrote: On 06/03/2013 08:47 PM, Greg KH wrote: On Fri, May 31, 2013 at 02:29:01PM +0300, Roger Quadros wrote: Hi, Improve Kconfig so that the relevant PHY driver can be explicitely selected by the controller driver instead of relying on the user to do so. Detailed description in patch 1. Felipe needs to take these, not I. Felipe, Could you please take these if appropriate? Thanks. it's for v3.11 merge window, right ? I think I'll enjoy the rest of my vacations before taking these patches ;-) I'll be back on office next monday, cheers Yes these are for 3.11 so no hurry :). Didn't mean to interrupt your vacations. cheers, -roger -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/4] ARM: dts: omap5-uevm: Add USB Host support
Hi Sricharan,
Thanks for sending this, but some parts are outdated. See below.
On 06/05/2013 09:46 AM, Sricharan R wrote:
From: Roger Quadros rog...@ti.com
Provide the RESET regulators for the USB PHYs, the USB Host
port modes and the PHY devices.
Also provide pin multiplexer information for the USB host
pins.
Cc: Roger Quadros rog...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
[Sricharan R r.sricha...@ti.com: Replaced constants with preprocessor
macros]
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/omap5-uevm.dts | 77
++
arch/arm/boot/dts/omap5.dtsi | 30 +++
2 files changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/omap5-uevm.dts
b/arch/arm/boot/dts/omap5-uevm.dts
index 843a001..cf862df 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -25,6 +25,47 @@
regulator-max-microvolt = 300;
};
+ /* HS USB Port 2 RESET */
+ hsusb2_reset: hsusb2_reset_reg {
+ compatible = regulator-fixed;
+ regulator-name = hsusb2_reset;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ gpio = gpio3 16 GPIO_ACTIVE_HIGH; /* gpio3_80 HUB_NRESET */
+ startup-delay-us = 7;
+ enable-active-high;
+ };
+
+ /* HS USB Host PHY on PORT 2 */
+ hsusb2_phy: hsusb2_phy {
+ compatible = usb-nop-xceiv;
+ reset-supply = hsusb2_reset;
+ };
+
+ /* HS USB Port 3 RESET */
+ hsusb3_reset: hsusb3_reset_reg {
+ compatible = regulator-fixed;
+ regulator-name = hsusb3_reset;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ gpio = gpio3 15 GPIO_ACTIVE_HIGH; /* gpio3_79 ETH_NRESET */
+ startup-delay-us = 7;
+ enable-active-high;
+ };
+
+ /* HS USB Host PHY on PORT 3 */
+ hsusb3_phy: hsusb3_phy {
+ compatible = usb-nop-xceiv;
+ reset-supply = hsusb3_reset;
+ };
+
+ /* hsusb2_phy is clocked by FREF_CLK1 i.e. auxclk1 */
+ clock_alias {
+ clock-name = auxclk1_ck;
+ clock-alias = main_clk;
+ device = hsusb2_phy;
+ clock-frequency = 1920; /* 19.2 MHz */
+ };
clock_alias node is not required. Instead we need to rely on proper clock
binding
and provide reference to the clock phandle in the PHY node.
as an example please see here
https://lkml.org/lkml/2013/4/19/124
However this clock binding technique is still under discussion/transition.
https://patchwork.kernel.org/patch/2541331/
So, I suggest you leave the auxclk1 part out for now and we can get it in later
once
the clock binding stuff is sorted out. The side effect of this is that PORT 2
(i.e. USB Hub)
will not work. USB Ethernet should still work IMO.
cheers,
-roger
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[PATCH] rtc: rtc-twl: fix initialization sequence
The twl-rtc has the following dependencies from other drivers during the boot:
pinctrl
|-i2c-omap
|- twl-core
|- twl-rtc
The i2c-omap probe may be deferred because pinctrl iss not ready yet. As result,
i2c-omap will be probed at late init time. Which, in turn, will delay twl-core
initialization till late init time too.
But, the twl-rtc driver is registered from finction twl_rtc_init() at
module(device) init time and contains part of its initialization code within it.
Unfortunatelly, this code depends on twl-core which may be not ready at that
moment and, as result, wrong register map will be selected
(on OMAP3 twl6030_rtc_reg_map will be selected instead of twl4030_rtc_reg_map).
static int __init twl_rtc_init(void)
{
if (twl_class_is_4030()) --- twl-core might be not ready here
--- and twl_class_is_4030() will return 0
rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
else
rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
return platform_driver_register(twl4030rtc_driver);
}
Hence, move register map selection code in twl_rtc_probe() to solve this issue.
Cc: Alessandro Zummo a.zu...@towertech.it
Cc: Andrew Morton a...@linux-foundation.org
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
---
drivers/rtc/rtc-twl.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
index bbda0fd..1698115 100644
--- a/drivers/rtc/rtc-twl.c
+++ b/drivers/rtc/rtc-twl.c
@@ -481,6 +481,11 @@ static int twl_rtc_probe(struct platform_device *pdev)
if (irq = 0)
goto out1;
+ if (twl_class_is_4030())
+ rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
+ else
+ rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
+
ret = twl_rtc_read_u8(rd_reg, REG_RTC_STATUS_REG);
if (ret 0)
goto out1;
@@ -622,11 +627,6 @@ static struct platform_driver twl4030rtc_driver = {
static int __init twl_rtc_init(void)
{
- if (twl_class_is_4030())
- rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
- else
- rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
-
return platform_driver_register(twl4030rtc_driver);
}
module_init(twl_rtc_init);
--
1.7.9.5
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Re: [PATCH] rtc: rtc-twl: fix initialization sequence
Pls, ignore this patch. It duplicates:
https://patchwork.kernel.org/patch/2448251/ - [v2,1/2] RTC: rtc-twl: Fix
rtc_reg_map initialization
from Peter Ujfalusi
On 06/05/2013 02:19 PM, Grygorii Strashko wrote:
The twl-rtc has the following dependencies from other drivers during the boot:
pinctrl
|-i2c-omap
|- twl-core
|- twl-rtc
The i2c-omap probe may be deferred because pinctrl iss not ready yet. As result,
i2c-omap will be probed at late init time. Which, in turn, will delay twl-core
initialization till late init time too.
But, the twl-rtc driver is registered from finction twl_rtc_init() at
module(device) init time and contains part of its initialization code within it.
Unfortunatelly, this code depends on twl-core which may be not ready at that
moment and, as result, wrong register map will be selected
(on OMAP3 twl6030_rtc_reg_map will be selected instead of twl4030_rtc_reg_map).
static int __init twl_rtc_init(void)
{
if (twl_class_is_4030()) --- twl-core might be not ready here
--- and twl_class_is_4030() will return 0
rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
else
rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
return platform_driver_register(twl4030rtc_driver);
}
Hence, move register map selection code in twl_rtc_probe() to solve this issue.
Cc: Alessandro Zummo a.zu...@towertech.it
Cc: Andrew Morton a...@linux-foundation.org
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
---
drivers/rtc/rtc-twl.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
index bbda0fd..1698115 100644
--- a/drivers/rtc/rtc-twl.c
+++ b/drivers/rtc/rtc-twl.c
@@ -481,6 +481,11 @@ static int twl_rtc_probe(struct platform_device *pdev)
if (irq = 0)
goto out1;
+ if (twl_class_is_4030())
+ rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
+ else
+ rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
+
ret = twl_rtc_read_u8(rd_reg, REG_RTC_STATUS_REG);
if (ret 0)
goto out1;
@@ -622,11 +627,6 @@ static struct platform_driver twl4030rtc_driver = {
static int __init twl_rtc_init(void)
{
- if (twl_class_is_4030())
- rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
- else
- rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
-
return platform_driver_register(twl4030rtc_driver);
}
module_init(twl_rtc_init);
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Re: [PATCH 1/2] i2c: omap: convert to module_platform_driver()
On 06/04/2013 09:29 PM, Kevin Hilman wrote:
Grygorii Strashko grygorii.stras...@ti.com writes:
Hi Kevin,
On 06/03/2013 11:59 PM, Kevin Hilman wrote:
Grygorii Strashko grygorii.stras...@ti.com writes:
The OMAP I2C driver has a relation to pinctrl-single driver. As result,
its probe will be deferred during system boot until late init time,
because the pinctrl-single is initizalized as moudle/device init time.
This, in turn, will delay initialization of all I2C devices (like mfd,
I2C regulators and etc.) and cause boot delay (more over, it can broken
initialization of drivers which are not ready to use deferred probe
mechanism yet, for example DSS).
There are no sense to keep OMAP I2C initialization on subsys init layer
any more, hence shift it to module/device layer where the i2c --
pinctrl-single dependency is resolved in drivers/Makefile now.
Cc: Wolfram Sang w...@the-dreams.de
Cc: Ben Dooks (embedded platforms) ben-li...@fluff.org
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: linux-omap@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
Testing this patch with PATCH 1/2, the twl_rtc driver fails to correctly
initialize on OMAP3:
twl_rtc rtc.22: hctosys: invalid date/time
instead of the expected result:
twl_rtc rtc.22: setting system clock to 2000-01-01 00:00:00 UTC
(946684800)
so something is still not right for the init sequence.
Kevin
I think, the root cause of the problem isn't this patch - it's just
yet another side effect
of using deferred probes :). I've taken a look on twl-rtc code and
found possible error place
static int __init twl_rtc_init(void)
{
if (twl_class_is_4030()) -- here,
rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
else
rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
return platform_driver_register(twl4030rtc_driver);
}
In drivers/Makefile:
obj-$(CONFIG_RTC_LIB)+= rtc/ -- RTC is placed before I2C
obj-y+= i2c/ media/ - and only here I2C bus
instantiates TWL-core device
and configures twl_priv-twl_id
Thats why it's working on my OMAP4/twl6030 board. Could you check if
below fix will work on OMAP3:
Yes, your fix works. Thanks for digging into it.
Care to send a proper patch? Please be sure to send to Andrew Morton
also, since he'll be the one to queue the RTC patch.
Hi Kevin,
The similar patch already exists:
https://patchwork.kernel.org/patch/2448251/ - [v2,1/2] RTC: rtc-twl: Fix
rtc_reg_map initialization
from Peter Ujfalusi
-grygorii
diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
index 8751a52..aaa5015 100644
--- a/drivers/rtc/rtc-twl.c
+++ b/drivers/rtc/rtc-twl.c
@@ -469,6 +469,11 @@ static int twl_rtc_probe(struct platform_device *pdev)
if (irq = 0)
goto out1;
+ if (twl_class_is_4030())
+ rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
+ else
+ rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
+
ret = twl_rtc_read_u8(rd_reg, REG_RTC_STATUS_REG);
if (ret 0)
goto out1;
@@ -610,11 +615,6 @@ static struct platform_driver twl4030rtc_driver = {
static int __init twl_rtc_init(void)
{
- if (twl_class_is_4030())
- rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
- else
- rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
-
return platform_driver_register(twl4030rtc_driver);
}
module_init(twl_rtc_init);
Unfortunately, I have no OMAP3 HW and can't check it.
I suggest you find a Beagle or Gumstix/Overo type board someplace.
There is an abundance of cheap OMAP3 hardware available.
Kevin
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Re: [PATCH 2/4] ARM: dts: omap5-uevm: Add USB Host support
Hi Roger,
On Wednesday 05 June 2013 04:02 PM, Roger Quadros wrote:
Hi Sricharan,
Thanks for sending this, but some parts are outdated. See below.
On 06/05/2013 09:46 AM, Sricharan R wrote:
From: Roger Quadros rog...@ti.com
Provide the RESET regulators for the USB PHYs, the USB Host
port modes and the PHY devices.
Also provide pin multiplexer information for the USB host
pins.
Cc: Roger Quadros rog...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
[Sricharan R r.sricha...@ti.com: Replaced constants with preprocessor
macros]
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/omap5-uevm.dts | 77
++
arch/arm/boot/dts/omap5.dtsi | 30 +++
2 files changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/omap5-uevm.dts
b/arch/arm/boot/dts/omap5-uevm.dts
index 843a001..cf862df 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -25,6 +25,47 @@
regulator-max-microvolt = 300;
};
+/* HS USB Port 2 RESET */
+hsusb2_reset: hsusb2_reset_reg {
+compatible = regulator-fixed;
+regulator-name = hsusb2_reset;
+regulator-min-microvolt = 330;
+regulator-max-microvolt = 330;
+gpio = gpio3 16 GPIO_ACTIVE_HIGH; /* gpio3_80 HUB_NRESET */
+startup-delay-us = 7;
+enable-active-high;
+};
+
+/* HS USB Host PHY on PORT 2 */
+hsusb2_phy: hsusb2_phy {
+compatible = usb-nop-xceiv;
+reset-supply = hsusb2_reset;
+};
+
+/* HS USB Port 3 RESET */
+hsusb3_reset: hsusb3_reset_reg {
+compatible = regulator-fixed;
+regulator-name = hsusb3_reset;
+regulator-min-microvolt = 330;
+regulator-max-microvolt = 330;
+gpio = gpio3 15 GPIO_ACTIVE_HIGH; /* gpio3_79 ETH_NRESET */
+startup-delay-us = 7;
+enable-active-high;
+};
+
+/* HS USB Host PHY on PORT 3 */
+hsusb3_phy: hsusb3_phy {
+compatible = usb-nop-xceiv;
+reset-supply = hsusb3_reset;
+};
+
+/* hsusb2_phy is clocked by FREF_CLK1 i.e. auxclk1 */
+clock_alias {
+clock-name = auxclk1_ck;
+clock-alias = main_clk;
+device = hsusb2_phy;
+clock-frequency = 1920; /* 19.2 MHz */
+};
clock_alias node is not required. Instead we need to rely on proper clock
binding
and provide reference to the clock phandle in the PHY node.
as an example please see here
https://lkml.org/lkml/2013/4/19/124
However this clock binding technique is still under discussion/transition.
https://patchwork.kernel.org/patch/2541331/
So, I suggest you leave the auxclk1 part out for now and we can get it in
later once
the clock binding stuff is sorted out. The side effect of this is that PORT 2
(i.e. USB Hub)
will not work. USB Ethernet should still work IMO.
Ok will drop that part then.
Thanks,
Sricharan
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Re: [PATCH v2 1/2] RTC: rtc-twl: Fix rtc_reg_map initialization
Hi Peter,
Tested on OMAP4460 SDP - see no issues during boot.
-grygorii
On 04/16/2013 11:30 AM, Peter Ujfalusi wrote:
Initialize the rtc_reg_map in platform_driver's probe function instead at
module_init time. This way we can make sure that the twl-core has been already
probed and initialized (twl_priv-twl_id is valid) since the platform device
for the RTC driver will be created by the twl-core after it finished it's
init.
Reported-by: Christoph Fritz chf.fr...@googlemail.com
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
Hi,
As Tomi commented on the first version:
www.spinics.net/lists/linux-omap/msg90064.html
www.spinics.net/lists/linux-omap/msg90066.html
I have separated the actual fix from the module_platform_driver() conversion.
Regards,
Peter
drivers/rtc/rtc-twl.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
index 8bc6c80..c385e9b 100644
--- a/drivers/rtc/rtc-twl.c
+++ b/drivers/rtc/rtc-twl.c
@@ -469,6 +469,12 @@ static int twl_rtc_probe(struct platform_device *pdev)
if (irq = 0)
goto out1;
+ /* Initialize the register map */
+ if (twl_class_is_4030())
+ rtc_reg_map = (u8 *)twl4030_rtc_reg_map;
+ else
+ rtc_reg_map = (u8 *)twl6030_rtc_reg_map;
+
ret = twl_rtc_read_u8(rd_reg, REG_RTC_STATUS_REG);
if (ret 0)
goto out1;
@@ -614,11 +620,6 @@ static struct platform_driver twl4030rtc_driver = {
static int __init twl_rtc_init(void)
{
- if (twl_class_is_4030())
- rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
- else
- rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
-
return platform_driver_register(twl4030rtc_driver);
}
module_init(twl_rtc_init);
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Re: [PATCH 2/4] ARM: dts: omap5-uevm: Add USB Host support
On 06/05/2013 11:12 AM, Sricharan R wrote:
Hi,
On Wednesday 05 June 2013 01:29 PM, Florian Vaussard wrote:
Hello,
Some very minor comments.
On 06/05/2013 08:46 AM, Sricharan R wrote:
From: Roger Quadros rog...@ti.com
Provide the RESET regulators for the USB PHYs, the USB Host
port modes and the PHY devices.
Also provide pin multiplexer information for the USB host
pins.
Cc: Roger Quadros rog...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
[Sricharan R r.sricha...@ti.com: Replaced constants with preprocessor macros]
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/omap5-uevm.dts | 77
++
arch/arm/boot/dts/omap5.dtsi | 30 +++
2 files changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 843a001..cf862df 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -25,6 +25,47 @@
regulator-max-microvolt = 300;
};
+/* HS USB Port 2 RESET */
+hsusb2_reset: hsusb2_reset_reg {
+compatible = regulator-fixed;
+regulator-name = hsusb2_reset;
+regulator-min-microvolt = 330;
+regulator-max-microvolt = 330;
+gpio = gpio3 16 GPIO_ACTIVE_HIGH; /* gpio3_80 HUB_NRESET */
+startup-delay-us = 7;
+enable-active-high;
+};
+
+/* HS USB Host PHY on PORT 2 */
+hsusb2_phy: hsusb2_phy {
+compatible = usb-nop-xceiv;
+reset-supply = hsusb2_reset;
+};
+
+/* HS USB Port 3 RESET */
+hsusb3_reset: hsusb3_reset_reg {
+compatible = regulator-fixed;
+regulator-name = hsusb3_reset;
+regulator-min-microvolt = 330;
+regulator-max-microvolt = 330;
+gpio = gpio3 15 GPIO_ACTIVE_HIGH; /* gpio3_79 ETH_NRESET */
+startup-delay-us = 7;
+enable-active-high;
+};
+
+/* HS USB Host PHY on PORT 3 */
+hsusb3_phy: hsusb3_phy {
+compatible = usb-nop-xceiv;
+reset-supply = hsusb3_reset;
+};
+
+/* hsusb2_phy is clocked by FREF_CLK1 i.e. auxclk1 */
+clock_alias {
+clock-name = auxclk1_ck;
+clock-alias = main_clk;
+device = hsusb2_phy;
+clock-frequency = 1920; /* 19.2 MHz */
+};
};
omap5_pmx_core {
@@ -35,6 +76,7 @@
dmic_pins
mcbsp1_pins
mcbsp2_pins
+usbhost_pins
;
twl6040_pins: pinmux_twl6040_pins {
@@ -120,6 +162,32 @@
0x16c (PIN_INPUT | MUX_MODE1)/* mcspi2_cs */
;
};
+
+usbhost_pins: pinmux_usbhost_pins {
+pinctrl-single,pins =
+0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe INPUT | MODE 0 */
+0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data INPUT | MODE 0 */
Comments are redundant with the constants, so maybe you can leave this part out.
Same for a few others below.
Ok, I agree here for attributes like pulls, i/o etc, comments are now not
required.
But comment is still good to describe just the mux mode functionality ?
One module will use different pins, like data, clk, gpios, etc. Just MUX_MODEX
does not
complete it..
Yes, the 'usbb2_hsic_strobe' part must stay, only 'INPUT | MODE 0'
should be removed
from comments.
+
+0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe INPUT | MODE 0
*/
+0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data INPUT | MODE 0 */
+
+0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 OUTPUT | MODE 6
HUB_NRESET */
+0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 OUTPUT | MODE 6
ETH_NRESET */
+;
+};
+};
+
+omap5_pmx_wkup {
+pinctrl-names = default;
+pinctrl-0 =
+usbhost_wkup_pins
+;
+
+usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
+pinctrl-single,pins =
+0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out OUTPUT | MODE 7 for
USB hub clk */
Mismatch between constants and comments, which mode should it be?
MODE 0. I see safe mode for 7. Comment should be corrected.
s/corrected/removed/. This will avoid this kind of inconsistency.
Regards,
Florian
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Broken DM816x support in Linux 3.10-rc4
Not so long ago I tried to boot Linux 3.10-rc4 kernel on DM816x EVM board. Unfortunately, my attempts were failed by reason of poor support of DM81xx-based devices in new kernels. Actually, on Linux 3.10-rc4 kernel early initialization of board is failed when it tries to initialize power domains: [0.00] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa17f8e4 [0.00] Internal error: : 1028 [#1] SMP ARM [0.00] Modules linked in: [0.00] CPU: 0 PID: 0 Comm: swapper Not tainted 3.10.0-rc3-1-g0e5443c-dirty #12 [0.00] task: c076fc50 ti: c0764000 task.ti: c0764000 [0.00] PC is at omap2_pwrdm_wait_transition+0x1c/0xac [0.00] LR is at pwrdm_register_pwrdms+0x15c/0x1ac [0.00] pc : [c0031698]lr : [c0036010]psr: 6193 [0.00] sp : c0765f28 ip : c07bebe0 fp : 0001 [0.00] r10: c07e6a90 r9 : r8 : c07e6944 [0.00] r7 : c0754a50 r6 : c064f264 r5 : c0775298 r4 : c0773e9c [0.00] r3 : f8e4 r2 : fa17f8e4 r1 : 0004 r0 : c0775298 [0.00] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel [0.00] Control: 10c5387d Table: 80004019 DAC: 0017 [0.00] Process swapper (pid: 0, stack limit = 0xc0764240) [0.00] Stack: (0xc0765f28 to 0xc0766000) [0.00] 5f20: c0773e9c c0775298 c064f264 c0754a50 c0773ee4 c0036010 [0.00] 5f40: 35170034 81600134 c05125a8 fa18 8200 c0771348 c07b1b48 c07475ac [0.00] 5f60: c0771348 c07191fc c0647c40 c0711598 16c0 c0d24fb4 c06450ac c070c148 [0.00] 5f80: c0765f98 c0765f90 c0771134 c0765fdc [0.00] 5fa0: c0643878 0001 c0748774 c0771134 c076c880 413fc082 [0.00] 5fc0: c07086fc c0748778 [0.00] 5fe0: 10c53c7d c076c910 c0748774 c0771134 80004059 80008074 [0.00] [c0031698] (omap2_pwrdm_wait_transition+0x1c/0xac) from [c0036010] (pwrdm_register_pwrdms+0x15c/0x1ac) [0.00] [c0036010] (pwrdm_register_pwrdms+0x15c/0x1ac) from [c07191fc] (omap3xxx_powerdomains_init+0x50/0x144) [0.00] [c07191fc] (omap3xxx_powerdomains_init+0x50/0x144) from [c0711598] (ti81xx_init_early+0xcc/0x178) [0.00] [c0711598] (ti81xx_init_early+0xcc/0x178) from [c070c148] (setup_arch+0x5ac/0x800) [0.00] [c070c148] (setup_arch+0x5ac/0x800) from [c07086fc] (start_kernel+0x7c/0x330) [0.00] [c07086fc] (start_kernel+0x7c/0x330) from [80008074] (0x80008074) [0.00] Code: e1d030f8 e5982000 e28330e4 e0822003 (e5921000) [0.00] ---[ end trace 1b75b31a2719ed1c ]--- So, I suggest you this patch series, which fixes that kernel crush and adds new functions/structures, required for early initialization on DM816x (power and clock domains, hwmods). After applying these patches the kernel is able to successfully continue booting till clock initialization (will be added later). Thanks, Aida -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/5] ARM: OMAP: DM816x: add hwmod support for DM81xx
OCP interface data structures were added in order to achieve successful initialization of hwmods on DM816x. Required DM81xx family IRQ definitions, offsets of the PRCM clock control registers and additional OMAP2PLUS DMA channel definitions were added as they are needed during the hwmod registration. omap3xxx_hwmod_init() call was substituted by dm81xx_hwmod_init(). Signed-off-by: Aida Mynzhasova aida.mynzhas...@skitlab.ru --- arch/arm/mach-omap2/Makefile |1 + arch/arm/mach-omap2/cm_dm81xx.h | 20 + arch/arm/mach-omap2/dm81xx.h | 28 +- arch/arm/mach-omap2/dma.h | 12 + arch/arm/mach-omap2/io.c |2 +- arch/arm/mach-omap2/omap_hwmod.h |1 + arch/arm/mach-omap2/omap_hwmod_dm81xx_data.c | 1209 + arch/arm/plat-omap/include/plat/dmtimer.h |6 + arch/arm/plat-omap/include/plat/irqs-dm81xx.h | 43 + 9 files changed, 1320 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-omap2/omap_hwmod_dm81xx_data.c create mode 100644 arch/arm/plat-omap/include/plat/irqs-dm81xx.h diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 132a1e2..3b5cc8b 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -202,6 +202,7 @@ obj-$(CONFIG_ARCH_OMAP3)+= omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_am33xx_data.o +obj-$(CONFIG_SOC_DM81XX) += omap_hwmod_dm81xx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o # EMU peripherals diff --git a/arch/arm/mach-omap2/cm_dm81xx.h b/arch/arm/mach-omap2/cm_dm81xx.h index f8988da..d8268cd 100644 --- a/arch/arm/mach-omap2/cm_dm81xx.h +++ b/arch/arm/mach-omap2/cm_dm81xx.h @@ -58,4 +58,24 @@ #define DM816X_CM_DEFAULT_PCI_CLKDM0x0010 #define DM816X_CM_DEFAULT_L3_SLOW_CLKDM0x0014 +#define DM81XX_CM_ALWON_UART_0_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0150) +#define DM81XX_CM_ALWON_UART_1_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0154) +#define DM81XX_CM_ALWON_UART_2_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0158) +#define DM81XX_CM_ALWON_GPIO_0_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x015C) +#define DM81XX_CM_ALWON_GPIO_1_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0160) +#define DM81XX_CM_ALWON_WDTIMER_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x018C) +#define DM81XX_CM_ALWON_SPI_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0190) +#define DM816X_CM_ALWON_I2C_0_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0164) +#define DM816X_CM_ALWON_I2C_1_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0168) +#define DM816X_CM_DEFAULT_USB_CLKCTRL_OFF (DM816X_CM_DEFAULT_MOD + 0x0058) +#define DM816X_CM_ALWON_TIMER_0_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x016C) +#define DM816X_CM_ALWON_TIMER_1_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0170) +#define DM816X_CM_ALWON_TIMER_2_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0174) +#define DM816X_CM_ALWON_TIMER_3_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0178) +#define DM816X_CM_ALWON_TIMER_4_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x017C) +#define DM816X_CM_ALWON_TIMER_5_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0180) +#define DM816X_CM_ALWON_TIMER_6_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0184) +#define DM816X_CM_ALWON_TIMER_7_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0188) +#define DM816X_CM_ALWON_SDIO_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x15B0) +#define DM81XX_CM_ALWON_SPI_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0190) #endif diff --git a/arch/arm/mach-omap2/dm81xx.h b/arch/arm/mach-omap2/dm81xx.h index a0b18a6..e92a2d2 100644 --- a/arch/arm/mach-omap2/dm81xx.h +++ b/arch/arm/mach-omap2/dm81xx.h @@ -30,7 +30,33 @@ #define DM81XX_TAP_BASE(DM81XX_CTRL_BASE + \ DM81XX_CONTROL_DEVICE_ID - 0x204) +#define DM81XX_MAILBOX_BASE0x480C8000 -#define DM81XX_ARM_INTC_BASE 0x4820 +#define DM816X_WDTIMER1_BASE 0x480C2000 + +#define DM816X_I2C0_BASE 0x48028000 +#define DM816X_I2C1_BASE 0x4802A000 + +#define DM81XX_ELM_BASE0x4808 + +#define DM81XX_GPIO0_BASE 0x48032000 +#define DM81XX_GPIO1_BASE 0x4804C000 + +#define DM81XX_USBSS_BASE 0x4740 + +#define DM81XX_USB0_BASE 0x47401000 +#define DM81XX_USB1_BASE 0x47401800 + +#define DM816X_TIMER0_BASE 0x4802E000 +#define DM816X_TIMER1_BASE 0x4804 +#define DM816X_TIMER2_BASE 0x48042000 +#define DM816X_TIMER3_BASE 0x48044000 +#define DM816X_TIMER4_BASE 0x48046000 +#define DM816X_TIMER5_BASE 0x48048000 +#define DM816X_TIMER6_BASE 0x4804A000 + +#define DM816X_MMC0_BASE
[PATCH 1/5] ARM: OMAP: DM81xx: multiple renames for DM81xx platform
This patch renames all DM81xx platform related structures, variables, files, and functions. Previously names with ti81 prefixes were used, which are inconsistent, because actual name of the platform is DM81xx. Also, for the same reason DM816x EVM was renamed from board-ti8168evm to board-dm816x-evm. Signed-off-by: Aida Mynzhasova aida.mynzhas...@skitlab.ru --- arch/arm/Kconfig.debug| 12 +++--- arch/arm/include/debug/omap2plus.S| 20 +- arch/arm/mach-omap2/Kconfig | 16 arch/arm/mach-omap2/Makefile |4 +- arch/arm/mach-omap2/board-dm816x-evm.c| 62 + arch/arm/mach-omap2/board-ti8168evm.c | 62 - arch/arm/mach-omap2/cclock3xxx_data.c |6 +-- arch/arm/mach-omap2/clock.h |4 +- arch/arm/mach-omap2/common.h |8 ++-- arch/arm/mach-omap2/control.h |8 ++-- arch/arm/mach-omap2/dm81xx.h | 36 + arch/arm/mach-omap2/id.c | 20 +- arch/arm/mach-omap2/include/mach/serial.h |8 ++-- arch/arm/mach-omap2/io.c | 26 ++-- arch/arm/mach-omap2/irq.c |4 +- arch/arm/mach-omap2/omap_phy_internal.c | 18 - arch/arm/mach-omap2/soc.h | 54 - arch/arm/mach-omap2/ti81xx.h | 36 - arch/arm/mach-omap2/usb-musb.c|4 +- arch/arm/mach-omap2/usb.h | 12 +++--- arch/arm/tools/mach-types |4 +- drivers/pci/quirks.c |6 +-- drivers/usb/musb/musb_dsps.c | 12 +++--- drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c |2 +- include/linux/platform_data/davinci_asp.h |2 +- 25 files changed, 223 insertions(+), 223 deletions(-) create mode 100644 arch/arm/mach-omap2/board-dm816x-evm.c delete mode 100644 arch/arm/mach-omap2/board-ti8168evm.c create mode 100644 arch/arm/mach-omap2/dm81xx.h delete mode 100644 arch/arm/mach-omap2/ti81xx.h diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 1d41908..55e18d6 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -571,14 +571,14 @@ choice config DEBUG_OMAP4UART4 bool OMAP4/5 UART4 - config DEBUG_TI81XXUART1 - bool TI81XX UART1 (ti8148evm) + config DEBUG_DM81XXUART1 + bool DM81XX UART1 (DM8148evm) - config DEBUG_TI81XXUART2 - bool TI81XX UART2 + config DEBUG_DM81XXUART2 + bool DM81XX UART2 - config DEBUG_TI81XXUART3 - bool TI81XX UART3 (ti8168evm) + config DEBUG_DM81XXUART3 + bool DM81XX UART3 (DM8168evm) config DEBUG_AM33XXUART1 bool AM33XX UART1 diff --git a/arch/arm/include/debug/omap2plus.S b/arch/arm/include/debug/omap2plus.S index 6d867ae..76d643b 100644 --- a/arch/arm/include/debug/omap2plus.S +++ b/arch/arm/include/debug/omap2plus.S @@ -30,10 +30,10 @@ #define OMAP4_UART3_BASE 0x4802 #define OMAP4_UART4_BASE 0x4806e000 -/* TI81XX serial ports */ -#define TI81XX_UART1_BASE 0x4802 -#define TI81XX_UART2_BASE 0x48022000 -#define TI81XX_UART3_BASE 0x48024000 +/* DM81XX serial ports */ +#define DM81XX_UART1_BASE 0x4802 +#define DM81XX_UART2_BASE 0x48022000 +#define DM81XX_UART3_BASE 0x48024000 /* AM3505/3517 UART4 */ #define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ @@ -111,16 +111,16 @@ omap_uart_lsr:.word 0 mov \rp, #UART_OFFSET(OMAP4_UART4_BASE) b 98f #endif -#ifdef CONFIG_DEBUG_TI81XXUART1 - mov \rp, #UART_OFFSET(TI81XX_UART1_BASE) +#ifdef CONFIG_DEBUG_DM81XXUART1 + mov \rp, #UART_OFFSET(DM81XX_UART1_BASE) b 98f #endif -#ifdef CONFIG_DEBUG_TI81XXUART2 - mov \rp, #UART_OFFSET(TI81XX_UART2_BASE) +#ifdef CONFIG_DEBUG_DM81XXUART2 + mov \rp, #UART_OFFSET(DM81XX_UART2_BASE) b 98f #endif -#ifdef CONFIG_DEBUG_TI81XXUART3 - mov \rp, #UART_OFFSET(TI81XX_UART3_BASE) +#ifdef CONFIG_DEBUG_DM81XXUART3 + mov \rp, #UART_OFFSET(DM81XX_UART3_BASE) b 98f #endif #ifdef CONFIG_DEBUG_AM33XXUART1 diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index f49cd51..376600b 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -135,8 +135,8 @@ config SOC_OMAP3430 default y select SOC_HAS_OMAP2_SDRC -config SOC_TI81XX - bool TI81XX support +config SOC_DM81XX + bool DM81xx support depends on ARCH_OMAP3 default y @@ -368,14 +368,14 @@ config MACH_OMAP_3630SDP default y select OMAP_PACKAGE_CBP -config MACH_TI8168EVM -
[PATCH 4/5] ARM: OMAP: DM816x: add clock domain support for DM816x
This patch adds required definitions and structures for clockdomain
initialization:
1. register offsets for DM81xx and DM816x clock domain modules;
2. clock domain register bits;
3. additional OMAP2/3 common clock domains: prm_clkdm and cm_clkdm;
4. clockdomain structure definitions for DM816x.
Also, omap3xxx_clockdomains_init() was substituted by new
dm81xx_clockdomains_init().
Signed-off-by: Aida Mynzhasova aida.mynzhas...@skitlab.ru
---
arch/arm/mach-omap2/Makefile |2 +
arch/arm/mach-omap2/clockdomain.h|3 +
arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 10 +
arch/arm/mach-omap2/clockdomains_dm81xx_data.c | 213 ++
arch/arm/mach-omap2/cm-regbits-dm81xx.h | 22 +++
arch/arm/mach-omap2/cm_dm81xx.h | 61 +++
arch/arm/mach-omap2/io.c |2 +-
7 files changed, 312 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-omap2/clockdomains_dm81xx_data.c
create mode 100644 arch/arm/mach-omap2/cm-regbits-dm81xx.h
create mode 100644 arch/arm/mach-omap2/cm_dm81xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 03121cc..132a1e2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -158,6 +158,8 @@ obj-$(CONFIG_ARCH_OMAP4)+= $(clockdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_AM33XX) += clockdomains_am33xx_data.o
+obj-$(CONFIG_SOC_DM81XX) += $(clockdomain-common)
+obj-$(CONFIG_SOC_DM81XX) += clockdomains_dm81xx_data.o
obj-$(CONFIG_SOC_OMAP5)+= $(clockdomain-common)
# Clock framework
diff --git a/arch/arm/mach-omap2/clockdomain.h
b/arch/arm/mach-omap2/clockdomain.h
index 2da3765..0a9d4fc 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -215,6 +215,7 @@ extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
+extern void __init dm81xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void clkdm_add_autodeps(struct clockdomain *clkdm);
@@ -228,5 +229,7 @@ extern struct clkdm_ops am33xx_clkdm_operations;
extern struct clkdm_dep gfx_24xx_wkdeps[];
extern struct clkdm_dep dsp_24xx_wkdeps[];
extern struct clockdomain wkup_common_clkdm;
+extern struct clockdomain cm_common_clkdm;
+extern struct clockdomain prm_common_clkdm;
#endif
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 49722196..8a62c7f 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -90,3 +90,13 @@ struct clockdomain wkup_common_clkdm = {
.dep_bit= OMAP_EN_WKUP_SHIFT,
.flags = CLKDM_ACTIVE_WITH_MPU,
};
+
+struct clockdomain prm_common_clkdm = {
+ .name = prm_clkdm,
+ .pwrdm = { .name = wkup_pwrdm },
+};
+
+struct clockdomain cm_common_clkdm = {
+ .name = cm_clkdm,
+ .pwrdm = { .name = core_pwrdm },
+};
diff --git a/arch/arm/mach-omap2/clockdomains_dm81xx_data.c
b/arch/arm/mach-omap2/clockdomains_dm81xx_data.c
new file mode 100644
index 000..daf390f
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains_dm81xx_data.c
@@ -0,0 +1,213 @@
+/*
+ * DM81XX Clock Domain data.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_DM81XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_DM81XX_H
+
+#include linux/kernel.h
+#include linux/io.h
+
+#include clockdomain.h
+
+#include cm_dm81xx.h
+#include cm-regbits-dm81xx.h
+
+/*
+ * TODO:
+ * - Add other domains as required
+ * - Fill up associated powerdomans (especially ALWON powerdomains are NULL at
+ * the moment
+ * - Consider dependencies across domains (probably not applicable till now)
+ */
+
+/* Common DM81XX */
+static struct clockdomain alwon_l3_slow_dm81xx_clkdm = {
+ .name = alwon_l3_slow_clkdm,
+ .pwrdm = { .name = alwon_pwrdm },
+ .cm_inst= DM81XX_CM_ALWON_MOD,
+ .clkdm_offs = DM81XX_CM_ALWON_L3_SLOW_CLKDM,
+
[PATCH 3/5] ARM: OMAP: DM816x: add powerdomains for DM816x
This patch adds required structures for powerdomain initialization on
the DM816x. It is impossible to use OMAP3430 structures in order to
initialize powerdomains on DM816x, because there are big differences
between PRCM module base address offsets on these CPUs.
Signed-off-by: Aida Mynzhasova aida.mynzhas...@skitlab.ru
---
arch/arm/mach-omap2/Makefile |3 +
arch/arm/mach-omap2/io.c |2 +-
arch/arm/mach-omap2/powerdomain.h|4 +
arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c | 43
arch/arm/mach-omap2/powerdomains3xxx_data.c | 43
arch/arm/mach-omap2/powerdomains_dm81xx_data.c | 115 ++
arch/arm/mach-omap2/prm-regbits-dm81xx.h | 24 +
arch/arm/mach-omap2/prm_dm81xx.c | 79 +++
arch/arm/mach-omap2/prm_dm81xx.h | 44 +
9 files changed, 313 insertions(+), 44 deletions(-)
create mode 100644 arch/arm/mach-omap2/powerdomains_dm81xx_data.c
create mode 100644 arch/arm/mach-omap2/prm-regbits-dm81xx.h
create mode 100644 arch/arm/mach-omap2/prm_dm81xx.c
create mode 100644 arch/arm/mach-omap2/prm_dm81xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 607a2bf..03121cc 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -113,6 +113,7 @@ obj-$(CONFIG_SOC_AM33XX)+= prm_am33xx.o
cm_am33xx.o
omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
prcm_mpu44xx.o prminst44xx.o \
vc44xx_data.o vp44xx_data.o
+obj-$(CONFIG_SOC_DM81XX) += prm_dm81xx.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_OMAP5)+= $(omap-prcm-4-5-common)
@@ -140,6 +141,8 @@ obj-$(CONFIG_ARCH_OMAP4)+= $(powerdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_AM33XX) += powerdomains_am33xx_data.o
+obj-$(CONFIG_SOC_DM81XX) += $(powerdomain-common)
+obj-$(CONFIG_SOC_DM81XX) += powerdomains_dm81xx_data.o
obj-$(CONFIG_SOC_OMAP5)+= $(powerdomain-common)
# PRCM clockdomain control
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3deba6e..2a9e5b3 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -516,7 +516,7 @@ void __init dm81xx_init_early(void)
omap3xxx_check_revision();
dm81xx_check_features();
omap3xxx_voltagedomains_init();
- omap3xxx_powerdomains_init();
+ dm81xx_powerdomains_init();
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
diff --git a/arch/arm/mach-omap2/powerdomain.h
b/arch/arm/mach-omap2/powerdomain.h
index 140c360..6d78990 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -252,11 +252,13 @@ extern void omap242x_powerdomains_init(void);
extern void omap243x_powerdomains_init(void);
extern void omap3xxx_powerdomains_init(void);
extern void am33xx_powerdomains_init(void);
+extern void dm81xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
extern struct pwrdm_ops am33xx_pwrdm_operations;
+extern struct pwrdm_ops dm81xx_pwrdm_operations;
extern struct pwrdm_ops omap4_pwrdm_operations;
/* Common Internal functions used across OMAP rev's */
@@ -266,6 +268,8 @@ extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
extern struct powerdomain wkup_omap2_pwrdm;
extern struct powerdomain gfx_omap2_pwrdm;
+extern struct powerdomain mpu_3xxx_pwrdm;
+extern struct powerdomain core_3xxx_pre_es3_1_pwrdm;
extern void pwrdm_lock(struct powerdomain *pwrdm);
extern void pwrdm_unlock(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 7b946f1..2c2b630 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -63,3 +63,46 @@ struct powerdomain wkup_omap2_pwrdm = {
.pwrsts = PWRSTS_ON,
.voltdm = { .name = wakeup },
};
+
+struct powerdomain mpu_3xxx_pwrdm = {
+ .name = mpu_pwrdm,
+ .prcm_offs= MPU_MOD,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .flags= PWRDM_HAS_MPU_QUIRK,
+ .banks= 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET,
+ },
+ .pwrsts_mem_on= {
+ [0] = PWRSTS_OFF_ON,
+ },
+ .voltdm = { .name = mpu_iva },
+};
+
+/*
+ * The
Re: [PATCH 1/2] i2c: omap: convert to module_platform_driver()
The similar patch already exists: https://patchwork.kernel.org/patch/2448251/ - [v2,1/2] RTC: rtc-twl: Fix rtc_reg_map initialization from Peter Ujfalusi So, I think it is best if you resend this patch after all the fixes it needs are applied or you resend the series with all patches it depends on. Which should then probably go via arm-soc. Or? signature.asc Description: Digital signature
Re: [PATCH 3/3] ARM: DTS: TWL4030: fix mux and wakeup for SYS_NIRQ line
Salut Kevin,
On 06/04/2013 12:19 AM, Kevin Hilman wrote:
Florian Vaussard florian.vauss...@epfl.ch writes:
Hello Kevin,
On 06/01/2013 12:45 AM, Kevin Hilman wrote:
On most OMAP3 platforms, the twl4030 IRQ line is connected to the
SYS_NIRQ line on OMAP. Therefore, configure the defaults for the
SYS_NIRQ pin in the twl4030 DTS file.
Boards that hook up the twl4030 differently can easily override this
in their board-specific DTS file.
This allows RTC wake from off-mode to work again on OMAP3-based
platforms with twl4030. Tested on 3530/Beagle, 3730/Beagle-xM,
3530/Overo, 3730/Overo-STORM.
Signed-off-by: Kevin Hilman khil...@linaro.org
---
arch/arm/boot/dts/twl4030.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index b3034da..c7fe9f6 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -13,6 +13,8 @@
compatible = ti,twl4030;
interrupt-controller;
#interrupt-cells = 1;
+ pinctrl-names = default;
+ pinctrl-0 = twl4030_pins;
rtc {
compatible = ti,twl4030-rtc;
@@ -92,3 +94,18 @@
#pwm-cells = 2;
};
};
+
+omap3_pmx_core {
Here you are making the TWL4030 to explicitly depend on OMAP3. Could
this chip be used by another target? If the case, I would put this
piece of code in the files including twl4030. Otherwise it's ok here.
I talked this over with Tony before posting. In theorry, it could be
used on other platforms. In practice, it's only used on OMAP. We can
easily move this to board files if needed later, but thought it would be
simpler to put it here. I'll let Benoit decide.
Yeah, I don't like that either. Some twl variants are used on other
platform. And these variants might include the original twl4030 as a
base. None of them are in mainline for sure, but anyway adding SoC stuff
in external IC file is not a good practice.
I don't want people in the future using that as an excuse for similar hacks.
The easiest way is to create an extra file including the platform free
twl4030 file and adding the OMAP3 specific config on top of that.
Every OMAP3 boards will the used that file. Otherwise you can hack each
boards.
Regards,
Benoit
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Re: [PATCH 2/4] ARM: dts: omap5-uevm: Add USB Host support
On 12:16-20130605, Sricharan R wrote:
From: Roger Quadros rog...@ti.com
[...]
diff --git a/arch/arm/boot/dts/omap5-uevm.dts
b/arch/arm/boot/dts/omap5-uevm.dts
index 843a001..cf862df 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
snip
+ /* hsusb2_phy is clocked by FREF_CLK1 i.e. auxclk1 */
+ clock_alias {
+ clock-name = auxclk1_ck;
+ clock-alias = main_clk;
is'nt this better to use with clock node?
+ device = hsusb2_phy;
+ clock-frequency = 1920; /* 19.2 MHz */
+ };
};
snip
--
Regards,
Nishanth Menon
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Re: [PATCH 3/3] ARM: DTS: TWL4030: fix mux and wakeup for SYS_NIRQ line
Benoit Cousson b-cous...@ti.com writes:
Salut Kevin,
On 06/04/2013 12:19 AM, Kevin Hilman wrote:
Florian Vaussard florian.vauss...@epfl.ch writes:
Hello Kevin,
On 06/01/2013 12:45 AM, Kevin Hilman wrote:
On most OMAP3 platforms, the twl4030 IRQ line is connected to the
SYS_NIRQ line on OMAP. Therefore, configure the defaults for the
SYS_NIRQ pin in the twl4030 DTS file.
Boards that hook up the twl4030 differently can easily override this
in their board-specific DTS file.
This allows RTC wake from off-mode to work again on OMAP3-based
platforms with twl4030. Tested on 3530/Beagle, 3730/Beagle-xM,
3530/Overo, 3730/Overo-STORM.
Signed-off-by: Kevin Hilman khil...@linaro.org
---
arch/arm/boot/dts/twl4030.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/twl4030.dtsi
b/arch/arm/boot/dts/twl4030.dtsi
index b3034da..c7fe9f6 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -13,6 +13,8 @@
compatible = ti,twl4030;
interrupt-controller;
#interrupt-cells = 1;
+ pinctrl-names = default;
+ pinctrl-0 = twl4030_pins;
rtc {
compatible = ti,twl4030-rtc;
@@ -92,3 +94,18 @@
#pwm-cells = 2;
};
};
+
+omap3_pmx_core {
Here you are making the TWL4030 to explicitly depend on OMAP3. Could
this chip be used by another target? If the case, I would put this
piece of code in the files including twl4030. Otherwise it's ok here.
I talked this over with Tony before posting. In theorry, it could be
used on other platforms. In practice, it's only used on OMAP. We can
easily move this to board files if needed later, but thought it would be
simpler to put it here. I'll let Benoit decide.
Yeah, I don't like that either. Some twl variants are used on other
platform. And these variants might include the original twl4030 as a
base. None of them are in mainline for sure, but anyway adding SoC stuff
in external IC file is not a good practice.
I don't want people in the future using that as an excuse for similar hacks.
The easiest way is to create an extra file including the platform free
twl4030 file and adding the OMAP3 specific config on top of that.
Every OMAP3 boards will the used that file. Otherwise you can hack each
boards.
Yeah, somehow I knew you would say that. I'll respin.
Kevin
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Re: [PATCH] rtc: rtc-twl: ensure IRQ is wakeup enabled
On 06/04/2013 08:46 PM, Kevin Hilman wrote:
Grygorii Strashko grygorii.stras...@ti.com writes:
Hi Kevin,
On 06/01/2013 01:37 AM, Kevin Hilman wrote:
Currently, the RTC IRQ is never wakeup-enabled so is not capable of
bringing the system out of suspend.
On OMAP platforms, we have gotten by without this because the TWL RTC
is on an I2C-connected chip which is capable of waking up the OMAP via
the IO ring when the OMAP is in low-power states.
However, if the OMAP suspends without hitting the low-power states
(and the IO ring is not enabled), RTC wakeups will not work because
the IRQ is not wakeup enabled.
As I understand, IRQ wake up capabilities are set/clear simultaneously with
IRQ unmasking/masking on OMAP4+ in omap-wakeupgen.c.
So, it should work without this patch on OMAP4+.
It might work on OMAP4 for wakeup from suspend, but without properly
declaring the IRQ as a wakeup source, it will not abort suspend if the
RTC fires during the suspend process. To abort suspend, the IRQ must be
declared as a wakeup IRQ.
But if TWL is used on non OMAP4+ platform then it is needed. (OMAP3:
I haven't found the place where IRQ wakeup capabilities are
configured, would be appreciate if you can point me on)
IRQ wakeup is a genirq feature that trickles into the irq_chip (in OMAP3
case, it's the twl4030 irq_chip.)
On OMAP3, as mentioned in the changelog, RTC wake has been working fine
without this because we default to CORE retention, so wakeup happens via
the IO ring. However, if you prevent retention during suspend, then
this IRQ will not wake the system.
Kevin
To fix, ensure the RTC IRQ is wakeup enabled whenever the RTC alarm is
set.
Cc: Alessandro Zummo a.zu...@towertech.it
Cc: Andrew Morton a...@linux-foundation.org
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Kevin Hilman khil...@linaro.org
---
drivers/rtc/rtc-twl.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
index 8751a52..bbda0fd 100644
--- a/drivers/rtc/rtc-twl.c
+++ b/drivers/rtc/rtc-twl.c
@@ -213,12 +213,24 @@ static int mask_rtc_irq_bit(unsigned char bit)
static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned
enabled)
{
+ struct platform_device *pdev = to_platform_device(dev);
+ int irq = platform_get_irq(pdev, 0);
+ static bool twl_rtc_wake_enabled;
int ret;
-if (enabled)
+ if (enabled) {
ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
- else
+ if (device_can_wakeup(dev) !twl_rtc_wake_enabled) {
+ enable_irq_wake(irq);
+ twl_rtc_wake_enabled = true;
+ }
+ } else {
ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
+ if (twl_rtc_wake_enabled) {
+ disable_irq_wake(irq);
+ twl_rtc_wake_enabled = false;
+ }
+ }
return ret;
}
twl-rtc has suspend/resume callbacks implemented, so I think it's the
better place
for this code and twl_rtc_wake_enabled can be dropped.
In theory, that might be the better place (and that's where I put these
at first), but unfortunately, it doesn't work that way because the
twl6030-irq core enables/diables the parent IRQ wake feature using PM
notifiers (which was done to avoid potential lock recursion[1].)
During suspend, the notifier runs at suspend_prepare() time, which is
well before the driver's -suspend() method is called. The result is
that the parents IRQ wakeup capabilies are never set.
Sorry, forget about this patch - have no questions for this patch anymore.
Thanks.
Just FYI. It seems, The suspend will never be aborted on OMAP4 by SYSN_IRQ
because of these two patches:
782baa2 mfd: Disable twl6030 IRQ during suspend
9c6079a genirq: Do not consider disabled wakeup irqs
-grygorii
Kevin
[1]
commit ab2b9260df67e29d5bd69d989f2f84f8c2ed4238
Author: Todd Poynor toddpoy...@google.com
Date: Tue Oct 4 11:52:29 2011 +0200
mfd: Fix twl6030 lockdep recursion warning on setting wake IRQs
LOCKDEP explicitly sets all irq_desc locks as a single lock-class,
causing possible recursive locking detected when the TWL RTC
driver calls through enable_irq_wake to twl6030_irq_set_wake,
which recursively calls irq_set_irq_wake. Although the
irq_desc and lock are different, LOCKDEP treats these as
equivalent, presumably due to problems that can be incurred
when locking more than one irq_desc, so best to avoid this.
Suspend/resume actions implemented as PM notifiers to avoid
touch the TWL core for this.
Signed-off-by: Todd Poynor toddpoy...@google.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Samuel Ortiz sa...@linux.intel.com
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[PATCH 5/5] ARM: OMAP: DM816x: add hwmod support for DM81xx
OCP interface data structures were added in order to achieve successful initialization of hwmods on DM816x. Required DM81xx family IRQ definitions, offsets of the PRCM clock control registers and additional OMAP2PLUS DMA channel definitions were added as they are needed during the hwmod registration. omap3xxx_hwmod_init() call was substituted by dm81xx_hwmod_init(). Signed-off-by: Aida Mynzhasova aida.mynzhas...@skitlab.ru --- arch/arm/mach-omap2/Makefile |1 + arch/arm/mach-omap2/cm_dm81xx.h | 20 + arch/arm/mach-omap2/dm81xx.h | 28 +- arch/arm/mach-omap2/dma.h | 12 + arch/arm/mach-omap2/io.c |2 +- arch/arm/mach-omap2/omap_hwmod.h |1 + arch/arm/mach-omap2/omap_hwmod_dm81xx_data.c | 1209 + arch/arm/plat-omap/include/plat/dmtimer.h |6 + arch/arm/plat-omap/include/plat/irqs-dm81xx.h | 43 + 9 files changed, 1320 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-omap2/omap_hwmod_dm81xx_data.c create mode 100644 arch/arm/plat-omap/include/plat/irqs-dm81xx.h diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 132a1e2..3b5cc8b 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -202,6 +202,7 @@ obj-$(CONFIG_ARCH_OMAP3)+= omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_am33xx_data.o +obj-$(CONFIG_SOC_DM81XX) += omap_hwmod_dm81xx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o # EMU peripherals diff --git a/arch/arm/mach-omap2/cm_dm81xx.h b/arch/arm/mach-omap2/cm_dm81xx.h index f8988da..d8268cd 100644 --- a/arch/arm/mach-omap2/cm_dm81xx.h +++ b/arch/arm/mach-omap2/cm_dm81xx.h @@ -58,4 +58,24 @@ #define DM816X_CM_DEFAULT_PCI_CLKDM0x0010 #define DM816X_CM_DEFAULT_L3_SLOW_CLKDM0x0014 +#define DM81XX_CM_ALWON_UART_0_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0150) +#define DM81XX_CM_ALWON_UART_1_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0154) +#define DM81XX_CM_ALWON_UART_2_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0158) +#define DM81XX_CM_ALWON_GPIO_0_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x015C) +#define DM81XX_CM_ALWON_GPIO_1_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0160) +#define DM81XX_CM_ALWON_WDTIMER_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x018C) +#define DM81XX_CM_ALWON_SPI_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0190) +#define DM816X_CM_ALWON_I2C_0_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0164) +#define DM816X_CM_ALWON_I2C_1_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0168) +#define DM816X_CM_DEFAULT_USB_CLKCTRL_OFF (DM816X_CM_DEFAULT_MOD + 0x0058) +#define DM816X_CM_ALWON_TIMER_0_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x016C) +#define DM816X_CM_ALWON_TIMER_1_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0170) +#define DM816X_CM_ALWON_TIMER_2_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0174) +#define DM816X_CM_ALWON_TIMER_3_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0178) +#define DM816X_CM_ALWON_TIMER_4_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x017C) +#define DM816X_CM_ALWON_TIMER_5_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0180) +#define DM816X_CM_ALWON_TIMER_6_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0184) +#define DM816X_CM_ALWON_TIMER_7_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0188) +#define DM816X_CM_ALWON_SDIO_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x15B0) +#define DM81XX_CM_ALWON_SPI_CLKCTRL_OFF(DM81XX_CM_ALWON_MOD + 0x0190) #endif diff --git a/arch/arm/mach-omap2/dm81xx.h b/arch/arm/mach-omap2/dm81xx.h index a0b18a6..e92a2d2 100644 --- a/arch/arm/mach-omap2/dm81xx.h +++ b/arch/arm/mach-omap2/dm81xx.h @@ -30,7 +30,33 @@ #define DM81XX_TAP_BASE(DM81XX_CTRL_BASE + \ DM81XX_CONTROL_DEVICE_ID - 0x204) +#define DM81XX_MAILBOX_BASE0x480C8000 -#define DM81XX_ARM_INTC_BASE 0x4820 +#define DM816X_WDTIMER1_BASE 0x480C2000 + +#define DM816X_I2C0_BASE 0x48028000 +#define DM816X_I2C1_BASE 0x4802A000 + +#define DM81XX_ELM_BASE0x4808 + +#define DM81XX_GPIO0_BASE 0x48032000 +#define DM81XX_GPIO1_BASE 0x4804C000 + +#define DM81XX_USBSS_BASE 0x4740 + +#define DM81XX_USB0_BASE 0x47401000 +#define DM81XX_USB1_BASE 0x47401800 + +#define DM816X_TIMER0_BASE 0x4802E000 +#define DM816X_TIMER1_BASE 0x4804 +#define DM816X_TIMER2_BASE 0x48042000 +#define DM816X_TIMER3_BASE 0x48044000 +#define DM816X_TIMER4_BASE 0x48046000 +#define DM816X_TIMER5_BASE 0x48048000 +#define DM816X_TIMER6_BASE 0x4804A000 + +#define DM816X_MMC0_BASE
[PATCH 0/5] Broken DM816x support in Linux 3.10-rc4
Not so long ago I tried to boot Linux 3.10-rc4 kernel on DM816x EVM board. Unfortunately, my attempts were failed by reason of poor support of DM81xx-based devices in new kernels. Actually, on Linux 3.10-rc4 kernel early initialization of board is failed when it tries to initialize power domains: [0.00] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa17f8e4 [0.00] Internal error: : 1028 [#1] SMP ARM [0.00] Modules linked in: [0.00] CPU: 0 PID: 0 Comm: swapper Not tainted 3.10.0-rc3-1-g0e5443c-dirty #12 [0.00] task: c076fc50 ti: c0764000 task.ti: c0764000 [0.00] PC is at omap2_pwrdm_wait_transition+0x1c/0xac [0.00] LR is at pwrdm_register_pwrdms+0x15c/0x1ac [0.00] pc : [c0031698]lr : [c0036010]psr: 6193 [0.00] sp : c0765f28 ip : c07bebe0 fp : 0001 [0.00] r10: c07e6a90 r9 : r8 : c07e6944 [0.00] r7 : c0754a50 r6 : c064f264 r5 : c0775298 r4 : c0773e9c [0.00] r3 : f8e4 r2 : fa17f8e4 r1 : 0004 r0 : c0775298 [0.00] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel [0.00] Control: 10c5387d Table: 80004019 DAC: 0017 [0.00] Process swapper (pid: 0, stack limit = 0xc0764240) [0.00] Stack: (0xc0765f28 to 0xc0766000) [0.00] 5f20: c0773e9c c0775298 c064f264 c0754a50 c0773ee4 c0036010 [0.00] 5f40: 35170034 81600134 c05125a8 fa18 8200 c0771348 c07b1b48 c07475ac [0.00] 5f60: c0771348 c07191fc c0647c40 c0711598 16c0 c0d24fb4 c06450ac c070c148 [0.00] 5f80: c0765f98 c0765f90 c0771134 c0765fdc [0.00] 5fa0: c0643878 0001 c0748774 c0771134 c076c880 413fc082 [0.00] 5fc0: c07086fc c0748778 [0.00] 5fe0: 10c53c7d c076c910 c0748774 c0771134 80004059 80008074 [0.00] [c0031698] (omap2_pwrdm_wait_transition+0x1c/0xac) from [c0036010] (pwrdm_register_pwrdms+0x15c/0x1ac) [0.00] [c0036010] (pwrdm_register_pwrdms+0x15c/0x1ac) from [c07191fc] (omap3xxx_powerdomains_init+0x50/0x144) [0.00] [c07191fc] (omap3xxx_powerdomains_init+0x50/0x144) from [c0711598] (ti81xx_init_early+0xcc/0x178) [0.00] [c0711598] (ti81xx_init_early+0xcc/0x178) from [c070c148] (setup_arch+0x5ac/0x800) [0.00] [c070c148] (setup_arch+0x5ac/0x800) from [c07086fc] (start_kernel+0x7c/0x330) [0.00] [c07086fc] (start_kernel+0x7c/0x330) from [80008074] (0x80008074) [0.00] Code: e1d030f8 e5982000 e28330e4 e0822003 (e5921000) [0.00] ---[ end trace 1b75b31a2719ed1c ]--- So, I suggest you this patch series, which fixes that kernel crush and adds new functions/structures, required for early initialization on DM816x (power and clock domains, hwmods). After applying these patches the kernel is able to successfully continue booting till clock initialization (will be added later). Thanks, Aida Aida Mynzhasova (5): ARM: OMAP: DM81xx: multiple renames for DM81xx platform ARM: OMAP: AM33xx: multiple renames for early initialization ARM: OMAP: DM816x: add powerdomains for DM816x ARM: OMAP: DM816x: add clock domain support for DM816x ARM: OMAP: DM816x: add hwmod support for DM81xx arch/arm/Kconfig.debug | 12 +- arch/arm/include/debug/omap2plus.S | 20 +- arch/arm/mach-omap2/Kconfig | 16 +- arch/arm/mach-omap2/Makefile | 22 +- arch/arm/mach-omap2/am33xx-restart.c |4 +- arch/arm/mach-omap2/board-dm816x-evm.c | 62 + arch/arm/mach-omap2/board-ti8168evm.c| 62 - arch/arm/mach-omap2/cclock33xx_data.c| 990 -- arch/arm/mach-omap2/cclock3xxx_data.c|6 +- arch/arm/mach-omap2/cclock_am33xx_data.c | 990 ++ arch/arm/mach-omap2/clock.h |4 +- arch/arm/mach-omap2/clockdomain.h|3 + arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 10 + arch/arm/mach-omap2/clockdomains33xx_data.c | 196 -- arch/arm/mach-omap2/clockdomains_am33xx_data.c | 196 ++ arch/arm/mach-omap2/clockdomains_dm81xx_data.c | 213 ++ arch/arm/mach-omap2/cm-regbits-33xx.h| 817 - arch/arm/mach-omap2/cm-regbits-am33xx.h | 817 + arch/arm/mach-omap2/cm-regbits-dm81xx.h | 22 + arch/arm/mach-omap2/cm33xx.c | 364 --- arch/arm/mach-omap2/cm33xx.h | 417 --- arch/arm/mach-omap2/cm_am33xx.c | 364 +++ arch/arm/mach-omap2/cm_am33xx.h | 417 +++ arch/arm/mach-omap2/cm_dm81xx.h | 81 + arch/arm/mach-omap2/common.h |8 +- arch/arm/mach-omap2/control.h|8 +- arch/arm/mach-omap2/dm81xx.h |
[PATCH 3/5] ARM: OMAP: DM816x: add powerdomains for DM816x
This patch adds required structures for powerdomain initialization on
the DM816x. It is impossible to use OMAP3430 structures in order to
initialize powerdomains on DM816x, because there are big differences
between PRCM module base address offsets on these CPUs.
Signed-off-by: Aida Mynzhasova aida.mynzhas...@skitlab.ru
---
arch/arm/mach-omap2/Makefile |3 +
arch/arm/mach-omap2/io.c |2 +-
arch/arm/mach-omap2/powerdomain.h|4 +
arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c | 43
arch/arm/mach-omap2/powerdomains3xxx_data.c | 43
arch/arm/mach-omap2/powerdomains_dm81xx_data.c | 115 ++
arch/arm/mach-omap2/prm-regbits-dm81xx.h | 24 +
arch/arm/mach-omap2/prm_dm81xx.c | 79 +++
arch/arm/mach-omap2/prm_dm81xx.h | 44 +
9 files changed, 313 insertions(+), 44 deletions(-)
create mode 100644 arch/arm/mach-omap2/powerdomains_dm81xx_data.c
create mode 100644 arch/arm/mach-omap2/prm-regbits-dm81xx.h
create mode 100644 arch/arm/mach-omap2/prm_dm81xx.c
create mode 100644 arch/arm/mach-omap2/prm_dm81xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 607a2bf..03121cc 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -113,6 +113,7 @@ obj-$(CONFIG_SOC_AM33XX)+= prm_am33xx.o
cm_am33xx.o
omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
prcm_mpu44xx.o prminst44xx.o \
vc44xx_data.o vp44xx_data.o
+obj-$(CONFIG_SOC_DM81XX) += prm_dm81xx.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_OMAP5)+= $(omap-prcm-4-5-common)
@@ -140,6 +141,8 @@ obj-$(CONFIG_ARCH_OMAP4)+= $(powerdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_AM33XX) += powerdomains_am33xx_data.o
+obj-$(CONFIG_SOC_DM81XX) += $(powerdomain-common)
+obj-$(CONFIG_SOC_DM81XX) += powerdomains_dm81xx_data.o
obj-$(CONFIG_SOC_OMAP5)+= $(powerdomain-common)
# PRCM clockdomain control
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3deba6e..2a9e5b3 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -516,7 +516,7 @@ void __init dm81xx_init_early(void)
omap3xxx_check_revision();
dm81xx_check_features();
omap3xxx_voltagedomains_init();
- omap3xxx_powerdomains_init();
+ dm81xx_powerdomains_init();
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
diff --git a/arch/arm/mach-omap2/powerdomain.h
b/arch/arm/mach-omap2/powerdomain.h
index 140c360..6d78990 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -252,11 +252,13 @@ extern void omap242x_powerdomains_init(void);
extern void omap243x_powerdomains_init(void);
extern void omap3xxx_powerdomains_init(void);
extern void am33xx_powerdomains_init(void);
+extern void dm81xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
extern struct pwrdm_ops am33xx_pwrdm_operations;
+extern struct pwrdm_ops dm81xx_pwrdm_operations;
extern struct pwrdm_ops omap4_pwrdm_operations;
/* Common Internal functions used across OMAP rev's */
@@ -266,6 +268,8 @@ extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
extern struct powerdomain wkup_omap2_pwrdm;
extern struct powerdomain gfx_omap2_pwrdm;
+extern struct powerdomain mpu_3xxx_pwrdm;
+extern struct powerdomain core_3xxx_pre_es3_1_pwrdm;
extern void pwrdm_lock(struct powerdomain *pwrdm);
extern void pwrdm_unlock(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 7b946f1..2c2b630 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -63,3 +63,46 @@ struct powerdomain wkup_omap2_pwrdm = {
.pwrsts = PWRSTS_ON,
.voltdm = { .name = wakeup },
};
+
+struct powerdomain mpu_3xxx_pwrdm = {
+ .name = mpu_pwrdm,
+ .prcm_offs= MPU_MOD,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .flags= PWRDM_HAS_MPU_QUIRK,
+ .banks= 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET,
+ },
+ .pwrsts_mem_on= {
+ [0] = PWRSTS_OFF_ON,
+ },
+ .voltdm = { .name = mpu_iva },
+};
+
+/*
+ * The
[PATCH 4/5] ARM: OMAP: DM816x: add clock domain support for DM816x
This patch adds required definitions and structures for clockdomain
initialization:
1. register offsets for DM81xx and DM816x clock domain modules;
2. clock domain register bits;
3. additional OMAP2/3 common clock domains: prm_clkdm and cm_clkdm;
4. clockdomain structure definitions for DM816x.
Also, omap3xxx_clockdomains_init() was substituted by new
dm81xx_clockdomains_init().
Signed-off-by: Aida Mynzhasova aida.mynzhas...@skitlab.ru
---
arch/arm/mach-omap2/Makefile |2 +
arch/arm/mach-omap2/clockdomain.h|3 +
arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 10 +
arch/arm/mach-omap2/clockdomains_dm81xx_data.c | 213 ++
arch/arm/mach-omap2/cm-regbits-dm81xx.h | 22 +++
arch/arm/mach-omap2/cm_dm81xx.h | 61 +++
arch/arm/mach-omap2/io.c |2 +-
7 files changed, 312 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-omap2/clockdomains_dm81xx_data.c
create mode 100644 arch/arm/mach-omap2/cm-regbits-dm81xx.h
create mode 100644 arch/arm/mach-omap2/cm_dm81xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 03121cc..132a1e2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -158,6 +158,8 @@ obj-$(CONFIG_ARCH_OMAP4)+= $(clockdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_AM33XX) += clockdomains_am33xx_data.o
+obj-$(CONFIG_SOC_DM81XX) += $(clockdomain-common)
+obj-$(CONFIG_SOC_DM81XX) += clockdomains_dm81xx_data.o
obj-$(CONFIG_SOC_OMAP5)+= $(clockdomain-common)
# Clock framework
diff --git a/arch/arm/mach-omap2/clockdomain.h
b/arch/arm/mach-omap2/clockdomain.h
index 2da3765..0a9d4fc 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -215,6 +215,7 @@ extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
+extern void __init dm81xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void clkdm_add_autodeps(struct clockdomain *clkdm);
@@ -228,5 +229,7 @@ extern struct clkdm_ops am33xx_clkdm_operations;
extern struct clkdm_dep gfx_24xx_wkdeps[];
extern struct clkdm_dep dsp_24xx_wkdeps[];
extern struct clockdomain wkup_common_clkdm;
+extern struct clockdomain cm_common_clkdm;
+extern struct clockdomain prm_common_clkdm;
#endif
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 49722196..8a62c7f 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -90,3 +90,13 @@ struct clockdomain wkup_common_clkdm = {
.dep_bit= OMAP_EN_WKUP_SHIFT,
.flags = CLKDM_ACTIVE_WITH_MPU,
};
+
+struct clockdomain prm_common_clkdm = {
+ .name = prm_clkdm,
+ .pwrdm = { .name = wkup_pwrdm },
+};
+
+struct clockdomain cm_common_clkdm = {
+ .name = cm_clkdm,
+ .pwrdm = { .name = core_pwrdm },
+};
diff --git a/arch/arm/mach-omap2/clockdomains_dm81xx_data.c
b/arch/arm/mach-omap2/clockdomains_dm81xx_data.c
new file mode 100644
index 000..daf390f
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains_dm81xx_data.c
@@ -0,0 +1,213 @@
+/*
+ * DM81XX Clock Domain data.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_DM81XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_DM81XX_H
+
+#include linux/kernel.h
+#include linux/io.h
+
+#include clockdomain.h
+
+#include cm_dm81xx.h
+#include cm-regbits-dm81xx.h
+
+/*
+ * TODO:
+ * - Add other domains as required
+ * - Fill up associated powerdomans (especially ALWON powerdomains are NULL at
+ * the moment
+ * - Consider dependencies across domains (probably not applicable till now)
+ */
+
+/* Common DM81XX */
+static struct clockdomain alwon_l3_slow_dm81xx_clkdm = {
+ .name = alwon_l3_slow_clkdm,
+ .pwrdm = { .name = alwon_pwrdm },
+ .cm_inst= DM81XX_CM_ALWON_MOD,
+ .clkdm_offs = DM81XX_CM_ALWON_L3_SLOW_CLKDM,
+
[PATCH 1/5] ARM: OMAP: DM81xx: multiple renames for DM81xx platform
This patch renames all DM81xx platform related structures, variables, files, and functions. Previously names with ti81 prefixes were used, which are inconsistent, because actual name of the platform is DM81xx. Also, for the same reason DM816x EVM was renamed from board-ti8168evm to board-dm816x-evm. Signed-off-by: Aida Mynzhasova aida.mynzhas...@skitlab.ru --- arch/arm/Kconfig.debug| 12 +++--- arch/arm/include/debug/omap2plus.S| 20 +- arch/arm/mach-omap2/Kconfig | 16 arch/arm/mach-omap2/Makefile |4 +- arch/arm/mach-omap2/board-dm816x-evm.c| 62 + arch/arm/mach-omap2/board-ti8168evm.c | 62 - arch/arm/mach-omap2/cclock3xxx_data.c |6 +-- arch/arm/mach-omap2/clock.h |4 +- arch/arm/mach-omap2/common.h |8 ++-- arch/arm/mach-omap2/control.h |8 ++-- arch/arm/mach-omap2/dm81xx.h | 36 + arch/arm/mach-omap2/id.c | 20 +- arch/arm/mach-omap2/include/mach/serial.h |8 ++-- arch/arm/mach-omap2/io.c | 26 ++-- arch/arm/mach-omap2/irq.c |4 +- arch/arm/mach-omap2/omap_phy_internal.c | 18 - arch/arm/mach-omap2/soc.h | 54 - arch/arm/mach-omap2/ti81xx.h | 36 - arch/arm/mach-omap2/usb-musb.c|4 +- arch/arm/mach-omap2/usb.h | 12 +++--- arch/arm/tools/mach-types |4 +- drivers/pci/quirks.c |6 +-- drivers/usb/musb/musb_dsps.c | 12 +++--- drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c |2 +- include/linux/platform_data/davinci_asp.h |2 +- 25 files changed, 223 insertions(+), 223 deletions(-) create mode 100644 arch/arm/mach-omap2/board-dm816x-evm.c delete mode 100644 arch/arm/mach-omap2/board-ti8168evm.c create mode 100644 arch/arm/mach-omap2/dm81xx.h delete mode 100644 arch/arm/mach-omap2/ti81xx.h diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 1d41908..55e18d6 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -571,14 +571,14 @@ choice config DEBUG_OMAP4UART4 bool OMAP4/5 UART4 - config DEBUG_TI81XXUART1 - bool TI81XX UART1 (ti8148evm) + config DEBUG_DM81XXUART1 + bool DM81XX UART1 (DM8148evm) - config DEBUG_TI81XXUART2 - bool TI81XX UART2 + config DEBUG_DM81XXUART2 + bool DM81XX UART2 - config DEBUG_TI81XXUART3 - bool TI81XX UART3 (ti8168evm) + config DEBUG_DM81XXUART3 + bool DM81XX UART3 (DM8168evm) config DEBUG_AM33XXUART1 bool AM33XX UART1 diff --git a/arch/arm/include/debug/omap2plus.S b/arch/arm/include/debug/omap2plus.S index 6d867ae..76d643b 100644 --- a/arch/arm/include/debug/omap2plus.S +++ b/arch/arm/include/debug/omap2plus.S @@ -30,10 +30,10 @@ #define OMAP4_UART3_BASE 0x4802 #define OMAP4_UART4_BASE 0x4806e000 -/* TI81XX serial ports */ -#define TI81XX_UART1_BASE 0x4802 -#define TI81XX_UART2_BASE 0x48022000 -#define TI81XX_UART3_BASE 0x48024000 +/* DM81XX serial ports */ +#define DM81XX_UART1_BASE 0x4802 +#define DM81XX_UART2_BASE 0x48022000 +#define DM81XX_UART3_BASE 0x48024000 /* AM3505/3517 UART4 */ #define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ @@ -111,16 +111,16 @@ omap_uart_lsr:.word 0 mov \rp, #UART_OFFSET(OMAP4_UART4_BASE) b 98f #endif -#ifdef CONFIG_DEBUG_TI81XXUART1 - mov \rp, #UART_OFFSET(TI81XX_UART1_BASE) +#ifdef CONFIG_DEBUG_DM81XXUART1 + mov \rp, #UART_OFFSET(DM81XX_UART1_BASE) b 98f #endif -#ifdef CONFIG_DEBUG_TI81XXUART2 - mov \rp, #UART_OFFSET(TI81XX_UART2_BASE) +#ifdef CONFIG_DEBUG_DM81XXUART2 + mov \rp, #UART_OFFSET(DM81XX_UART2_BASE) b 98f #endif -#ifdef CONFIG_DEBUG_TI81XXUART3 - mov \rp, #UART_OFFSET(TI81XX_UART3_BASE) +#ifdef CONFIG_DEBUG_DM81XXUART3 + mov \rp, #UART_OFFSET(DM81XX_UART3_BASE) b 98f #endif #ifdef CONFIG_DEBUG_AM33XXUART1 diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index f49cd51..376600b 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -135,8 +135,8 @@ config SOC_OMAP3430 default y select SOC_HAS_OMAP2_SDRC -config SOC_TI81XX - bool TI81XX support +config SOC_DM81XX + bool DM81xx support depends on ARCH_OMAP3 default y @@ -368,14 +368,14 @@ config MACH_OMAP_3630SDP default y select OMAP_PACKAGE_CBP -config MACH_TI8168EVM -
Re: [PATCH] rtc: rtc-twl: ensure IRQ is wakeup enabled
Grygorii Strashko grygorii.stras...@ti.com writes:
On 06/04/2013 08:46 PM, Kevin Hilman wrote:
Grygorii Strashko grygorii.stras...@ti.com writes:
Hi Kevin,
On 06/01/2013 01:37 AM, Kevin Hilman wrote:
Currently, the RTC IRQ is never wakeup-enabled so is not capable of
bringing the system out of suspend.
On OMAP platforms, we have gotten by without this because the TWL RTC
is on an I2C-connected chip which is capable of waking up the OMAP via
the IO ring when the OMAP is in low-power states.
However, if the OMAP suspends without hitting the low-power states
(and the IO ring is not enabled), RTC wakeups will not work because
the IRQ is not wakeup enabled.
As I understand, IRQ wake up capabilities are set/clear simultaneously with
IRQ unmasking/masking on OMAP4+ in omap-wakeupgen.c.
So, it should work without this patch on OMAP4+.
It might work on OMAP4 for wakeup from suspend, but without properly
declaring the IRQ as a wakeup source, it will not abort suspend if the
RTC fires during the suspend process. To abort suspend, the IRQ must be
declared as a wakeup IRQ.
But if TWL is used on non OMAP4+ platform then it is needed. (OMAP3:
I haven't found the place where IRQ wakeup capabilities are
configured, would be appreciate if you can point me on)
IRQ wakeup is a genirq feature that trickles into the irq_chip (in OMAP3
case, it's the twl4030 irq_chip.)
On OMAP3, as mentioned in the changelog, RTC wake has been working fine
without this because we default to CORE retention, so wakeup happens via
the IO ring. However, if you prevent retention during suspend, then
this IRQ will not wake the system.
Kevin
To fix, ensure the RTC IRQ is wakeup enabled whenever the RTC alarm is
set.
Cc: Alessandro Zummo a.zu...@towertech.it
Cc: Andrew Morton a...@linux-foundation.org
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Kevin Hilman khil...@linaro.org
---
drivers/rtc/rtc-twl.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
index 8751a52..bbda0fd 100644
--- a/drivers/rtc/rtc-twl.c
+++ b/drivers/rtc/rtc-twl.c
@@ -213,12 +213,24 @@ static int mask_rtc_irq_bit(unsigned char bit)
static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned
enabled)
{
+ struct platform_device *pdev = to_platform_device(dev);
+ int irq = platform_get_irq(pdev, 0);
+ static bool twl_rtc_wake_enabled;
int ret;
- if (enabled)
+ if (enabled) {
ret =
set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
- else
+ if (device_can_wakeup(dev) !twl_rtc_wake_enabled) {
+ enable_irq_wake(irq);
+ twl_rtc_wake_enabled = true;
+ }
+ } else {
ret =
mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
+ if (twl_rtc_wake_enabled) {
+ disable_irq_wake(irq);
+ twl_rtc_wake_enabled = false;
+ }
+ }
return ret;
}
twl-rtc has suspend/resume callbacks implemented, so I think it's the
better place
for this code and twl_rtc_wake_enabled can be dropped.
In theory, that might be the better place (and that's where I put these
at first), but unfortunately, it doesn't work that way because the
twl6030-irq core enables/diables the parent IRQ wake feature using PM
notifiers (which was done to avoid potential lock recursion[1].)
During suspend, the notifier runs at suspend_prepare() time, which is
well before the driver's -suspend() method is called. The result is
that the parents IRQ wakeup capabilies are never set.
Sorry, forget about this patch - have no questions for this patch anymore.
Thanks.
Just FYI. It seems, The suspend will never be aborted on OMAP4 by SYSN_IRQ
because of these two patches:
782baa2 mfd: Disable twl6030 IRQ during suspend
9c6079a genirq: Do not consider disabled wakeup irqs
You're right for the parent TWL IRQ, but the child interrupts (e.g. RTC)
would still abort suspend if wakeup enabled.
Kevin
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Re: [PATCH] gpio/omap: omap_gpio_init_context stub must be inline
* Arnd Bergmann a...@arndb.de [130531 09:05]:
The bug fix 352a2d5bf gpio/omap: ensure gpio context is initialised
has caused a new warning for omap1_defconfig:
drivers/gpio/gpio-omap.c:1465:13: warning: 'omap_gpio_init_context' defined
but not used [-Wunused-function]
static void omap_gpio_init_context(struct gpio_bank *p) {}
^
The solution is to mark the stub function as 'static inline' so
it gets left out of the build when unused.
Acked-by: Tony Lindgren t...@atomide.com
Signed-off-by: Arnd Bergmann a...@arndb.de
---
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index d3f7d2d..e5fba65 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1462,7 +1462,7 @@ static void omap_gpio_restore_context(struct gpio_bank
*bank)
#else
#define omap_gpio_runtime_suspend NULL
#define omap_gpio_runtime_resume NULL
-static void omap_gpio_init_context(struct gpio_bank *p) {}
+static inline void omap_gpio_init_context(struct gpio_bank *p) {}
#endif
static const struct dev_pm_ops gpio_pm_ops = {
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Re: [net-next PATCH v3 1/6] net: cpsw: enhance pinctrl support
* Mugunthan V N mugunthan...@ti.com [130530 01:14]:
On 5/28/2013 7:35 PM, Mugunthan V N wrote:
On 5/28/2013 3:06 AM, Tony Lindgren wrote:
* Mugunthan V N mugunthan...@ti.com [130526 11:28]:
From: Hebbar Gururaja gururaja.heb...@ti.com
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- default on boot, resume
- sleep on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
drivers/net/ethernet/ti/cpsw.c | 48
1 file changed, 48 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c
b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..c9ed730 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
#include linux/if_vlan.h
#include linux/platform_data/cpsw.h
+#include linux/pinctrl/consumer.h
#include cpsw_ale.h
#include cpts.h
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+/* Two optional pin states - default sleep */
+struct pinctrl*pinctrl;
+struct pinctrl_state*pins_def;
+struct pinctrl_state*pins_sleep;
};
Which pins do you need to dynamically remux? If it's not all
the pins, you should have three sets: default, active and idle.
This way the static pins in the default group don't need to be
constantly toggled.
Regards,
Tony
Tony
I am using this for all the pins, in probe all the cpsw pins will
be configured
and i have used the same in suspend/resume callback for power saving.
Tony
Do you have any comments on this, or is it ok with two pinctrl_state nodes?
If you always need to remux all the pins, then yes that's fine with me.
Regards,
Tony
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Re: [PATCH] gpio/omap: omap_gpio_init_context stub must be inline
On Friday 31 May 2013 11:59 AM, Arnd Bergmann wrote:
The bug fix 352a2d5bf gpio/omap: ensure gpio context is initialised
has caused a new warning for omap1_defconfig:
drivers/gpio/gpio-omap.c:1465:13: warning: 'omap_gpio_init_context' defined
but not used [-Wunused-function]
static void omap_gpio_init_context(struct gpio_bank *p) {}
^
The solution is to mark the stub function as 'static inline' so
it gets left out of the build when unused.
Signed-off-by: Arnd Bergmann a...@arndb.de
---
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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Re: [PATCH] i2c: Let users disable Probe an I2C bus for certain devices
Hi On 06/04/2013 08:49 PM, Wolfram Sang wrote: On Tue, Jun 04, 2013 at 08:33:42PM +0300, Grygorii Strashko wrote: Currently the I2C devices instantiation Method 3 Probe an I2C bus for certain devices (see Documentation/i2c/instantiating-devices) is always enabled for all platforms (boards) and can't be disabled. Not true. Set .class = 0 for your adapter. I always ask authors of new drivers if they really need to set .class to something. Agree, sorry, my statement is wrong. it would be right to say ..can't be disabled without kernel code modification. Few notes here: 1) boot delay issue isn't related to new drivers. There are hwmon/lm75.c, i2c/busses/i2c-gpio.c and i2c/busses/i2c-omap.c 2) Initially, I've fighted with it on TI K3.4 product kernel where DT isn't supported yet. And first thing, which I've tried to do is to correct .class parameter for adapter, but with assumption: Default behavior shouldn't be changed as I2C detection might be used by some of OMAP boards. I've started from i2c-omap.c and OMAP4/5 (my target). As result, I was need to make changes in *7* files to set and pass platform parameter to i2c-omap.c driver which will allow to change .class to 0 on demand. At this point, I've realized that i still need to deal with i2c-gpio.c - which is generic driver. 3) Thinking about Mainline: To reach the same target - no I2C detection - and taking into account above assumption No changes in default behavior the following will need to be done: - change i2c-omap/i2c-gpio DT bindings and add parameter which will allow to change .class value for adapter. Not sure, it's possible because this parameter will be Linux and not HW specific (smth. like i2c_disable_detection) - update drivers i2c-omap/i2c-gpio to use i2c_disable_detection - update OMAP4/5 DTS files So, It seemed a good solution for me to add 6 lines of code in i2c-core.c instead of doing all that stuff. Thanks/sorry for your time. - grygorii -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [net-next PATCH v3 1/6] net: cpsw: enhance pinctrl support
On 6/5/2013 9:19 PM, Tony Lindgren wrote:
* Mugunthan V N mugunthan...@ti.com [130530 01:14]:
On 5/28/2013 7:35 PM, Mugunthan V N wrote:
On 5/28/2013 3:06 AM, Tony Lindgren wrote:
* Mugunthan V N mugunthan...@ti.com [130526 11:28]:
From: Hebbar Gururaja gururaja.heb...@ti.com
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- default on boot, resume
- sleep on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
drivers/net/ethernet/ti/cpsw.c | 48
1 file changed, 48 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c
b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..c9ed730 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
#include linux/if_vlan.h
#include linux/platform_data/cpsw.h
+#include linux/pinctrl/consumer.h
#include cpsw_ale.h
#include cpts.h
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+/* Two optional pin states - default sleep */
+struct pinctrl*pinctrl;
+struct pinctrl_state*pins_def;
+struct pinctrl_state*pins_sleep;
};
Which pins do you need to dynamically remux? If it's not all
the pins, you should have three sets: default, active and idle.
This way the static pins in the default group don't need to be
constantly toggled.
Regards,
Tony
Tony
I am using this for all the pins, in probe all the cpsw pins will
be configured
and i have used the same in suspend/resume callback for power saving.
Tony
Do you have any comments on this, or is it ok with two pinctrl_state nodes?
If you always need to remux all the pins, then yes that's fine with me.
Regards,
Tony
David
As Tony accepted the implementation, I will resend the patch series as one
of the patch (pasted below) in this series is already merged in net-next.
f6655d6 Mugunthan V N ARM: dts: AM33XX: Add CPSW phy_id device tree
data to am335x-evmsk Mon Jun 3 20:10:09 2013 +
Regards
Mugunthan V N
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Re: [PATCH 3/4] ARM: dts: omap5-uevm: Add LED support for uEVM blue LED
Sricharan
Thanks for sending this up in the series.
On 06/05/2013 01:46 AM, Sricharan R wrote:
From: Dan Murphy dmur...@ti.com
Add support for blue LED 1 off of GPIO 153.
Make the LED a heartbeat LED
Configure the MUX for GPIO output.
Cc: Dan Murphy dmur...@ti.com
Signed-off-by: Dan Murphy dmur...@ti.com
[Sricharan R r.sricha...@ti.com: Replaced constants with preprocessor
macros]
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/omap5-uevm.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/omap5-uevm.dts
b/arch/arm/boot/dts/omap5-uevm.dts
index cf862df..a2aed5b 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -66,6 +66,16 @@
device = hsusb2_phy;
clock-frequency = 1920; /* 19.2 MHz */
};
+
+ leds {
+ compatible = gpio-leds;
+ led@1 {
+ label = omap5:blue:usr1;
+ gpios = gpio5 25 GPIO_ACTIVE_HIGH; /* gpio5_153 D1
LED */
+ linux,default-trigger = heartbeat;
+ default-state = off;
+ };
+ };
};
omap5_pmx_core {
@@ -77,6 +87,7 @@
mcbsp1_pins
mcbsp2_pins
usbhost_pins
+ led_gpio_pins
;
twl6040_pins: pinmux_twl6040_pins {
@@ -175,6 +186,12 @@
0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 OUTPUT | MODE
6 ETH_NRESET */
;
};
+
+ led_gpio_pins: pinmux_led_gpio_pins {
+ pinctrl-single,pins =
+ 0x196 (PIN_OUTPUT | MUX_MODE6) /*
uart3_cts_rctx.gpio5_153 OUTPUT | MODE6 */
Same comment from Florian. We can drop the OUTPUT | MODE6 in the comment.
+ ;
+ };
};
omap5_pmx_wkup {
--
--
Dan Murphy
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[net-next PATCH v4 0/5] Adding pinctrl PM support for CPSW and MDIO
This patch series adds the following features * Adding pinctrl PM support for CPSW and MDIO for Power Optimization * Adding phy address to the CPSW node for EVMsk board Changes from initial version * Fixed the multiline function call indentation as per David Miller recommendation. Changes from v2 * Fixed the multi comment style as per net coding style * Fixed checkpatch error (more than 80 characters) Changes from v3 * Removed below patch as it has already merged to net-next ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk * Rebased to net-next as there was a merge conflict in DT files Hebbar Gururaja (1): net: cpsw: enhance pinctrl support Mugunthan V N (4): net: davinci_mdio: enhance pinctrl support ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM arch/arm/boot/dts/am335x-bone.dts | 38 arch/arm/boot/dts/am335x-evm.dts | 36 +++ arch/arm/boot/dts/am335x-evmsk.dts | 50 drivers/net/ethernet/ti/cpsw.c | 48 ++ drivers/net/ethernet/ti/davinci_mdio.c | 45 5 files changed, 217 insertions(+) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[net-next PATCH v4 1/5] net: cpsw: enhance pinctrl support
From: Hebbar Gururaja gururaja.heb...@ti.com
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- default on boot, resume
- sleep on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
drivers/net/ethernet/ti/cpsw.c | 48
1 file changed, 48 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index a45f64e..0599515 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
#include linux/if_vlan.h
#include linux/platform_data/cpsw.h
+#include linux/pinctrl/consumer.h
#include cpsw_ale.h
#include cpts.h
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+ /* Two optional pin states - default sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_def;
+ struct pinctrl_state*pins_sleep;
};
#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
@@ -1691,6 +1697,35 @@ static int cpsw_probe(struct platform_device *pdev)
*/
pm_runtime_enable(pdev-dev);
+ priv-pinctrl = devm_pinctrl_get(pdev-dev);
+ if (!IS_ERR(priv-pinctrl)) {
+ priv-pins_def = pinctrl_lookup_state(priv-pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ /* enable pins to be muxed in and configured */
+ if (IS_ERR(priv-pins_def))
+ dev_warn(pdev-dev, could not get default
pinstate\n);
+ else
+ if (pinctrl_select_state(priv-pinctrl,
+priv-pins_def))
+ dev_err(pdev-dev,
+ could not set default pins\n);
+
+ priv-pins_sleep = pinctrl_lookup_state(priv-pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(priv-pins_sleep))
+ dev_warn(pdev-dev, could not get sleep pinstate\n);
+ } else {
+ /* Since we continue even when pinctrl node is not found,
+* Invalidate pins as not available. This is to make sure that
+* IS_ERR(pins_xxx) results in failure when used.
+*/
+ priv-pins_def = ERR_PTR(-ENODATA);
+ priv-pins_sleep = ERR_PTR(-ENODATA);
+
+ dev_warn(pdev-dev,
+pins are not configured from the driver\n);
+ }
+
if (cpsw_probe_dt(priv-data, pdev)) {
pr_err(cpsw: platform data missing\n);
ret = -ENODEV;
@@ -1974,11 +2009,17 @@ static int cpsw_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct net_device *ndev = platform_get_drvdata(pdev);
+ struct cpsw_priv*priv = netdev_priv(ndev);
if (netif_running(ndev))
cpsw_ndo_stop(ndev);
pm_runtime_put_sync(pdev-dev);
+ /* Optionally let pins go into sleep states */
+ if (!IS_ERR(priv-pins_sleep))
+ if (pinctrl_select_state(priv-pinctrl, priv-pins_sleep))
+ dev_err(dev, could not set pins to sleep state\n);
+
return 0;
}
@@ -1986,8 +2027,15 @@ static int cpsw_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct net_device *ndev = platform_get_drvdata(pdev);
+ struct cpsw_priv*priv = netdev_priv(ndev);
pm_runtime_get_sync(pdev-dev);
+
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(priv-pins_def))
+ if (pinctrl_select_state(priv-pinctrl, priv-pins_def))
+ dev_err(dev, could not set default pins\n);
+
if (netif_running(ndev))
cpsw_ndo_open(ndev);
return 0;
--
1.7.9.5
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[net-next PATCH v4 4/5] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
Add pinmux configurations for MII based CPSW ethernet to AM335x EVMsk.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am335x-evmsk.dts | 50
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 4297899..4827486 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -51,6 +51,46 @@
0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT
| MODE7 */
;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+
+ /* Slave 2 */
+ 0x40 0x2/* gpmc_a0.rgmii2_tctl, MODE2
| OUTPUT */
+ 0x44 0x22 /* gpmc_a1.rgmii2_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x48 0x2/* gpmc_a2.rgmii2_td3, MODE2 |
OUTPUT */
+ 0x4c 0x2/* gpmc_a3.rgmii2_td2, MODE2 |
OUTPUT */
+ 0x50 0x2/* gpmc_a4.rgmii2_td1, MODE2 |
OUTPUT */
+ 0x54 0x2/* gpmc_a5.rgmii2_td0, MODE2 |
OUTPUT */
+ 0x58 0x2/* gpmc_a6.rgmii2_tclk, MODE2
| OUTPUT */
+ 0x5c 0x22 /* gpmc_a7.rgmii2_rclk, MODE2
| INPUT_PULLDOWN */
+ 0x60 0x22 /* gpmc_a8.rgmii2_rd3, MODE2 |
INPUT_PULLDOWN */
+ 0x64 0x22 /* gpmc_a9.rgmii2_rd2, MODE2 |
INPUT_PULLDOWN */
+ 0x68 0x22 /* gpmc_a10.rgmii2_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x6c 0x22 /* gpmc_a11.rgmii2_rd0, MODE2
| INPUT_PULLDOWN */
+ ;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins =
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ ;
+ };
};
ocp {
@@ -249,6 +289,16 @@
};
};
+mac {
+ pinctrl-names = default;
+ pinctrl-0 = cpsw_default;
+};
+
+davinci_mdio {
+ pinctrl-names = default;
+ pinctrl-0 = davinci_mdio_default;
+};
+
cpsw_emac0 {
phy_id = davinci_mdio, 0;
phy-mode = rgmii-txid;
--
1.7.9.5
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[net-next PATCH v4 2/5] net: davinci_mdio: enhance pinctrl support
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- default on boot, resume
- sleep on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
drivers/net/ethernet/ti/davinci_mdio.c | 45
1 file changed, 45 insertions(+)
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c
b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec17..9e6aaeb 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -38,6 +38,7 @@
#include linux/davinci_emac.h
#include linux/of.h
#include linux/of_device.h
+#include linux/pinctrl/consumer.h
/*
* This timeout definition is a worst-case ultra defensive measure against
@@ -94,6 +95,11 @@ struct davinci_mdio_data {
struct mii_bus *bus;
boolsuspended;
unsigned long access_time; /* jiffies */
+
+ /* Two optional pin states - default sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_def;
+ struct pinctrl_state*pins_sleep;
};
static void __davinci_mdio_reset(struct davinci_mdio_data *data)
@@ -347,6 +353,35 @@ static int davinci_mdio_probe(struct platform_device *pdev)
data-bus-parent = dev;
data-bus-priv = data;
+ data-pinctrl = devm_pinctrl_get(pdev-dev);
+ if (!IS_ERR(data-pinctrl)) {
+ data-pins_def = pinctrl_lookup_state(data-pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ /* enable pins to be muxed in and configured */
+ if (IS_ERR(data-pins_def))
+ dev_warn(pdev-dev, could not get default
pinstate\n);
+ else
+ if (pinctrl_select_state(data-pinctrl,
+data-pins_def))
+ dev_err(pdev-dev,
+ could not set default pins\n);
+
+ data-pins_sleep = pinctrl_lookup_state(data-pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(data-pins_sleep))
+ dev_warn(pdev-dev, could not get sleep pinstate\n);
+ } else {
+ /* Since we continue even when pinctrl node is not found,
+* Invalidate pins as not available. This is to make sure that
+* IS_ERR(pins_xxx) results in failure when used.
+*/
+ data-pins_def = ERR_PTR(-ENODATA);
+ data-pins_sleep = ERR_PTR(-ENODATA);
+
+ dev_warn(pdev-dev,
+pins are not configured from the driver\n);
+ }
+
pm_runtime_enable(pdev-dev);
pm_runtime_get_sync(pdev-dev);
data-clk = clk_get(pdev-dev, fck);
@@ -454,6 +489,11 @@ static int davinci_mdio_suspend(struct device *dev)
data-suspended = true;
spin_unlock(data-lock);
+ /* Optionally let pins go into sleep states */
+ if (!IS_ERR(data-pins_sleep))
+ if (pinctrl_select_state(data-pinctrl, data-pins_sleep))
+ dev_err(dev, could not set pins to sleep state\n);
+
return 0;
}
@@ -465,6 +505,11 @@ static int davinci_mdio_resume(struct device *dev)
spin_lock(data-lock);
pm_runtime_get_sync(data-dev);
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(data-pins_def))
+ if (pinctrl_select_state(data-pinctrl, data-pins_def))
+ dev_err(dev, could not set default pins\n);
+
/* restart the scan state machine */
ctrl = __raw_readl(data-regs-control);
ctrl |= CONTROL_ENABLE;
--
1.7.9.5
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[net-next PATCH v4 3/5] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am335x-bone.dts | 38 +
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 4b5a8e0..008a13b 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,6 +36,33 @@
0x60 0x17 /* gpmc_a8.gpio1_24,
OUTPUT_PULLUP | MODE7 */
;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x110 0x20 /* mii1_rxerr.mii1_rxerr, MODE0
| INPUT */
+ 0x114 0x0 /* mii1_txen.mii1_txen, MODE0 |
OUTPUT */
+ 0x118 0x20 /* mii1_rxdv.mii1_rxdv, MODE0 |
INPUT_PULLDOWN */
+ 0x11c 0x0 /* mii1_txd3.mii1_txd3, MODE0 |
OUTPUT */
+ 0x120 0x0 /* mii1_txd2.mii1_txd2, MODE0 |
OUTPUT */
+ 0x124 0x0 /* mii1_txd1.mii1_txd1, MODE0 |
OUTPUT */
+ 0x128 0x0 /* mii1_txd0.mii1_txd0, MODE0 |
OUTPUT */
+ 0x12c 0x20 /* mii1_txclk.mii1_txclk, MODE0
| INPUT_PULLDOWN */
+ 0x130 0x20 /* mii1_rxclk.mii1_rxclk, MODE0
| INPUT_PULLDOWN */
+ 0x134 0x20 /* mii1_rxd3.mii1_rxd3, MODE0 |
INPUT_PULLDOWN */
+ 0x138 0x20 /* mii1_rxd2.mii1_rxd2, MODE0 |
INPUT_PULLDOWN */
+ 0x13c 0x20 /* mii1_rxd1.mii1_rxd1, MODE0 |
INPUT_PULLDOWN */
+ 0x140 0x20 /* mii1_rxd0.mii1_rxd0, MODE0 |
INPUT_PULLDOWN */
+ ;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins =
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ ;
+ };
};
ocp {
@@ -138,3 +165,14 @@
phy_id = davinci_mdio, 1;
phy-mode = mii;
};
+
+mac {
+ pinctrl-names = default;
+ pinctrl-0 = cpsw_default;
+
+};
+
+davinci_mdio {
+ pinctrl-names = default;
+ pinctrl-0 = davinci_mdio_default;
+};
--
1.7.9.5
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[net-next PATCH v4 5/5] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am335x-evm.dts | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 814ee03..5db4b05 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,32 @@
0x154 0x27 /* spi0_d0.gpio0_3, INPUT |
MODE7 */
;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+ ;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins =
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ ;
+ };
};
ocp {
@@ -237,6 +263,16 @@
};
};
+mac {
+ pinctrl-names = default;
+ pinctrl-0 = cpsw_default;
+};
+
+davinci_mdio {
+ pinctrl-names = default;
+ pinctrl-0 = davinci_mdio_default;
+};
+
cpsw_emac0 {
phy_id = davinci_mdio, 0;
phy-mode = rgmii-txid;
--
1.7.9.5
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[PATCH] OMAPDSS: Remove kfree for memory allocated with devm_kzalloc
It's not necessary to free memory allocated with devm_kzalloc in a remove function and using kfree leads to a double free. Signed-off-by: Emil Goode emilgo...@gmail.com --- drivers/video/omap2/displays/panel-picodlp.c |2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/video/omap2/displays/panel-picodlp.c b/drivers/video/omap2/displays/panel-picodlp.c index 62f2db0..859e111 100644 --- a/drivers/video/omap2/displays/panel-picodlp.c +++ b/drivers/video/omap2/displays/panel-picodlp.c @@ -469,8 +469,6 @@ static void picodlp_panel_remove(struct omap_dss_device *dssdev) i2c_unregister_device(picod-picodlp_i2c_client); dev_set_drvdata(dssdev-dev, NULL); dev_dbg(dssdev-dev, removing picodlp panel\n); - - kfree(picod); } static int picodlp_panel_enable(struct omap_dss_device *dssdev) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] RTC: rtc-twl: Fix rtc_reg_map initialization
Peter Ujfalusi peter.ujfal...@ti.com writes:
Initialize the rtc_reg_map in platform_driver's probe function instead at
module_init time. This way we can make sure that the twl-core has been already
probed and initialized (twl_priv-twl_id is valid) since the platform device
for the RTC driver will be created by the twl-core after it finished it's
init.
Reported-by: Christoph Fritz chf.fr...@googlemail.com
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
Tested-by: Kevin Hilman khil...@linaro.org
Confirmed this fixes some init problems when using DT boot on OMAP3.
Peter, you might want to resend (with acks collected) and be sure that
it's sent to Andrew Morton who is maintaining drivers/rtc currently.
Kevin
---
Hi,
As Tomi commented on the first version:
www.spinics.net/lists/linux-omap/msg90064.html
www.spinics.net/lists/linux-omap/msg90066.html
I have separated the actual fix from the module_platform_driver() conversion.
Regards,
Peter
drivers/rtc/rtc-twl.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
index 8bc6c80..c385e9b 100644
--- a/drivers/rtc/rtc-twl.c
+++ b/drivers/rtc/rtc-twl.c
@@ -469,6 +469,12 @@ static int twl_rtc_probe(struct platform_device *pdev)
if (irq = 0)
goto out1;
+ /* Initialize the register map */
+ if (twl_class_is_4030())
+ rtc_reg_map = (u8 *)twl4030_rtc_reg_map;
+ else
+ rtc_reg_map = (u8 *)twl6030_rtc_reg_map;
+
ret = twl_rtc_read_u8(rd_reg, REG_RTC_STATUS_REG);
if (ret 0)
goto out1;
@@ -614,11 +620,6 @@ static struct platform_driver twl4030rtc_driver = {
static int __init twl_rtc_init(void)
{
- if (twl_class_is_4030())
- rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
- else
- rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
-
return platform_driver_register(twl4030rtc_driver);
}
module_init(twl_rtc_init);
--
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Re: [PATCH v2 2/2] RTC: rtc-twl: Cleanup with module_platform_driver() conversion
On Tue, Apr 16, 2013 at 1:30 AM, Peter Ujfalusi peter.ujfal...@ti.com wrote: Use module_platform_driver() to register the platform driver. Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com Acked-by: Kevin Hilman khil...@linaro.org -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/1] ARM : omap3 : fix wrong container_of in clock36xx.c
Hi On Thu, 30 May 2013, Jean-Philippe Francois wrote: omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the clock to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned clock have parent defined as clk_divider. Instead of using container_of to eventually get to the register and directly mess with the divider, change freq via clk_set_rate, and let the clock framework toggle the divider value. Tested with 3.9 on dm3730. Signed-off-by: Jean-Philippe Fran??ois jp.franc...@cynove.com Tested this patch before applying, and noticed that it causes the retention dynamic idle power management test to fail here on the 3730beaglexm: http://www.pwsan.com/omap/testlogs/fixes_b_v3.10-rc/20130605113443/pm/3730beaglexm/3730beaglexm_log.txt Not sure at this point if this is caused by the patch, or if the patch is just unmasking another bug. Jean, Mike, Rajendra, care to take a look at this? - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [net-next PATCH v4 1/5] net: cpsw: enhance pinctrl support
On Wed, Jun 05, 2013 at 10:38:15PM +0530, Mugunthan V N wrote: From: Hebbar Gururaja gururaja.heb...@ti.com Amend cpsw controller to optionally take a pin control handle and set the state of the pins to: - default on boot, resume - sleep on suspend() Linus Walleij posted some patches which factor the state setting code out into generic functions earlier on today - it probably makes sense to pick those up rather than open coding signature.asc Description: Digital signature
Re: [BISECTED] 3.10-rc1 OMAP1 GPIO IRQ regression
On Mon, 20 May 2013 10:46:21 -0700, Tony Lindgren t...@atomide.com wrote:
* Tony Lindgren t...@atomide.com [130516 14:50]:
* Aaro Koskinen aaro.koski...@iki.fi [130516 14:05]:
On Thu, May 16, 2013 at 11:09:34AM -0700, Tony Lindgren wrote:
* Aaro Koskinen aaro.koski...@iki.fi [130513 13:58]:
I tested 3.10-rc1 on OMAP1 / Nokia 770, and Retu MFD probe is broken:
[2.264221] retu-mfd 2-0001: Retu v3.2 found
[2.281951] retu-mfd 2-0001: Failed to allocate IRQs: -12
[2.300140] retu-mfd: probe of 2-0001 failed with error -12
The error is coming from regmap code. According to git bisect, it is
caused by:
commit ede4d7a5b9835510fd1f724367f68d2fa4128453
Author: Jon Hunter jon-hun...@ti.com
Date: Fri Mar 1 11:22:47 2013 -0600
gpio/omap: convert gpio irq domain to linear mapping
The commit does not anymore revert cleanly, and I haven't yet tried
crafting a manual revert, so any fix proposals/ideas are welcome...
Hmm this might be a bit trickier to fix. Obviously the real solution
is to convert omap1 to SPARSE_IRQ like we did for omap2+.
For the -rc cycle, it might be possible to fix this by adding a
different irq_to_gpio() and gpio_to_irq() functions for omap1.
The commit reverts cleanly if we also revert
3513cdeccc647d41c4a9ff923af17deaaac04a66 (gpio/omap: optimise interrupt
service routine), which seems to be just some minor optimization. The
result is below, and with it 770 works again.
Hmm in this case it seems that we should just fix it rather than go back
to the old code, so let's take a look at that first.
Does the following fix it for you or do we need to fix something else
there too?
Hi Tony,
Do you want me to apply this fix? It sounds like it solves the symptoms,
but I'd like to know more about what the root cause is.
Send me your s-o-b line and I'll apply the patch
g.
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1094,6 +1094,7 @@ static int omap_gpio_probe(struct platform_device *pdev)
const struct omap_gpio_platform_data *pdata;
struct resource *res;
struct gpio_bank *bank;
+ int irq_base;
match = of_match_device(of_match_ptr(omap_gpio_match), dev);
@@ -1135,11 +1136,23 @@ static int omap_gpio_probe(struct platform_device
*pdev)
pdata-get_context_loss_count;
}
-
- bank-domain = irq_domain_add_linear(node, bank-width,
- irq_domain_simple_ops, NULL);
- if (!bank-domain)
+ /*
+ * REVISIT: Once we have omap1 supporting SPARSE_IRQ, we can drop
+ * irq_alloc_descs() and irq_domain_add_legacy() and just do:
+ *
+ * bank-domain = irq_domain_add_linear(node, bank-width,
+ * irq_domain_simple_ops, NULL);
+ * if (!bank-domain)
+ * return -ENODEV;
+ */
+ irq_base = irq_alloc_descs(-1, 0, bank-width, 0);
+ if (irq_base 0) {
+ dev_err(dev, Couldn't allocate IRQ numbers\n);
return -ENODEV;
+ }
+
+ bank-domain = irq_domain_add_legacy(node, bank-width, irq_base,
+ 0, irq_domain_simple_ops, NULL);
if (bank-regs-set_dataout bank-regs-clr_dataout)
bank-set_dataout = _set_gpio_dataout_reg;
--
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.
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Re: [PATCH 1/1] of/irq: store IRQ trigger/level in struct resource flags
On Tue, 09 Apr 2013 00:44:05 +0200, Javier Martinez Canillas javier.marti...@collabora.co.uk wrote: On 04/09/2013 12:05 AM, Rob Herring wrote: On 04/05/2013 02:48 AM, Javier Martinez Canillas wrote: This means that drivers that need the IRQ type/level flags defined in the DT won't be able to get it. But the interrupt controllers that need the information should be able to get to it via irqd_get_trigger_type. What problem exactly are you trying to fix? What driver would use this? Yes but this is not about the interrupt controller wanting this information but a device driver that is using the IORESOURCE_IRQ struct resource that has the information about the virtual IRQ associated with a GPIO-IRQ. The driver doesn't know neither care if its IRQ line is connected to a line of an real IRQ controller or to a GPIO controller that allows a GPIO line to be used as an IRQ. My understanding of the IORESOURCE_IRQ_xxx (and DMA) bits are they are ISA specific and therefore should not be used on non-ISA buses. Many TI OMAP2+ SoC based boards have an SMSC LAN911x/912x controller (drivers/net/ethernet/smsc/smsc911x.c) that is connected to the OMAP processor through its General-Purpose Memory Controller (GPMC) and this LAN driver obtain its IRQ and I/O address space from a struct resource IORESOURCE_IRQ and IORESOURCE_MEM respectively, that is filled by the DeviceTree core. It does this: irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); irq_flags = irq_res-flags IRQF_TRIGGER_MASK; Since of_irq_to_resource() doesn't fill the trigger/level flags on the IORESOURCE_IRQ struct resource, irq_flags will always be 0 regarding the value specified on the second cell of the interrupts DT property. A previous discussion about this can be found here [1]. I can't remember if there was ever a reason for not returning the IRQ flags, but I don't have any major objection to doing so if drivers find them useful. The one concern I do have however is if it will cause any problems with drivers that expect flags == IORESOURCE_IRQ without any additional flags. Any users doing that are buggy anyway, but I do want to be careful about breakage. I'll go over your patch and reply with comments. g. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] of/irq: store IRQ trigger/level in struct resource flags
On Fri, 5 Apr 2013 09:48:08 +0200, Javier Martinez Canillas javier.marti...@collabora.co.uk wrote: [...] irq_of_parse_and_map() calls to irq_create_of_mapping() which calls to the correct xlate function handler according to #interrupt-cells (irq_domain_xlate_onecell or irq_domain_xlate_twocell) and to irq_set_irq_type() to set the IRQ type. But the type is never returned so it can't be saved on the IRQ struct resource flags member. This means that drivers that need the IRQ type/level flags defined in the DT won't be able to get it. Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk [...] diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h index 535cecf..98aec57 100644 --- a/include/linux/of_irq.h +++ b/include/linux/of_irq.h @@ -66,6 +66,10 @@ extern int of_irq_map_one(struct device_node *device, int index, extern unsigned int irq_create_of_mapping(struct device_node *controller, const u32 *intspec, unsigned int intsize); +extern unsigned int irq_create_of_mapping_type(struct device_node *controller, +const u32 *intspec, +unsigned int intsize, +unsigned int *otype); I count 11 users of irq_create_of_mapping(). That's a managable number to update. Instead of creating a new function, please modify the existing one and split it off into a separate patch. Otherwise the patch looks fine to me. g. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4
здравствуйте, On Wed, 5 Jun 2013, Aida Mynzhasova wrote: Not so long ago I tried to boot Linux 3.10-rc4 kernel on DM816x EVM board. Unfortunately, my attempts were failed by reason of poor support of DM81xx-based devices in new kernels. Yeah, TI pretty much gave up on trying to get support for that chip upstream a few years ago. Same for DM814x. So, I suggest you this patch series, which fixes that kernel crush and adds new functions/structures, required for early initialization on DM816x (power and clock domains, hwmods). After applying these patches the kernel is able to successfully continue booting till clock initialization (will be added later). OK, it will be great to get my DM8168EVM booting on mainline. But there are a few preliminary issues with the patches: 1. All new chip and board support needs to be DT-only. So, no new board files. Also, all the hwmod data shouldn't have IRQ, DMA, etc. data - that should come from DT. See for example the recently posted patch [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up 2. Looks like patch 2 is missing from the list. If it's too big for the list, please break it down into smaller patches. 3. Did you write this code and data, hwmods, etc., or did it come from a TI kernel? Please note this clearly in the patch descriptions. - Paul
Re: [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
On Wed, 29 May 2013, Santosh Shilimkar wrote: From: Vaibhav Hiremath hvaib...@ti.com AM33XX only supports DT boot mode and with addition of extracting module resources like, irq, dma and address space from DT block, so now we can remove duplicate information from hwmod data file. OK, guess I'll take your word for it that it all works. The BeagleBone-white with appended DTB hasn't booted here since v3.7. And the BeagleBone-black with discrete DTB doesn't boot at all with current mainline, only with the TI vendor kernel DTB... Acked-by: Paul Walmsley p...@pwsan.com - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4
Hi, also, On Wed, 5 Jun 2013, Aida Mynzhasova wrote: Aida Mynzhasova (5): ARM: OMAP: AM33xx: multiple renames for early initialization If this patch is what's responsible for all the file renaming, please drop it. Looks from the change summary that it's just useless churn (although I haven't seen the patch here since it never made it to the lists) - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
