Re: [PATCH v4 0/2] ARM: dts: Beaglebone MMC fixes
On Tue, Sep 17, 2013 at 03:30:23PM +0200, Benoit Cousson wrote: I've just applied it on top of Joel's one. Benoit, Can you tell me where to find your git tree so that I can follow these patches' progress? Thanks, Richard -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/2] ARM: dts: Beaglebone MMC fixes
On 10/25/2013 04:04 AM, Richard Cochran wrote: On Tue, Sep 17, 2013 at 03:30:23PM +0200, Benoit Cousson wrote: I've just applied it on top of Joel's one. Benoit, Can you tell me where to find your git tree so that I can follow these patches' progress? https://git.kernel.org/cgit/linux/kernel/git/bcousson/linux-omap-dt.git/log/?h=for_3.13/dts -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: OMAP2+: smsc911x: fix return value check in gpmc_smsc911x_init()
From: Wei Yongjun yongjun_...@trendmicro.com.cn
In case of error, the function platform_device_register_resndata()
returns ERR_PTR() and never returns NULL. The NULL test in the return
value check should be replaced with IS_ERR().
Signed-off-by: Wei Yongjun yongjun_...@trendmicro.com.cn
---
arch/arm/mach-omap2/gpmc-smsc911x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c
b/arch/arm/mach-omap2/gpmc-smsc911x.c
index ef99011..2757504 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -83,7 +83,7 @@ void __init gpmc_smsc911x_init(struct
omap_smsc911x_platform_data *gpmc_cfg)
pdev = platform_device_register_resndata(NULL, smsc911x, gpmc_cfg-id,
gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources),
gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config));
- if (!pdev) {
+ if (IS_ERR(pdev)) {
pr_err(Unable to register platform device\n);
gpio_free(gpmc_cfg-gpio_reset);
goto free2;
--
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[PATCH 3/3] ARM: OMAP2: omap4-sdp: remove unneeded gpios from dss-common
DISPLAY_SEL_GPIO and DLP_POWER_ON_GPIO are now handled in the .dts file,
so we can remove them from dss-common.c.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/mach-omap2/dss-common.c | 21 -
1 file changed, 21 deletions(-)
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
index bf89eff..cc70cf9 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -113,9 +113,6 @@ void __init omap4_panda_display_init_of(void)
/* OMAP4 Blaze display data */
-#define DISPLAY_SEL_GPIO 59 /* LCD2/PicoDLP switch */
-#define DLP_POWER_ON_GPIO 40
-
static struct panel_dsicm_platform_data dsi1_panel = {
.name = lcd,
.source = dsi.0,
@@ -185,26 +182,8 @@ static struct omap_dss_board_info sdp4430_dss_data = {
.default_display_name = lcd,
};
-/*
- * we select LCD2 by default (instead of Pico DLP) by setting DISPLAY_SEL_GPIO.
- * Setting DLP_POWER_ON gpio enables the VDLP_2V5 VDLP_1V8 and VDLP_1V0 rails
- * used by picodlp on the 4430sdp platform. Keep this gpio disabled as LCD2 is
- * selected by default
- */
void __init omap_4430sdp_display_init_of(void)
{
- int r;
-
- r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
- display_sel);
- if (r)
- pr_err(%s: Could not get display_sel GPIO\n, __func__);
-
- r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
- DLP POWER ON);
- if (r)
- pr_err(%s: Could not get DLP POWER ON GPIO\n, __func__);
-
omap_display_init(sdp4430_dss_data);
platform_device_register(sdp4430_lcd_device);
--
1.8.1.2
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[PATCH 1/3] ARM: dts: omap4-panda: add DPI pinmuxing
New u-boot versions no longer set the pinmuxing for Panda's DPI output,
and the muxing has to be done in the .dts file.
Add pinmuxing for DPI and TFP410. Without these, the DVI output on Panda
does not work with recent u-boot.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/boot/dts/omap4-panda-common.dtsi | 43 +++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index faa95b5..fcb8856 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -129,6 +129,8 @@
twl6040_pins
mcpdm_pins
mcbsp1_pins
+ dss_dpi_pins
+ tfp410_pins
dss_hdmi_pins
tpd12s015_pins
hsusbb1_pins
@@ -166,6 +168,47 @@
;
};
+ dss_dpi_pins: pinmux_dss_dpi_pins {
+ pinctrl-single,pins =
+ 0x122 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */
+ 0x124 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */
+ 0x126 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */
+ 0x128 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */
+ 0x12a (PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */
+ 0x12c (PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */
+ 0x12e (PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */
+ 0x130 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */
+ 0x132 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */
+ 0x134 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */
+ 0x136 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */
+
+ 0x174 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */
+ 0x176 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */
+ 0x178 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */
+ 0x17a (PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */
+ 0x17c (PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */
+ 0x17e (PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */
+ 0x180 (PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */
+ 0x182 (PIN_OUTPUT | MUX_MODE5) /* dispc2_de */
+ 0x184 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */
+ 0x186 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */
+ 0x188 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */
+ 0x18a (PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */
+ 0x18c (PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */
+ 0x18e (PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */
+
+ 0x190 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */
+ 0x192 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */
+ 0x194 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */
+ ;
+ };
+
+ tfp410_pins: pinmux_tfp410_pins {
+ pinctrl-single,pins =
+ 0x144 (PIN_OUTPUT | MUX_MODE3) /* gpio_0 */
+ ;
+ };
+
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins =
0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /*
hdmi_cec.hdmi_cec */
--
1.8.1.2
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[PATCH 2/3] ARM: dts: omap4-sdp: add LCD pinmuxing
Add pinmuxing for the LCD panels.
Both panels have a reset GPIO, but the second one has some extra
complexity: some boards have a PicoDLP projector, which shares resources
with the LCD2. We don't currently support switching between the PicoDL
and the LCD2, so we use pin pull-ups and pull-downs to select the LCD2.
GPIO40 is pulled down, which disables the PicoDLP power. GPIO59 is
pulled up, which selects the LCD2.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/boot/dts/omap4-sdp.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 7951b4e..ed14a7a 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -166,6 +166,8 @@
mcbsp2_pins
dss_hdmi_pins
tpd12s015_pins
+ lcd1_pins
+ lcd2_pins
;
uart2_pins: pinmux_uart2_pins {
@@ -268,6 +270,25 @@
;
};
+ lcd1_pins: pinmux_lcd1_pins {
+ pinctrl-single,pins =
+ 0x52 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpio_102 */
+ ;
+ };
+
+ /*
+* GPIO 59 is used to switch between LCD2 and PicoDLP. We don't support
+* the switching, so set the pin to PULLUP which enables the LCD2.
+* GPIO 40 enables power to PicoDLP. Use PULLDOWN to disable power.
+*/
+ lcd2_pins: pinmux_lcd2_pins {
+ pinctrl-single,pins =
+ 0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpio_40 */
+ 0x46 (PIN_OUTPUT_PULLUP | MUX_MODE3)/* gpio_59 */
+ 0x56 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpio_104 */
+ ;
+ };
+
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins =
0xe2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
--
1.8.1.2
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[PATCH v2 2/5] mtd: nand: omap2: Fix device detection path
From: Pekon Gupta pe...@ti.com
Because the device bus can be 8-bit or 16-bit width, yet ONFI detection
cannot work in 16-bit mode, we need to set the NAND_BUSWIDTH_AUTO option
which allows proper initialization configuration.
Once the bus width is detected, nand_scan_ident() updates the nand_chip struct
'option' field to use the appropriate read/write functions and configure
the ECC engine.
Signed-off-by: Pekon Gupta pe...@ti.com
[rebased and clean-up a bit pekon's original work]
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
drivers/mtd/nand/omap2.c | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 4ecf0e5..e01a936 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1855,8 +1855,7 @@ static int omap_nand_probe(struct platform_device *pdev)
info-mtd.name = dev_name(pdev-dev);
info-mtd.owner = THIS_MODULE;
- info-nand.options = pdata-devsize;
- info-nand.options |= NAND_SKIP_BBTSCAN;
+ info-nand.options |= NAND_SKIP_BBTSCAN | NAND_BUSWIDTH_AUTO;
#ifdef CONFIG_MTD_NAND_OMAP_BCH
info-of_node = pdata-of_node;
#endif
@@ -1903,6 +1902,10 @@ static int omap_nand_probe(struct platform_device *pdev)
info-nand.chip_delay = 50;
}
+ err = nand_scan_ident(info-mtd, 1, NULL);
+ if (err 0)
+ goto out_release_mem_region;
+
switch (pdata-xfer_type) {
case NAND_OMAP_PREFETCH_POLLED:
info-nand.read_buf = omap_read_buf_pref;
@@ -2013,17 +2016,6 @@ static int omap_nand_probe(struct platform_device *pdev)
}
}
- /* DIP switches on some boards change between 8 and 16 bit
-* bus widths for flash. Try the other width if the first try fails.
-*/
- if (nand_scan_ident(info-mtd, 1, NULL)) {
- info-nand.options ^= NAND_BUSWIDTH_16;
- if (nand_scan_ident(info-mtd, 1, NULL)) {
- err = -ENXIO;
- goto out_release_mem_region;
- }
- }
-
/* rom code layout */
if (pdata-ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
--
1.8.1.5
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[PATCH v2 3/5] mtd: nand: omap2: Fix OMAP_BCH option dependency
This option does not need to depend in MTD_NAND, for it's enclosed under it. Also, it's wrong to make it depend in ARCH_OMAP3 only since the controller is used in a wider range of SoCs. Instead, just leave the dependency on the OMAP2 driver option. Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com --- drivers/mtd/nand/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index d885298..8187466 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -95,7 +95,7 @@ config MTD_NAND_OMAP2 platforms. config MTD_NAND_OMAP_BCH - depends on MTD_NAND MTD_NAND_OMAP2 ARCH_OMAP3 + depends on MTD_NAND_OMAP2 tristate Enable support for hardware BCH error correction default n select BCH -- 1.8.1.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 4/5] mtd: nand: omap2: Use devm_kzalloc
This simplifies the error path and makes the code less error-prone. Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com --- drivers/mtd/nand/omap2.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index e01a936..d3155b2 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -1837,7 +1837,7 @@ static int omap_nand_probe(struct platform_device *pdev) return -ENODEV; } - info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL); + info = devm_kzalloc(pdev-dev, sizeof(*info), GFP_KERNEL); if (!info) return -ENOMEM; @@ -2067,8 +2067,6 @@ out_release_mem_region: free_irq(info-gpmc_irq_fifo, info); release_mem_region(info-phys_base, info-mem_size); out_free_info: - kfree(info); - return err; } @@ -2091,7 +2089,6 @@ static int omap_nand_remove(struct platform_device *pdev) nand_release(info-mtd); iounmap(info-nand.IO_ADDR_R); release_mem_region(info-phys_base, info-mem_size); - kfree(info); return 0; } -- 1.8.1.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/5] ARM: am335x-bone: Add support for 16-bit NAND cape
From: Pekon Gupta pe...@ti.com
Add GPMC timing configurations and NAND partitions for the Beaglebone
NAND cape. Further information and datasheets of this cape can be found at:
- http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
- http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module
Signed-off-by: Pekon Gupta pe...@ti.com
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
This patch is not really intended for inclusion. I'm just adding it
to the series for reference and in case anyone wants to test.
In particular, this patch includes two different GPMC configurations:
one at am335x-bone-common.dtsi, and another one at am335x-boneblack.dts,
overriding the first one. The former is Pekon's, while the latter is mine,
to support the flash device on my setup.
arch/arm/boot/dts/am335x-bone-common.dtsi | 28
arch/arm/boot/dts/am335x-bone.dts | 75 +++
arch/arm/boot/dts/am335x-boneblack.dts| 69
3 files changed, 172 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi
b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 2f66ded..73dcc58 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -107,6 +107,34 @@
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
;
};
+
+ nandflash_pins_s0: nandflash_pins_s0 {
+ pinctrl-single,pins =
+ 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad7.gpmc_ad7 */
+ 0x20 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad8.gpmc_ad8 */
+ 0x24 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad9.gpmc_ad9 */
+ 0x28 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad10.gpmc_ad10 */
+ 0x2c (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad11.gpmc_ad11 */
+ 0x30 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad12.gpmc_ad12 */
+ 0x34 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad13.gpmc_ad13 */
+ 0x38 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad14.gpmc_ad14 */
+ 0x3c (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad15.gpmc_ad15 */
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /*
gpmc_wpn.gpio0_30 */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_wen.gpmc_wen */
+ 0x9c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_be0n_cle.gpmc_be0n_cle */
+ ;
+ };
};
ocp {
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 7993c48..d9172c7 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -9,3 +9,78 @@
#include am33xx.dtsi
#include am335x-bone-common.dtsi
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nandflash_pins_s0;
+ ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
+ nand@0,0 {
+ reg = 0 0 0; /* CS0, offset 0 */
+ nand-bus-width = 16;
+ ti,nand-ecc-opt = bch8;
+ gpmc,device-width = 2;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 740;
+ gpmc,cs-wr-off-ns = 740;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 740;
+ gpmc,adv-wr-off-ns = 740;
+ gpmc,we-on-ns = 90;
+ gpmc,we-off-ns = 600;
+ gpmc,oe-on-ns = 150;
+ gpmc,oe-off-ns = 650;
+
[PATCH v2 0/5] Assorted OMAP2 NAND clean-ups
Hello everyone, As it was discussed recently in the mailing list, the omap2-nand driver currently has an issue preventing proper ONFI detection of 16-bit devices (other drivers may suffer from this same issue). In an attempt to address such issue, patch 2/5 mtd: nand: omap2: Fix device detection path uses NAND_BUSWIDTH_AUTO (actually discarding any DT property) and leaves the bus width detection the NAND core code. I've based the patch in previously sent work by Pekon Gupta, did some work and added my name on it. I hope it's fine to handle the authorship like this. Otherwise, feel free to tell. This has been tested in a Beaglebone black (AM335x) board with a 16-bit Micron NAND device, both ONFI and array-based detections work fine: [1.253200] omap-gpmc 5000.gpmc: GPMC revision 6.0 [1.260638] NAND device: Manufacturer ID: 0x2c, Chip ID: 0xcc (Micron MT29F4G16ABADAH4) [1.269110] NAND device: 512MiB, SLC, page size: 2048, OOB size: 64 [1.275721] Missing elm_id property, fall back to Software BCH [1.283546] enabling NAND BCH ecc with 8-bit correction [1.290219] 8 ofpart partitions found on MTD device omap2-nand.0 [1.296591] Creating 8 MTD partitions on omap2-nand.0: [1.302192] 0x-0x0002 : SPL1 [1.309884] 0x0002-0x0004 : SPL2 [1.316332] 0x0004-0x0006 : SPL3 [1.322599] 0x0006-0x0008 : SPL4 [1.328877] 0x0008-0x0026 : U-boot [1.336763] 0x0026-0x0028 : environment [1.343575] 0x0028-0x0078 : Kernel [1.354074] 0x0078-0x1000 : File-System Also, a quick run of nandtest ends successfully: $ nandtest /dev/mtd7 ECC corrections: 0 ECC failures : 0 Bad blocks : 2 BBT blocks : 0 Bad block at 0x Bad block at 0x0052 [...] Finished pass 1 successfully The first patch 1/5 is included just for reference of the DT GPMC configuration currently in use, together with required pinmuxing, in case anyone feels like testing. It's not intended to be merged, since it doesn't belong to the Beaglebone board itself, but instead it's an attached daughter board. The other patches are just minor cleanups I came across while looking at the code. As usual, the patchset applies on top of latest l2-mtd's master branch. Pekon, Brian: Do you think this solution might work for 8-bit and 16-bit devices? I've been going through the GPMC code again, and it looks like some cleaning is needed there two, but that's a different story! Feel free to comment or provide any feedback! Changes from v1: * As noticed by Belisko Marek, re-added the out_free_info label in PATCH 4/5 to prevent build failures. The result is the same and the label is removed in the last patch, together with the last users of it. Ezequiel Garcia (3): mtd: nand: omap2: Fix OMAP_BCH option dependency mtd: nand: omap2: Use devm_kzalloc mtd: nand: omap2: Use devm_ioremap_resource Pekon Gupta (2): ARM: am335x-bone: Add support for 16-bit NAND cape mtd: nand: omap2: Fix device detection path arch/arm/boot/dts/am335x-bone-common.dtsi | 28 arch/arm/boot/dts/am335x-bone.dts | 75 +++ arch/arm/boot/dts/am335x-boneblack.dts| 69 drivers/mtd/nand/Kconfig | 2 +- drivers/mtd/nand/omap2.c | 52 + 5 files changed, 185 insertions(+), 41 deletions(-) -- 1.8.1.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 5/5] mtd: nand: omap2: Use devm_ioremap_resource
This simplifies the code and makes it less error-prone. In fact,
this commit fixes a missing iounmap() in the cleanup error path.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
drivers/mtd/nand/omap2.c | 31 +++
1 file changed, 7 insertions(+), 24 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index d3155b2..2d896da 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1830,6 +1830,7 @@ static int omap_nand_probe(struct platform_device *pdev)
unsigned sig;
struct resource *res;
struct mtd_part_parser_data ppdata = {};
+ void __iomem*base;
pdata = dev_get_platdata(pdev-dev);
if (pdata == NULL) {
@@ -1861,29 +1862,15 @@ static int omap_nand_probe(struct platform_device *pdev)
#endif
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res == NULL) {
- err = -EINVAL;
- dev_err(pdev-dev, error getting memory resource\n);
- goto out_free_info;
- }
-
- info-phys_base = res-start;
- info-mem_size = resource_size(res);
-
- if (!request_mem_region(info-phys_base, info-mem_size,
- pdev-dev.driver-name)) {
- err = -EBUSY;
- goto out_free_info;
- }
-
- info-nand.IO_ADDR_R = ioremap(info-phys_base, info-mem_size);
- if (!info-nand.IO_ADDR_R) {
- err = -ENOMEM;
- goto out_release_mem_region;
+ base = devm_ioremap_resource(pdev-dev, res);
+ if (IS_ERR(base)) {
+ err = PTR_ERR(base);
+ return err;
}
info-nand.controller = info-controller;
+ info-nand.IO_ADDR_R = base;
info-nand.IO_ADDR_W = info-nand.IO_ADDR_R;
info-nand.cmd_ctrl = omap_hwcontrol;
@@ -1904,7 +1891,7 @@ static int omap_nand_probe(struct platform_device *pdev)
err = nand_scan_ident(info-mtd, 1, NULL);
if (err 0)
- goto out_release_mem_region;
+ return err;
switch (pdata-xfer_type) {
case NAND_OMAP_PREFETCH_POLLED:
@@ -2065,8 +2052,6 @@ out_release_mem_region:
free_irq(info-gpmc_irq_count, info);
if (info-gpmc_irq_fifo 0)
free_irq(info-gpmc_irq_fifo, info);
- release_mem_region(info-phys_base, info-mem_size);
-out_free_info:
return err;
}
@@ -2087,8 +2072,6 @@ static int omap_nand_remove(struct platform_device *pdev)
/* Release NAND device, its internal structures and partitions */
nand_release(info-mtd);
- iounmap(info-nand.IO_ADDR_R);
- release_mem_region(info-phys_base, info-mem_size);
return 0;
}
--
1.8.1.5
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Re: [PATCH 3/3] ARM: OMAP2: omap4-sdp: remove unneeded gpios from dss-common
On 10/25/2013 05:07 AM, Tomi Valkeinen wrote:
DISPLAY_SEL_GPIO and DLP_POWER_ON_GPIO are now handled in the .dts file,
so we can remove them from dss-common.c.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/mach-omap2/dss-common.c | 21 -
1 file changed, 21 deletions(-)
diff --git a/arch/arm/mach-omap2/dss-common.c
b/arch/arm/mach-omap2/dss-common.c
index bf89eff..cc70cf9 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -113,9 +113,6 @@ void __init omap4_panda_display_init_of(void)
/* OMAP4 Blaze display data */
-#define DISPLAY_SEL_GPIO 59 /* LCD2/PicoDLP switch */
-#define DLP_POWER_ON_GPIO40
-
static struct panel_dsicm_platform_data dsi1_panel = {
.name = lcd,
.source = dsi.0,
@@ -185,26 +182,8 @@ static struct omap_dss_board_info sdp4430_dss_data = {
.default_display_name = lcd,
};
-/*
- * we select LCD2 by default (instead of Pico DLP) by setting
DISPLAY_SEL_GPIO.
- * Setting DLP_POWER_ON gpio enables the VDLP_2V5 VDLP_1V8 and VDLP_1V0 rails
- * used by picodlp on the 4430sdp platform. Keep this gpio disabled as LCD2
is
- * selected by default
- */
void __init omap_4430sdp_display_init_of(void)
{
- int r;
-
- r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
- display_sel);
- if (r)
- pr_err(%s: Could not get display_sel GPIO\n, __func__);
-
- r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
- DLP POWER ON);
- if (r)
- pr_err(%s: Could not get DLP POWER ON GPIO\n, __func__);
-
omap_display_init(sdp4430_dss_data);
platform_device_register(sdp4430_lcd_device);
would you not be depending on the weak IO pull done using mux to drive
these GPIO pins since the GPIO is not requested and held?
Could we not use Documentation/devicetree/bindings/gpio/gpio.txt
binding to map to the right GPIO and drive it using the GPIO module?
--
Regards,
Nishanth Menon
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RE: [PATCH v2 4/5] mtd: nand: omap2: Use devm_kzalloc
Hi, This simplifies the error path and makes the code less error-prone. Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com --- drivers/mtd/nand/omap2.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index e01a936..d3155b2 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -1837,7 +1837,7 @@ static int omap_nand_probe(struct platform_device *pdev) return -ENODEV; } - info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL); + info = devm_kzalloc(pdev-dev, sizeof(*info), GFP_KERNEL); if (!info) return -ENOMEM; @@ -2067,8 +2067,6 @@ out_release_mem_region: free_irq(info-gpmc_irq_fifo, info); release_mem_region(info-phys_base, info-mem_size); out_free_info: - kfree(info); - return err; } @@ -2091,7 +2089,6 @@ static int omap_nand_remove(struct platform_device *pdev) nand_release(info-mtd); iounmap(info-nand.IO_ADDR_R); release_mem_region(info-phys_base, info-mem_size); - kfree(info); return 0; } -- 1.8.1.5 I think these changes are already done as part of following patch.. http://lists.infradead.org/pipermail/linux-mtd/2013-October/049418.html Did your rebase on my patch-set ? with regards, pekon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: OMAP2: omap4-sdp: remove unneeded gpios from dss-common
On 25/10/13 13:18, Nishanth Menon wrote:
void __init omap_4430sdp_display_init_of(void)
{
-int r;
-
-r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
-display_sel);
-if (r)
-pr_err(%s: Could not get display_sel GPIO\n, __func__);
-
-r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
-DLP POWER ON);
-if (r)
-pr_err(%s: Could not get DLP POWER ON GPIO\n, __func__);
-
omap_display_init(sdp4430_dss_data);
platform_device_register(sdp4430_lcd_device);
would you not be depending on the weak IO pull done using mux to drive
these GPIO pins since the GPIO is not requested and held?
Yes. Is that not enough?
Could we not use Documentation/devicetree/bindings/gpio/gpio.txt
binding to map to the right GPIO and drive it using the GPIO module?
Hmm, what do you mean?
I do mux the pins to gpios, but there's nothing in the kernel that would
use those gpios. That's why we had the hack above, but I'd love to get
rid of it.
Can I set the pins to GPIO mode, and set the GPIO to high/low in the .dts?
If things were perfect, we probably would have a driver for the switch
part. I have no idea what kind of driver that would be, though, so at
the moment we've just gone with the use-LCD2-by-default route.
Tomi
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Re: [PATCH 6/6] experimental: arm: dts: dra7xx: Add a DT node for VPE
Hi Laurent,
Sorry about the late response, I had scrapped the DT patch out of the
VPE series since there were dependencies on crossbar drivers and some
other baseport stuff. Comments below.
On Friday 09 August 2013 03:41 AM, Laurent Pinchart wrote:
Hi Archit,
Thank you for the patch.
On Friday 02 August 2013 19:33:43 Archit Taneja wrote:
Add a DT node for VPE in dra7.dtsi. This is experimental because we might
need to split the VPE address space a bit more, and also because the IRQ
line described is accessible the IRQ crossbar driver is added for DRA7XX.
Cc: Rajendra Nayak rna...@ti.com
Cc: Sricharan R r.sricha...@ti.com
Signed-off-by: Archit Taneja arc...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 11 +++
Documentation is missing :-) As this is an experimental patch you can probably
document the bindings later.
Yes, I will work on that.
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index ce9a0f0..3237972 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -484,6 +484,17 @@
dmas = sdma 70, sdma 71;
dma-names = tx0, rx0;
};
+
+ vpe {
+ compatible = ti,vpe;
+ ti,hwmods = vpe;
+ reg = 0x489d 0xd000, 0x489dd000 0x400;
+ reg-names = vpe, vpdma;
+ interrupts = 0 159 0x4;
+ #address-cells = 1;
+ #size-cells = 0;
Are #address-cells and #size-cells really needed ?
These aren't needed, vpe derives the address info from it's parent(ocp).
I didn't know that the child nodes inherit these params from the parent.
Archit
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Re: [PATCH v2 4/5] mtd: nand: omap2: Use devm_kzalloc
On Fri, Oct 25, 2013 at 10:25:02AM +, Gupta, Pekon wrote: Hi, This simplifies the error path and makes the code less error-prone. Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com --- drivers/mtd/nand/omap2.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index e01a936..d3155b2 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -1837,7 +1837,7 @@ static int omap_nand_probe(struct platform_device *pdev) return -ENODEV; } - info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL); + info = devm_kzalloc(pdev-dev, sizeof(*info), GFP_KERNEL); if (!info) return -ENOMEM; @@ -2067,8 +2067,6 @@ out_release_mem_region: free_irq(info-gpmc_irq_fifo, info); release_mem_region(info-phys_base, info-mem_size); out_free_info: - kfree(info); - return err; } @@ -2091,7 +2089,6 @@ static int omap_nand_remove(struct platform_device *pdev) nand_release(info-mtd); iounmap(info-nand.IO_ADDR_R); release_mem_region(info-phys_base, info-mem_size); - kfree(info); return 0; } -- 1.8.1.5 I think these changes are already done as part of following patch.. http://lists.infradead.org/pipermail/linux-mtd/2013-October/049418.html Did your rebase on my patch-set ? Hm.. well the problem with that patch is that it's in the middle of an unrelated series. As I already told you, I think you should have pushed that as a one-patch fix. Have you seen that suggestion? On the other side, you're fixing too many things in that single patch, for my taste. Maybe I'm not the smarter developer, but going through that patch is not easy to catch if there's no mistake done. Usually if it's possible to split a patch (maintaining consistency) it makes the reviewing process easier. If you'd rather send this devm_xxx change yourself that's fine by me, but *please* split the patch in two and write proper commit messages. Anyway: this is just a silly change, the important one is the other nand_scan_ident() fix. Could you help me review that? I'm interested in knowing how will that work with 8-bit and 16-bit devices. -- Ezequiel García, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: OMAP2: omap4-sdp: remove unneeded gpios from dss-common
On 10/25/2013 05:25 AM, Tomi Valkeinen wrote:
On 25/10/13 13:18, Nishanth Menon wrote:
void __init omap_4430sdp_display_init_of(void)
{
- int r;
-
- r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
- display_sel);
- if (r)
- pr_err(%s: Could not get display_sel GPIO\n, __func__);
-
- r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
- DLP POWER ON);
- if (r)
- pr_err(%s: Could not get DLP POWER ON GPIO\n, __func__);
-
omap_display_init(sdp4430_dss_data);
platform_device_register(sdp4430_lcd_device);
would you not be depending on the weak IO pull done using mux to drive
these GPIO pins since the GPIO is not requested and held?
Yes. Is that not enough?
It depend on what the signal draw is and io drive strength which
varies - original intent of weak pulls were to have a non-active
default state which are overriden by GPIOs as needed. Else we would
not be having strong pulls here in pads.
Typical padmux drive strength for OMAP4460 is around 100uA, min is
around 50uA. meanwhile as Documentation/gpio.txt generically states,
the buffers driving at 1.8v on OMAP4460 could be around 6mA or upto
8mA. Again, these depend on the specific pin in discussion and Data
manual explain is larger detail
Lower current is fine if the switch is ok with it and risk for
transients are reasonably safe. However, board designs generally
assume the stronger GPIO drive strength.
Could we not use Documentation/devicetree/bindings/gpio/gpio.txt
binding to map to the right GPIO and drive it using the GPIO module?
Hmm, what do you mean?
I do mux the pins to gpios, but there's nothing in the kernel that would
use those gpios. That's why we had the hack above, but I'd love to get
rid of it.
Can I set the pins to GPIO mode, and set the GPIO to high/low in the .dts?
If things were perfect, we probably would have a driver for the switch
part. I have no idea what kind of driver that would be, though, so at
the moment we've just gone with the use-LCD2-by-default route.
I meant you could, in theory provide the gpio numbers and pull
directions in dts and allow the init to drive them as needed.
Something like:
drivers/i2c/busses/i2c-gpio.c as a reference and use
of_get_named_gpio/of_get_gpio to pick themup..
--
Regards,
Nishanth Menon
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Re: [PATCH v11 00/10] [PATCH v10 00/10] mtd:nand:omap2: clean-up of supported ECC schemes
Pekon, On Thu, Oct 24, 2013 at 06:20:16PM +0530, Pekon Gupta wrote: *changes v10 - v11* - [PATCH v10 04/10] replaced with newer [PATCH v11 04/11] so that nand_scan_ident() is called only once. discussion thread with Brian Norris computersforpe...@gmail.com http://lists.infradead.org/pipermail/linux-mtd/2013-October/049335.html - No change in any other patch *changes v9 - v10* [PATCH 1/10], [PATCH 2/10] swapped [PATCH v9 1/9] and [PATCH v9 2/9] so that DT parsing updates (with backward compatibility) happen before the deprecation of DT values. This way DTB does not break functionally between the patches. [PATCH 3/10] no update [PATCH 4/10] dropped [PATCH v9 4/9] introducing NAND_BUSWIDTH_AUTO, instead using DT 'nand-bus-width' for device bus-width. Refer discussion thread http://lists.infradead.org/pipermail/linux-mtd/2013-October/049198.html [PATCH 5/10] no update [PATCH 6/10] no update [PATCH 7/10] separated out drivers/mtd/nand/Kconfig updates into separate [PATCH v10 10/10] cleanup: s/info-nand\./nand_chip- [PATCH 8/10] no update [PATCH 9/10] cleanup: s/out_release_mem_region/return_error [PATCH 10/10] new spawned from [PATCH v9 8/9] for Kconfig updates *changes v8 - v9* [PATCH 1/9] no update from [PATCH v8 1/6] [PATCH 2/9] only commit log updated from [PATCH v8 2/6] As per feedbacks from Brian Norris computersforpe...@gmail.com previous revision [PATCH v8 3/6] and [PATCH 4/6] are split into following sub-patches: - [PATCH 3/9] new replaces local reference with generic names (mtd, nand_chip) - [PATCH 4/9] new enables auto-detection of bus-width - [PATCH 5/9] new removes omap3_init_bch: populates ecc-scheme data - [PATCH 6/9] new removes omap3_init_bch_tail: populates ecc-layout - [PATCH 7/9] new replaces lib/bch.c with nand_bch.c wrapper [PATCH 8/9] no update same as [PATCH v8 5/6] [PATCH 9/9] removed devm_free_xx functions *Changes v7 - v8* [PATCH 1/6] no updates [PATCH 2/6] - updated DT parsing of ti,nand-ecc-opts so that its ham1 remains compatible to sw,hw,hw-romcode - updated DT parsing of ti,elm-id to retain compatibility to elm_id - using of_parse_phandle() to get ELM device pointer from DT [PATCH 3..6/6] commit log updates *Changes v6 - v7* [PATCH 1/6] NEW split from [PATCH v6 2/4] as per feedbacks from Brian Norris computersforpe...@gmail.com [PATCH 2/6] incorporated feedbacks from DT maintainers [PATCH 3/6] cleaned and incorporated feedbacks from Brian Norris computersforpe...@gmail.com [PATCH 4/6] rebasing changes and cleanup [PATCH 5/6] updated omap3430-sdp.dts [PATCH 6/6] NEW updated for devm_xx *Changes v5 - v6* [PATCH 1/4]: - updated DT binding for gpmc-nand based on 'Olof Johansson's feedbacks http://lists.infradead.org/pipermail/linux-mtd/2013-August/048394.html - detection of ELM device via ti,elm-id DT node, moved to gpmc.c driver [PATCH 2/4] - removed: support for following obselete ECC schemes OMAP_ECC_HAMMING_CODE_DEFAULT (S/W based 1-bit Hamming ECC) OMAP_ECC_HAMMING_CODE_HW_ROMCODE (H/W based 1-bit Hamming ECC scheme) - updated: using omap_oobinfo as chip-ecc.layout for all ecc-schemes - clean: error messages [PATCH 3/4] cleaned to include changes for OMAP_ECC_BCH8_CODE_HW only [PATCH 4/4] updated to include DT property changes *Changes v4 - v5* - Rebased to linux-next IMPORTANT: Need to revert commit fb1585b, [PATCH 2/4] part of previous version http://lists.infradead.org/pipermail/linux-mtd/2013-July/047441.html - Swapped PATCH-1 PATCH-2 to maintain bisectibility compilation dependency http://lists.infradead.org/pipermail/linux-mtd/2013-July/047461.html - PATCH-2: re-ordered call to is_elm_present() for later updates ELM driver - dropped changes in include/linux/platform_data/elm.h (not needed) - PATCH-3: re-ordered call to is_elm_present() for later updates ELM driver - Re-formated patch description (replaced tabs with white-spaces) *Changes v3 - v4* (Resent with CC: devicetree-disc...@lists.ozlabs.org) - [Patch 1/3] removed MTD_NAND_OMAP_BCH8 MTD_NAND_OMAP_BCH4 from nand/Kconfig ECC scheme selectable via nand DT (nand-ecc-opt). - [*] rebased for l2-mtd.git *Changes v2 - v3* (Resent with Author Name fixed) - PATCH-1: re-arranged code to remove redundancy, added NAND_BUSWIDTH_AUTO - PATCH-2: updated nand-ecc-opt DT mapping and Documentation - PATCH-3: code-cleaning + changes to match PATCH-1 - PATCH-4 DROPPED update DT attribute for ti,nand-ecc-opt - received feedback to keep DT mapping independent of linuxism - PATCH-4:NEW : ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt - independent patch for AM335x-evm.dts update based on PATCH-2 *Changes v1 - v2* added [PATCH 3/4] and [PATCH 4/4] After this patch series, omap2-nand driver will supports following ECC schemes:
RE: [PATCH v2 4/5] mtd: nand: omap2: Use devm_kzalloc
From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com] Hm.. well the problem with that patch is that it's in the middle of an unrelated series. As I already told you, I think you should have pushed that as a one-patch fix. Have you seen that suggestion? Yes, I know.. actually the original patch series, when it started somewhere April (or before) is very different from the version v11 now :-). This devm_ update was added in middle of v6-v7 version change (Most of the changes since first version of this patchset is captured in Cover-letter). On the other side, you're fixing too many things in that single patch, for my taste. Maybe I'm not the smarter developer, but going through that patch is not easy to catch if there's no mistake done. Usually if it's possible to split a patch (maintaining consistency) it makes the reviewing process easier. If you'd rather send this devm_xxx change yourself that's fine by me, Ahh nothing like that.. Brian had already reviewed these couple of times And it was only [Patch 04/10] which was last one remaining.. I just said it because this might show up in merge conflict .. or rejects.. but *please* split the patch in two and write proper commit messages. Anyway: this is just a silly change, the important one is the other nand_scan_ident() fix. Could you help me review that? I'm interested in knowing how will that work with 8-bit and 16-bit devices. -- Yes, I'm just preparing the scenario where BUSWIDTH_AUTO would fail.. unless you do GPMC driver changes also.. same issue was found by Matthieu CASTET (matthieu.cas...@parrot.com) (please see my other mail) with regards, pekon
Re: [PATCH 3/3] ARM: OMAP2: omap4-sdp: remove unneeded gpios from dss-common
On 25/10/13 13:54, Nishanth Menon wrote: would you not be depending on the weak IO pull done using mux to drive these GPIO pins since the GPIO is not requested and held? Yes. Is that not enough? It depend on what the signal draw is and io drive strength which varies - original intent of weak pulls were to have a non-active default state which are overriden by GPIOs as needed. Else we would not be having strong pulls here in pads. Typical padmux drive strength for OMAP4460 is around 100uA, min is around 50uA. meanwhile as Documentation/gpio.txt generically states, the buffers driving at 1.8v on OMAP4460 could be around 6mA or upto 8mA. Again, these depend on the specific pin in discussion and Data manual explain is larger detail Lower current is fine if the switch is ok with it and risk for transients are reasonably safe. However, board designs generally assume the stronger GPIO drive strength. Ok. Well, it definitely sounds safer to have a proper gpio pull there, then. Could we not use Documentation/devicetree/bindings/gpio/gpio.txt binding to map to the right GPIO and drive it using the GPIO module? Hmm, what do you mean? I do mux the pins to gpios, but there's nothing in the kernel that would use those gpios. That's why we had the hack above, but I'd love to get rid of it. Can I set the pins to GPIO mode, and set the GPIO to high/low in the .dts? If things were perfect, we probably would have a driver for the switch part. I have no idea what kind of driver that would be, though, so at the moment we've just gone with the use-LCD2-by-default route. I meant you could, in theory provide the gpio numbers and pull directions in dts and allow the init to drive them as needed. Something like: drivers/i2c/busses/i2c-gpio.c as a reference and use of_get_named_gpio/of_get_gpio to pick themup.. I'm still not quite following... What init are you referring to? The problem here is that the gpios don't really belong to anyone in the kernel, as we don't have a driver for the switch. Or did you mean that we'd still have the code in dss-common.c, but just get the gpio numbers from the .dts instead? That makes sense, although I'd want to get rid of that code altogether. Should we have support in the gpio-controller to define default values for gpios? I don't think we can rely on the boot loader to set things correctly. Tomi signature.asc Description: OpenPGP digital signature
Re: [PATCH 3/3] ARM: OMAP2: omap4-sdp: remove unneeded gpios from dss-common
On 10/25/2013 05:54 AM, Nishanth Menon wrote:
On 10/25/2013 05:25 AM, Tomi Valkeinen wrote:
On 25/10/13 13:18, Nishanth Menon wrote:
void __init omap_4430sdp_display_init_of(void)
{
- int r;
-
- r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
- display_sel);
- if (r)
- pr_err(%s: Could not get display_sel GPIO\n, __func__);
-
- r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
- DLP POWER ON);
- if (r)
- pr_err(%s: Could not get DLP POWER ON GPIO\n, __func__);
-
omap_display_init(sdp4430_dss_data);
platform_device_register(sdp4430_lcd_device);
would you not be depending on the weak IO pull done using mux to drive
these GPIO pins since the GPIO is not requested and held?
Yes. Is that not enough?
It depend on what the signal draw is and io drive strength which
varies - original intent of weak pulls were to have a non-active
default state which are overriden by GPIOs as needed. Else we would
not be having strong pulls here in pads.
Typical padmux drive strength for OMAP4460 is around 100uA, min is
around 50uA. meanwhile as Documentation/gpio.txt generically states,
the buffers driving at 1.8v on OMAP4460 could be around 6mA or upto
8mA. Again, these depend on the specific pin in discussion and Data
manual explain is larger detail
Lower current is fine if the switch is ok with it and risk for
transients are reasonably safe. However, board designs generally
assume the stronger GPIO drive strength.
one additional angle before I forget - this is something we do as part
of power optimization - to identify pins which are programmed for a
pull in non-functional scenario as it has direct impact on idle power
numbers.
For example patch #3 in this series
omap4_pmx_core {
pinctrl-0
...
lcd2_pins
..
}
lcd2_pins
lcd2_pins: pinmux_lcd2_pins {
+ pinctrl-single,pins =
+ 0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpio_40 */
+ 0x46 (PIN_OUTPUT_PULLUP | MUX_MODE3)/* gpio_59 */
+ 0x56 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpio_104 */
+ ;
3 pins are driven around 300uA at boot, even with display OFF - which
means wasted current that could have been optimized by hooking the pin
to the dts node corresponding to the device and used by the driver
appropriately.
Unfortunately, folks feel simplifying the driver is traditionally a
better alternative but with a 400 odd pins on a typical SoC of today,
these defaults add up and end user tends to suffer with bad overall
power numbers :(..
--
Regards,
Nishanth Menon
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RE: [PATCH v2 0/5] Assorted OMAP2 NAND clean-ups
Hi, -Original Message- From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com] [...] Pekon, Brian: Do you think this solution might work for 8-bit and 16-bit devices? I think NAND_BUSWIDTH_AUTO (without GPMC changes) would fail in following scenarios.. Case-1: configuring gpmc,device-width=1 from DT when using x16 device. As your NAND driver is using NAND_BUSWIDTH_AUTO, it should ignore this DT config, and based on ONFI params it should work as x16 Case-2: configuring gpmc,device-width=2 from DT when using x8 device. As your NAND driver is using NAND_BUSWIDTH_AUTO, it should ignore this DT config, and based on ONFI params it should work as x8 NAND device may get detected correctly, but try doing write and read to NAND, and I think, it would fail for Case-2 at-least.. Can you please check ? I've been going through the GPMC code again, and it looks like some cleaning is needed there two, but that's a different story! Actually having NAND_BUSWIDTH_AUTO would require change in GPMC driver also.. please refer my comments in.. http://lists.infradead.org/pipermail/linux-mtd/2013-October/049284.html reason of failure is given above... with regards, pekon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: OMAP2: omap4-sdp: remove unneeded gpios from dss-common
On 25/10/13 14:14, Nishanth Menon wrote:
one additional angle before I forget - this is something we do as part
of power optimization - to identify pins which are programmed for a
pull in non-functional scenario as it has direct impact on idle power
numbers.
For example patch #3 in this series
omap4_pmx_core {
pinctrl-0
...
lcd2_pins
..
}
lcd2_pins
lcd2_pins: pinmux_lcd2_pins {
+ pinctrl-single,pins =
+ 0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpio_40 */
+ 0x46 (PIN_OUTPUT_PULLUP | MUX_MODE3)/* gpio_59 */
+ 0x56 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpio_104 */
+ ;
3 pins are driven around 300uA at boot, even with display OFF - which
means wasted current that could have been optimized by hooking the pin
to the dts node corresponding to the device and used by the driver
appropriately.
Unfortunately, folks feel simplifying the driver is traditionally a
better alternative but with a 400 odd pins on a typical SoC of today,
these defaults add up and end user tends to suffer with bad overall
power numbers :(..
Good point. I guess that also makes my point of having default values
for GPIOs a bit silly. Driving the GPIO high by default would be ever
worse than the mux pull-up, I believe.
Tomi
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Re: [PATCH v2 4/5] mtd: nand: omap2: Use devm_kzalloc
On Fri, Oct 25, 2013 at 11:09:14AM +, Gupta, Pekon wrote: From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com] Hm.. well the problem with that patch is that it's in the middle of an unrelated series. As I already told you, I think you should have pushed that as a one-patch fix. Have you seen that suggestion? Yes, I know.. actually the original patch series, when it started somewhere April (or before) is very different from the version v11 now :-). This devm_ update was added in middle of v6-v7 version change (Most of the changes since first version of this patchset is captured in Cover-letter). Well, in order to *avoid* having a patchset flowing for 5 months and 11 revisions you coudl try to keep series small. You could have that single fix merged if you send it alone. Not sure why you insist in *not* doing that. On the other side, you're fixing too many things in that single patch, for my taste. Maybe I'm not the smarter developer, but going through that patch is not easy to catch if there's no mistake done. Usually if it's possible to split a patch (maintaining consistency) it makes the reviewing process easier. If you'd rather send this devm_xxx change yourself that's fine by me, Ahh nothing like that.. Brian had already reviewed these couple of times Ah, good. In that case you should add Reviewed-by if Brian already reviewed it. IMHO, the patch could be cleaner and the commit message could be better. And it was only [Patch 04/10] which was last one remaining.. Yes, and because you added *another* patch to the series you keep spinning patchset versions. I just said it because this might show up in merge conflict .. or rejects.. but *please* split the patch in two and write proper commit messages. Anyway: this is just a silly change, the important one is the other nand_scan_ident() fix. Could you help me review that? I'm interested in knowing how will that work with 8-bit and 16-bit devices. -- Yes, I'm just preparing the scenario where BUSWIDTH_AUTO would fail.. unless you do GPMC driver changes also.. same issue was found by Matthieu CASTET (matthieu.cas...@parrot.com) (please see my other mail) OK, let's try to focus in that patch alone, I'd like to move forward. -- Ezequiel García, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: OMAP2: omap4-sdp: remove unneeded gpios from dss-common
On 10/25/2013 06:13 AM, Tomi Valkeinen wrote: On 25/10/13 13:54, Nishanth Menon wrote: [..] Could we not use Documentation/devicetree/bindings/gpio/gpio.txt binding to map to the right GPIO and drive it using the GPIO module? Hmm, what do you mean? I do mux the pins to gpios, but there's nothing in the kernel that would use those gpios. That's why we had the hack above, but I'd love to get rid of it. Can I set the pins to GPIO mode, and set the GPIO to high/low in the .dts? If things were perfect, we probably would have a driver for the switch part. I have no idea what kind of driver that would be, though, so at the moment we've just gone with the use-LCD2-by-default route. I meant you could, in theory provide the gpio numbers and pull directions in dts and allow the init to drive them as needed. Something like: drivers/i2c/busses/i2c-gpio.c as a reference and use of_get_named_gpio/of_get_gpio to pick themup.. I'm still not quite following... What init are you referring to? The problem here is that the gpios don't really belong to anyone in the kernel, as we don't have a driver for the switch. Or did you mean that we'd still have the code in dss-common.c, but just get the gpio numbers from the .dts instead? That makes sense, although I'd want to get rid of that code altogether. Should we have support in the gpio-controller to define default values for gpios? I don't think we can rely on the boot loader to set things correctly. I am unfortunately, not in a position to know how you plan to architect dss_common or the various panels associated with it. if you model these as panels and a generic driver which controls the panel could request and control pins and gpios as needed I suppose. gpio controller cannot drive default pull direction, that is the job of the driver using the gpio. Simplest example that I can think of to use to point as reference is [1] [1] http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/leds/leds-gpio.c#n173 -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 3/5] mtd: nand: omap2: Fix OMAP_BCH option dependency
From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com] Subject: [PATCH v2 3/5] mtd: nand: omap2: Fix OMAP_BCH option dependency This option does not need to depend in MTD_NAND, for it's enclosed under it. Also, it's wrong to make it depend in ARCH_OMAP3 only since the controller is used in a wider range of SoCs. Instead, just leave the dependency on the OMAP2 driver option. Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com --- drivers/mtd/nand/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index d885298..8187466 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -95,7 +95,7 @@ config MTD_NAND_OMAP2 platforms. config MTD_NAND_OMAP_BCH - depends on MTD_NAND MTD_NAND_OMAP2 ARCH_OMAP3 + depends on MTD_NAND_OMAP2 tristate Enable support for hardware BCH error correction default n select BCH -- 1.8.1.5 Acked-by: Pekon Gupta pe...@ti.com Reported-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com with regards, pekon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: OMAP2: omap4-sdp: remove unneeded gpios from dss-common
On 25/10/13 14:21, Nishanth Menon wrote: The problem here is that the gpios don't really belong to anyone in the kernel, as we don't have a driver for the switch. Or did you mean that we'd still have the code in dss-common.c, but just get the gpio numbers from the .dts instead? That makes sense, although I'd want to get rid of that code altogether. Should we have support in the gpio-controller to define default values for gpios? I don't think we can rely on the boot loader to set things correctly. I am unfortunately, not in a position to know how you plan to architect dss_common or the various panels associated with it. if you The dss-common.c is just a hack, needed during the transition to DT. It's supposed to go away as soon as we have proper DT support for DSS. In this case it has just been a convenient place to set the gpios at boot time. The gpios are not touched after that. model these as panels and a generic driver which controls the panel could request and control pins and gpios as needed I suppose. gpio controller cannot drive default pull direction, that is the job of the driver using the gpio. I agree. But what to do when there is no driver that uses the gpio, but the gpio still affects the drivers? That's more or less the situation here. The SDP board has an LCD and a PicoDLP projector, and the board designers have shared resources between those, meaning only one can be used at a time. Having the GPIO pulled down means that LCD2 won't have backlight (although the gpio doesn't actually enable the backlight, it just handles the routing if I'm not mistaken) , but PicoDLP will have something (parallel video datalines, if I recall right). I can't add that GPIO to either the LCD driver or the PicoDLP driver, as it's not a property of either of them. Tomi signature.asc Description: OpenPGP digital signature
Re: [PATCH 3/3] ARM: OMAP2: omap4-sdp: remove unneeded gpios from dss-common
On 25/10/13 14:14, Nishanth Menon wrote:
lcd2_pins: pinmux_lcd2_pins {
+ pinctrl-single,pins =
+ 0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpio_40 */
+ 0x46 (PIN_OUTPUT_PULLUP | MUX_MODE3)/* gpio_59 */
+ 0x56 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpio_104 */
+ ;
3 pins are driven around 300uA at boot, even with display OFF - which
means wasted current that could have been optimized by hooking the pin
to the dts node corresponding to the device and used by the driver
appropriately.
One more clarification question.
The gpio 40 is used to enable powers for the picodlp. Shouldn't that one
have a pinctrl pull-down in any case? If it's left floating, and the
driver is not compiled in or doesn't start, the powers could get enabled
depending on sunspot, right?
And I guess the same goes for all gpios used to enable something.
Tomi
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Re: [PATCH v2 0/5] Assorted OMAP2 NAND clean-ups
Pekon, On Fri, Oct 25, 2013 at 11:15:57AM +, Gupta, Pekon wrote: Hi, -Original Message- From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com] [...] Pekon, Brian: Do you think this solution might work for 8-bit and 16-bit devices? I think NAND_BUSWIDTH_AUTO (without GPMC changes) would fail in following scenarios.. Case-1: configuring gpmc,device-width=1 from DT when using x16 device. ... which is wrong. That's why we have a DT property to configure that. The GPMC *must* be properly configured. As your NAND driver is using NAND_BUSWIDTH_AUTO, it should ignore this DT config, and based on ONFI params it should work as x16 Hm.. I don't think so. The auto-stuff is just for the NAND driver, not for the memory controller. I don't know much about hardware, but in my mind I imagine them as different controllers. Case-2: configuring gpmc,device-width=2 from DT when using x8 device. ... which is also wrong. Once again, you're mis-configuring the GPMC. We cannot expect the NAND driver to work properly if the GPMC is not properly initialized, don't you think? Actually having NAND_BUSWIDTH_AUTO would require change in GPMC driver also.. please refer my comments in.. http://lists.infradead.org/pipermail/linux-mtd/2013-October/049284.html Well, I think the approach should be different and much simpler: GPMC *must* be properly configured and then NAND can do ONFI detection starting in 8-bit and then switching to 16-bit if needed. This is what this patch is doing: it _fixes_ the NAND driver ONFI detection, _provided_ the GPMC is well-prepared. You seem to think that GPMC + NAND should be able to automagically detect the device and work, but I don't think that's even physically possible, for the reasons you have just exposed. I think this fix is simple enough. BTW: The GPMC code ignores the DT value in 'gpmc,device-width' and uses 'nand-bus-width' instead, but that's a different bug and a different fix :) -- Ezequiel García, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/5] mtd: nand: omap2: Fix OMAP_BCH option dependency
On Fri, Oct 25, 2013 at 11:26:06AM +, Gupta, Pekon wrote: From: Ezequiel Garcia [mailto:ezequiel.gar...@free-electrons.com] Subject: [PATCH v2 3/5] mtd: nand: omap2: Fix OMAP_BCH option dependency This option does not need to depend in MTD_NAND, for it's enclosed under it. Also, it's wrong to make it depend in ARCH_OMAP3 only since the controller is used in a wider range of SoCs. Instead, just leave the dependency on the OMAP2 driver option. Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com --- drivers/mtd/nand/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index d885298..8187466 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -95,7 +95,7 @@ config MTD_NAND_OMAP2 platforms. config MTD_NAND_OMAP_BCH - depends on MTD_NAND MTD_NAND_OMAP2 ARCH_OMAP3 + depends on MTD_NAND_OMAP2 tristate Enable support for hardware BCH error correction default n select BCH -- 1.8.1.5 Acked-by: Pekon Gupta pe...@ti.com Thanks! Reported-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com FWIW, If I'm signing-off this commit, it's implicit that I'm the reporter. -- Ezequiel García, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC/PATCH] arm: omap2plus_defconfig: enable more drivers
enable a few more drivers as modules on omap2plus_defconfig, this helps us getting more platforms working out of the box by just building omap2plus_defconfig. Signed-off-by: Felipe Balbi ba...@ti.com --- Hi Tony, would you consider enabling these drivers ? I didn't, yet, make sure that these drivers won't cause PM regressions. Wanted to make sure you'd be ok enabling so many of them. cheers arch/arm/configs/omap2plus_defconfig | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 98a50c3..6530956 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -134,6 +134,7 @@ CONFIG_KEYBOARD_MATRIX=m CONFIG_KEYBOARD_TWL4030=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=y +CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m CONFIG_INPUT_MISC=y CONFIG_INPUT_TWL4030_PWRBUTTON=y # CONFIG_LEGACY_PTYS is not set @@ -169,6 +170,7 @@ CONFIG_DRA752_THERMAL=y CONFIG_WATCHDOG=y CONFIG_OMAP_WATCHDOG=y CONFIG_TWL4030_WATCHDOG=y +CONFIG_MFD_TI_AM335X_TSCADC=m CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65217=y CONFIG_MFD_TPS65910=y @@ -214,13 +216,21 @@ CONFIG_USB=y CONFIG_USB_DEBUG=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_MON=y +CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_TUSB6010=m +CONFIG_USB_MUSB_OMAP2PLUS=m +CONFIG_USB_MUSB_AM35X=m +CONFIG_USB_MUSB_DSPS=m CONFIG_USB_WDM=y CONFIG_USB_STORAGE=y CONFIG_USB_DWC3=m +# CONFIG_USB_DWC3_EXYNOS is not set +CONFIG_USB_DWC3_DEBUG=y +CONFIG_USB_DWC3_VERBOSE=y CONFIG_USB_TEST=y -CONFIG_NOP_USB_XCEIV=y CONFIG_OMAP_USB2=y CONFIG_OMAP_USB3=y +CONFIG_AM335X_PHY_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DEBUG=y CONFIG_USB_GADGET_DEBUG_FILES=y @@ -242,14 +252,28 @@ CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PALMAS=m CONFIG_RTC_DRV_TWL92330=y CONFIG_RTC_DRV_TWL4030=y +CONFIG_RTC_DRV_TPS65910=m CONFIG_RTC_DRV_OMAP=y CONFIG_DMADEVICES=y CONFIG_TI_EDMA=y CONFIG_DMA_OMAP=y CONFIG_EXTCON=y CONFIG_EXTCON_PALMAS=y +CONFIG_MEMORY=y +CONFIG_TI_EMIF=m +CONFIG_IIO=m +CONFIG_IIO_BUFFER=y +CONFIG_IIO_KFIFO_BUF=m +CONFIG_TI_AM335X_ADC=m +CONFIG_TWL6030_GPADC=m +CONFIG_PWM=y +CONFIG_PWM_TIECAP=m +CONFIG_PWM_TIEHRPWM=m +CONFIG_PWM_TWL=m +CONFIG_PWM_TWL_LED=m CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -- 1.8.4.GIT -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] ARM: OMAP: dmtimers improvements.
* Shilimkar, Santosh santosh.shilim...@ti.com [131024 11:11]: Sorry for top posting Probably we should move the dmtimer to drivers/misc or create drivers/timer/ This has been pending for quite some time now Tony, what you say ? Yes that should be done and we should cc Thomas Gleixner to see if he has any better ideas for some of those exported functions. Things that can be done with hrtimer should be done with hrtimer, but at least the coprocessor use of timers and PWM need to use timers directly. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH] arm: omap2plus_defconfig: enable more drivers
* Felipe Balbi ba...@ti.com [131025 07:20]: enable a few more drivers as modules on omap2plus_defconfig, this helps us getting more platforms working out of the box by just building omap2plus_defconfig. Signed-off-by: Felipe Balbi ba...@ti.com --- Hi Tony, would you consider enabling these drivers ? I didn't, yet, make sure that these drivers won't cause PM regressions. Wanted to make sure you'd be ok enabling so many of them. Sure, we should have all common drivers enabled, preferrably as loadable modules where possible. Probably at least MUSB gadgets need to be loadable modulees as at least I have my test setup in a rack with USB cables connected all the time. That way the PM tests can be done without the USB modules loaded. Or maybe we can just PM runtime suspend the USB drivers for PM tests? Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] ARM: OMAP2: omap4-sdp: remove unneeded gpios from dss-common
On 10/25/2013 06:46 AM, Tomi Valkeinen wrote:
On 25/10/13 14:14, Nishanth Menon wrote:
lcd2_pins: pinmux_lcd2_pins {
+pinctrl-single,pins =
+0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpio_40 */
+0x46 (PIN_OUTPUT_PULLUP | MUX_MODE3)/* gpio_59 */
+0x56 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpio_104 */
+;
3 pins are driven around 300uA at boot, even with display OFF - which
means wasted current that could have been optimized by hooking the pin
to the dts node corresponding to the device and used by the driver
appropriately.
One more clarification question.
The gpio 40 is used to enable powers for the picodlp. Shouldn't that one
have a pinctrl pull-down in any case? If it's left floating, and the
driver is not compiled in or doesn't start, the powers could get enabled
depending on sunspot, right?
And I guess the same goes for all gpios used to enable something.
Fair question. The selection of pull up, gpio control needs to be
balanced.
if the peripheral in question has a regulator controlled supply, none
of the pins would matter - driver can adequately sequence this to
ensure there are no weird side-effects. in such a scenario, i'd have a
default MODE3 with no pulls, sequence as follows:
a) control gpio to required default level (disabled)
b) control regulator
c) set GPIO to enable.
if the peripheral in question is always on and controlled with just a
enable pin, it is safer to keep the pin muxed with weak pull.
If the enable has no real functional impact without setting another
pin (say power_on), or if any transient glitches on the line has no
functional impact, I might go with no pull configuration.
It all depends on the schematics and peripherals involved w.r.t how
you'd optimally select the configuration.
--
Regards,
Nishanth Menon
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Re: [RFC/PATCH] arm: omap2plus_defconfig: enable more drivers
Hi, On Fri, Oct 25, 2013 at 07:44:26AM -0700, Tony Lindgren wrote: * Felipe Balbi ba...@ti.com [131025 07:20]: enable a few more drivers as modules on omap2plus_defconfig, this helps us getting more platforms working out of the box by just building omap2plus_defconfig. Signed-off-by: Felipe Balbi ba...@ti.com --- Hi Tony, would you consider enabling these drivers ? I didn't, yet, make sure that these drivers won't cause PM regressions. Wanted to make sure you'd be ok enabling so many of them. Sure, we should have all common drivers enabled, preferrably as loadable modules where possible. Probably at least MUSB gadgets need to be loadable modulees as at least I have my test setup in a rack with USB cables connected all the time. That way the PM tests can be done without the USB modules loaded. Or maybe we can just PM runtime suspend the USB drivers for PM tests? I'd rather just unload the drivers if they cause issues. The thing is that with a patch like $subject, we get more working out-of-the-box and since most everything is really already in mainline (at least after v3.13 merge window) except for DTS (which should go up on v3.14, all the pending stuff), then we should be in really good shape after enabling all the necessary modules. -- balbi signature.asc Description: Digital signature
[PATCHv9 01/43] clk: Add support for regmap register read/write
Previously, only direct register read/write was supported. Now a per-clock
regmap can be provided for same purpose, which allows the clock drivers
to access clock registers behind e.g. I2C bus.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-divider.c|6 +++---
drivers/clk/clk-gate.c |6 +++---
drivers/clk/clk-mux.c|6 +++---
include/linux/clk-provider.h | 23 +++
4 files changed, 28 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8d3009e..9c17b1a 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw
*hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int div, val;
- val = clk_readl(divider-reg) divider-shift;
+ val = clk_readl(divider-reg, divider-regmap) divider-shift;
val = div_mask(divider);
div = _get_div(divider, val);
@@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw,
unsigned long rate,
if (divider-flags CLK_DIVIDER_HIWORD_MASK) {
val = div_mask(divider) (divider-shift + 16);
} else {
- val = clk_readl(divider-reg);
+ val = clk_readl(divider-reg, divider-regmap);
val = ~(div_mask(divider) divider-shift);
}
val |= value divider-shift;
- clk_writel(val, divider-reg);
+ clk_writel(val, divider-reg, divider-regmap);
if (divider-lock)
spin_unlock_irqrestore(divider-lock, flags);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 4a58c55..3c7f686 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
if (set)
reg |= BIT(gate-bit_idx);
} else {
- reg = clk_readl(gate-reg);
+ reg = clk_readl(gate-reg, gate-regmap);
if (set)
reg |= BIT(gate-bit_idx);
@@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
reg = ~BIT(gate-bit_idx);
}
- clk_writel(reg, gate-reg);
+ clk_writel(reg, gate-reg, gate-regmap);
if (gate-lock)
spin_unlock_irqrestore(gate-lock, flags);
@@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
u32 reg;
struct clk_gate *gate = to_clk_gate(hw);
- reg = clk_readl(gate-reg);
+ reg = clk_readl(gate-reg, gate-regmap);
/* if a set bit disables this clk, flip it before masking */
if (gate-flags CLK_GATE_SET_TO_DISABLE)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 4f96ff3..68eb8c2 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
* val = 0x4 really means bit 2, index starts at bit 0
*/
- val = clk_readl(mux-reg) mux-shift;
+ val = clk_readl(mux-reg, mux-regmap) mux-shift;
val = mux-mask;
if (mux-table) {
@@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
if (mux-flags CLK_MUX_HIWORD_MASK) {
val = mux-mask (mux-shift + 16);
} else {
- val = clk_readl(mux-reg);
+ val = clk_readl(mux-reg, mux-regmap);
val = ~(mux-mask mux-shift);
}
val |= index mux-shift;
- clk_writel(val, mux-reg);
+ clk_writel(val, mux-reg, mux-regmap);
if (mux-lock)
spin_unlock_irqrestore(mux-lock, flags);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7e59253..63ff78c 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -13,6 +13,7 @@
#include linux/clk.h
#include linux/io.h
+#include linux/regmap.h
#ifdef CONFIG_COMMON_CLK
@@ -209,6 +210,7 @@ void of_fixed_clk_setup(struct device_node *np);
*
* @hw:handle between common and hardware-specific interfaces
* @reg: register controlling gate
+ * @regmap:regmap for accessing the gate register (if any)
* @bit_idx: single bit controlling gate
* @flags: hardware-specific flags
* @lock: register lock
@@ -227,6 +229,7 @@ void of_fixed_clk_setup(struct device_node *np);
struct clk_gate {
struct clk_hw hw;
void __iomem*reg;
+ struct regmap *regmap;
u8 bit_idx;
u8 flags;
spinlock_t *lock;
@@ -251,6 +254,7 @@ struct clk_div_table {
*
* @hw:handle between common and hardware-specific interfaces
* @reg: register containing the divider
+ * @regmap:regmap for accessing the divider
[PATCHv9 03/43] clk: mux: add init call which supports regmap
Multiplexer clock can now be initialized to use regmap for control register
access.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-mux.c| 17 +++--
include/linux/clk-provider.h |4
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 68eb8c2..2cf7d59 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -113,9 +113,9 @@ const struct clk_ops clk_mux_ro_ops = {
};
EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
-struct clk *clk_register_mux_table(struct device *dev, const char *name,
+struct clk *clk_register_mux_table_regmap(struct device *dev, const char *name,
const char **parent_names, u8 num_parents, unsigned long flags,
- void __iomem *reg, u8 shift, u32 mask,
+ void __iomem *reg, struct regmap *regmap, u8 shift, u32 mask,
u8 clk_mux_flags, u32 *table, spinlock_t *lock)
{
struct clk_mux *mux;
@@ -149,6 +149,7 @@ struct clk *clk_register_mux_table(struct device *dev,
const char *name,
/* struct clk_mux assignments */
mux-reg = reg;
+ mux-regmap = regmap;
mux-shift = shift;
mux-mask = mask;
mux-flags = clk_mux_flags;
@@ -163,6 +164,18 @@ struct clk *clk_register_mux_table(struct device *dev,
const char *name,
return clk;
}
+EXPORT_SYMBOL_GPL(clk_register_mux_table_regmap);
+
+struct clk *clk_register_mux_table(struct device *dev, const char *name,
+ const char **parent_names, u8 num_parents, unsigned long flags,
+ void __iomem *reg, u8 shift, u32 mask,
+ u8 clk_mux_flags, u32 *table, spinlock_t *lock)
+{
+ return clk_register_mux_table_regmap(dev, name, parent_names,
+num_parents, flags, reg, NULL,
+shift, mask, clk_mux_flags, table,
+lock);
+}
EXPORT_SYMBOL_GPL(clk_register_mux_table);
struct clk *clk_register_mux(struct device *dev, const char *name,
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 369d7c0..9a1423e 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -362,6 +362,10 @@ struct clk *clk_register_mux_table(struct device *dev,
const char *name,
const char **parent_names, u8 num_parents, unsigned long flags,
void __iomem *reg, u8 shift, u32 mask,
u8 clk_mux_flags, u32 *table, spinlock_t *lock);
+struct clk *clk_register_mux_table_regmap(struct device *dev, const char *name,
+ const char **parent_names, u8 num_parents, unsigned long flags,
+ void __iomem *reg, struct regmap *regmap, u8 shift, u32 mask,
+ u8 clk_mux_flags, u32 *table, spinlock_t *lock);
void of_fixed_factor_clk_setup(struct device_node *node);
--
1.7.9.5
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[PATCHv9 00/43] ARM: TI SoC clock DT conversion
Hi all, Version 9 contains following major changes: - Clock nodes changed to use offsets instead of direct memory addresses * of_iomap() no longer called by individual clock drivers * prcm-driver provides regmap for accessing the registers based on the offsets * added support for regmaps to generic clock code * added support for regmaps to clock code under mach-omap2 - Devicetree layout changed to be hierarchical: ocp-ip-clocks/clockdomains * allows above mentioned offsets to be used - Clock init mechanism changed completely, called now from prm_common.c, see patch #38. This patch contains some rather nasty looking hackery so if anybody has any idea how to make it cleaner, comments appreciated. Otherwise it can be cleaned later once strict hwmod dependencies are cleared and we don't need to do the early init hacks anymore. - ti,mux-gate-clock type was killed, instead added support for ti,composite-clock (see patch #08 for base + components in patches #09 + #11 + #13) Some minor changes also done: - changed ti,autoidle-low to ti,invert-autoidle-bit - ordering of patches changed to reflect merge locations (drivers/clk, arch/arm/boot/dts, arch/arm/mach-omap2) - maybe some others, too much code to track should have covered most of the major comments from Paul though Dependencies (included in the test branch): - regmap: debugfs: Fix a boot time crash with early regmap init - ARM: dts: OMAP5: Add mailbox dt node - ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register(v4) - clk: of: helper for determining number of parent clocks Testing done: - omap3-beagle: boot + suspend/resume (ret + off) - omap4-panda-es: boot + suspend/resume - omap5-uevm: boot - dra7-evm: boot - am335x-bone: boot Test branches available: tree: https://github.com/t-kristo/linux-pm.git DTS data branch: 3.12-rc6-dt-clks-for-benoit CLK driver branch: 3.12-rc6-dt-clks-for-mike Misc OMAP stuff branch: 3.12-rc6-dt-clks-for-tony Fully functioning test branch: 3.12-rc6-dt-clks-v9 -Tero -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv9 07/43] CLK: TI: add autoidle support
TI clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clock.c |6 +++
drivers/clk/ti/Makefile |2 +-
drivers/clk/ti/autoidle.c | 109 +++
include/linux/clk/ti.h |9
4 files changed, 125 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/autoidle.c
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0c38ca9..223f432b 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
list_for_each_entry(c, clk_hw_omap_clocks, node)
if (c-ops c-ops-allow_idle)
c-ops-allow_idle(c);
+
+ of_ti_clk_allow_autoidle_all();
+
return 0;
}
@@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
list_for_each_entry(c, clk_hw_omap_clocks, node)
if (c-ops c-ops-deny_idle)
c-ops-deny_idle(c);
+
+ of_ti_clk_deny_autoidle_all();
+
return 0;
}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 05af5d8..533efb4 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
ifneq ($(CONFIG_OF),)
-obj-y += clk.o dpll.o
+obj-y += clk.o dpll.o autoidle.o
endif
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
new file mode 100644
index 000..efa2a3e
--- /dev/null
+++ b/drivers/clk/ti/autoidle.c
@@ -0,0 +1,109 @@
+/*
+ * TI clock autoidle support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo t-kri...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk-provider.h
+#include linux/slab.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk/ti.h
+
+struct clk_ti_autoidle {
+ u32 reg;
+ struct regmap *regmap;
+ u8 shift;
+ u8 flags;
+ const char *name;
+ struct list_headnode;
+};
+
+#define AUTOIDLE_LOW 0x1
+
+static LIST_HEAD(autoidle_clks);
+
+static void ti_allow_autoidle(struct clk_ti_autoidle *clk)
+{
+ u32 val;
+
+ regmap_read(clk-regmap, clk-reg, val);
+
+ if (clk-flags AUTOIDLE_LOW)
+ val = ~(1 clk-shift);
+ else
+ val |= (1 clk-shift);
+
+ regmap_write(clk-regmap, clk-reg, val);
+}
+
+static void ti_deny_autoidle(struct clk_ti_autoidle *clk)
+{
+ u32 val;
+
+ regmap_read(clk-regmap, clk-reg, val);
+
+ if (clk-flags AUTOIDLE_LOW)
+ val |= (1 clk-shift);
+ else
+ val = ~(1 clk-shift);
+
+ regmap_write(clk-regmap, clk-reg, val);
+}
+
+void of_ti_clk_allow_autoidle_all(void)
+{
+ struct clk_ti_autoidle *c;
+
+ list_for_each_entry(c, autoidle_clks, node)
+ ti_allow_autoidle(c);
+}
+
+void of_ti_clk_deny_autoidle_all(void)
+{
+ struct clk_ti_autoidle *c;
+
+ list_for_each_entry(c, autoidle_clks, node)
+ ti_deny_autoidle(c);
+}
+
+int __init of_ti_autoidle_setup(struct device_node *node,
+ struct regmap *regmap)
+{
+ u32 shift;
+ struct clk_ti_autoidle *clk;
+
+ if (of_property_read_u32(node, ti,autoidle-shift, shift))
+ return 0;
+
+ clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+
+ if (!clk) {
+ pr_err(%s: kzalloc failed\n, __func__);
+ return -ENOMEM;
+ }
+
+ clk-shift = shift;
+ clk-name = node-name;
+ of_property_read_u32(node, reg, clk-reg);
+ clk-regmap = regmap;
+
+ if (of_property_read_bool(node, ti,invert-autoidle-bit))
+ clk-flags |= AUTOIDLE_LOW;
+
+ list_add(clk-node, autoidle_clks);
+
+ return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 7ab02fa..e45005c 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -178,6 +178,15 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long
rate,
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
void ti_dt_clk_init_provider(struct device_node *np, struct regmap
[PATCHv9 10/43] clk: ti: add support for TI fixed factor clock
This behaves exactly in similar manner to basic fixed-factor-clock, but
adds a few properties on top for handling clock hardware autoidling.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../bindings/clock/ti/fixed-factor-clock.txt | 29 +
drivers/clk/ti/Makefile|2 +-
drivers/clk/ti/fixed-factor.c | 65
3 files changed, 95 insertions(+), 1 deletion(-)
create mode 100644
Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
create mode 100644 drivers/clk/ti/fixed-factor.c
diff --git a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
new file mode 100644
index 000..60b9e34
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
@@ -0,0 +1,29 @@
+Binding for TI fixed factor rate clock sources.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be ti,fixed-factor-clock.
+- #clock-cells : from common clock binding; shall be set to 0.
+- ti,clock-div: fixed divider.
+- ti,clock-mult: fixed multiplier.
+- clocks: parent clock.
+
+Optional properties:
+- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock
+- reg: offset for the autoidle register of this clock
+- ti,invert-autoidle-bit: autoidle is enabled by setting the bit to 0
+- ti,set-rate-parent: clk_set_rate is propagated to parent
+
+Example:
+ clock {
+ compatible = ti,fixed-factor-clock;
+ clocks = parentclk;
+ #clock-cells = 0;
+ ti,clock-div = 2;
+ ti,clock-mult = 1;
+ };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 640ebf9..f57fc4b 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,4 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
- composite.o
+ fixed-factor.o composite.o
endif
diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c
new file mode 100644
index 000..e0549c6
--- /dev/null
+++ b/drivers/clk/ti/fixed-factor.c
@@ -0,0 +1,65 @@
+/*
+ * TI Fixed Factor Clock
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo t-kri...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk-provider.h
+#include linux/slab.h
+#include linux/err.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk/ti.h
+
+/**
+ * of_ti_fixed_factor_clk_setup() - Setup function for TI fixed factor clock
+ */
+static int __init of_ti_fixed_factor_clk_setup(struct device_node *node,
+ struct regmap *regmap)
+{
+ struct clk *clk;
+ const char *clk_name = node-name;
+ const char *parent_name;
+ u32 div, mult;
+ u32 flags = 0;
+
+ if (of_property_read_u32(node, ti,clock-div, div)) {
+ pr_err(%s Fixed factor clock %s must have a clock-div
property\n,
+ __func__, node-name);
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, ti,clock-mult, mult)) {
+ pr_err(%s Fixed factor clock %s must have a clokc-mult
property\n,
+ __func__, node-name);
+ return -EINVAL;
+ }
+
+ if (of_property_read_bool(node, ti,set-rate-parent))
+ flags |= CLK_SET_RATE_PARENT;
+
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
+ mult, div);
+
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ return of_ti_autoidle_setup(node, regmap);
+ }
+
+ return PTR_ERR(clk);
+}
+CLK_OF_DECLARE(ti_fixed_factor_clk, ti,fixed-factor-clock,
+ of_ti_fixed_factor_clk_setup);
--
1.7.9.5
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[PATCHv9 02/43] clk: divider: add init call which supports regmap
Divider clock can now be initialized to use regmap for control register
access.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-divider.c| 37 -
include/linux/clk-provider.h |6 ++
2 files changed, 38 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 9c17b1a..3767879 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -251,7 +251,7 @@ EXPORT_SYMBOL_GPL(clk_divider_ops);
static struct clk *_register_divider(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
- void __iomem *reg, u8 shift, u8 width,
+ void __iomem *reg, struct regmap *regmap, u8 shift, u8 width,
u8 clk_divider_flags, const struct clk_div_table *table,
spinlock_t *lock)
{
@@ -281,6 +281,7 @@ static struct clk *_register_divider(struct device *dev,
const char *name,
/* struct clk_divider assignments */
div-reg = reg;
+ div-regmap = regmap;
div-shift = shift;
div-width = width;
div-flags = clk_divider_flags;
@@ -314,8 +315,8 @@ struct clk *clk_register_divider(struct device *dev, const
char *name,
void __iomem *reg, u8 shift, u8 width,
u8 clk_divider_flags, spinlock_t *lock)
{
- return _register_divider(dev, name, parent_name, flags, reg, shift,
- width, clk_divider_flags, NULL, lock);
+ return _register_divider(dev, name, parent_name, flags, reg, NULL,
+ shift, width, clk_divider_flags, NULL, lock);
}
EXPORT_SYMBOL_GPL(clk_register_divider);
@@ -339,7 +340,33 @@ struct clk *clk_register_divider_table(struct device *dev,
const char *name,
u8 clk_divider_flags, const struct clk_div_table *table,
spinlock_t *lock)
{
- return _register_divider(dev, name, parent_name, flags, reg, shift,
- width, clk_divider_flags, table, lock);
+ return _register_divider(dev, name, parent_name, flags, reg, NULL,
+ shift, width, clk_divider_flags, table, lock);
}
EXPORT_SYMBOL_GPL(clk_register_divider_table);
+
+/**
+ * clk_register_divider_table_regmap - register a table based divider clock
+ * with the clock framework
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @reg: register address to adjust divider
+ * @regmap: regmap for accessing the divider register (if any)
+ * @shift: number of bits to shift the bitfield
+ * @width: width of the bitfield
+ * @clk_divider_flags: divider-specific flags for this clock
+ * @table: array of divider/value pairs ending with a div set to 0
+ * @lock: shared register lock for this clock
+ */
+struct clk *clk_register_divider_table_regmap(struct device *dev,
+ const char *name, const char *parent_name, unsigned long flags,
+ void __iomem *reg, struct regmap *regmap, u8 shift, u8 width,
+ u8 clk_divider_flags, const struct clk_div_table *table,
+ spinlock_t *lock)
+{
+ return _register_divider(dev, name, parent_name, flags, reg, regmap,
+ shift, width, clk_divider_flags, table, lock);
+}
+EXPORT_SYMBOL_GPL(clk_register_divider_table_regmap);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 63ff78c..369d7c0 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -306,12 +306,18 @@ struct clk *clk_register_divider_table(struct device
*dev, const char *name,
void __iomem *reg, u8 shift, u8 width,
u8 clk_divider_flags, const struct clk_div_table *table,
spinlock_t *lock);
+struct clk *clk_register_divider_table_regmap(struct device *dev,
+ const char *name, const char *parent_name, unsigned long flags,
+ void __iomem *reg, struct regmap *regmap, u8 shift, u8 width,
+ u8 clk_divider_flags, const struct clk_div_table *table,
+ spinlock_t *lock);
/**
* struct clk_mux - multiplexer clock
*
* @hw:handle between common and hardware-specific interfaces
* @reg: register controlling multiplexer
+ * @regmap:regmap for accessing the mux register (if any)
* @shift: shift to multiplexer bit field
* @width: width of mutliplexer bit field
* @flags: hardware-specific flags
--
1.7.9.5
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[PATCHv9 09/43] CLK: ti: add support for ti divider-clock
This patch adds support for TI divider clock binding, which simply uses
the basic clock divider to provide the features needed.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/divider.txt | 86 +++
drivers/clk/ti/Makefile|3 +-
drivers/clk/ti/divider.c | 239
3 files changed, 327 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/divider.txt
create mode 100644 drivers/clk/ti/divider.c
diff --git a/Documentation/devicetree/bindings/clock/ti/divider.txt
b/Documentation/devicetree/bindings/clock/ti/divider.txt
new file mode 100644
index 000..65e3dcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/divider.txt
@@ -0,0 +1,86 @@
+Binding for TI divider clock
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped adjustable clock rate divider that does not gate and has
+only one input clock or parent. By default the value programmed into
+the register is one less than the actual divisor value. E.g:
+
+register value actual divisor value
+0 1
+1 2
+2 3
+
+This assumption may be modified by the following optional properties:
+
+ti,index-starts-at-one - valid divisor values start at 1, not the default
+of 0. E.g:
+register value actual divisor value
+1 1
+2 2
+3 3
+
+ti,index-power-of-two - valid divisor values are powers of two. E.g:
+register value actual divisor value
+0 1
+1 2
+2 4
+
+Additionally an array of valid dividers may be supplied like so:
+
+ dividers = 4, 8, 0, 16;
+
+Which will map the resulting values to a divisor table by their index:
+register value actual divisor value
+0 4
+1 8
+2 invalid divisor, skipped
+3 16
+
+Any zero value in this array means the corresponding bit-value is invalid
+and must not be used.
+
+The binding must also provide the register to control the divider and
+unless the divider array is provided, min and max dividers. Optionally
+the number of bits to shift that mask, if necessary. If the shift value
+is missing it is the same as supplying a zero shift.
+
+Required properties:
+- compatible : shall be ti,divider-clock.
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link to phandle of parent clock
+- reg : offset for register controlling adjustable divider
+
+Optional properties:
+- clock-output-names : from common clock binding.
+- ti,dividers : array of integers defining divisors
+- ti,bit-shift : number of bits to shift the divider value, defaults to 0
+- ti,min-div : min divisor for dividing the input clock rate, only
+ needed if the first divisor is offset from the default value (1)
+- ti,max-div : max divisor for dividing the input clock rate, only needed
+ if ti,dividers is not defined.
+- ti,index-starts-at-one : valid divisor programming starts at 1, not zero
+- ti,index-power-of-two : valid divisor programming must be a power of two
+- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock
+- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
+- ti,set-rate-parent : clk_set_rate is propagated to parent
+
+Examples:
+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
+ #clock-cells = 0;
+ compatible = ti,divider-clock;
+ clocks = dpll_usb_ck;
+ ti,max-div = 127;
+ reg = 0x190;
+ ti,index-starts-at-one;
+};
+
+aess_fclk: aess_fclk@4a004528 {
+ #clock-cells = 0;
+ compatible = ti,divider-clock;
+ clocks = abe_clk;
+ ti,bit-shift = 24;
+ reg = 0x528;
+ ti,max-div = 2;
+};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index a4a7595..640ebf9 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,4 @@
ifneq ($(CONFIG_OF),)
-obj-y += clk.o dpll.o autoidle.o composite.o
+obj-y += clk.o dpll.o autoidle.o divider.o \
+ composite.o
endif
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
new file mode 100644
index 000..787bc8f
--- /dev/null
+++ b/drivers/clk/ti/divider.c
@@ -0,0 +1,239 @@
+/*
+ * TI Divider Clock
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo t-kri...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or
[PATCHv9 08/43] clk: ti: add composite clock support
This is a multipurpose clock node, which contains support for multiple
sub-clocks. Uses basic composite clock type to implement the actual
functionality, and TI specific gate, mux and divider clocks.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/composite.txt | 54 +
drivers/clk/ti/Makefile|2 +-
drivers/clk/ti/composite.c | 222
include/linux/clk/ti.h |8 +
4 files changed, 285 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/composite.txt
create mode 100644 drivers/clk/ti/composite.c
diff --git a/Documentation/devicetree/bindings/clock/ti/composite.txt
b/Documentation/devicetree/bindings/clock/ti/composite.txt
new file mode 100644
index 000..5f43c47
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/composite.txt
@@ -0,0 +1,54 @@
+Binding for TI composite clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped composite clock with multiple different sub-types;
+
+a multiplexer clock with multiple input clock signals or parents, one
+of which can be selected as output, this behaves exactly as [2]
+
+an adjustable clock rate divider, this behaves exactly as [3]
+
+a gating function which can be used to enable and disable the output
+clock, this behaves exactly as [4]
+
+The binding must provide a list of the component clocks that shall be
+merged to this clock. The component clocks shall be of one of the
+ti,*composite*-clock types.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/mux.txt
+[3] Documentation/devicetree/bindings/clock/ti/divider.txt
+[4] Documentation/devicetree/bindings/clock/ti/gate.txt
+
+Required properties:
+- compatible : shall be: ti,composite-clock
+- clocks : link phandles of component clocks
+- #clock-cells : from common clock binding; shall be set to 0.
+
+Examples:
+
+usb_l4_gate_ick: usb_l4_gate_ick {
+ #clock-cells = 0;
+ compatible = ti,composite-interface-clock;
+ clocks = l4_ick;
+ ti,bit-shift = 5;
+ reg = 0x0a10;
+};
+
+usb_l4_div_ick: usb_l4_div_ick {
+ #clock-cells = 0;
+ compatible = ti,composite-divider-clock;
+ clocks = l4_ick;
+ ti,bit-shift = 4;
+ ti,max-div = 1;
+ reg = 0x0a40;
+ ti,index-starts-at-one;
+};
+
+usb_l4_ick: usb_l4_ick {
+ #clock-cells = 0;
+ compatible = ti,composite-clock;
+ clocks = usb_l4_gate_ick, usb_l4_div_ick;
+};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 533efb4..a4a7595 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
ifneq ($(CONFIG_OF),)
-obj-y += clk.o dpll.o autoidle.o
+obj-y += clk.o dpll.o autoidle.o composite.o
endif
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
new file mode 100644
index 000..9ce7e54
--- /dev/null
+++ b/drivers/clk/ti/composite.c
@@ -0,0 +1,222 @@
+/*
+ * TI composite clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo t-kri...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk-provider.h
+#include linux/slab.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk/ti.h
+#include linux/list.h
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return clk_divider_ops.recalc_rate(hw, parent_rate);
+}
+
+static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ return -EINVAL;
+}
+
+static int ti_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long parent_rate)
+{
+ return -EINVAL;
+}
+
+static const struct clk_ops ti_composite_divider_ops = {
+ .recalc_rate= ti_composite_recalc_rate,
+ .round_rate = ti_composite_round_rate,
+ .set_rate = ti_composite_set_rate,
+};
+
+static const struct clk_ops ti_composite_gate_ops = {
+ .enable = omap2_dflt_clk_enable,
+ .disable= omap2_dflt_clk_disable,
+ .is_enabled =
[PATCHv9 05/43] CLK: TI: add DT alias clock registration mechanism
Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific clock names.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/clk/ti/Makefile |2 +-
drivers/clk/ti/clk.c| 52 +++
include/linux/clk/ti.h | 23 +
3 files changed, 76 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 93177987..05af5d8 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
ifneq ($(CONFIG_OF),)
-obj-y += dpll.o
+obj-y += clk.o dpll.o
endif
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
new file mode 100644
index 000..ad58b01
--- /dev/null
+++ b/drivers/clk/ti/clk.c
@@ -0,0 +1,52 @@
+/*
+ * TI clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo t-kri...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/clk/ti.h
+#include linux/of.h
+
+/**
+ * ti_dt_clocks_register - register DT duplicate clocks during boot
+ * @oclks: list of clocks to register
+ *
+ * Register duplicate or non-standard DT clock entries during boot. By
+ * default, DT clocks are found based on their node name. If any
+ * additional con-id / dev-id - clock mapping is required, use this
+ * function to list these.
+ */
+void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
+{
+ struct ti_dt_clk *c;
+ struct device_node *node;
+ struct clk *clk;
+ struct of_phandle_args clkspec;
+
+ for (c = oclks; c-node_name != NULL; c++) {
+ node = of_find_node_by_name(NULL, c-node_name);
+ clkspec.np = node;
+ clk = of_clk_get_from_provider(clkspec);
+
+ if (!IS_ERR(clk)) {
+ c-lk.clk = clk;
+ clkdev_add(c-lk);
+ } else {
+ pr_warn(%s: failed to lookup clock node %s\n,
+ __func__, c-node_name);
+ }
+ }
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index c187023..9786752 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -15,6 +15,8 @@
#ifndef __LINUX_CLK_TI_H__
#define __LINUX_CLK_TI_H__
+#include linux/clkdev.h
+
/**
* struct dpll_data - DPLL registers and integration data
* @mult_div1_reg: register containing the DPLL M and N bitfields
@@ -135,6 +137,25 @@ struct clk_hw_omap {
/* DPLL Type and DCO Selection Flags */
#define DPLL_J_TYPE0x1
+/**
+ * struct ti_dt_clk - OMAP DT clock alias declarations
+ * @lk: clock lookup definition
+ * @node_name: clock DT node to map to
+ */
+struct ti_dt_clk {
+ struct clk_lookup lk;
+ char*node_name;
+};
+
+#define DT_CLK(dev, con, name) \
+ { \
+ .lk = { \
+ .dev_id = dev, \
+ .con_id = con, \
+ }, \
+ .node_name = name, \
+ }
+
void omap2_init_clk_hw_omap_clocks(struct clk *clk);
int omap3_noncore_dpll_enable(struct clk_hw *hw);
void omap3_noncore_dpll_disable(struct clk_hw *hw);
@@ -155,6 +176,8 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
+void ti_dt_clocks_register(struct ti_dt_clk *oclks);
+
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
--
1.7.9.5
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[PATCHv9 06/43] CLK: ti: add init support for clock IP blocks
ti_dt_clk_init_provider() can now be used to initialize the contents of
a single clock IP block. This parses all the clocks under the IP block
and calls the corresponding init function for them.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/ti/clk.c | 59
include/linux/clk/ti.h |1 +
2 files changed, 60 insertions(+)
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index ad58b01..7f030d7 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -19,6 +19,9 @@
#include linux/clkdev.h
#include linux/clk/ti.h
#include linux/of.h
+#include linux/list.h
+
+extern struct of_device_id __clk_of_table[];
/**
* ti_dt_clocks_register - register DT duplicate clocks during boot
@@ -50,3 +53,59 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
}
}
}
+
+typedef int (*ti_of_clk_init_cb_t)(struct device_node *, struct regmap *);
+
+struct clk_init_item {
+ struct regmap *regmap;
+ struct device_node *np;
+ ti_of_clk_init_cb_t init_cb;
+ struct list_head node;
+};
+
+static LIST_HEAD(retry_list);
+
+void __init ti_dt_clk_init_provider(struct device_node *parent,
+ struct regmap *regmap)
+{
+ const struct of_device_id *match;
+ struct device_node *np;
+ ti_of_clk_init_cb_t clk_init_cb;
+ struct clk_init_item *retry;
+ struct clk_init_item *tmp;
+ int ret;
+
+ for_each_child_of_node(parent, np) {
+ match = of_match_node(__clk_of_table, np);
+ if (!match)
+ continue;
+ clk_init_cb = match-data;
+ pr_debug(%s: initializing: %s\n, __func__, np-name);
+ ret = clk_init_cb(np, regmap);
+ if (ret == -EAGAIN) {
+ pr_debug(%s: adding to again list...\n, np-name);
+ retry = kzalloc(sizeof(*retry), GFP_KERNEL);
+ retry-np = np;
+ retry-regmap = regmap;
+ retry-init_cb = clk_init_cb;
+ list_add(retry-node, retry_list);
+ } else if (ret) {
+ pr_err(%s: clock init failed for %s (%d)!\n, __func__,
+ np-name, ret);
+ }
+ }
+
+ list_for_each_entry_safe(retry, tmp, retry_list, node) {
+ pr_debug(%s: retry-init: %s\n, __func__, retry-np-name);
+ ret = retry-init_cb(retry-np, retry-regmap);
+ if (ret == -EAGAIN) {
+ pr_debug(%s failed again?\n, retry-np-name);
+ } else {
+ if (ret)
+ pr_err(%s: clock init failed for %s (%d)!\n,
+ __func__, retry-np-name, ret);
+ list_del(retry-node);
+ kfree(retry);
+ }
+ }
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 9786752..7ab02fa 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -177,6 +177,7 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long
rate,
unsigned long parent_rate);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
+void ti_dt_clk_init_provider(struct device_node *np, struct regmap *regmap);
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
--
1.7.9.5
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[PATCHv9 15/43] CLK: TI: add omap5 clock init file
clk-54xx.c now contains the clock init functionality for omap5, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/io.c |1 +
drivers/clk/ti/Makefile |1 +
drivers/clk/ti/clk-54xx.c | 239 +
include/linux/clk/ti.h|1 +
4 files changed, 242 insertions(+)
create mode 100644 drivers/clk/ti/clk-54xx.c
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index ff2113c..e360ddf 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -650,6 +650,7 @@ void __init omap5_init_early(void)
omap54xx_clockdomains_init();
omap54xx_hwmod_init();
omap_hwmod_init_postsetup();
+ omap_clk_init = omap5xxx_dt_clk_init;
}
#endif
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 381f1f8..935e5d2 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,4 +3,5 @@ obj-y += clk.o dpll.o
autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
composite.o mux.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
+obj-$(CONFIG_SOC_OMAP5)+= clk-54xx.o
endif
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
new file mode 100644
index 000..c876e6e
--- /dev/null
+++ b/drivers/clk/ti/clk-54xx.c
@@ -0,0 +1,239 @@
+/*
+ * OMAP5 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kri...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/list.h
+#include linux/clk-private.h
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/clk/ti.h
+
+#define OMAP5_DPLL_ABE_DEFFREQ 98304000
+
+static struct ti_dt_clk omap54xx_clks[] = {
+ DT_CLK(NULL, pad_clks_src_ck, pad_clks_src_ck),
+ DT_CLK(NULL, pad_clks_ck, pad_clks_ck),
+ DT_CLK(NULL, secure_32k_clk_src_ck, secure_32k_clk_src_ck),
+ DT_CLK(NULL, slimbus_src_clk, slimbus_src_clk),
+ DT_CLK(NULL, slimbus_clk, slimbus_clk),
+ DT_CLK(NULL, sys_32k_ck, sys_32k_ck),
+ DT_CLK(NULL, virt_1200_ck, virt_1200_ck),
+ DT_CLK(NULL, virt_1300_ck, virt_1300_ck),
+ DT_CLK(NULL, virt_1680_ck, virt_1680_ck),
+ DT_CLK(NULL, virt_1920_ck, virt_1920_ck),
+ DT_CLK(NULL, virt_2600_ck, virt_2600_ck),
+ DT_CLK(NULL, virt_2700_ck, virt_2700_ck),
+ DT_CLK(NULL, virt_3840_ck, virt_3840_ck),
+ DT_CLK(NULL, sys_clkin, sys_clkin),
+ DT_CLK(NULL, xclk60mhsp1_ck, xclk60mhsp1_ck),
+ DT_CLK(NULL, xclk60mhsp2_ck, xclk60mhsp2_ck),
+ DT_CLK(NULL, abe_dpll_bypass_clk_mux, abe_dpll_bypass_clk_mux),
+ DT_CLK(NULL, abe_dpll_clk_mux, abe_dpll_clk_mux),
+ DT_CLK(NULL, dpll_abe_ck, dpll_abe_ck),
+ DT_CLK(NULL, dpll_abe_x2_ck, dpll_abe_x2_ck),
+ DT_CLK(NULL, dpll_abe_m2x2_ck, dpll_abe_m2x2_ck),
+ DT_CLK(NULL, abe_24m_fclk, abe_24m_fclk),
+ DT_CLK(NULL, abe_clk, abe_clk),
+ DT_CLK(NULL, abe_iclk, abe_iclk),
+ DT_CLK(NULL, abe_lp_clk_div, abe_lp_clk_div),
+ DT_CLK(NULL, dpll_abe_m3x2_ck, dpll_abe_m3x2_ck),
+ DT_CLK(NULL, dpll_core_ck, dpll_core_ck),
+ DT_CLK(NULL, dpll_core_x2_ck, dpll_core_x2_ck),
+ DT_CLK(NULL, dpll_core_h21x2_ck, dpll_core_h21x2_ck),
+ DT_CLK(NULL, c2c_fclk, c2c_fclk),
+ DT_CLK(NULL, c2c_iclk, c2c_iclk),
+ DT_CLK(NULL, custefuse_sys_gfclk_div, custefuse_sys_gfclk_div),
+ DT_CLK(NULL, dpll_core_h11x2_ck, dpll_core_h11x2_ck),
+ DT_CLK(NULL, dpll_core_h12x2_ck, dpll_core_h12x2_ck),
+ DT_CLK(NULL, dpll_core_h13x2_ck, dpll_core_h13x2_ck),
+ DT_CLK(NULL, dpll_core_h14x2_ck, dpll_core_h14x2_ck),
+ DT_CLK(NULL, dpll_core_h22x2_ck, dpll_core_h22x2_ck),
+ DT_CLK(NULL, dpll_core_h23x2_ck, dpll_core_h23x2_ck),
+ DT_CLK(NULL, dpll_core_h24x2_ck, dpll_core_h24x2_ck),
+ DT_CLK(NULL, dpll_core_m2_ck, dpll_core_m2_ck),
+ DT_CLK(NULL, dpll_core_m3x2_ck, dpll_core_m3x2_ck),
+ DT_CLK(NULL, iva_dpll_hs_clk_div, iva_dpll_hs_clk_div),
+ DT_CLK(NULL, dpll_iva_ck, dpll_iva_ck),
+ DT_CLK(NULL, dpll_iva_x2_ck, dpll_iva_x2_ck),
+ DT_CLK(NULL, dpll_iva_h11x2_ck, dpll_iva_h11x2_ck),
+ DT_CLK(NULL, dpll_iva_h12x2_ck, dpll_iva_h12x2_ck),
+ DT_CLK(NULL, mpu_dpll_hs_clk_div, mpu_dpll_hs_clk_div),
+ DT_CLK(NULL, dpll_mpu_ck, dpll_mpu_ck),
+ DT_CLK(NULL, dpll_mpu_m2_ck, dpll_mpu_m2_ck),
+ DT_CLK(NULL, per_dpll_hs_clk_div, per_dpll_hs_clk_div),
+
[PATCHv9 04/43] CLK: TI: Add DPLL clock support
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/dpll.txt | 81 +++
arch/arm/mach-omap2/clock.h| 144 +
arch/arm/mach-omap2/clock3xxx.h|2 -
drivers/clk/Makefile |1 +
drivers/clk/ti/Makefile|3 +
drivers/clk/ti/dpll.c | 632
include/linux/clk/ti.h | 161 +
7 files changed, 879 insertions(+), 145 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
create mode 100644 drivers/clk/ti/Makefile
create mode 100644 drivers/clk/ti/dpll.c
create mode 100644 include/linux/clk/ti.h
diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt
b/Documentation/devicetree/bindings/clock/ti/dpll.txt
new file mode 100644
index 000..7b87721
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
@@ -0,0 +1,81 @@
+Binding for Texas Instruments DPLL clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped DPLL with usually two selectable input clocks
+(reference clock and bypass clock), with digital phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) This binding has several
+sub-types, which effectively result in slightly different setup
+for the actual DPLL clock.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of:
+ ti,omap3-dpll-clock,
+ ti,omap3-dpll-core-clock,
+ ti,omap3-dpll-per-clock,
+ ti,omap3-dpll-per-j-type-clock,
+ ti,omap4-dpll-clock,
+ ti,omap4-dpll-x2-clock,
+ ti,omap4-dpll-core-clock,
+ ti,omap4-dpll-m4xen-clock,
+ ti,omap4-dpll-j-type-clock,
+ ti,am3-dpll-no-gate-clock,
+ ti,am3-dpll-j-type-clock,
+ ti,am3-dpll-no-gate-j-type-clock,
+ ti,am3-dpll-clock,
+ ti,am3-dpll-core-clock,
+ ti,am3-dpll-x2-clock,
+
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks, first entry lists reference clock
+ and second entry bypass clock
+- reg : offsets for the register set for controlling the DPLL.
+ Registers are listed in following order:
+ control - contains the control register base address
+ idlest - contains the idle status register base address
+ autoidle - contains the autoidle register base address
+ mult-div1 - contains the multiplier / divider register base address
+ ti,am3-* dpll types list the registers in the same order, except autoidle
+ register is left out as this hardware does not have it, e.g.:
+ reg = 0x40, 0x50, 0x60;
+ results in following register map:
+ base + 0x40 - control
+ base + 0x50 - idlest
+ base + 0x60 - mult-div1
+
+Optional properties:
+- DPLL mode setting - defining any one or more of the following overrides
+ default setting.
+ - ti,low-power-stop : DPLL supports low power stop mode, gating output
+ - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
+ - ti,lock : DPLL locks in programmed rate
+
+Examples:
+ dpll_core_ck: dpll_core_ck@44e00490 {
+ #clock-cells = 0;
+ compatible = ti,omap4-dpll-core-clock;
+ clocks = sys_clkin_ck, sys_clkin_ck;
+ reg = 0x490, 0x45c, 0x488, 0x468;
+ };
+
+ dpll2_ck: dpll2_ck@48004004 {
+ #clock-cells = 0;
+ compatible = ti,omap3-dpll-clock;
+ clocks = sys_ck, dpll2_fck;
+ ti,low-power-stop;
+ ti,low-power-bypass;
+ ti,lock;
+ reg = 0x4, 0x24, 0x34, 0x40;
+ };
+
+ dpll_core_ck: dpll_core_ck@44e00490 {
+ #clock-cells = 0;
+ compatible = ti,am3-dpll-core-clock;
+ clocks = sys_clkin_ck, sys_clkin_ck;
+ reg = 0x90, 0x5c, 0x68;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7aa32cd..079536a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
#include linux/clkdev.h
#include linux/clk-provider.h
+#include linux/clk/ti.h
struct omap_clk {
u16 cpu;
@@ -178,83 +179,6 @@ struct clksel {
const struct clksel_rate *rates;
};
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N
[PATCHv9 21/43] CLK: TI: add omap3 clock init file
clk-3xxx.c now contains the clock init functionality for omap3, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/clock3xxx.h |1 -
drivers/clk/ti/Makefile |2 +-
drivers/clk/ti/clk-3xxx.c | 400 +++
include/linux/clk/ti.h |5 +
4 files changed, 406 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/ti/clk-3xxx.c
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index dab90e2..78d9f56 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -11,7 +11,6 @@
int omap3xxx_clk_init(void);
int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
-void omap3_clk_lock_dpll5(void);
extern struct clk *sdrc_ick_p;
extern struct clk *arm_fck_p;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index e42a703..ab386c8 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,7 +3,7 @@ obj-y += clk.o dpll.o
autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
composite.o mux.o apll.o
obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o
-obj-$(CONFIG_ARCH_OMAP3) += interface.o
+obj-$(CONFIG_ARCH_OMAP3) += interface.o clk-3xxx.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5)+= clk-54xx.o
obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
new file mode 100644
index 000..739ceaa
--- /dev/null
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -0,0 +1,400 @@
+/*
+ * OMAP3 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kri...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/list.h
+#include linux/clk-provider.h
+#include linux/clk/ti.h
+
+
+static struct ti_dt_clk omap3xxx_clks[] = {
+ DT_CLK(NULL, apb_pclk, dummy_apb_pclk),
+ DT_CLK(NULL, omap_32k_fck, omap_32k_fck),
+ DT_CLK(NULL, virt_12m_ck, virt_12m_ck),
+ DT_CLK(NULL, virt_13m_ck, virt_13m_ck),
+ DT_CLK(NULL, virt_1920_ck, virt_1920_ck),
+ DT_CLK(NULL, virt_2600_ck, virt_2600_ck),
+ DT_CLK(NULL, virt_38_4m_ck, virt_38_4m_ck),
+ DT_CLK(NULL, osc_sys_ck, osc_sys_ck),
+ DT_CLK(twl, fck, osc_sys_ck),
+ DT_CLK(NULL, sys_ck, sys_ck),
+ DT_CLK(NULL, omap_96m_alwon_fck, omap_96m_alwon_fck),
+ DT_CLK(etb, emu_core_alwon_ck, emu_core_alwon_ck),
+ DT_CLK(NULL, sys_altclk, sys_altclk),
+ DT_CLK(NULL, mcbsp_clks, mcbsp_clks),
+ DT_CLK(NULL, sys_clkout1, sys_clkout1),
+ DT_CLK(NULL, dpll1_ck, dpll1_ck),
+ DT_CLK(NULL, dpll1_x2_ck, dpll1_x2_ck),
+ DT_CLK(NULL, dpll1_x2m2_ck, dpll1_x2m2_ck),
+ DT_CLK(NULL, dpll3_ck, dpll3_ck),
+ DT_CLK(NULL, core_ck, core_ck),
+ DT_CLK(NULL, dpll3_x2_ck, dpll3_x2_ck),
+ DT_CLK(NULL, dpll3_m2_ck, dpll3_m2_ck),
+ DT_CLK(NULL, dpll3_m2x2_ck, dpll3_m2x2_ck),
+ DT_CLK(NULL, dpll3_m3_ck, dpll3_m3_ck),
+ DT_CLK(NULL, dpll3_m3x2_ck, dpll3_m3x2_ck),
+ DT_CLK(NULL, dpll4_ck, dpll4_ck),
+ DT_CLK(NULL, dpll4_x2_ck, dpll4_x2_ck),
+ DT_CLK(NULL, omap_96m_fck, omap_96m_fck),
+ DT_CLK(NULL, cm_96m_fck, cm_96m_fck),
+ DT_CLK(NULL, omap_54m_fck, omap_54m_fck),
+ DT_CLK(NULL, omap_48m_fck, omap_48m_fck),
+ DT_CLK(NULL, omap_12m_fck, omap_12m_fck),
+ DT_CLK(NULL, dpll4_m2_ck, dpll4_m2_ck),
+ DT_CLK(NULL, dpll4_m2x2_ck, dpll4_m2x2_ck),
+ DT_CLK(NULL, dpll4_m3_ck, dpll4_m3_ck),
+ DT_CLK(NULL, dpll4_m3x2_ck, dpll4_m3x2_ck),
+ DT_CLK(NULL, dpll4_m4_ck, dpll4_m4_ck),
+ DT_CLK(NULL, dpll4_m4x2_ck, dpll4_m4x2_ck),
+ DT_CLK(NULL, dpll4_m5_ck, dpll4_m5_ck),
+ DT_CLK(NULL, dpll4_m5x2_ck, dpll4_m5x2_ck),
+ DT_CLK(NULL, dpll4_m6_ck, dpll4_m6_ck),
+ DT_CLK(NULL, dpll4_m6x2_ck, dpll4_m6x2_ck),
+ DT_CLK(etb, emu_per_alwon_ck, emu_per_alwon_ck),
+ DT_CLK(NULL, clkout2_src_ck, clkout2_src_ck),
+ DT_CLK(NULL, sys_clkout2, sys_clkout2),
+ DT_CLK(NULL, corex2_fck, corex2_fck),
+ DT_CLK(NULL, dpll1_fck, dpll1_fck),
+
[PATCHv9 17/43] CLK: TI: DRA7: Add APLL support
From: J Keerthy j-keer...@ti.com
The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.
APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.
Signed-off-by: J Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/apll.txt | 31 +++
drivers/clk/ti/Makefile|2 +-
drivers/clk/ti/apll.c | 239
3 files changed, 271 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/apll.txt
create mode 100644 drivers/clk/ti/apll.c
diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt
b/Documentation/devicetree/bindings/clock/ti/apll.txt
new file mode 100644
index 000..7faf5a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/apll.txt
@@ -0,0 +1,31 @@
+Binding for Texas Instruments APLL clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped APLL with usually two selectable input clocks
+(reference clock and bypass clock), with analog phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) APLL mostly behaves like
+a subtype of a DPLL [2], although a simplified one at that.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
+
+Required properties:
+- compatible : shall be ti,dra7-apll-clock
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
+- reg : address and length of the register set for controlling the APLL.
+ It contains the information of registers in the following order:
+ control - contains the control register base address
+ idlest - contains the idlest register base address
+
+Examples:
+ apll_pcie_ck: apll_pcie_ck@4a008200 {
+ #clock-cells = 0;
+ clocks = apll_pcie_in_clk_mux, dpll_pcie_ref_ck;
+ reg = 0x4a00821c 0x4, 0x4a008220 0x4;
+ compatible = ti,dra7-apll-clock;
+ };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 935e5d2..3d71e1e 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,7 +1,7 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
- composite.o mux.o
+ composite.o mux.o apll.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5)+= clk-54xx.o
endif
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
new file mode 100644
index 000..18dbbee
--- /dev/null
+++ b/drivers/clk/ti/apll.c
@@ -0,0 +1,239 @@
+/*
+ * OMAP APLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * J Keerthy j-keer...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk-provider.h
+#include linux/module.h
+#include linux/slab.h
+#include linux/io.h
+#include linux/err.h
+#include linux/string.h
+#include linux/log2.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk/ti.h
+#include linux/delay.h
+
+#define APLL_FORCE_LOCK 0x1
+#define APLL_AUTO_IDLE 0x2
+#define MAX_APLL_WAIT_TRIES100
+
+static int dra7_apll_enable(struct clk_hw *hw)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ int r = 0, i = 0;
+ struct dpll_data *ad;
+ const char *clk_name;
+ u8 state = 1;
+ u32 v;
+
+ ad = clk-dpll_data;
+ if (!ad)
+ return -EINVAL;
+
+ clk_name = __clk_get_name(clk-hw.clk);
+
+ state = __ffs(ad-idlest_mask);
+
+ /* Check is already locked */
+ regmap_read(clk-regmap, (u32)ad-idlest_reg, v);
+
+ if ((v ad-idlest_mask) == state)
+ return r;
+
+ regmap_read(clk-regmap, (u32)ad-control_reg, v);
+ v = ~ad-enable_mask;
+ v |= APLL_FORCE_LOCK __ffs(ad-enable_mask);
+ regmap_write(clk-regmap, (u32)ad-control_reg, v);
+
+ state = __ffs(ad-idlest_mask);
+
+ while (1) {
+ v =
[PATCHv9 13/43] clk: ti: add support for basic mux clock
ti,mux-clock provides now a binding for basic mux support. This is just
using the basic clock type.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
Documentation/devicetree/bindings/clock/ti/mux.txt | 67 ++
drivers/clk/ti/Makefile|2 +-
drivers/clk/ti/mux.c | 129
3 files changed, 197 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/mux.txt
create mode 100644 drivers/clk/ti/mux.c
diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt
b/Documentation/devicetree/bindings/clock/ti/mux.txt
new file mode 100644
index 000..9a2fd8e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/mux.txt
@@ -0,0 +1,67 @@
+Binding for TI mux clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped multiplexer with multiple input clock signals or
+parents, one of which can be selected as output. This clock does not
+gate or adjust the parent rate via a divider or multiplier.
+
+By default the clocks property lists the parents in the same order
+as they are programmed into the regster. E.g:
+
+ clocks = foo_clock, bar_clock, baz_clock;
+
+results in programming the register as follows:
+
+register value selected parent clock
+0 foo_clock
+1 bar_clock
+2 baz_clock
+
+Some clock controller IPs do not allow a value of zero to be programmed
+into the register, instead indexing begins at 1. The optional property
+index-starts-at-one modified the scheme as follows:
+
+register value selected clock parent
+1 foo_clock
+2 bar_clock
+3 baz_clock
+
+The binding must provide the register to control the mux. Optionally
+the number of bits to shift the control field in the register can be
+supplied. If the shift value is missing it is the same as supplying
+a zero shift.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be ti,mux-clock.
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks
+- reg : register offset for register controlling adjustable mux
+
+Optional properties:
+- ti,bit-shift : number of bits to shift the bit-mask, defaults to
+ 0 if not present
+- ti,index-starts-at-one : valid input select programming starts at 1, not
+ zero
+- ti,set-rate-parent : clk_set_rate is propagated to parent clock
+
+Examples:
+
+sys_clkin_ck: sys_clkin_ck@4a306110 {
+ #clock-cells = 0;
+ compatible = ti,mux-clock;
+ clocks = virt_1200_ck, virt_1300_ck, virt_1680_ck,
virt_1920_ck, virt_2600_ck, virt_2700_ck,
virt_3840_ck;
+ reg = 0x4a306110 0x4;
+ ti,index-starts-at-one;
+};
+
+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
+ #clock-cells = 0;
+ compatible = ti,mux-clock;
+ clocks = sys_clkin_ck, sys_32k_ck;
+ ti,bit-shift = 24;
+ reg = 0x4a306108 0x4;
+};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 67056fb..ef61d39 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,5 +1,5 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
- composite.o
+ composite.o mux.o
endif
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
new file mode 100644
index 000..9c5259a
--- /dev/null
+++ b/drivers/clk/ti/mux.c
@@ -0,0 +1,129 @@
+/*
+ * TI Multiplexer Clock
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo t-kri...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk-provider.h
+#include linux/slab.h
+#include linux/err.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk/ti.h
+
+/**
+ * of_mux_clk_setup() - Setup function for simple mux rate clock
+ */
+static int of_mux_clk_setup(struct device_node *node, struct regmap *regmap)
+{
+ struct clk *clk;
+ const char *clk_name = node-name;
+ void __iomem *reg;
+ int num_parents;
+ const char **parent_names;
+ int i;
+ u8 clk_mux_flags = 0;
+ u32 mask = 0;
+ u32 shift = 0;
+ u32 flags =
[PATCHv9 20/43] CLK: TI: add interface clock support for OMAP3
OMAP3 has interface clocks in addition to functional clocks, which
require special handling for the autoidle and idle status register
offsets mainly.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/interface.txt | 54
arch/arm/mach-omap2/clock.h|5 -
drivers/clk/ti/Makefile|1 +
drivers/clk/ti/interface.c | 139
include/linux/clk/ti.h |5 +
5 files changed, 199 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/interface.txt
create mode 100644 drivers/clk/ti/interface.c
diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt
b/Documentation/devicetree/bindings/clock/ti/interface.txt
new file mode 100644
index 000..064e8ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/interface.txt
@@ -0,0 +1,54 @@
+Binding for Texas Instruments interface clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features, including
+companion clock finding (match corresponding functional gate
+clock) and hardware autoidle enable / disable.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+
+Required properties:
+- compatible : shall be one of:
+ ti,omap3-interface-clock - basic OMAP3 interface clock
+ ti,omap3-no-wait-interface-clock - interface clock which has no hardware
+ capability for waiting clock to be ready
+ ti,omap3-hsotgusb-interface-clock - interface clock with USB specific HW
+ handling
+ ti,omap3-dss-interface-clock - interface clock with DSS specific HW
handling
+ ti,omap3-ssi-interface-clock - interface clock with SSI specific HW
handling
+ ti,am35xx-interface-clock - interface clock with AM35xx specific HW
handling
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : base address for the control register
+
+Optional properties:
+- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
+
+Examples:
+ aes1_ick: aes1_ick@48004a14 {
+ #clock-cells = 0;
+ compatible = ti,omap3-interface-clock;
+ clocks = security_l4_ick2;
+ reg = 0x48004a14 0x4;
+ ti,bit-shift = 3;
+ };
+
+ cam_ick: cam_ick@48004f10 {
+ #clock-cells = 0;
+ compatible = ti,omap3-no-wait-interface-clock;
+ clocks = l4_ick;
+ reg = 0x48004f10 0x4;
+ ti,bit-shift = 0;
+ };
+
+ ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
+ #clock-cells = 0;
+ compatible = ti,omap3-ssi-interface-clock;
+ clocks = ssi_l4_ick;
+ reg = 0x48004a10 0x4;
+ ti,bit-shift = 0;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b33f1e8..d1b227e 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -266,13 +266,8 @@ extern const struct clksel_rate gfx_l3_rates[];
extern const struct clksel_rate dsp_ick_rates[];
extern struct clk dummy_ck;
-extern const struct clk_hw_omap_ops clkhwops_iclk;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
-extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
extern const struct clk_hw_omap_ops clkhwops_apll54;
extern const struct clk_hw_omap_ops clkhwops_apll96;
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 7eb6f2b..e42a703 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,6 +3,7 @@ obj-y += clk.o dpll.o
autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
composite.o mux.o apll.o
obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o
+obj-$(CONFIG_ARCH_OMAP3) += interface.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5)+= clk-54xx.o
obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
new file mode 100644
index 000..c5f25d9
--- /dev/null
+++
[PATCHv9 19/43] CLK: TI: add am33xx clock init file
clk-33xx.c now contains the clock init functionality for am33xx, including
DT clock registration and adding of static clkdev entries.
This patch also moves the omap2_clk_enable_init_clocks declaration to
the driver include, as this is needed by the am33xx clock init code.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/clock.h |1 -
drivers/clk/ti/Makefile |1 +
drivers/clk/ti/clk-33xx.c | 161 +++
include/linux/clk/ti.h |2 +
4 files changed, 164 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk-33xx.c
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2a52da2..b33f1e8 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -247,7 +247,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_val);
int omap2_clk_enable_autoidle_all(void);
-void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
const char *core_ck_name,
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index f8ae4b5..7eb6f2b 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -2,6 +2,7 @@ ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
composite.o mux.o apll.o
+obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5)+= clk-54xx.o
obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
new file mode 100644
index 000..776ee45
--- /dev/null
+++ b/drivers/clk/ti/clk-33xx.c
@@ -0,0 +1,161 @@
+/*
+ * AM33XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kri...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/list.h
+#include linux/clk-provider.h
+#include linux/clk/ti.h
+
+static struct ti_dt_clk am33xx_clks[] = {
+ DT_CLK(NULL, clk_32768_ck, clk_32768_ck),
+ DT_CLK(NULL, clk_rc32k_ck, clk_rc32k_ck),
+ DT_CLK(NULL, virt_1920_ck, virt_1920_ck),
+ DT_CLK(NULL, virt_2400_ck, virt_2400_ck),
+ DT_CLK(NULL, virt_2500_ck, virt_2500_ck),
+ DT_CLK(NULL, virt_2600_ck, virt_2600_ck),
+ DT_CLK(NULL, sys_clkin_ck, sys_clkin_ck),
+ DT_CLK(NULL, tclkin_ck, tclkin_ck),
+ DT_CLK(NULL, dpll_core_ck, dpll_core_ck),
+ DT_CLK(NULL, dpll_core_x2_ck, dpll_core_x2_ck),
+ DT_CLK(NULL, dpll_core_m4_ck, dpll_core_m4_ck),
+ DT_CLK(NULL, dpll_core_m5_ck, dpll_core_m5_ck),
+ DT_CLK(NULL, dpll_core_m6_ck, dpll_core_m6_ck),
+ DT_CLK(NULL, dpll_mpu_ck, dpll_mpu_ck),
+ DT_CLK(cpu0, NULL, dpll_mpu_ck),
+ DT_CLK(NULL, dpll_mpu_m2_ck, dpll_mpu_m2_ck),
+ DT_CLK(NULL, dpll_ddr_ck, dpll_ddr_ck),
+ DT_CLK(NULL, dpll_ddr_m2_ck, dpll_ddr_m2_ck),
+ DT_CLK(NULL, dpll_ddr_m2_div2_ck, dpll_ddr_m2_div2_ck),
+ DT_CLK(NULL, dpll_disp_ck, dpll_disp_ck),
+ DT_CLK(NULL, dpll_disp_m2_ck, dpll_disp_m2_ck),
+ DT_CLK(NULL, dpll_per_ck, dpll_per_ck),
+ DT_CLK(NULL, dpll_per_m2_ck, dpll_per_m2_ck),
+ DT_CLK(NULL, dpll_per_m2_div4_wkupdm_ck,
dpll_per_m2_div4_wkupdm_ck),
+ DT_CLK(NULL, dpll_per_m2_div4_ck, dpll_per_m2_div4_ck),
+ DT_CLK(NULL, adc_tsc_fck, adc_tsc_fck),
+ DT_CLK(NULL, cefuse_fck, cefuse_fck),
+ DT_CLK(NULL, clkdiv32k_ck, clkdiv32k_ck),
+ DT_CLK(NULL, clkdiv32k_ick, clkdiv32k_ick),
+ DT_CLK(NULL, dcan0_fck, dcan0_fck),
+ DT_CLK(481cc000.d_can, NULL, dcan0_fck),
+ DT_CLK(NULL, dcan1_fck, dcan1_fck),
+ DT_CLK(481d.d_can, NULL, dcan1_fck),
+ DT_CLK(NULL, pruss_ocp_gclk, pruss_ocp_gclk),
+ DT_CLK(NULL, mcasp0_fck, mcasp0_fck),
+ DT_CLK(NULL, mcasp1_fck, mcasp1_fck),
+ DT_CLK(NULL, mmu_fck, mmu_fck),
+ DT_CLK(NULL, smartreflex0_fck, smartreflex0_fck),
+ DT_CLK(NULL, smartreflex1_fck, smartreflex1_fck),
+ DT_CLK(NULL, sha0_fck, sha0_fck),
+
[PATCHv9 22/43] CLK: TI: add am43xx clock init file
clk-43xx.c now contains the clock init functionality for am43xx, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/clk/ti/Makefile |2 +-
drivers/clk/ti/clk-43xx.c | 118 +
include/linux/clk/ti.h|1 +
3 files changed, 120 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk-43xx.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index ab386c8..007c3c2 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,7 +1,7 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
- composite.o mux.o apll.o
+ composite.o mux.o apll.o clk-43xx.o
obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o
obj-$(CONFIG_ARCH_OMAP3) += interface.o clk-3xxx.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
new file mode 100644
index 000..67c8de5
--- /dev/null
+++ b/drivers/clk/ti/clk-43xx.c
@@ -0,0 +1,118 @@
+/*
+ * AM43XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kri...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/list.h
+#include linux/clk-provider.h
+#include linux/clk/ti.h
+
+static struct ti_dt_clk am43xx_clks[] = {
+ DT_CLK(NULL, clk_32768_ck, clk_32768_ck),
+ DT_CLK(NULL, clk_rc32k_ck, clk_rc32k_ck),
+ DT_CLK(NULL, virt_1920_ck, virt_1920_ck),
+ DT_CLK(NULL, virt_2400_ck, virt_2400_ck),
+ DT_CLK(NULL, virt_2500_ck, virt_2500_ck),
+ DT_CLK(NULL, virt_2600_ck, virt_2600_ck),
+ DT_CLK(NULL, sys_clkin_ck, sys_clkin_ck),
+ DT_CLK(NULL, tclkin_ck, tclkin_ck),
+ DT_CLK(NULL, dpll_core_ck, dpll_core_ck),
+ DT_CLK(NULL, dpll_core_x2_ck, dpll_core_x2_ck),
+ DT_CLK(NULL, dpll_core_m4_ck, dpll_core_m4_ck),
+ DT_CLK(NULL, dpll_core_m5_ck, dpll_core_m5_ck),
+ DT_CLK(NULL, dpll_core_m6_ck, dpll_core_m6_ck),
+ DT_CLK(NULL, dpll_mpu_ck, dpll_mpu_ck),
+ DT_CLK(NULL, dpll_mpu_m2_ck, dpll_mpu_m2_ck),
+ DT_CLK(NULL, dpll_ddr_ck, dpll_ddr_ck),
+ DT_CLK(NULL, dpll_ddr_m2_ck, dpll_ddr_m2_ck),
+ DT_CLK(NULL, dpll_disp_ck, dpll_disp_ck),
+ DT_CLK(NULL, dpll_disp_m2_ck, dpll_disp_m2_ck),
+ DT_CLK(NULL, dpll_per_ck, dpll_per_ck),
+ DT_CLK(NULL, dpll_per_m2_ck, dpll_per_m2_ck),
+ DT_CLK(NULL, dpll_per_m2_div4_wkupdm_ck,
dpll_per_m2_div4_wkupdm_ck),
+ DT_CLK(NULL, dpll_per_m2_div4_ck, dpll_per_m2_div4_ck),
+ DT_CLK(NULL, adc_tsc_fck, adc_tsc_fck),
+ DT_CLK(NULL, clkdiv32k_ck, clkdiv32k_ck),
+ DT_CLK(NULL, clkdiv32k_ick, clkdiv32k_ick),
+ DT_CLK(NULL, dcan0_fck, dcan0_fck),
+ DT_CLK(NULL, dcan1_fck, dcan1_fck),
+ DT_CLK(NULL, pruss_ocp_gclk, pruss_ocp_gclk),
+ DT_CLK(NULL, mcasp0_fck, mcasp0_fck),
+ DT_CLK(NULL, mcasp1_fck, mcasp1_fck),
+ DT_CLK(NULL, smartreflex0_fck, smartreflex0_fck),
+ DT_CLK(NULL, smartreflex1_fck, smartreflex1_fck),
+ DT_CLK(NULL, sha0_fck, sha0_fck),
+ DT_CLK(NULL, aes0_fck, aes0_fck),
+ DT_CLK(NULL, timer1_fck, timer1_fck),
+ DT_CLK(NULL, timer2_fck, timer2_fck),
+ DT_CLK(NULL, timer3_fck, timer3_fck),
+ DT_CLK(NULL, timer4_fck, timer4_fck),
+ DT_CLK(NULL, timer5_fck, timer5_fck),
+ DT_CLK(NULL, timer6_fck, timer6_fck),
+ DT_CLK(NULL, timer7_fck, timer7_fck),
+ DT_CLK(NULL, wdt1_fck, wdt1_fck),
+ DT_CLK(NULL, l3_gclk, l3_gclk),
+ DT_CLK(NULL, dpll_core_m4_div2_ck, dpll_core_m4_div2_ck),
+ DT_CLK(NULL, l4hs_gclk, l4hs_gclk),
+ DT_CLK(NULL, l3s_gclk, l3s_gclk),
+ DT_CLK(NULL, l4ls_gclk, l4ls_gclk),
+ DT_CLK(NULL, clk_24mhz, clk_24mhz),
+ DT_CLK(NULL, cpsw_125mhz_gclk, cpsw_125mhz_gclk),
+ DT_CLK(NULL, cpsw_cpts_rft_clk, cpsw_cpts_rft_clk),
+ DT_CLK(NULL, gpio0_dbclk_mux_ck, gpio0_dbclk_mux_ck),
+ DT_CLK(NULL, gpio0_dbclk, gpio0_dbclk),
+ DT_CLK(NULL, gpio1_dbclk, gpio1_dbclk),
+ DT_CLK(NULL, gpio2_dbclk, gpio2_dbclk),
+ DT_CLK(NULL, gpio3_dbclk, gpio3_dbclk),
+ DT_CLK(NULL, gpio4_dbclk, gpio4_dbclk),
+
[PATCHv9 12/43] CLK: TI: add support for clockdomain binding
Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/clockdomain.txt | 21 +++
arch/arm/mach-omap2/clock.h|1 -
drivers/clk/ti/Makefile|3 +-
drivers/clk/ti/clockdomain.c | 58
include/linux/clk/ti.h |3 +
5 files changed, 84 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/clockdomain.txt
create mode 100644 drivers/clk/ti/clockdomain.c
diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
new file mode 100644
index 000..45e6f7c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
@@ -0,0 +1,21 @@
+Binding for Texas Instruments clockdomain.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. Every clock on
+TI SoC belongs to one clockdomain, but software only needs this
+information for specific clocks which require their parent
+clockdomain to be controlled when the clock is enabled/disabled.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be ti,clockdomain
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of clocks within this domain
+
+Examples:
+ dss_clkdm: dss_clkdm {
+ compatible = ti,clockdomain;
+ clocks = dss1_alwon_fck_3430es2, dss_ick_3430es2;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 08b3360..8be0279 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -38,7 +38,6 @@ struct omap_clk {
}
struct clockdomain;
-#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
static struct clk _name = { \
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 7cba389..67056fb 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,5 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
- fixed-factor.o gate.o composite.o
+ fixed-factor.o gate.o clockdomain.o \
+ composite.o
endif
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
new file mode 100644
index 000..1b3099e
--- /dev/null
+++ b/drivers/clk/ti/clockdomain.c
@@ -0,0 +1,58 @@
+/*
+ * OMAP clockdomain support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo t-kri...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk-provider.h
+#include linux/slab.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk/ti.h
+
+static void __init of_ti_clockdomain_setup(struct device_node *node)
+{
+ struct clk *clk;
+ struct clk_hw *clk_hw;
+ const char *clkdm_name = node-name;
+ int i;
+ int num_clks;
+
+ num_clks = of_count_phandle_with_args(node, clocks, #clock-cells);
+
+ for (i = 0; i num_clks; i++) {
+ clk = of_clk_get(node, i);
+ if (__clk_get_flags(clk) CLK_IS_BASIC) {
+ pr_warn(%s: can't setup clkdm for basic clk %s\n,
+ __func__, __clk_get_name(clk));
+ continue;
+ }
+ clk_hw = __clk_get_hw(clk);
+ to_clk_hw_omap(clk_hw)-clkdm_name = clkdm_name;
+ omap2_init_clk_clkdm(clk_hw);
+ }
+}
+
+static struct of_device_id ti_clkdm_match_table[] __initdata = {
+ { .compatible = ti,clockdomain },
+ { }
+};
+
+void __init ti_dt_clockdomains_setup(void)
+{
+ struct device_node *np;
+ for_each_matching_node(np, ti_clkdm_match_table) {
+ of_ti_clockdomain_setup(np);
+ }
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 29baca8..70446fb 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -190,6 +190,8 @@ struct ti_dt_clk {
.node_name = name, \
[PATCHv9 11/43] CLK: TI: add support for gate clock
This patch adds support for TI specific gate clocks. These behave as basic
gate-clock, but have different ops / hw-ops for controlling the actual
gate, for example waiting until the clock is ready. Several sub-types
are supported:
- ti,gate-clock: basic gate clock with default ops/hwops
- ti,clkdm-gate-clock: clockdomain level gate control
- ti,dss-gate-clock: gate clock with DSS specific hardware handling
- ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling
- ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/gate.txt | 77 ++
arch/arm/mach-omap2/clock.h| 29 ---
drivers/clk/ti/Makefile|2 +-
drivers/clk/ti/gate.c | 258
include/linux/clk/ti.h | 36 +++
5 files changed, 372 insertions(+), 30 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
create mode 100644 drivers/clk/ti/gate.c
diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt
b/Documentation/devicetree/bindings/clock/ti/gate.txt
new file mode 100644
index 000..18c4d86
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
@@ -0,0 +1,77 @@
+Binding for Texas Instruments gate clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features. If no register
+is provided for this clock, the code assumes that a clockdomain
+will be controlled instead and the corresponding hw-ops for
+that is used.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
+
+Required properties:
+- compatible : shall be one of:
+ ti,gate-clock - basic gate clock
+ ti,wait-gate-clock - gate clock which waits until clock is active before
+returning from clk_enable()
+ ti,dss-gate-clock - gate clock with DSS specific hardware handling
+ ti,am35xx-gate-clock - gate clock with AM35xx specific hardware handling
+ ti,clkdm-gate-clock - clockdomain gate clock, which derives its functional
+ clock directly from a clockdomain, see [3] how
+ to map clockdomains properly
+ ti,hsdiv-gate-clock - gate clock with OMAP36xx specific hardware handling,
+ required for a hardware errata
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : offset for register controlling adjustable gate, not needed for
+ ti,clkdm-gate-clock type
+- ti,bit-shift : bit shift for programming the clock gate, not needed for
+ti,clkdm-gate-clock type
+
+Optional properties:
+- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
+ gates the clock and clearing the bit ungates the clock.
+
+Examples:
+ mmchs2_fck: mmchs2_fck@48004a00 {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = core_96m_fck;
+ reg = 0x48004a00 0x4;
+ ti,bit-shift = 25;
+ };
+
+ dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
+ #clock-cells = 0;
+ compatible = ti,dss-gate-clock;
+ clocks = dpll4_m4x2_ck;
+ reg = 0x48004e00 0x4;
+ ti,bit-shift = 0;
+ };
+
+ emac_ick: emac_ick@4800259c {
+ #clock-cells = 0;
+ compatible = ti,am35xx-gate-clock;
+ clocks = ipss_ick;
+ reg = 0x4800259c 0x4;
+ ti,bit-shift = 1;
+ };
+
+ emu_src_ck: emu_src_ck {
+ #clock-cells = 0;
+ compatible = ti,clkdm-gate-clock;
+ clocks = emu_src_mux_ck;
+ };
+
+ dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
+ #clock-cells = 0;
+ compatible = ti,hsdiv-gate-clock;
+ clocks = dpll4_m2x2_mul_ck;
+ ti,bit-shift = 0x1b;
+ reg = 0x48004d00 0x4;
+ ti,set-bit-to-disable;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 079536a..08b3360 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -179,25 +179,6 @@ struct clksel {
const struct clksel_rate *rates;
};
-/*
- * struct clk.flags possibilities
- *
- * XXX document the rest of the clock flags here
- *
- * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
- * bits share the same register. This flag allows the
- * omap4_dpllmx*() code to determine which GATE_CTRL bit field
- * should
[PATCHv9 14/43] CLK: TI: add omap4 clock init file
clk-44xx.c now contains the clock init functionality for omap4, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/clock.h |1 -
drivers/clk/ti/Makefile |1 +
drivers/clk/ti/clk-44xx.c | 328 +++
include/linux/clk/ti.h |3 +
4 files changed, 332 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk-44xx.c
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 8be0279..2a52da2 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -247,7 +247,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_val);
int omap2_clk_enable_autoidle_all(void);
-int omap2_clk_disable_autoidle_all(void);
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index ef61d39..381f1f8 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -2,4 +2,5 @@ ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
composite.o mux.o
+obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
endif
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
new file mode 100644
index 000..3e2090b
--- /dev/null
+++ b/drivers/clk/ti/clk-44xx.c
@@ -0,0 +1,328 @@
+/*
+ * OMAP4 Clock data
+ *
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (p...@pwsan.com)
+ * Rajendra Nayak (rna...@ti.com)
+ * Benoit Cousson (b-cous...@ti.com)
+ * Mike Turquette (mturque...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
+ *
+ * XXX All of the remaining MODULEMODE clock nodes should be removed
+ * once the drivers are updated to use pm_runtime or to use the appropriate
+ * upstream clock node for rate/parent selection.
+ */
+
+#include linux/kernel.h
+#include linux/list.h
+#include linux/clk-private.h
+#include linux/clkdev.h
+#include linux/clk/ti.h
+
+/*
+ * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
+ * 3.6.3.2.3 CM1_ABE Clock Generator states that the DPLL_ABE_X2_CLK
+ * must be set to 196.608 MHz and hence, the DPLL locked frequency is
+ * half of this value.
+ */
+#define OMAP4_DPLL_ABE_DEFFREQ 98304000
+
+/*
+ * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
+ * 3.6.3.9.5 DPLL_USB Preferred Settings shows that the preferred
+ * locked frequency for the USB DPLL is 960MHz.
+ */
+#define OMAP4_DPLL_USB_DEFFREQ 96000
+
+static struct ti_dt_clk omap44xx_clks[] = {
+ DT_CLK(NULL, extalt_clkin_ck, extalt_clkin_ck),
+ DT_CLK(NULL, pad_clks_src_ck, pad_clks_src_ck),
+ DT_CLK(NULL, pad_clks_ck, pad_clks_ck),
+ DT_CLK(NULL, pad_slimbus_core_clks_ck, pad_slimbus_core_clks_ck),
+ DT_CLK(NULL, secure_32k_clk_src_ck, secure_32k_clk_src_ck),
+ DT_CLK(NULL, slimbus_src_clk, slimbus_src_clk),
+ DT_CLK(NULL, slimbus_clk, slimbus_clk),
+ DT_CLK(NULL, sys_32k_ck, sys_32k_ck),
+ DT_CLK(NULL, virt_1200_ck, virt_1200_ck),
+ DT_CLK(NULL, virt_1300_ck, virt_1300_ck),
+ DT_CLK(NULL, virt_1680_ck, virt_1680_ck),
+ DT_CLK(NULL, virt_1920_ck, virt_1920_ck),
+ DT_CLK(NULL, virt_2600_ck, virt_2600_ck),
+ DT_CLK(NULL, virt_2700_ck, virt_2700_ck),
+ DT_CLK(NULL, virt_3840_ck, virt_3840_ck),
+ DT_CLK(NULL, sys_clkin_ck, sys_clkin_ck),
+ DT_CLK(NULL, tie_low_clock_ck, tie_low_clock_ck),
+ DT_CLK(NULL, utmi_phy_clkout_ck, utmi_phy_clkout_ck),
+ DT_CLK(NULL, xclk60mhsp1_ck, xclk60mhsp1_ck),
+ DT_CLK(NULL, xclk60mhsp2_ck, xclk60mhsp2_ck),
+ DT_CLK(NULL, xclk60motg_ck, xclk60motg_ck),
+ DT_CLK(NULL, abe_dpll_bypass_clk_mux_ck,
abe_dpll_bypass_clk_mux_ck),
+ DT_CLK(NULL, abe_dpll_refclk_mux_ck, abe_dpll_refclk_mux_ck),
+ DT_CLK(NULL, dpll_abe_ck, dpll_abe_ck),
+ DT_CLK(NULL, dpll_abe_x2_ck, dpll_abe_x2_ck),
+ DT_CLK(NULL, dpll_abe_m2x2_ck, dpll_abe_m2x2_ck),
+ DT_CLK(NULL, abe_24m_fclk,
[PATCHv9 18/43] CLK: TI: add dra7 clock init file
clk-7xx.c now contains the clock init functionality for dra7, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/clk/ti/Makefile |1 +
drivers/clk/ti/clk-7xx.c | 332 ++
include/linux/clk/ti.h |1 +
3 files changed, 334 insertions(+)
create mode 100644 drivers/clk/ti/clk-7xx.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 3d71e1e..f8ae4b5 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -4,4 +4,5 @@ obj-y += clk.o dpll.o
autoidle.o divider.o \
composite.o mux.o apll.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5)+= clk-54xx.o
+obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o
endif
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
new file mode 100644
index 000..9977653
--- /dev/null
+++ b/drivers/clk/ti/clk-7xx.c
@@ -0,0 +1,332 @@
+/*
+ * DRA7 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kri...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/list.h
+#include linux/clk-private.h
+#include linux/clkdev.h
+#include linux/clk/ti.h
+
+#define DRA7_DPLL_ABE_DEFFREQ 361267200
+#define DRA7_DPLL_GMAC_DEFFREQ 10
+
+
+static struct ti_dt_clk dra7xx_clks[] = {
+ DT_CLK(NULL, atl_clkin0_ck, atl_clkin0_ck),
+ DT_CLK(NULL, atl_clkin1_ck, atl_clkin1_ck),
+ DT_CLK(NULL, atl_clkin2_ck, atl_clkin2_ck),
+ DT_CLK(NULL, atlclkin3_ck, atlclkin3_ck),
+ DT_CLK(NULL, hdmi_clkin_ck, hdmi_clkin_ck),
+ DT_CLK(NULL, mlb_clkin_ck, mlb_clkin_ck),
+ DT_CLK(NULL, mlbp_clkin_ck, mlbp_clkin_ck),
+ DT_CLK(NULL, pciesref_acs_clk_ck, pciesref_acs_clk_ck),
+ DT_CLK(NULL, ref_clkin0_ck, ref_clkin0_ck),
+ DT_CLK(NULL, ref_clkin1_ck, ref_clkin1_ck),
+ DT_CLK(NULL, ref_clkin2_ck, ref_clkin2_ck),
+ DT_CLK(NULL, ref_clkin3_ck, ref_clkin3_ck),
+ DT_CLK(NULL, rmii_clk_ck, rmii_clk_ck),
+ DT_CLK(NULL, sdvenc_clkin_ck, sdvenc_clkin_ck),
+ DT_CLK(NULL, secure_32k_clk_src_ck, secure_32k_clk_src_ck),
+ DT_CLK(NULL, sys_32k_ck, sys_32k_ck),
+ DT_CLK(NULL, virt_1200_ck, virt_1200_ck),
+ DT_CLK(NULL, virt_1300_ck, virt_1300_ck),
+ DT_CLK(NULL, virt_1680_ck, virt_1680_ck),
+ DT_CLK(NULL, virt_1920_ck, virt_1920_ck),
+ DT_CLK(NULL, virt_2000_ck, virt_2000_ck),
+ DT_CLK(NULL, virt_2600_ck, virt_2600_ck),
+ DT_CLK(NULL, virt_2700_ck, virt_2700_ck),
+ DT_CLK(NULL, virt_3840_ck, virt_3840_ck),
+ DT_CLK(NULL, sys_clkin1, sys_clkin1),
+ DT_CLK(NULL, sys_clkin2, sys_clkin2),
+ DT_CLK(NULL, usb_otg_clkin_ck, usb_otg_clkin_ck),
+ DT_CLK(NULL, video1_clkin_ck, video1_clkin_ck),
+ DT_CLK(NULL, video1_m2_clkin_ck, video1_m2_clkin_ck),
+ DT_CLK(NULL, video2_clkin_ck, video2_clkin_ck),
+ DT_CLK(NULL, video2_m2_clkin_ck, video2_m2_clkin_ck),
+ DT_CLK(NULL, abe_dpll_sys_clk_mux, abe_dpll_sys_clk_mux),
+ DT_CLK(NULL, abe_dpll_bypass_clk_mux, abe_dpll_bypass_clk_mux),
+ DT_CLK(NULL, abe_dpll_clk_mux, abe_dpll_clk_mux),
+ DT_CLK(NULL, dpll_abe_ck, dpll_abe_ck),
+ DT_CLK(NULL, dpll_abe_x2_ck, dpll_abe_x2_ck),
+ DT_CLK(NULL, dpll_abe_m2x2_ck, dpll_abe_m2x2_ck),
+ DT_CLK(NULL, abe_24m_fclk, abe_24m_fclk),
+ DT_CLK(NULL, abe_clk, abe_clk),
+ DT_CLK(NULL, aess_fclk, aess_fclk),
+ DT_CLK(NULL, abe_giclk_div, abe_giclk_div),
+ DT_CLK(NULL, abe_lp_clk_div, abe_lp_clk_div),
+ DT_CLK(NULL, abe_sys_clk_div, abe_sys_clk_div),
+ DT_CLK(NULL, adc_gfclk_mux, adc_gfclk_mux),
+ DT_CLK(NULL, dpll_pcie_ref_ck, dpll_pcie_ref_ck),
+ DT_CLK(NULL, dpll_pcie_ref_m2ldo_ck, dpll_pcie_ref_m2ldo_ck),
+ DT_CLK(NULL, apll_pcie_ck, apll_pcie_ck),
+ DT_CLK(NULL, apll_pcie_clkvcoldo, apll_pcie_clkvcoldo),
+ DT_CLK(NULL, apll_pcie_clkvcoldo_div, apll_pcie_clkvcoldo_div),
+ DT_CLK(NULL, apll_pcie_m2_ck, apll_pcie_m2_ck),
+ DT_CLK(NULL, sys_clk1_dclk_div, sys_clk1_dclk_div),
+ DT_CLK(NULL, sys_clk2_dclk_div, sys_clk2_dclk_div),
+ DT_CLK(NULL, dpll_abe_m2_ck, dpll_abe_m2_ck),
+ DT_CLK(NULL, per_abe_x1_dclk_div, per_abe_x1_dclk_div),
+ DT_CLK(NULL, dpll_abe_m3x2_ck, dpll_abe_m3x2_ck),
+ DT_CLK(NULL, dpll_core_ck, dpll_core_ck),
+ DT_CLK(NULL, dpll_core_x2_ck, dpll_core_x2_ck),
+ DT_CLK(NULL, dpll_core_h12x2_ck,
[PATCHv9 30/43] ARM: dts: am33xx clock data
This patch creates a unique node for each clock in the AM33xx power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/am33xx-clocks.dtsi | 672 ++
arch/arm/boot/dts/am33xx.dtsi|2 +
2 files changed, 674 insertions(+)
create mode 100644 arch/arm/boot/dts/am33xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi
b/arch/arm/boot/dts/am33xx-clocks.dtsi
new file mode 100644
index 000..4f70931
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -0,0 +1,672 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+scrm: scrm@44e1 {
+ compatible = ti,scrm;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x44e1 0x2000;
+
+ sys_clkin_ck: sys_clkin_ck {
+ #clock-cells = 0;
+ compatible = ti,mux-clock;
+ clocks = virt_1920_ck, virt_2400_ck,
virt_2500_ck, virt_2600_ck;
+ ti,bit-shift = 22;
+ reg = 0x0040;
+ };
+
+ adc_tsc_fck: adc_tsc_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ dcan0_fck: dcan0_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ dcan1_fck: dcan1_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ mcasp0_fck: mcasp0_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ mcasp1_fck: mcasp1_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ smartreflex0_fck: smartreflex0_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ smartreflex1_fck: smartreflex1_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ sha0_fck: sha0_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ aes0_fck: aes0_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ rng_fck: rng_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-no-wait-gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 0;
+ reg = 0x0664;
+ };
+
+ ehrpwm0_tbclk: ehrpwm0_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-clock;
+ clocks = ehrpwm0_gate_tbclk;
+ };
+
+ ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-no-wait-gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 1;
+ reg = 0x0664;
+ };
+
+ ehrpwm1_tbclk: ehrpwm1_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-clock;
+ clocks = ehrpwm1_gate_tbclk;
+ };
+
+ ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-no-wait-gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 2;
+ reg = 0x0664;
+ };
+
+ ehrpwm2_tbclk: ehrpwm2_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-clock;
+ clocks = ehrpwm2_gate_tbclk;
+ };
+};
+prcm: prcm@44e0 {
+
[PATCHv9 32/43] ARM: dts: AM35xx: use DT clock data
AM35xx now uses the clock data from device tree. Most of the data is
shared with OMAP3xxx, but as there is some delta, a new base .dtsi
file is also created for the SoC.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/am3517-evm.dts|2 +-
arch/arm/boot/dts/am3517.dtsi | 31 +++
arch/arm/boot/dts/am3517_mt_ventoux.dts |2 +-
3 files changed, 33 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/am3517.dtsi
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index e99dfaf..9ff51d7 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-#include omap34xx.dtsi
+#include am3517.dtsi
/ {
model = TI AM3517 EVM (AM3517/05);
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
new file mode 100644
index 000..c555443
--- /dev/null
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Device Tree Source for AM3517 SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed as is without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include omap3.dtsi
+
+/ {
+ cpus {
+ cpu@0 {
+ /* OMAP343x/OMAP35xx variants OPP1-5 */
+ operating-points =
+ /* kHzuV */
+ 125000 975000
+ 25 1075000
+ 50 120
+ 55 127
+ 60 135
+ ;
+ clock-latency = 30; /* From legacy driver */
+ };
+ };
+};
+
+/include/ am35xx-clocks.dtsi
+/include/ omap36xx-am35xx-omap3430es2plus-clocks.dtsi
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts
b/arch/arm/boot/dts/am3517_mt_ventoux.dts
index fdf5ce6..d00e934 100644
--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-#include omap34xx.dtsi
+#include am3517.dtsi
/ {
model = TeeJet Mt.Ventoux;
--
1.7.9.5
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[PATCHv9 36/43] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm
If the main clock for a hwmod is of basic clock type, it is illegal to type
cast this to clk_hw_omap and will result in bogus data. Fixed by checking
the clock flags before attempting the type cast.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/omap_hwmod.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index d35145d..5f8f587 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -656,6 +656,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
if (oh-clkdm) {
return oh-clkdm;
} else if (oh-_clk) {
+ if (__clk_get_flags(oh-_clk) CLK_IS_BASIC)
+ return NULL;
clk = to_clk_hw_omap(__clk_get_hw(oh-_clk));
return clk-clkdm;
}
--
1.7.9.5
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[PATCHv9 38/43] ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT
This patch provides top level functionality for the DT clock initialization.
Clock tree is initialized hierarchically starting from IP modules (CM/PRM/PRCM)
going down towards individual clock nodes, and finally initializing
clockdomains once all the clocks are ready.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/prm.h|1 +
arch/arm/mach-omap2/prm_common.c | 133 ++
2 files changed, 134 insertions(+)
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ac25ae6..623db40 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -18,6 +18,7 @@
# ifndef __ASSEMBLER__
extern void __iomem *prm_base;
extern void omap2_set_globals_prm(void __iomem *prm);
+int of_prcm_init(void);
# endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 228b850..6fa74c6 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -23,12 +23,18 @@
#include linux/irq.h
#include linux/interrupt.h
#include linux/slab.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk-provider.h
+#include linux/clk/ti.h
+#include linux/of_platform.h
#include prm2xxx_3xxx.h
#include prm2xxx.h
#include prm3xxx.h
#include prm44xx.h
#include common.h
+#include soc.h
/*
* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -453,3 +459,130 @@ int prm_unregister(struct prm_ll_data *pld)
return 0;
}
+
+static struct of_device_id omap_prcm_dt_match_table[] __initdata = {
+ { .compatible = ti,prcm },
+ { .compatible = ti,prm },
+ { .compatible = ti,cm },
+ { .compatible = ti,cm2 },
+ { .compatible = ti,scrm },
+ { }
+};
+
+
+/*
+ * XXX: implementation for the regmap read/write should be moved to
+ * individual PRCM IP drivers, once those are available.
+ */
+static int ti_clk_regmap_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+ void __iomem *mem = context;
+ *val = __raw_readl(mem + reg);
+ return 0;
+}
+
+static int ti_clk_regmap_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ void __iomem *mem = context;
+ __raw_writel(val, mem + reg);
+ return 0;
+}
+
+static struct regmap_config ti_clk_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .reg_read = ti_clk_regmap_read,
+ .reg_write = ti_clk_regmap_write,
+ .fast_io = true,
+ .cache_type = REGCACHE_NONE,
+ .reg_format_endian = REGMAP_ENDIAN_NATIVE,
+ .val_format_endian = REGMAP_ENDIAN_NATIVE,
+};
+
+static LIST_HEAD(prcm_early_devs);
+
+struct prcm_early_dev {
+ struct device_node *node;
+ struct platform_device *dev;
+ struct list_head link;
+};
+
+int __init of_prcm_init(void)
+{
+ struct device_node *np;
+ void __iomem *mem;
+ struct regmap *regmap;
+ struct platform_device *pdev;
+ struct prcm_early_dev *edev;
+
+ for_each_matching_node(np, omap_prcm_dt_match_table) {
+ pdev = platform_device_alloc(np-name, 0);
+ dev_set_name(pdev-dev, %s, pdev-name);
+ edev = kzalloc(sizeof(*edev), GFP_KERNEL);
+ edev-dev = pdev;
+ edev-node = np;
+ list_add(edev-link, prcm_early_devs);
+ mem = of_iomap(np, 0);
+ ti_clk_regmap_config.name = 0;
+ regmap = regmap_init(pdev-dev, NULL, mem,
+ti_clk_regmap_config);
+ ti_dt_clk_init_provider(np, regmap);
+ }
+
+ ti_dt_clockdomains_setup();
+
+ return 0;
+}
+
+static int prcm_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *of_id =
+ of_match_device(omap_prcm_dt_match_table, pdev-dev);
+ struct prcm_early_dev *edev;
+ int ret;
+
+ if (!of_id)
+ return 0;
+
+ list_for_each_entry(edev, prcm_early_devs, link) {
+ if (edev-node == pdev-dev.of_node) {
+ platform_device_add(edev-dev);
+ edev-dev-dev.driver = pdev-dev.driver;
+ ret = device_bind_driver(edev-dev-dev);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int prcm_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static struct platform_driver prcm_driver = {
+ .probe = prcm_probe,
+ .remove = prcm_remove,
+ .driver = {
+ .name = prcm-driver,
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(omap_prcm_dt_match_table),
+ },
+};
+
+static __init int prcm_init(void)
+{
+ return platform_driver_register(prcm_driver);
+}
+
+static __exit void
[PATCHv9 24/43] ARM: dts: omap5 clock data
This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/omap5.dtsi |2 +
arch/arm/boot/dts/omap54xx-clocks.dtsi | 1416
2 files changed, 1418 insertions(+)
create mode 100644 arch/arm/boot/dts/omap54xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index eeaa5ed..8c9cee4 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -107,6 +107,8 @@
interrupts = GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
+ /include/ omap54xx-clocks.dtsi
+
counter32k: counter@4ae04000 {
compatible = ti,omap-counter32k;
reg = 0x4ae04000 0x40;
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi
b/arch/arm/boot/dts/omap54xx-clocks.dtsi
new file mode 100644
index 000..7301852
--- /dev/null
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -0,0 +1,1416 @@
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+cm_core_aon: cm_core_aon@4a004000 {
+ compatible = ti,cm;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x4a004000 0x2000;
+
+ pad_clks_src_ck: pad_clks_src_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 1200;
+ };
+
+ pad_clks_ck: pad_clks_ck {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = pad_clks_src_ck;
+ ti,bit-shift = 8;
+ reg = 0x0108;
+ };
+
+ secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 32768;
+ };
+
+ slimbus_src_clk: slimbus_src_clk {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 1200;
+ };
+
+ slimbus_clk: slimbus_clk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = slimbus_src_clk;
+ ti,bit-shift = 10;
+ reg = 0x0108;
+ };
+
+ sys_32k_ck: sys_32k_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 32768;
+ };
+
+ virt_1200_ck: virt_1200_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 1200;
+ };
+
+ virt_1300_ck: virt_1300_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 1300;
+ };
+
+ virt_1680_ck: virt_1680_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 1680;
+ };
+
+ virt_1920_ck: virt_1920_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 1920;
+ };
+
+ virt_2600_ck: virt_2600_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 2600;
+ };
+
+ virt_2700_ck: virt_2700_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 2700;
+ };
+
+ virt_3840_ck: virt_3840_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 3840;
+ };
+
+ xclk60mhsp1_ck: xclk60mhsp1_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 6000;
+ };
+
+ xclk60mhsp2_ck: xclk60mhsp2_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 6000;
+ };
+
+ dpll_abe_ck: dpll_abe_ck {
+ #clock-cells = 0;
+ compatible = ti,omap4-dpll-m4xen-clock;
+ clocks = abe_dpll_clk_mux, abe_dpll_bypass_clk_mux;
+ reg = 0x01e0, 0x01e4, 0x01e8, 0x01ec;
+ };
+
+ dpll_abe_x2_ck: dpll_abe_x2_ck {
+ #clock-cells = 0;
+ compatible = ti,omap4-dpll-x2-clock;
+ clocks = dpll_abe_ck;
+ };
+
+ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+ #clock-cells = 0;
+ compatible = ti,divider-clock;
+ clocks = dpll_abe_x2_ck;
+ ti,max-div = 31;
+ ti,autoidle-shift = 8;
+
[PATCHv9 28/43] ARM: dts: DRA7: Add PCIe related clock nodes
From: J Keerthy j-keer...@ti.com
This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.
Signed-off-by: J Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 76955c1..5b7efc3 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1180,6 +1180,31 @@ cm_core: cm_core@4a008000 {
reg = 0x021c, 0x0220;
};
+ optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+ compatible = ti,divider-clock;
+ clocks = apll_pcie_ck;
+ #clock-cells = 0;
+ reg = 0x021c;
+ ti,bit-shift = 8;
+ ti,max-div = 2;
+ };
+
+ optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+ compatible = ti,gate-clock;
+ clocks = apll_pcie_ck;
+ #clock-cells = 0;
+ reg = 0x13b0;
+ ti,bit-shift = 9;
+ };
+
+ optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+ compatible = ti,gate-clock;
+ clocks = optfclk_pciephy_div;
+ #clock-cells = 0;
+ reg = 0x13b0;
+ ti,bit-shift = 10;
+ };
+
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = 0;
compatible = fixed-factor-clock;
--
1.7.9.5
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[PATCHv9 27/43] ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock
From: J Keerthy j-keer...@ti.com
This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.
Signed-off-by: J Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 1226921..76955c1 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1198,13 +1198,10 @@ cm_core: cm_core@4a008000 {
apll_pcie_m2_ck: apll_pcie_m2_ck {
#clock-cells = 0;
- compatible = ti,divider-clock;
+ compatible = fixed-factor-clock;
clocks = apll_pcie_ck;
- ti,max-div = 127;
- ti,autoidle-shift = 8;
- reg = 0x0224;
- ti,index-starts-at-one;
- ti,invert-autoidle-bit;
+ clock-mult = 1;
+ clock-div = 1;
};
dpll_per_ck: dpll_per_ck {
--
1.7.9.5
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[PATCHv9 16/43] CLK: TI: omap5: Initialize USB_DPLL at boot
From: Roger Quadros rog...@ti.com
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/clk/ti/clk-54xx.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index c876e6e..0ef9f58 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -19,6 +19,12 @@
#define OMAP5_DPLL_ABE_DEFFREQ 98304000
+/*
+ * OMAP543x TRM, section 3.6.3.9.5 DPLL_USB Preferred Settings
+ * states it must be at 960MHz
+ */
+#define OMAP5_DPLL_USB_DEFFREQ 96000
+
static struct ti_dt_clk omap54xx_clks[] = {
DT_CLK(NULL, pad_clks_src_ck, pad_clks_src_ck),
DT_CLK(NULL, pad_clks_ck, pad_clks_ck),
@@ -220,7 +226,7 @@ static struct ti_dt_clk omap54xx_clks[] = {
int __init omap5xxx_dt_clk_init(void)
{
int rc;
- struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+ struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
ti_dt_clocks_register(omap54xx_clks);
@@ -235,5 +241,15 @@ int __init omap5xxx_dt_clk_init(void)
if (rc)
pr_err(%s: failed to configure ABE DPLL!\n, __func__);
+ usb_dpll = clk_get_sys(NULL, dpll_usb_ck);
+ rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
+ if (rc)
+ pr_err(%s: failed to configure USB DPLL!\n, __func__);
+
+ usb_dpll = clk_get_sys(NULL, dpll_usb_m2_ck);
+ rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
+ if (rc)
+ pr_err(%s: failed to set USB_DPLL M2 OUT\n, __func__);
+
return 0;
}
--
1.7.9.5
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[PATCHv9 26/43] ARM: dts: clk: Add apll related clocks
From: J Keerthy j-keer...@ti.com
The patch adds a mux node to choose the parent of apll_pcie_ck node.
Signed-off-by: J Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index ba43e7d..1226921 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,11 +1165,19 @@ cm_core: cm_core@4a008000 {
ti,invert-autoidle-bit;
};
+ apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+ compatible = ti,mux-clock;
+ clocks = dpll_pcie_ref_ck, pciesref_acs_clk_ck;
+ #clock-cells = 0;
+ reg = 0x021c 0x4;
+ ti,bit-shift = 7;
+ };
+
apll_pcie_ck: apll_pcie_ck {
#clock-cells = 0;
- compatible = ti,omap4-dpll-clock;
- clocks = dpll_pcie_ref_ck, dpll_pcie_ref_ck;
- reg = 0x0200, 0x0204, 0x0208, 0x020c;
+ compatible = ti,dra7-apll-clock;
+ clocks = apll_pcie_in_clk_mux, dpll_pcie_ref_ck;
+ reg = 0x021c, 0x0220;
};
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
--
1.7.9.5
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[PATCHv9 37/43] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name
DT clocks are mostly missing clkdm info now, and this causes an issue with
counter32k which makes its slave idlemode wrong and prevents core idle.
Fixed by initializing the hwmod clkdm pointers for omap3 also which makes
sure the clkdm flag matching logic works properly.
This patch also changes the return value for _init_clkdm to 0 for
incorrect clkdm_name, as this a warning, not a fatal error.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/omap_hwmod.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5f8f587..ae33fae 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1546,7 +1546,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
if (!oh-clkdm) {
pr_warning(omap_hwmod: %s: could not associate to clkdm %s\n,
oh-name, oh-clkdm_name);
- return -EINVAL;
+ return 0;
}
pr_debug(omap_hwmod: %s: associated to clkdm %s\n,
@@ -4117,6 +4117,7 @@ void __init omap_hwmod_init(void)
soc_ops.assert_hardreset = _omap2_assert_hardreset;
soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+ soc_ops.init_clkdm = _init_clkdm;
} else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
soc_ops.enable_module = _omap4_enable_module;
soc_ops.disable_module = _omap4_disable_module;
--
1.7.9.5
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[PATCHv9 29/43] ARM: dts: DRA7: link in clock DT data
Clock tree DT data is now included from base dra7.dtsi file.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d0df4c4..bf7797e 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -104,6 +104,8 @@
interrupts = GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
+ /include/ dra7xx-clocks.dtsi
+
counter32k: counter@4ae04000 {
compatible = ti,omap-counter32k;
reg = 0x4ae04000 0x40;
--
1.7.9.5
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[PATCHv9 33/43] ARM: dts: am43xx clock data
This patch creates a unique node for each clock in the AM43xx power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/am4372.dtsi|2 +
arch/arm/boot/dts/am43xx-clocks.dtsi | 666 ++
2 files changed, 668 insertions(+)
create mode 100644 arch/arm/boot/dts/am43xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 974d103..1fb3ac2 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -67,6 +67,8 @@
ranges;
ti,hwmods = l3_main;
+ /include/ am43xx-clocks.dtsi
+
edma: edma@4900 {
compatible = ti,edma3;
ti,hwmods = tpcc, tptc0, tptc1, tptc2;
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi
b/arch/arm/boot/dts/am43xx-clocks.dtsi
new file mode 100644
index 000..1cc5071
--- /dev/null
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -0,0 +1,666 @@
+/*
+ * Device Tree Source for AM43xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+scrm: scrm@44e1 {
+ compatible = ti,scrm;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x44e1 0x2000;
+
+ sys_clkin_ck: sys_clkin_ck {
+ #clock-cells = 0;
+ compatible = ti,mux-clock;
+ clocks = virt_1920_ck, virt_2400_ck,
virt_2500_ck, virt_2600_ck;
+ ti,bit-shift = 22;
+ reg = 0x0040;
+ };
+
+ adc_tsc_fck: adc_tsc_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ dcan0_fck: dcan0_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ dcan1_fck: dcan1_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ mcasp0_fck: mcasp0_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ mcasp1_fck: mcasp1_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ smartreflex0_fck: smartreflex0_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ smartreflex1_fck: smartreflex1_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ sha0_fck: sha0_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ aes0_fck: aes0_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+};
+prcm: prcm@44df {
+ compatible = ti,prcm;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x44df 0x11000;
+
+ clk_32768_ck: clk_32768_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 32768;
+ };
+
+ clk_rc32k_ck: clk_rc32k_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 32768;
+ };
+
+ virt_1920_ck: virt_1920_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 1920;
+ };
+
+ virt_2400_ck: virt_2400_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 2400;
+ };
+
+ virt_2500_ck: virt_2500_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 2500;
+ };
+
+ virt_2600_ck: virt_2600_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+
[PATCHv9 41/43] ARM: OMAP: DRA7: Enable clock init
Initializes clock data from device tree. Signed-off-by: Tero Kristo t-kri...@ti.com Tested-by: Nishanth Menon n...@ti.com Acked-by: Tony Lindgren t...@atomide.com --- arch/arm/mach-omap2/io.c |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 22e0689..dd8c37b 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -671,6 +671,7 @@ void __init dra7xx_init_early(void) dra7xx_clockdomains_init(); dra7xx_hwmod_init(); omap_hwmod_init_postsetup(); + omap_clk_soc_init = dra7xx_dt_clk_init; } #endif -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv9 43/43] ARM: OMAP3: use DT clock init if DT data is available
OMAP3 platforms support both DT and non-DT boot at the moment, make
the clock init work according to the used setup.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/io.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index d7afb58..962cc04 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -488,21 +488,29 @@ void __init omap3_init_early(void)
void __init omap3430_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_soc_init = omap3430_dt_clk_init;
}
void __init omap35xx_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_soc_init = omap3430_dt_clk_init;
}
void __init omap3630_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_soc_init = omap3630_dt_clk_init;
}
void __init am35xx_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_soc_init = am35xx_dt_clk_init;
}
void __init ti81xx_init_early(void)
@@ -520,7 +528,10 @@ void __init ti81xx_init_early(void)
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
- omap_clk_soc_init = omap3xxx_clk_init;
+ if (of_have_populated_dt())
+ omap_clk_soc_init = ti81xx_dt_clk_init;
+ else
+ omap_clk_soc_init = omap3xxx_clk_init;
}
void __init omap3_init_late(void)
--
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[PATCHv9 42/43] ARM: AM33xx: remove old clock data and link in new clock init code
AM33xx clocks have now been moved to DT, thus remove the old data file
and use the new init code under OMAP clock driver.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/Makefile |1 -
arch/arm/mach-omap2/cclock33xx_data.c | 1064 -
arch/arm/mach-omap2/io.c |2 +-
3 files changed, 1 insertion(+), 1066 deletions(-)
delete mode 100644 arch/arm/mach-omap2/cclock33xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f518360..020079e 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -187,7 +187,6 @@ obj-$(CONFIG_ARCH_OMAP3)+= clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
obj-$(CONFIG_SOC_OMAP5)+= $(clock-common)
obj-$(CONFIG_SOC_OMAP5)+= dpll3xxx.o dpll44xx.o
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c
b/arch/arm/mach-omap2/cclock33xx_data.c
deleted file mode 100644
index 865d30e..000
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ /dev/null
@@ -1,1064 +0,0 @@
-/*
- * AM33XX Clock data
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath hvaib...@ti.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed as is WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include linux/kernel.h
-#include linux/list.h
-#include linux/clk-private.h
-#include linux/clkdev.h
-#include linux/io.h
-
-#include am33xx.h
-#include soc.h
-#include iomap.h
-#include clock.h
-#include control.h
-#include cm.h
-#include cm33xx.h
-#include cm-regbits-33xx.h
-#include prm.h
-
-/* Modulemode control */
-#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
-#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
-
-/*LIST_HEAD(clocks);*/
-
-/* Root clocks */
-
-/* RTC 32k */
-DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
-
-/* On-Chip 32KHz RC OSC */
-DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
-
-/* Crystal input clks */
-DEFINE_CLK_FIXED_RATE(virt_1920_ck, CLK_IS_ROOT, 1920, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_2400_ck, CLK_IS_ROOT, 2400, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_2500_ck, CLK_IS_ROOT, 2500, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_2600_ck, CLK_IS_ROOT, 2600, 0x0);
-
-/* Oscillator clock */
-/* 19.2, 24, 25 or 26 MHz */
-static const char *sys_clkin_ck_parents[] = {
- virt_1920_ck, virt_2400_ck, virt_2500_ck,
- virt_2600_ck,
-};
-
-/*
- * sys_clk in: input to the dpll and also used as funtional clock for,
- * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
- *
- */
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
- AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
- AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
- AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
- 0, NULL);
-
-/* External clock - 12 MHz */
-DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 1200, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
- .clk_bypass = sys_clkin_ck,
- .clk_ref= sys_clkin_ck,
- .control_reg= AM33XX_CM_CLKMODE_DPLL_CORE,
- .modes = (1 DPLL_LOW_POWER_BYPASS) | (1 DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
- .mult_mask = AM33XX_DPLL_MULT_MASK,
- .div1_mask = AM33XX_DPLL_DIV_MASK,
- .enable_mask= AM33XX_DPLL_EN_MASK,
- .idlest_mask= AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider= 128,
- .min_divider= 1,
-};
-
-/* CLKDCOLDO output */
-static const char *dpll_core_ck_parents[] = {
- sys_clkin_ck,
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
- .recalc_rate= omap3_dpll_recalc,
- .get_parent = omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
- .hw = {
- .clk= dpll_core_ck,
- },
- .dpll_data = dpll_core_dd,
- .ops= clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-
[PATCHv9 34/43] ARM: OMAP2+: clock: add support for regmap
Using regmap is required for isolating the actual memory access from
the clock code. Now, the driver providing the support for the clock IP
block can provide a regmap for this purpose.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clock.c | 20
arch/arm/mach-omap2/clock.h |3 +++
2 files changed, 23 insertions(+)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 223f432b..560c49b 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -57,6 +57,26 @@ static bool clkdm_control = true;
static LIST_HEAD(clk_hw_omap_clocks);
+void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
+{
+ if (clk-regmap)
+ regmap_write(clk-regmap, (u32)reg, val);
+ else
+ __raw_writel(val, reg);
+}
+
+u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
+{
+ u32 val;
+
+ if (clk-regmap)
+ regmap_read(clk-regmap, (u32)reg, val);
+ else
+ val = __raw_readl(reg);
+
+ return val;
+}
+
/*
* Used for clocks that have the same value as the parent clock,
* divided by some factor
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index d1b227e..a166683 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -252,6 +252,9 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
const char *core_ck_name,
const char *mpu_ck_name);
+u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
+void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
+
extern u16 cpu_mask;
extern const struct clkops clkops_omap2_dflt_wait;
--
1.7.9.5
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[PATCHv9 39/43] ARM: OMAP2+: io: use new clock init API
clk_init is now separated to a common function which gets called for all
SoC:s, which initializes the DT clocks and calls the SoC specific clock init.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/common.h |2 +-
arch/arm/mach-omap2/io.c | 32 +++-
arch/arm/mach-omap2/timer.c |6 ++
3 files changed, 26 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 4a5684b..513d17a 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -299,7 +299,7 @@ struct omap_hwmod;
extern int omap_dss_reset(struct omap_hwmod *);
/* SoC specific clock initializer */
-extern int (*omap_clk_init)(void);
+int omap_clk_init(void);
#endif /* __ASSEMBLER__ */
#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index e360ddf..2f90f38 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -55,10 +55,10 @@
#include prm44xx.h
/*
- * omap_clk_init: points to a function that does the SoC-specific
+ * omap_clk_soc_init: points to a function that does the SoC-specific
* clock initializations
*/
-int (*omap_clk_init)(void);
+int (*omap_clk_soc_init)(void);
/*
* The machine specific code may provide the extra mapping besides the
@@ -419,7 +419,7 @@ void __init omap2420_init_early(void)
omap242x_clockdomains_init();
omap2420_hwmod_init();
omap_hwmod_init_postsetup();
- omap_clk_init = omap2420_clk_init;
+ omap_clk_soc_init = omap2420_clk_init;
}
void __init omap2420_init_late(void)
@@ -448,7 +448,7 @@ void __init omap2430_init_early(void)
omap243x_clockdomains_init();
omap2430_hwmod_init();
omap_hwmod_init_postsetup();
- omap_clk_init = omap2430_clk_init;
+ omap_clk_soc_init = omap2430_clk_init;
}
void __init omap2430_init_late(void)
@@ -482,7 +482,7 @@ void __init omap3_init_early(void)
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
- omap_clk_init = omap3xxx_clk_init;
+ omap_clk_soc_init = omap3xxx_clk_init;
}
void __init omap3430_init_early(void)
@@ -520,7 +520,7 @@ void __init ti81xx_init_early(void)
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
- omap_clk_init = omap3xxx_clk_init;
+ omap_clk_soc_init = omap3xxx_clk_init;
}
void __init omap3_init_late(void)
@@ -581,7 +581,7 @@ void __init am33xx_init_early(void)
am33xx_clockdomains_init();
am33xx_hwmod_init();
omap_hwmod_init_postsetup();
- omap_clk_init = am33xx_clk_init;
+ omap_clk_soc_init = am33xx_clk_init;
}
#endif
@@ -619,7 +619,7 @@ void __init omap4430_init_early(void)
omap44xx_clockdomains_init();
omap44xx_hwmod_init();
omap_hwmod_init_postsetup();
- omap_clk_init = omap4xxx_clk_init;
+ omap_clk_soc_init = omap4xxx_clk_init;
}
void __init omap4430_init_late(void)
@@ -650,7 +650,7 @@ void __init omap5_init_early(void)
omap54xx_clockdomains_init();
omap54xx_hwmod_init();
omap_hwmod_init_postsetup();
- omap_clk_init = omap5xxx_dt_clk_init;
+ omap_clk_soc_init = omap5xxx_dt_clk_init;
}
#endif
@@ -685,3 +685,17 @@ void __init omap_sdrc_init(struct omap_sdrc_params
*sdrc_cs0,
_omap2_init_reprogram_sdrc();
}
}
+
+int __init omap_clk_init(void)
+{
+ int ret = 0;
+
+ if (!omap_clk_soc_init)
+ return 0;
+
+ ret = of_prcm_init();
+ if (!ret)
+ ret = omap_clk_soc_init();
+
+ return ret;
+}
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 87a42de..9812709 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -558,8 +558,7 @@ static inline void __init realtime_counter_init(void)
clksrc_nr, clksrc_src, clksrc_prop) \
void __init omap##name##_gptimer_timer_init(void) \
{ \
- if (omap_clk_init) \
- omap_clk_init();\
+ omap_clk_init();\
omap_dmtimer_init();\
omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);\
omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
@@ -570,8 +569,7 @@ void __init omap##name##_gptimer_timer_init(void)
\
clksrc_nr, clksrc_src, clksrc_prop) \
void __init omap##name##_sync32k_timer_init(void) \
{ \
- if (omap_clk_init)
[PATCHv9 25/43] ARM: dts: dra7 clock data
This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).
TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 1998 ++
1 file changed, 1998 insertions(+)
create mode 100644 arch/arm/boot/dts/dra7xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
new file mode 100644
index 000..ba43e7d
--- /dev/null
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,1998 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+cm_core_aon: cm_core_aon@4a005000 {
+ compatible = ti,cm;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x4a005000 0x2000;
+
+ atl_clkin0_ck: atl_clkin0_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ atl_clkin1_ck: atl_clkin1_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ atl_clkin2_ck: atl_clkin2_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ atlclkin3_ck: atlclkin3_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ hdmi_clkin_ck: hdmi_clkin_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ mlb_clkin_ck: mlb_clkin_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ mlbp_clkin_ck: mlbp_clkin_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 1;
+ };
+
+ ref_clkin0_ck: ref_clkin0_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ ref_clkin1_ck: ref_clkin1_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ ref_clkin2_ck: ref_clkin2_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ ref_clkin3_ck: ref_clkin3_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ rmii_clk_ck: rmii_clk_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ sdvenc_clkin_ck: sdvenc_clkin_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 32768;
+ };
+
+ sys_32k_ck: sys_32k_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 32768;
+ };
+
+ virt_1200_ck: virt_1200_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 1200;
+ };
+
+ virt_1300_ck: virt_1300_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 1300;
+ };
+
+ virt_1680_ck: virt_1680_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 1680;
+ };
+
+ virt_1920_ck: virt_1920_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 1920;
+ };
+
+ virt_2000_ck: virt_2000_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 2000;
+ };
+
+ virt_2600_ck: virt_2600_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 2600;
+ };
+
+ virt_2700_ck: virt_2700_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency =
[PATCHv9 23/43] ARM: dts: omap4 clock data
This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/omap4.dtsi |2 +
arch/arm/boot/dts/omap443x-clocks.dtsi | 18 +
arch/arm/boot/dts/omap443x.dtsi|2 +
arch/arm/boot/dts/omap4460.dtsi|2 +
arch/arm/boot/dts/omap446x-clocks.dtsi | 27 +
arch/arm/boot/dts/omap44xx-clocks.dtsi | 1664
6 files changed, 1715 insertions(+)
create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 0d8fdba..26d48eb 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -107,6 +107,8 @@
interrupts = GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
+ /include/ omap44xx-clocks.dtsi
+
counter32k: counter@4a304000 {
compatible = ti,omap-counter32k;
reg = 0x4a304000 0x20;
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi
b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 000..643755b
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+prm {
+ bandgap_fclk: bandgap_fclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = sys_32k_ck;
+ ti,bit-shift = 8;
+ reg = 0x1888;
+ };
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index bcf455e..f67e191 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -31,3 +31,5 @@
compatible = ti,omap4430-bandgap;
};
};
+
+/include/ omap443x-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index c2f0f39..1758601 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -39,3 +39,5 @@
gpios = gpio3 22 0; /* tshut */
};
};
+
+/include/ omap446x-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi
b/arch/arm/boot/dts/omap446x-clocks.dtsi
new file mode 100644
index 000..d5ba999
--- /dev/null
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+prm {
+ div_ts_ck: div_ts_ck {
+ #clock-cells = 0;
+ compatible = ti,divider-clock;
+ clocks = l4_wkup_clk_mux_ck;
+ ti,bit-shift = 24;
+ reg = 0x1888;
+ ti,dividers = 8, 16, 32;
+ };
+
+ bandgap_ts_fclk: bandgap_ts_fclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = div_ts_ck;
+ ti,bit-shift = 8;
+ reg = 0x1888;
+ };
+};
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi
b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 000..121d60a
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -0,0 +1,1664 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+cm1: cm1@4a004000 {
+ compatible = ti,cm;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x4a004000 0x2000;
+
+ extalt_clkin_ck: extalt_clkin_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 5900;
+ };
+
+ pad_clks_src_ck: pad_clks_src_ck {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 1200;
+ };
+
+ pad_clks_ck: pad_clks_ck {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = pad_clks_src_ck;
+ ti,bit-shift = 8;
+ reg = 0x0108;
+ };
+
+ pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+
[PATCHv9 35/43] ARM: OMAP2+: clock: use driver API instead of direct memory read/write
Clock nodes shall use the services provided by underlying drivers to access
the hardware registers instead of direct memory read/write. Thus, change
all the code to use the new omap2_clk_readl / omap2_clk_writel APIs for this.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clkt_clksel.c | 10 +-
arch/arm/mach-omap2/clkt_dpll.c |6 +++---
arch/arm/mach-omap2/clkt_iclk.c | 20
arch/arm/mach-omap2/clock.c | 24
arch/arm/mach-omap2/clock36xx.c |7 ---
arch/arm/mach-omap2/dpll3xxx.c| 37 -
arch/arm/mach-omap2/dpll44xx.c| 12 ++--
7 files changed, 62 insertions(+), 54 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt_clksel.c
b/arch/arm/mach-omap2/clkt_clksel.c
index 0ec9f6f..7ee2610 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -97,12 +97,12 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32
field_val)
{
u32 v;
- v = __raw_readl(clk-clksel_reg);
+ v = omap2_clk_readl(clk, clk-clksel_reg);
v = ~clk-clksel_mask;
v |= field_val __ffs(clk-clksel_mask);
- __raw_writel(v, clk-clksel_reg);
+ omap2_clk_writel(v, clk, clk-clksel_reg);
- v = __raw_readl(clk-clksel_reg); /* OCP barrier */
+ v = omap2_clk_readl(clk, clk-clksel_reg); /* OCP barrier */
}
/**
@@ -204,7 +204,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk)
if (!clk-clksel || !clk-clksel_mask)
return 0;
- v = __raw_readl(clk-clksel_reg);
+ v = omap2_clk_readl(clk, clk-clksel_reg);
v = clk-clksel_mask;
v = __ffs(clk-clksel_mask);
@@ -320,7 +320,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
WARN((!clk-clksel || !clk-clksel_mask),
clock: %s: attempt to call on a non-clksel clock, clk_name);
- r = __raw_readl(clk-clksel_reg) clk-clksel_mask;
+ r = omap2_clk_readl(clk, clk-clksel_reg) clk-clksel_mask;
r = __ffs(clk-clksel_mask);
for (clks = clk-clksel; clks-parent !found; clks++) {
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 924c230..47f9562 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -196,7 +196,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
if (!dd)
return -EINVAL;
- v = __raw_readl(dd-control_reg);
+ v = omap2_clk_readl(clk, dd-control_reg);
v = dd-enable_mask;
v = __ffs(dd-enable_mask);
@@ -243,7 +243,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
return 0;
/* Return bypass rate if DPLL is bypassed */
- v = __raw_readl(dd-control_reg);
+ v = omap2_clk_readl(clk, dd-control_reg);
v = dd-enable_mask;
v = __ffs(dd-enable_mask);
@@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
return __clk_get_rate(dd-clk_bypass);
}
- v = __raw_readl(dd-mult_div1_reg);
+ v = omap2_clk_readl(clk, dd-mult_div1_reg);
dpll_mult = v dd-mult_mask;
dpll_mult = __ffs(dd-mult_mask);
dpll_div = v dd-div1_mask;
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index f10eb03..333f0a6 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -25,25 +25,29 @@
/* XXX */
void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
{
- u32 v, r;
+ u32 v;
+ void __iomem *r;
- r = ((__force u32)clk-enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+ r = (__force void __iomem *)
+ ((__force u32)clk-enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
- v = __raw_readl((__force void __iomem *)r);
+ v = omap2_clk_readl(clk, r);
v |= (1 clk-enable_bit);
- __raw_writel(v, (__force void __iomem *)r);
+ omap2_clk_writel(v, clk, r);
}
/* XXX */
void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
{
- u32 v, r;
+ u32 v;
+ void __iomem *r;
- r = ((__force u32)clk-enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+ r = (__force void __iomem *)
+ ((__force u32)clk-enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
- v = __raw_readl((__force void __iomem *)r);
+ v = omap2_clk_readl(clk, r);
v = ~(1 clk-enable_bit);
- __raw_writel(v, (__force void __iomem *)r);
+ omap2_clk_writel(v, clk, r);
}
/* Public data */
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 560c49b..dd7a739 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -118,14 +118,14 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
* elapsed. XXX Deprecated - should be moved into drivers for the
* individual IP block that the IDLEST register exists in.
*/
-static int
Re: [PATCHv9 30/43] ARM: dts: am33xx clock data
On Fri, 2013-10-25 at 18:57 +0300, Tero Kristo wrote:
+ mcasp0_fck: mcasp0_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
+
+ mcasp1_fck: mcasp1_fck {
+ #clock-cells = 0;
+ compatible = fixed-factor-clock;
+ clocks = sys_clkin_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
What is you use case for these clocks with a fixed factor of 1? Wouldn't
it be simpler to just use sys_clkin_ck from the devices?
Regards,
Jan
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