Re: [PATCH v6 3/7] regulator: add pbias regulator support
On Thursday 19 December 2013 10:03 PM, Tony Lindgren wrote:
Looks good to me, just few minor comments below.
* Balaji T K balaj...@ti.com [131219 04:40]:
--- /dev/null
+++ b/drivers/regulator/pbias-regulator.c
@@ -0,0 +1,255 @@
+/*
+ * pbias-regulator.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Balaji T K balaj...@ti.com
Maybe use 2013 here instead?
yes
+static int pbias_regulator_enable(struct regulator_dev *rdev)
+{
+ struct pbias_regulator_data *data = rdev_get_drvdata(rdev);
+ const struct pbias_reg_info *info = data-info;
+ int ret;
+
+ ret = regmap_update_bits(data-syscon, data-pbias_reg,
+ info-enable_mask, info-enable);
+
+ return ret;
+}
Do we need need to check the values after enable here? AFAIK setting
the PBIAS voltage change can also fail and that's probably why it has
failure due to mismatch in input voltage, should to be avoided and should
be taken care in s/w by the caller before pbias regulator set voltage/enable.
also the interrupt available.
But interrupt was never used/tested AFAIK, there is some settling time
before the generated interrupt status is truely valid, so pbias interrupt is not
reliable.
+static const struct pbias_reg_info pbias_mmc_omap3 = {
+ .enable = BIT(1),
+ .enable_mask = BIT(1),
+ .vmode = BIT(0),
+ .name = pbias_mmc_omap3
+};
+
+static const struct pbias_reg_info pbias_sim_omap3 = {
+ .enable = BIT(9),
+ .enable_mask = BIT(9),
+ .vmode = BIT(8),
+ .name = pbias_sim_omap3
+};
+
+static const struct pbias_reg_info pbias_mmc_omap4 = {
+ .enable = BIT(26) | BIT(22),
+ .enable_mask = BIT(26) | BIT(25) | BIT(22),
+ .vmode = BIT(21),
+ .name = pbias_mmc_omap4
+};
+
+static const struct pbias_reg_info pbias_mmc_omap5 = {
+ .enable = BIT(27) | BIT(26),
+ .enable_mask = BIT(27) | BIT(25) | BIT(26),
+ .vmode = BIT(21),
+ .name = pbias_mmc_omap5
+};
+static struct of_regulator_match pbias_matches[] = {
+ { .name = pbias_mmc_omap3, .driver_data = (void *)pbias_mmc_omap3},
+ { .name = pbias_sim_omap3, .driver_data = (void *)pbias_sim_omap3},
+ { .name = pbias_mmc_omap4, .driver_data = (void *)pbias_mmc_omap4},
+ { .name = pbias_mmc_omap5, .driver_data = (void *)pbias_mmc_omap5},
+};
We probably need also pbias_mmc_omap2430 as that regiter mapping is
separate from omap3?
between omap2430 and omap3430, 3460 pbias register address are different,
other than that enable,enable_mask and vmode are
one and the same, so re-used pbias_mmc_omap3 name and struct pbias_reg_info
pbias_mmc_omap3
for omap2430 too, save one entry in of_regulator_match!
If separate name is needed for omap2430, I can add one for 2430,
and reuse the const struct pbias_reg_info pbias_mmc_omap3 of omap3
since the bit map for enable/disable and voltage configuration will be same.
Then pbias_matches will look like.
+static struct of_regulator_match pbias_matches[] = {
+ { .name = pbias_mmc_omap2430, .driver_data = (void
*)pbias_mmc_omap3},
+ { .name = pbias_mmc_omap3, .driver_data = (void *)pbias_mmc_omap3},
+ { .name = pbias_sim_omap3, .driver_data = (void *)pbias_sim_omap3},
+ { .name = pbias_mmc_omap4, .driver_data = (void *)pbias_mmc_omap4},
+ { .name = pbias_mmc_omap5, .driver_data = (void *)pbias_mmc_omap5},
+};
Let me know if you still think that separate regulator name is needed for 2430,
I can respin this series.
Other than that, good to see this finally happen. This should allow us to
get rid of most of the platform data callbacks for omap_hsmmc.c driver.
Regards,
Tony
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/8] ARM: Convert boot_lock to raw_lock [omap]
From: Frank Rowand frank.row...@am.sony.com
The arm boot_lock is used by the secondary processor startup code. The locking
task is the idle thread, which has idle-sched_class == idle_sched_class.
idle_sched_class-enqueue_task == NULL, so if the idle task blocks on the
lock, the attempt to wake it when the lock becomes available will fail:
try_to_wake_up()
...
activate_task()
enqueue_task()
p-sched_class-enqueue_task(rq, p, flags)
Fix by converting boot_lock to a raw spin lock.
Cc: Tony Lindgren t...@atomide.com
Cc: linux-omap@vger.kernel.org
Cc: Frank Rowand frank.row...@sonymobile.com
Signed-off-by: Frank Rowand frank.row...@am.sony.com
Link: http://lkml.kernel.org/r/4e77b952.3010...@am.sony.com
Signed-off-by: Thomas Gleixner t...@linutronix.de
Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de
---
arch/arm/mach-omap2/omap-smp.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 75e95d4..1ddafec 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -44,7 +44,7 @@ u16 pm44xx_errata;
/* SCU base address */
static void __iomem *scu_base;
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
void __iomem *omap4_get_scu_base(void)
{
@@ -75,8 +75,8 @@ static void omap4_secondary_init(unsigned int cpu)
/*
* Synchronise with the boot thread.
*/
- spin_lock(boot_lock);
- spin_unlock(boot_lock);
+ raw_spin_lock(boot_lock);
+ raw_spin_unlock(boot_lock);
}
static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -90,7 +90,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct
task_struct *idle)
* Set synchronisation state between this boot processor
* and the secondary one
*/
- spin_lock(boot_lock);
+ raw_spin_lock(boot_lock);
/*
* Update the AuxCoreBoot0 with boot state for secondary core.
@@ -167,7 +167,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct
task_struct *idle)
* Now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
- spin_unlock(boot_lock);
+ raw_spin_unlock(boot_lock);
return 0;
}
--
1.8.5.1
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv11 07/49] clk: divider: add support for low level ops
On Friday 20 December 2013 12:32 AM, Tero Kristo wrote: On 12/19/2013 08:26 PM, Tony Lindgren wrote: * Tero Kristo t-kri...@ti.com [131219 03:26]: Divider clock can now be registered to use low level register access ops. Preferred initialization method is via clock description. This seems to make omap2 not boot for me. No output whatsoever even with DEBUG_LL and earlyprintk. Thats weird... I was kind of afraid something like this might happen though as these patches touch the clock low level routines globally, but I can't see what could be broken... I got hold of a 2430sdp and saw the same behavior, however DEBUG_LL and earlyprintk worked and this is what I see [0.00] Unable to handle kernel NULL pointer dereference at virtual address [0.00] pgd = c0004000 [0.00] [] *pgd= [0.00] Internal error: Oops: 5 [#1] SMP ARM [0.00] Modules linked in: [0.00] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.13.0-rc4-00056-ga9fa93e #2 [0.00] task: c07dfcb8 ti: c07d4000 task.ti: c07d4000 [0.00] PC is at clk_mux_get_parent+0x14/0xcc [0.00] LR is at clk_mux_get_parent+0x10/0xcc [0.00] pc : [c044a234]lr : [c044a230]psr: a1d3 [0.00] sp : c07d5f40 ip : fp : [0.00] r10: c07dc880 r9 : 4107b366 r8 : c07f46a4 [0.00] r7 : c0edfa80 r6 : r5 : c07f6810 r4 : 0002 [0.00] r3 : r2 : r1 : c069da67 r0 : 0002 [0.00] Flags: NzCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel [0.00] Control: 00c5387d Table: 80004000 DAC: 0017 [0.00] Process swapper/0 (pid: 0, stack limit = 0xc07d4248) [0.00] Stack: (0xc07d5f40 to 0xc07d6000) [0.00] 5f40: c044a220 0002 c6001f40 c0448e54 c07dfcb8 c0862f7c c07f3600 c07f4368 [0.00] 5f60: c0edfa80 c07b6b80 4107b366 c07dc880 c077edf4 c0531008 c07f4380 [0.00] 5f80: c07f34d4 c077f20c c0878964 c0edfa80 c07b6b80 c0877ac4 c0877640 [0.00] 5fa0: c0edfa80 c0777268 0001 c07792ac c07b5250 c077221c 0002 c076e974 [0.00] 5fc0: c076e57c c07b6b80 00c5387d [0.00] 5fe0: c07dc928 c07b6b7c c07e1474 80004008 8052c544 80008074 [0.00] [c044a234] (clk_mux_get_parent+0x14/0xcc) from [c0448e54] (__clk_init+0xe4/0x3f0) [0.00] [c0448e54] (__clk_init+0xe4/0x3f0) from [c077edf4] (omap_clocks_register+0x24/0x48) [0.00] [c077edf4] (omap_clocks_register+0x24/0x48) from [c077f20c] (omap2430_clk_init+0x4c/0x124) [0.00] [c077f20c] (omap2430_clk_init+0x4c/0x124) from [c0777268] (omap_clk_init+0x28/0x30) [0.00] [c0777268] (omap_clk_init+0x28/0x30) from [c07792ac] (omap2_sync32k_timer_init+0x8/0x58) [0.00] [c07792ac] (omap2_sync32k_timer_init+0x8/0x58) from [c077221c] (time_init+0x1c/0x30) [0.00] [c077221c] (time_init+0x1c/0x30) from [c076e974] (start_kernel+0x1d4/0x360) [0.00] [c076e974] (start_kernel+0x1d4/0x360) from [80008074] (0x80008074) [0.00] Code: e1a05000 e590 ebfff7f5 e595300c (e5933000) [0.00] ---[ end trace 3406ff24bd97382e ]--- [0.00] Kernel panic - not syncing: Attempted to kill the idle task! I'll try and debug further but any quick thoughts on what could be wrong? -Tero -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv11 07/49] clk: divider: add support for low level ops
On 12/20/2013 12:07 PM, Rajendra Nayak wrote: On Friday 20 December 2013 12:32 AM, Tero Kristo wrote: On 12/19/2013 08:26 PM, Tony Lindgren wrote: * Tero Kristo t-kri...@ti.com [131219 03:26]: Divider clock can now be registered to use low level register access ops. Preferred initialization method is via clock description. This seems to make omap2 not boot for me. No output whatsoever even with DEBUG_LL and earlyprintk. Thats weird... I was kind of afraid something like this might happen though as these patches touch the clock low level routines globally, but I can't see what could be broken... I got hold of a 2430sdp and saw the same behavior, however DEBUG_LL and earlyprintk worked and this is what I see [0.00] Unable to handle kernel NULL pointer dereference at virtual address [0.00] pgd = c0004000 [0.00] [] *pgd= [0.00] Internal error: Oops: 5 [#1] SMP ARM [0.00] Modules linked in: [0.00] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.13.0-rc4-00056-ga9fa93e #2 [0.00] task: c07dfcb8 ti: c07d4000 task.ti: c07d4000 [0.00] PC is at clk_mux_get_parent+0x14/0xcc [0.00] LR is at clk_mux_get_parent+0x10/0xcc [0.00] pc : [c044a234]lr : [c044a230]psr: a1d3 [0.00] sp : c07d5f40 ip : fp : [0.00] r10: c07dc880 r9 : 4107b366 r8 : c07f46a4 [0.00] r7 : c0edfa80 r6 : r5 : c07f6810 r4 : 0002 [0.00] r3 : r2 : r1 : c069da67 r0 : 0002 [0.00] Flags: NzCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel [0.00] Control: 00c5387d Table: 80004000 DAC: 0017 [0.00] Process swapper/0 (pid: 0, stack limit = 0xc07d4248) [0.00] Stack: (0xc07d5f40 to 0xc07d6000) [0.00] 5f40: c044a220 0002 c6001f40 c0448e54 c07dfcb8 c0862f7c c07f3600 c07f4368 [0.00] 5f60: c0edfa80 c07b6b80 4107b366 c07dc880 c077edf4 c0531008 c07f4380 [0.00] 5f80: c07f34d4 c077f20c c0878964 c0edfa80 c07b6b80 c0877ac4 c0877640 [0.00] 5fa0: c0edfa80 c0777268 0001 c07792ac c07b5250 c077221c 0002 c076e974 [0.00] 5fc0: c076e57c c07b6b80 00c5387d [0.00] 5fe0: c07dc928 c07b6b7c c07e1474 80004008 8052c544 80008074 [0.00] [c044a234] (clk_mux_get_parent+0x14/0xcc) from [c0448e54] (__clk_init+0xe4/0x3f0) [0.00] [c0448e54] (__clk_init+0xe4/0x3f0) from [c077edf4] (omap_clocks_register+0x24/0x48) [0.00] [c077edf4] (omap_clocks_register+0x24/0x48) from [c077f20c] (omap2430_clk_init+0x4c/0x124) [0.00] [c077f20c] (omap2430_clk_init+0x4c/0x124) from [c0777268] (omap_clk_init+0x28/0x30) [0.00] [c0777268] (omap_clk_init+0x28/0x30) from [c07792ac] (omap2_sync32k_timer_init+0x8/0x58) [0.00] [c07792ac] (omap2_sync32k_timer_init+0x8/0x58) from [c077221c] (time_init+0x1c/0x30) [0.00] [c077221c] (time_init+0x1c/0x30) from [c076e974] (start_kernel+0x1d4/0x360) [0.00] [c076e974] (start_kernel+0x1d4/0x360) from [80008074] (0x80008074) [0.00] Code: e1a05000 e590 ebfff7f5 e595300c (e5933000) [0.00] ---[ end trace 3406ff24bd97382e ]--- [0.00] Kernel panic - not syncing: Attempted to kill the idle task! I'll try and debug further but any quick thoughts on what could be wrong? I have a fix for this already and will be posting v12 today. I will just re-post the drivers/clk part of the series though, rest of the patches should be fine. This bug was silly actually, I didn't think of the static clock data initialization through the macros from clk-private.h... This caused the resulting clock structures to have NULL for clk_ll_ops as it bypassed the init function where I set it up. So, I will need to check against NULL every time I do anything with ll_ops. -Tero -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC v2 REPOST 0/8] Beaglebone-Black HDMI audio
Changes since the first RFC version of the patches: - Drop out already applied: ASoC: hdmi-codec: Add SNDRV_PCM_FMTBIT_32_LE playback format - Change sound node's compatible property form: ti,am33xx-beaglebone-black to ti,am33xx-beaglebone-black-audio - Some minor style issue fixes from TI internal review The patches have been rebased on top of: git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound topic/davinci The associated dts change can be found here: http://www.spinics.net/lists/linux-omap/msg101072.html Best regards, Jyri Jyri Sarha (8): clk: add gpio controlled clock ASoC: davinci-evm: Add named clock reference to DT bindings ASoC: davinci-evm: HDMI audio support for TDA998x trough McASP I2S bus ASoC: hdmi-codec: Add devicetree binding with documentation ASoC: davinci: HDMI audio build for AM33XX and TDA998x drm/tilcdc: Add I2C HDMI audio config for tda998x ARM: OMAP2+: omap2plus_defconfig: Enable tilcdc and TDA998X HDMI support ARM: OMAP2+: omap2plus_defconfig: Enable BeagleBone Black HDMI audio support .../devicetree/bindings/clock/gpio-clock.txt | 21 ++ .../bindings/sound/davinci-evm-audio.txt | 13 +- Documentation/devicetree/bindings/sound/hdmi.txt | 17 ++ arch/arm/configs/omap2plus_defconfig |5 + drivers/clk/Makefile |1 + drivers/clk/clk-gpio.c | 210 ++ drivers/gpu/drm/tilcdc/tilcdc_slave.c | 24 ++- include/linux/clk-provider.h | 25 +++ sound/soc/codecs/hdmi.c| 10 + sound/soc/davinci/Kconfig | 12 ++ sound/soc/davinci/Makefile |1 + sound/soc/davinci/davinci-evm.c| 227 +++- 12 files changed, 559 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/gpio-clock.txt create mode 100644 Documentation/devicetree/bindings/sound/hdmi.txt create mode 100644 drivers/clk/clk-gpio.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC v2 REPOST 1/8] clk: add gpio controlled clock
The added clk-gpio is a basic clock that can be enabled and disabled
trough a gpio output. The DT binding document for the clock is also
added. For EPROBE_DEFER handling the registering of the clock has to
be delayed until of_clk_get() call time.
Signed-off-by: Jyri Sarha jsa...@ti.com
cc: mturque...@linaro.org
cc: bcous...@baylibre.com
---
.../devicetree/bindings/clock/gpio-clock.txt | 21 ++
drivers/clk/Makefile |1 +
drivers/clk/clk-gpio.c | 210
include/linux/clk-provider.h | 25 +++
4 files changed, 257 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/gpio-clock.txt
create mode 100644 drivers/clk/clk-gpio.c
diff --git a/Documentation/devicetree/bindings/clock/gpio-clock.txt
b/Documentation/devicetree/bindings/clock/gpio-clock.txt
new file mode 100644
index 000..54fea39
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/gpio-clock.txt
@@ -0,0 +1,21 @@
+Binding for simple gpio controlled clock.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be gpio-clock.
+- #clock-cells : from common clock binding; shall be set to 0.
+- enable-gpios : GPIO reference for enabling and disabling the clock.
+
+Optional properties:
+- clocks: Maximum of one parent clock is supported.
+
+Example:
+ clock {
+ compatible = gpio-clock;
+ clocks = parentclk;
+ #clock-cells = 0;
+ enable-gpios = gpio 1 GPIO_ACTIVE_HIGH;
+ };
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7b11106..568b7be 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-rate.o
obj-$(CONFIG_COMMON_CLK) += clk-gate.o
obj-$(CONFIG_COMMON_CLK) += clk-mux.o
obj-$(CONFIG_COMMON_CLK) += clk-composite.o
+obj-$(CONFIG_COMMON_CLK) += clk-gpio.o
# SoCs specific
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c
new file mode 100644
index 000..e04b0e1
--- /dev/null
+++ b/drivers/clk/clk-gpio.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2013 Texas Instruments
+ * Author: Jyri Sarha jsa...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Gpio controlled clock implementation
+ */
+
+#include linux/clk-provider.h
+#include linux/module.h
+#include linux/slab.h
+#include linux/gpio.h
+#include linux/of_gpio.h
+#include linux/err.h
+#include linux/device.h
+
+/**
+ * DOC: basic gpio controlled clock which can be enabled and disabled
+ * with gpio output
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parent is (un)prepared
+ * enable - clk_enable and clk_disable are functional control gpio
+ * rate - inherits rate from parent. No clk_set_rate support
+ * parent - fixed parent. No clk_set_parent support
+ */
+
+#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
+
+static int clk_gpio_enable(struct clk_hw *hw)
+{
+ struct clk_gpio *gpio = to_clk_gpio(hw);
+ int value = gpio-active_low ? 0 : 1;
+
+ gpio_set_value(gpio-gpio, value);
+
+ return 0;
+}
+
+static void clk_gpio_disable(struct clk_hw *hw)
+{
+ struct clk_gpio *gpio = to_clk_gpio(hw);
+ int value = gpio-active_low ? 1 : 0;
+
+ gpio_set_value(gpio-gpio, value);
+}
+
+static int clk_gpio_is_enabled(struct clk_hw *hw)
+{
+ struct clk_gpio *gpio = to_clk_gpio(hw);
+ int value = gpio_get_value(gpio-gpio);
+
+ return gpio-active_low ? !value : value;
+}
+
+const struct clk_ops clk_gpio_ops = {
+ .enable = clk_gpio_enable,
+ .disable = clk_gpio_disable,
+ .is_enabled = clk_gpio_is_enabled,
+};
+EXPORT_SYMBOL_GPL(clk_gpio_ops);
+
+/**
+ * clk_register_gpio - register a gpip clock with the clock framework
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_name: name of this clock's parent
+ * @flags: framework-specific flags for this clock
+ * @gpio: gpio to control this clock
+ * @active_low: gpio polarity
+ */
+struct clk *clk_register_gpio(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ unsigned int gpio, bool active_low)
+{
+ struct clk_gpio *clk_gpio;
+ struct clk *clk = ERR_PTR(-EINVAL);
+ struct clk_init_data init = { NULL };
+ unsigned long gpio_flags;
+ int err;
+
+ if (active_low)
+ gpio_flags = GPIOF_OUT_INIT_LOW;
+ else
+ gpio_flags = GPIOF_OUT_INIT_HIGH;
+
+ err = gpio_request_one(gpio, gpio_flags, name);
+
+ if (err) {
+ pr_err(%s: %s:
Re: [PATCHv11 07/49] clk: divider: add support for low level ops
On Friday 20 December 2013 03:59 PM, Tero Kristo wrote: On 12/20/2013 12:07 PM, Rajendra Nayak wrote: On Friday 20 December 2013 12:32 AM, Tero Kristo wrote: On 12/19/2013 08:26 PM, Tony Lindgren wrote: * Tero Kristo t-kri...@ti.com [131219 03:26]: Divider clock can now be registered to use low level register access ops. Preferred initialization method is via clock description. This seems to make omap2 not boot for me. No output whatsoever even with DEBUG_LL and earlyprintk. Thats weird... I was kind of afraid something like this might happen though as these patches touch the clock low level routines globally, but I can't see what could be broken... I got hold of a 2430sdp and saw the same behavior, however DEBUG_LL and earlyprintk worked and this is what I see [0.00] Unable to handle kernel NULL pointer dereference at virtual address [0.00] pgd = c0004000 [0.00] [] *pgd= [0.00] Internal error: Oops: 5 [#1] SMP ARM [0.00] Modules linked in: [0.00] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.13.0-rc4-00056-ga9fa93e #2 [0.00] task: c07dfcb8 ti: c07d4000 task.ti: c07d4000 [0.00] PC is at clk_mux_get_parent+0x14/0xcc [0.00] LR is at clk_mux_get_parent+0x10/0xcc [0.00] pc : [c044a234]lr : [c044a230]psr: a1d3 [0.00] sp : c07d5f40 ip : fp : [0.00] r10: c07dc880 r9 : 4107b366 r8 : c07f46a4 [0.00] r7 : c0edfa80 r6 : r5 : c07f6810 r4 : 0002 [0.00] r3 : r2 : r1 : c069da67 r0 : 0002 [0.00] Flags: NzCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel [0.00] Control: 00c5387d Table: 80004000 DAC: 0017 [0.00] Process swapper/0 (pid: 0, stack limit = 0xc07d4248) [0.00] Stack: (0xc07d5f40 to 0xc07d6000) [0.00] 5f40: c044a220 0002 c6001f40 c0448e54 c07dfcb8 c0862f7c c07f3600 c07f4368 [0.00] 5f60: c0edfa80 c07b6b80 4107b366 c07dc880 c077edf4 c0531008 c07f4380 [0.00] 5f80: c07f34d4 c077f20c c0878964 c0edfa80 c07b6b80 c0877ac4 c0877640 [0.00] 5fa0: c0edfa80 c0777268 0001 c07792ac c07b5250 c077221c 0002 c076e974 [0.00] 5fc0: c076e57c c07b6b80 00c5387d [0.00] 5fe0: c07dc928 c07b6b7c c07e1474 80004008 8052c544 80008074 [0.00] [c044a234] (clk_mux_get_parent+0x14/0xcc) from [c0448e54] (__clk_init+0xe4/0x3f0) [0.00] [c0448e54] (__clk_init+0xe4/0x3f0) from [c077edf4] (omap_clocks_register+0x24/0x48) [0.00] [c077edf4] (omap_clocks_register+0x24/0x48) from [c077f20c] (omap2430_clk_init+0x4c/0x124) [0.00] [c077f20c] (omap2430_clk_init+0x4c/0x124) from [c0777268] (omap_clk_init+0x28/0x30) [0.00] [c0777268] (omap_clk_init+0x28/0x30) from [c07792ac] (omap2_sync32k_timer_init+0x8/0x58) [0.00] [c07792ac] (omap2_sync32k_timer_init+0x8/0x58) from [c077221c] (time_init+0x1c/0x30) [0.00] [c077221c] (time_init+0x1c/0x30) from [c076e974] (start_kernel+0x1d4/0x360) [0.00] [c076e974] (start_kernel+0x1d4/0x360) from [80008074] (0x80008074) [0.00] Code: e1a05000 e590 ebfff7f5 e595300c (e5933000) [0.00] ---[ end trace 3406ff24bd97382e ]--- [0.00] Kernel panic - not syncing: Attempted to kill the idle task! I'll try and debug further but any quick thoughts on what could be wrong? I have a fix for this already and will be posting v12 today. I will just re-post the drivers/clk part of the series though, rest of the patches should be fine. This bug was silly actually, I didn't think of the static clock data initialization through the macros from clk-private.h... This caused the resulting clock structures to have NULL for clk_ll_ops as it bypassed the init function where I set it up. So, I will need to check against NULL every time I do anything with ll_ops. yeah, the crash was indeed when ll_ops was dereferenced despite being NULL. -Tero -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC v2 REPOST 2/8] ASoC: davinci-evm: Add named clock reference to DT bindings
The referenced clock is used to get codec clock rate and the clock is
disabled and enabled in startup and shutdown snd_soc_ops call
backs. The change is also documented in DT bindigs document.
Signed-off-by: Jyri Sarha jsa...@ti.com
cc: bcous...@baylibre.com
---
.../bindings/sound/davinci-evm-audio.txt |9 ++-
sound/soc/davinci/davinci-evm.c| 60 +++-
2 files changed, 66 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
index 865178d..4aa00f6 100644
--- a/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
+++ b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
@@ -5,12 +5,19 @@ Required properties:
- ti,model : The user-visible name of this sound complex.
- ti,audio-codec : The phandle of the TLV320AIC3x audio codec
- ti,mcasp-controller : The phandle of the McASP controller
-- ti,codec-clock-rate : The Codec Clock rate (in Hz) applied to the Codec
- ti,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources and
sinks are the codec's pins, and the jacks on the board:
+Optional properties:
+- ti,codec-clock-rate : The Codec Clock rate (in Hz) applied to the Codec.
+- clocks : Reference to the clock used as codec clock
+- clock-names : The codec clock should be named ti,codec-clock
+- Either codec-clock-rate or the codec-clock reference has to be defined. If
+ the both are defined the driver attempts to set referenced clock to the
+ defined rate and takes the rate from the clock reference.
+
Board connectors:
* Headphone Jack
diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index 70ff377..b28c9fd 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -17,6 +17,7 @@
#include linux/platform_data/edma.h
#include linux/i2c.h
#include linux/of_platform.h
+#include linux/clk.h
#include sound/core.h
#include sound/pcm.h
#include sound/soc.h
@@ -30,9 +31,30 @@
#include davinci-i2s.h
struct snd_soc_card_drvdata_davinci {
+ struct clk *mclk;
unsigned sysclk;
};
+static int evm_startup(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream-private_data;
+ struct snd_soc_card *soc_card = rtd-codec-card;
+ struct clk *mclk = ((struct snd_soc_card_drvdata_davinci *)
+ snd_soc_card_get_drvdata(soc_card))-mclk;
+
+ return clk_prepare_enable(mclk);
+}
+
+static void evm_shutdown(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream-private_data;
+ struct snd_soc_card *soc_card = rtd-codec-card;
+ struct clk *mclk = ((struct snd_soc_card_drvdata_davinci *)
+ snd_soc_card_get_drvdata(soc_card))-mclk;
+
+ clk_disable_unprepare(mclk);
+}
+
static int evm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
@@ -59,6 +81,8 @@ static int evm_hw_params(struct snd_pcm_substream *substream,
}
static struct snd_soc_ops evm_ops = {
+ .startup = evm_startup,
+ .shutdown = evm_shutdown,
.hw_params = evm_hw_params,
};
@@ -348,6 +372,7 @@ static int davinci_evm_probe(struct platform_device *pdev)
of_match_device(of_match_ptr(davinci_evm_dt_ids), pdev-dev);
struct snd_soc_dai_link *dai = (struct snd_soc_dai_link *) match-data;
struct snd_soc_card_drvdata_davinci *drvdata = NULL;
+ struct clk *mclk;
int ret = 0;
evm_soc_card.dai_link = dai;
@@ -367,13 +392,38 @@ static int davinci_evm_probe(struct platform_device *pdev)
if (ret)
return ret;
+ mclk = of_clk_get_by_name(np, ti,codec-clock);
+ if (PTR_ERR(mclk) == -EPROBE_DEFER) {
+ return -EPROBE_DEFER;
+ } else if (IS_ERR(mclk)) {
+ dev_dbg(pdev-dev, Codec clock not found.\n);
+ mclk = NULL;
+ }
+
drvdata = devm_kzalloc(pdev-dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
+ drvdata-mclk = mclk;
+
ret = of_property_read_u32(np, ti,codec-clock-rate, drvdata-sysclk);
- if (ret 0)
- return -EINVAL;
+
+ if (ret 0) {
+ if (!drvdata-mclk) {
+ dev_err(pdev-dev,
+ No clock or clock rate defined.\n);
+ return -EINVAL;
+ }
+ drvdata-sysclk = clk_get_rate(drvdata-mclk);
+ } else if (drvdata-mclk) {
+ unsigned int requestd_rate = drvdata-sysclk;
+ clk_set_rate(drvdata-mclk, drvdata-sysclk);
+ drvdata-sysclk =
[PATCH RFC v2 REPOST 3/8] ASoC: davinci-evm: HDMI audio support for TDA998x trough McASP I2S bus
Add machine driver support for BeagleBone-Black and other boards with
tilcdc support and NXP TDA998X HDMI transmitter connected to McASP
port in I2S mode. The 44100 Hz sample-rate and it's multiples can not
be supported on Beaglebone-Black because of limited clock-rate
support. The only supported sample format is SNDRV_PCM_FORMAT_S32_LE.
The 8 least significant bits are ignored.
Signed-off-by: Jyri Sarha jsa...@ti.com
cc: bcous...@baylibre.com
---
.../bindings/sound/davinci-evm-audio.txt |4 +-
sound/soc/davinci/davinci-evm.c| 167 +++-
2 files changed, 168 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
index 4aa00f6..f1e1031 100644
--- a/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
+++ b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
@@ -1,7 +1,9 @@
* Texas Instruments SoC audio setups with TLV320AIC3X Codec
Required properties:
-- compatible : ti,da830-evm-audio : forDM365/DA8xx/OMAPL1x/AM33xx
+- compatible :
+ ti,da830-evm-audio : for DM365/DA8xx/OMAPL1x/AM33xx
+ ti,am33xx-beaglebone-black-audio : for Beaglebone-black HDMI audio
- ti,model : The user-visible name of this sound complex.
- ti,audio-codec : The phandle of the TLV320AIC3x audio codec
- ti,mcasp-controller : The phandle of the McASP controller
diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index b28c9fd..3d3138d 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -21,6 +21,7 @@
#include sound/core.h
#include sound/pcm.h
#include sound/soc.h
+#include sound/pcm_params.h
#include asm/dma.h
#include asm/mach-types.h
@@ -33,8 +34,13 @@
struct snd_soc_card_drvdata_davinci {
struct clk *mclk;
unsigned sysclk;
+ struct snd_pcm_hw_constraint_list *rate_constraint;
};
+/* If changing sample format the tda998x configuration (REG_CTS_N) needs
+ to be changed. */
+#define TDA998X_SAMPLE_FORMAT SNDRV_PCM_FORMAT_S32_LE
+
static int evm_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream-private_data;
@@ -80,12 +86,80 @@ static int evm_hw_params(struct snd_pcm_substream
*substream,
return 0;
}
+static int evm_tda998x_startup(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream-runtime;
+ struct snd_soc_pcm_runtime *rtd = substream-private_data;
+ struct snd_soc_card *soc_card = rtd-codec-card;
+ struct snd_soc_card_drvdata_davinci *drvdata =
+ (struct snd_soc_card_drvdata_davinci *)
+ snd_soc_card_get_drvdata(soc_card);
+ struct snd_mask *fmt = constrs_mask(runtime-hw_constraints,
+ SNDRV_PCM_HW_PARAM_FORMAT);
+ snd_mask_none(fmt);
+ snd_mask_set(fmt, TDA998X_SAMPLE_FORMAT);
+
+ runtime-hw.rate_min = drvdata-rate_constraint-list[0];
+ runtime-hw.rate_max = drvdata-rate_constraint-list[
+ drvdata-rate_constraint-count - 1];
+ runtime-hw.rates = SNDRV_PCM_RATE_KNOT;
+
+ snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
+ drvdata-rate_constraint);
+ snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_CHANNELS,
+2, 2);
+
+ return evm_startup(substream);
+}
+
+static unsigned int evm_get_bclk(struct snd_pcm_hw_params *params)
+{
+ int sample_size = snd_pcm_format_width(params_format(params));
+ int rate = params_rate(params);
+ int channels = params_channels(params);
+
+ return sample_size * channels * rate;
+}
+
+static int evm_tda998x_hw_params(struct snd_pcm_substream *substream,
+struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream-private_data;
+ struct snd_soc_dai *cpu_dai = rtd-cpu_dai;
+ struct snd_soc_codec *codec = rtd-codec;
+ struct snd_soc_card *soc_card = codec-card;
+ struct platform_device *pdev = to_platform_device(soc_card-dev);
+ unsigned int bclk_freq = evm_get_bclk(params);
+ unsigned sysclk = ((struct snd_soc_card_drvdata_davinci *)
+ snd_soc_card_get_drvdata(soc_card))-sysclk;
+ int ret;
+
+ ret = snd_soc_dai_set_clkdiv(cpu_dai, 1, sysclk / bclk_freq);
+ if (ret 0) {
+ dev_err(pdev-dev, can't set CPU DAI clock divider %d\n,
+ ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(cpu_dai, 0, sysclk, SND_SOC_CLOCK_IN);
+ if (ret 0)
+ return ret;
+
+ return ret;
+}
+
static struct snd_soc_ops evm_ops = {
.startup = evm_startup,
.shutdown = evm_shutdown,
.hw_params = evm_hw_params,
};
+static struct
[PATCH RFC v2 REPOST 4/8] ASoC: hdmi-codec: Add devicetree binding with documentation
Signed-off-by: Jyri Sarha jsa...@ti.com
cc: bcous...@baylibre.com
---
Documentation/devicetree/bindings/sound/hdmi.txt | 17 +
sound/soc/codecs/hdmi.c | 10 ++
2 files changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/hdmi.txt
diff --git a/Documentation/devicetree/bindings/sound/hdmi.txt
b/Documentation/devicetree/bindings/sound/hdmi.txt
new file mode 100644
index 000..31af7bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/hdmi.txt
@@ -0,0 +1,17 @@
+Device-Tree bindings for dummy HDMI codec
+
+Required properties:
+ - compatible: should be linux,hdmi-audio.
+
+CODEC output pins:
+ * TX
+
+CODEC input pins:
+ * RX
+
+Example node:
+
+ hdmi_audio: hdmi_audio@0 {
+ compatible = linux,hdmi-audio;
+ status = okay;
+ };
diff --git a/sound/soc/codecs/hdmi.c b/sound/soc/codecs/hdmi.c
index 32797a8..9cb1c7d 100644
--- a/sound/soc/codecs/hdmi.c
+++ b/sound/soc/codecs/hdmi.c
@@ -20,6 +20,7 @@
*/
#include linux/module.h
#include sound/soc.h
+#include linux/of_device.h
#define DRV_NAME hdmi-audio-codec
@@ -60,6 +61,14 @@ static struct snd_soc_dai_driver hdmi_codec_dai = {
};
+#ifdef CONFIG_OF
+static const struct of_device_id hdmi_audio_codec_ids[] = {
+ { .compatible = linux,hdmi-audio, },
+ { }
+};
+MODULE_DEVICE_TABLE(of, hdmi_audio_codec_ids);
+#endif
+
static struct snd_soc_codec_driver hdmi_codec = {
.dapm_widgets = hdmi_widgets,
.num_dapm_widgets = ARRAY_SIZE(hdmi_widgets),
@@ -83,6 +92,7 @@ static struct platform_driver hdmi_codec_driver = {
.driver = {
.name = DRV_NAME,
.owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(hdmi_audio_codec_ids),
},
.probe = hdmi_codec_probe,
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC v2 REPOST 5/8] ASoC: davinci: HDMI audio build for AM33XX and TDA998x
Adds configuration option for HDMI audio support for AM33XX based boards with NXP TDA998x HDMI transmitter. The audio is connected to NXP TDA998x trough McASP running in i2s mode. Signed-off-by: Jyri Sarha jsa...@ti.com --- sound/soc/davinci/Kconfig | 12 sound/soc/davinci/Makefile |1 + 2 files changed, 13 insertions(+) diff --git a/sound/soc/davinci/Kconfig b/sound/soc/davinci/Kconfig index a8ec1fc..40dd5d1 100644 --- a/sound/soc/davinci/Kconfig +++ b/sound/soc/davinci/Kconfig @@ -26,6 +26,18 @@ config SND_AM33XX_SOC_EVM AM335X-EVMSK, and BeagelBone with AudioCape boards have this setup. +config SND_AM335X_SOC_NXPTDA_EVM + tristate HDMI Audio for the AM33XX chip based boards with TDA998x + depends on SND_DAVINCI_SOC SOC_AM33XX + depends on DRM_TILCDC DRM_I2C_NXP_TDA998X + select SND_SOC_HDMI_CODEC + select SND_DAVINCI_SOC_MCASP + help + Say Y or M if you want to add support for HDMI SoC audio on + AM33XX boards with NXP TDA998x HDMI transmitter. For example + BeagleBoneBack. The audio is connected to NXP TDA998x trough + McASP running in i2s mode. + config SND_DAVINCI_SOC_EVM tristate SoC Audio support for DaVinci DM6446, DM355 or DM365 EVM depends on SND_DAVINCI_SOC diff --git a/sound/soc/davinci/Makefile b/sound/soc/davinci/Makefile index 744d4d9..7587a70 100644 --- a/sound/soc/davinci/Makefile +++ b/sound/soc/davinci/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_SND_DAVINCI_SOC_VCIF) += snd-soc-davinci-vcif.o snd-soc-evm-objs := davinci-evm.o obj-$(CONFIG_SND_DAVINCI_SOC_GENERIC_EVM) += snd-soc-evm.o +obj-$(CONFIG_SND_AM335X_SOC_NXPTDA_EVM) += snd-soc-evm.o -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC v2 REPOST 6/8] drm/tilcdc: Add I2C HDMI audio config for tda998x
The configuration is needed for HDMI audio. The swap and mirr
parameters have to be correctly set in the configuration in order to
have proper colors in the HDMI picture.
Signed-off-by: Jyri Sarha jsa...@ti.com
cc: airl...@linux.ie
---
drivers/gpu/drm/tilcdc/tilcdc_slave.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave.c
b/drivers/gpu/drm/tilcdc/tilcdc_slave.c
index 595068b..e43240a 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_slave.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_slave.c
@@ -19,6 +19,7 @@
#include linux/pinctrl/pinmux.h
#include linux/pinctrl/consumer.h
#include drm/drm_encoder_slave.h
+#include drm/i2c/tda998x.h
#include tilcdc_drv.h
@@ -111,8 +112,29 @@ static const struct drm_encoder_helper_funcs
slave_encoder_helper_funcs = {
.restore= drm_i2c_encoder_restore,
};
+static struct tda998x_encoder_params tda998x_pdata = {
+ .swap_b = 0x3,
+ .mirr_b = 0x0,
+ .swap_a = 0x2,
+ .mirr_a = 0x0,
+ .swap_d = 0x1,
+ .mirr_d = 0x0,
+ .swap_c = 0x0,
+ .mirr_c = 0x0,
+ .swap_f = 0x5,
+ .mirr_f = 0x0,
+ .swap_e = 0x4,
+ .mirr_e = 0x0,
+ .audio_cfg = 0x3, /* I2S mode */
+ .audio_clk_cfg = 1, /* select clock pin */
+ .audio_frame[1] = 1,/* channels - 1 */
+ .audio_format = AFMT_I2S,
+ .audio_sample_rate = 48000,
+};
+
static const struct i2c_board_info info = {
- I2C_BOARD_INFO(tda998x, 0x70)
+ I2C_BOARD_INFO(tda998x, 0x70),
+ .platform_data = tda998x_pdata,
};
static struct drm_encoder *slave_encoder_create(struct drm_device *dev,
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC v2 REPOST 7/8] ARM: OMAP2+: omap2plus_defconfig: Enable tilcdc and TDA998X HDMI support
This enables HDMI video support on Beaglebone-Black. Signed-off-by: Jyri Sarha jsa...@ti.com cc: t...@atomide.com --- arch/arm/configs/omap2plus_defconfig |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 254cf05..52b0d92 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -176,6 +176,9 @@ CONFIG_REGULATOR_TPS65023=y CONFIG_REGULATOR_TPS6507X=y CONFIG_REGULATOR_TPS65217=y CONFIG_REGULATOR_TPS65910=y +CONFIG_DRM=m +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_TILCDC=m CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_MODE_HELPERS=y -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC v2 REPOST 8/8] ARM: OMAP2+: omap2plus_defconfig: Enable BeagleBone Black HDMI audio support
Select following: CONFIG_SND_DAVINCI_SOC=m CONFIG_SND_AM335X_SOC_NXPTDA_EVM=m Signed-off-by: Jyri Sarha jsa...@ti.com cc: t...@atomide.com --- arch/arm/configs/omap2plus_defconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 52b0d92..c1a9730 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -216,6 +216,8 @@ CONFIG_SND_OMAP_SOC=m CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m +CONFIG_SND_DAVINCI_SOC=m +CONFIG_SND_AM335X_SOC_NXPTDA_EVM=m CONFIG_USB=y CONFIG_USB_DEBUG=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv11 01/49] clk: add support for registering clocks from description
On Thu, 19 Dec 2013, Tero Kristo wrote:
From: Mike Turquette mturquet...@linaro.org
Is this E-mail address correct? It's one byte off of the Signed-off-by:
address.
clk_register_desc is the primary interface for populating the clock tree
with new clock nodes. In time, this will replace the various hardware-specific
registration functions (e.g. clk_register_gate).
Signed-off-by: Mike Turquette mturque...@linaro.org
Signed-off-by: Tero Kristo t-kri...@ti.com
---
...
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 2cf2ea6..29281f6 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1905,6 +1905,77 @@ fail_out:
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7e59253..7fddcb3 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -161,6 +161,28 @@ struct clk_init_data {
};
/**
+ * struct clk_desc - clock init descriptor for providing init time parameters
+ * for a clock.
+ *
+ * @name: clock name
As mentioned in
http://patchwork.ozlabs.org/patch/294253/
please remove the blank line between the summary line and the arguments.
Documentation/kernel-doc-nano.txt says:
The @argument descriptions must begin on the very next line following
this opening short function description line, with no intervening
empty comment lines.
- Paul
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv11 04/49] clk: mux: add support for registering mux clock from descriptor
On Thu, 19 Dec 2013, Tero Kristo wrote:
New clk_register_desc() call can be used to register this clock type now.
Signed-off-by: Tero Kristo t-kri...@ti.com
...
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 9fa279d..7dd6842 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -393,6 +393,26 @@ struct clk_mux {
spinlock_t *lock;
};
+/**
+ * struct clk_mux_desc - init descriptor for multiplexer clock
+ *
+ * @desc:handle between common and hardware-specific interfaces
As mentioned in
http://patchwork.ozlabs.org/patch/294253/
please remove the blank line between the summary line and the arguments.
Documentation/kernel-doc-nano.txt says:
The @argument descriptions must begin on the very next line following
this opening short function description line, with no intervening
empty comment lines.
- Paul
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv11 03/49] clk: divider: add support for registering divider clock from descriptor
On Thu, 19 Dec 2013, Tero Kristo wrote:
New clk_register_desc() call can be used to register this clock type now.
Signed-off-by: Tero Kristo t-kri...@ti.com
...
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 82dfe84..9fa279d 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -323,11 +323,34 @@ struct clk_divider {
spinlock_t *lock;
};
+/**
+ * struct clk_divider_desc - init descriptor for divider clock
+ *
+ * @desc:handle between common and hardware-specific interfaces
As mentioned in
http://patchwork.ozlabs.org/patch/294253/
please remove the blank line between the summary line and the arguments.
Documentation/kernel-doc-nano.txt says:
The @argument descriptions must begin on the very next line following
this opening short function description line, with no intervening
empty comment lines.
- Paul
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv11 05/49] clk: gate: add support for registering gate clock from descriptor
On Thu, 19 Dec 2013, Tero Kristo wrote:
New clk_register_desc() call can be used to register this clock type now.
Signed-off-by: Tero Kristo t-kri...@ti.com
...
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7dd6842..27a9765 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -269,10 +269,29 @@ struct clk_gate {
spinlock_t *lock;
};
+/**
+ * struct clk_gate_desc - init descriptor for gating clock
+ *
+ * @desc:handle between common and hardware-specific interfaces
I like the kernel-doc-nano, but as mentioned in
http://patchwork.ozlabs.org/patch/294253/
please remove the blank line between the summary line and the arguments.
Documentation/kernel-doc-nano.txt says:
The @argument descriptions must begin on the very next line following
this opening short function description line, with no intervening
empty comment lines.
- Paul
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv11 06/49] clk: add support for low level register ops
On Thu, 19 Dec 2013, Tero Kristo wrote:
Low level register ops are needed for providing SoC or IP block specific
access routines to clock registers. Subsequent patches add support for
the low level ops for the individual clock drivers.
Signed-off-by: Tero Kristo t-kri...@ti.com
...
---
drivers/clk/clk.c| 28
include/linux/clk-provider.h | 13 +
2 files changed, 41 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 29281f6..23a742b 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -34,6 +34,34 @@ static HLIST_HEAD(clk_root_list);
static HLIST_HEAD(clk_orphan_list);
static LIST_HEAD(clk_notifier_list);
+/**
+ * clk_readl_default - default clock register read support function
+ * @reg: register to read
+ *
+ * Default implementation for reading a clock register.
+ */
+static u32 clk_readl_default(u32 __iomem *reg)
Why u32 __iomem rather than void *? Not that this will affect OMAP, but
will this need to be changed later to support 64-bit addresses?
__raw_writel() and __raw_readl() are defined with void __iomem * as
their address argument, which will be 64 bits on arm64, correct?
+{
+ return readl(reg);
+}
+
+/**
+ * clk_writel_default - default clock register write support function
+ * @val: value to write
+ * @reg: register to write to
+ *
+ * Default implementation for writing a clock register.
+ */
+static void clk_writel_default(u32 val, u32 __iomem *reg)
Same question as the above.
+{
+ writel(val, reg);
+}
+
+struct clk_ll_ops clk_ll_ops_default = {
+ .clk_readl = clk_readl_default,
+ .clk_writel = clk_writel_default
+};
+
/*** locking ***/
static void clk_prepare_lock(void)
{
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 27a9765..cc5bee0 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -199,6 +199,24 @@ struct clk_hw {
const struct clk_init_data *init;
};
+/**
+ * struct clk_ll_ops - low-level register access ops for a clock
+ *
+ * @clk_readl: pointer to register read function
Please remove the blank line above as mentioned before.
+ * @clk_writel: pointer to register write function
+ *
+ * Low-level register access ops are generally used by the basic clock types
+ * (clk-gate, clk-mux, clk-divider etc.) to provide support for various
+ * low-level hardware interfaces (direct MMIO, regmap etc.), but can also be
+ * used by other hardware-specific clock drivers if needed.
+ */
+struct clk_ll_ops {
+ u32 (*clk_readl)(u32 __iomem *reg);
+ void(*clk_writel)(u32 val, u32 __iomem *reg);
+};
+
+extern struct clk_ll_ops clk_ll_ops_default;
+
/*
* DOC: Basic clock implementations common to many platforms
*
--
1.7.9.5
- Paul
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv10 21/41] ARM: dts: omap4 clock data
On Tue, 17 Dec 2013, Tero Kristo wrote:
On 12/17/2013 11:44 AM, Paul Walmsley wrote:
On Tue, 26 Nov 2013, Tero Kristo wrote:
This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.
Signed-off-by: Tero Kristo t-kri...@ti.com
...
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index a1e0585..c2e3993 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -107,6 +107,34 @@
interrupts = GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
+ cm1: cm1@4a004000 {
+ compatible = ti,clock-master;
These devices are low-level IP blocks, and should have accurate compatible
strings like any other low-level IP block. At some point in the future,
these IP blocks will have device driver code that matches up with these DT
nodes, and is probed via these compatible strings. These should be
corrected now, so unnecessary DT data synchronization problems don't
appear with later kernels.
So this should be something like:
compatible = ti,omap4-cm1;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x4a004000 0x2000;
+ };
+
+ prm: prm@4a306000 {
+ compatible = ti,clock-master;
Similarly this should be
compatible = ti,omap4-prm;
How about just adding dual compatible strings? Keep the current one and add
the other as extra.
compatible = ti,clock-master, ti,omap4-prm;
Easier to handle it this way.
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x4a306000 0x3000;
+ };
+
+ cm2: cm2@4a008000 {
+ compatible = ti,clock-master;
compatible = ti,omap4-cm2;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x4a008000 0x3000;
+ };
+
+ scrm: scrm@4a30a000 {
+ compatible = ti,clock-master;
compatible = ti,omap4-scrm;
...
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi
b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 000..643755b
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+prm {
+ bandgap_fclk: bandgap_fclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = sys_32k_ck;
+ ti,bit-shift = 8;
+ reg = 0x1888;
+ };
So we've already discussed that clocks should be moved underneath
separate clocks { node in the IP block data. And similarly...
Yeah, I have actually wip v11 which has this done. I ended up creating this
though:
...
prm {
prm_clocks: clocks {
};
};
... and references like:
prm_clocks {
};
It seems the references to existing clocks {} nodes is impossible otherwise as
I need to add some extra clocks to these.
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi
b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 000..2b59d54
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
...
+ emu_sys_clkdm: emu_sys_clkdm {
+ compatible = ti,clockdomain;
+ clocks = trace_clk_div_ck;
+ };
... all of the clockdomains should be moved underneath clockdomains {
nodes in the IP block DT data.
Ok that can be done.
Thanks for making these changes; the data looks better now.
- Paul
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv11 06/49] clk: add support for low level register ops
On 12/20/2013 01:00 PM, Paul Walmsley wrote:
On Thu, 19 Dec 2013, Tero Kristo wrote:
Low level register ops are needed for providing SoC or IP block specific
access routines to clock registers. Subsequent patches add support for
the low level ops for the individual clock drivers.
Signed-off-by: Tero Kristo t-kri...@ti.com
...
---
drivers/clk/clk.c| 28
include/linux/clk-provider.h | 13 +
2 files changed, 41 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 29281f6..23a742b 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -34,6 +34,34 @@ static HLIST_HEAD(clk_root_list);
static HLIST_HEAD(clk_orphan_list);
static LIST_HEAD(clk_notifier_list);
+/**
+ * clk_readl_default - default clock register read support function
+ * @reg: register to read
+ *
+ * Default implementation for reading a clock register.
+ */
+static u32 clk_readl_default(u32 __iomem *reg)
Why u32 __iomem rather than void *? Not that this will affect OMAP, but
will this need to be changed later to support 64-bit addresses?
__raw_writel() and __raw_readl() are defined with void __iomem * as
their address argument, which will be 64 bits on arm64, correct?
Just copy pasting the current implementation from the clk-provider.h file.
However, pointer is pointer no? This is just used to refer to a 32bit
value, the pointer itself can be either 32bit or 64bit. If the registers
are changed to be 64 bit though but that will require changing most
of the clock code as it is littered with 'u32 val;' type declarations.
Anyway, I can change this to be void __iomem.
+{
+ return readl(reg);
+}
+
+/**
+ * clk_writel_default - default clock register write support function
+ * @val: value to write
+ * @reg: register to write to
+ *
+ * Default implementation for writing a clock register.
+ */
+static void clk_writel_default(u32 val, u32 __iomem *reg)
Same question as the above.
+{
+ writel(val, reg);
+}
+
+struct clk_ll_ops clk_ll_ops_default = {
+ .clk_readl = clk_readl_default,
+ .clk_writel = clk_writel_default
+};
+
/*** locking ***/
static void clk_prepare_lock(void)
{
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 27a9765..cc5bee0 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -199,6 +199,24 @@ struct clk_hw {
const struct clk_init_data *init;
};
+/**
+ * struct clk_ll_ops - low-level register access ops for a clock
+ *
+ * @clk_readl: pointer to register read function
Please remove the blank line above as mentioned before.
Yea I just copy pasted the comment sections
+ * @clk_writel: pointer to register write function
+ *
+ * Low-level register access ops are generally used by the basic clock types
+ * (clk-gate, clk-mux, clk-divider etc.) to provide support for various
+ * low-level hardware interfaces (direct MMIO, regmap etc.), but can also be
+ * used by other hardware-specific clock drivers if needed.
+ */
+struct clk_ll_ops {
+ u32 (*clk_readl)(u32 __iomem *reg);
+ void(*clk_writel)(u32 val, u32 __iomem *reg);
+};
+
+extern struct clk_ll_ops clk_ll_ops_default;
+
/*
* DOC: Basic clock implementations common to many platforms
*
--
1.7.9.5
- Paul
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP display subsystem - does it work?
On Thu, Dec 19, 2013 at 10:22:53AM -0800, Tony Lindgren wrote:
* Russell King - ARM Linux li...@arm.linux.org.uk [131219 09:58]:
On Wed, Dec 18, 2013 at 10:23:54AM -0800, Tony Lindgren wrote:
* Tomi Valkeinen tomi.valkei...@ti.com [131218 05:56]:
I don't have an LDP board at hand, and I wasn't able to find out
anything from
the logs.
I think I should change omapfb to print something if it's probed
succesfully,
as the deferred probing makes finding out if something is probed fine
or not
quite murky. Without deferred probing, it was simpler: no errors - the
driver
must be (most likely) ok.
Although... In an earlier log, where there was no panel driver, the log
has
these errors:
Error opening /dev/fb0: No such device
There are none in the latest log, which makes me guess the omapfb has
been
probed, and fb0 is actually there. But the X is still dying for some
reason...
I'll look at this more. Maybe someone in our team can find a board to
test.
Hmm I had the framebuffer working with DT on LDP after fixing the twl4030
gpio regression with 0b2aa8bed3e1 (gpio: twl4030: Fix regression for twl
gpio output) using this pdata quirks patch:
[PATCH 3/5] ARM: OMAP2+: Add DT init code for DPI displays and make omap3
LDP to use it
AFAIK the pdata hack above should not be needed now, but I have not tried
with Tomi's DSS DT patches yet.
Tomi do you have some sample panel dpi .dts entry somewhere for the LDP I
could try at some point?
Russell, maybe all you're missing is just omapfb.vram=0:2M,1:5M or similar
from your kernel cmdline?
Note that I'm trying to get non-DT stuff working properly here first, in
such a state that it has done in the past with mainline kernels. This is
quite an old regression, but it's still a regression nevertheless.
Yeah that should just work now.
I've just built and booted a kernel with the backlight support in. No
change.
I just tried it here with v3.13-rc4 in legacy mode using omap2plus_defconfig
with the following test script and seems to work just fine for producing a
nice random color pattern on the LCD:
#!/bin/sh
mount -o rw,remount /
depmod -a
modprobe panel-generic-dpi
modprobe panel-dpi
modprobe omapfb vram=0:2M,1:5M
if [ -c /dev/fb0 ]; then
dd if=/dev/urandom of=/dev/fb0;
fi
Note that as the panel name has changed recently so my script tries to
load both panel modules.
I don't think the problem is with the creation of the framebuffer.
Maybe you're missing something from your .config file still?
Maybe, but that's the problem - finding out what is missing. This is the
endless problem where things keep changing - it's very difficult to keep
a working configuration working because the config symbols keep changing.
Also, bear in mind that there's many different variants of the LDP hardware
with stuff connected up in different ways (I'm aware that the keypad is
just randomly allocated). I wouldn't be surprised if this also applied
to how the backlight on the LCD was done.
BTW, I'm seeing MMC errors with my LDP here though, does that work
for you?
I see no errors there.
Okay, while digging through the changes, I found this - this is the old
code. gpio + 15 is the backlight enable GPIO.
static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned
ngpio)
{
- ldp_panel_data.gpios[0] = gpio + 7;
- ldp_panel_data.gpio_invert[0] = true;
- ldp_panel_data.gpios[1] = gpio + 15;
- ldp_panel_data.gpio_invert[1] = true;
return 0;
}
...
-static int generic_dpi_panel_power_on(struct omap_dss_device *dssdev)
-{
...
- for (i = 0; i panel_data-num_gpios; ++i) {
- gpio_set_value_cansleep(panel_data-gpios[i],
- panel_data-gpio_invert[i] ? 0 : 1);
- }
-static void generic_dpi_panel_power_off(struct omap_dss_device *dssdev)
-{
...
- for (i = panel_data-num_gpios - 1; i = 0; --i) {
- gpio_set_value_cansleep(panel_data-gpios[i],
- panel_data-gpio_invert[i] ? 1 : 0);
- }
-static int generic_dpi_panel_probe(struct omap_dss_device *dssdev)
-{
- for (i = 0; i panel_data-num_gpios; ++i) {
- r = devm_gpio_request_one(dssdev-dev, panel_data-gpios[i],
- panel_data-gpio_invert[i] ?
- GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
- panel gpio);
- if (r)
- return r;
- }
So, when gpio_invert[] is set, the signal is active low for on. What
does the new code do?
static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned
ngpio)
{
+ /* LCD enable GPIO */
+ ldp_lcd_pdata.enable_gpio = gpio + 7;
+ /* Backlight enable GPIO */
+
Re: [alsa-devel] [PATCH RFC v2 REPOST 0/8] Beaglebone-Black HDMI audio
On Fri, Dec 20, 2013 at 12:36:56PM +0200, Jyri Sarha wrote: Changes since the first RFC version of the patches: Please don't bury your e-mails in the middle of old threads, that's a good way of getting them missed. signature.asc Description: Digital signature
Re: [PATCH v6 5/7] ARM: dts: add pbias dt node
On Thursday 19 December 2013 10:03 PM, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131219 04:40]:
@@ -485,6 +503,7 @@
dmas = sdma 61, sdma 62;
dma-names = tx, rx;
status = disabled;
+ pbias-supply = pbias_mmc_reg;
};
mmc2: mmc@480b4000 {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index d624345..f127901 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -29,6 +29,24 @@
pinctrl-single,function-mask = 0x3f;
};
+ omap2_scm_general: tisyscon@49002270 {
+ compatible = ti,control-syscon, syscon,
simple-bus;
+ reg = 0x49002270 0x240;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ pbias_regulator: pbias_regulator {
+ compatible = ti,pbias-omap;
+ reg = 0x230 0x4;
+ pbias_mmc_reg: pbias_mmc_omap3 {
+ regulator-name = pbias_mmc_omap3;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 300;
+ regulator-enable-ramp-delay = 100;
+ };
+ };
+ };
+
gpio1: gpio@4900c000 {
compatible = ti,omap2-gpio;
reg = 0x4900c000 0x200;
Here too you may need to set up pbias_mmc_omap2430?
2430 pbias reg config is same as 3430/3630 w.r.t to mmc pbias i/o,
hence using the same name, if you think regulator name needs to be changed
let me know the more appropriate one.
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/2] ARM: dts: tps65910 backup battery regulator
This patch adds a devicetree node for the backup battery regulator.
Signed-off-by: Markus Pargmann m...@pengutronix.de
---
arch/arm/boot/dts/tps65910.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi
index 92693a8..b0ac665 100644
--- a/arch/arm/boot/dts/tps65910.dtsi
+++ b/arch/arm/boot/dts/tps65910.dtsi
@@ -82,5 +82,10 @@
reg = 12;
regulator-compatible = vmmc;
};
+
+ vbb_reg: regulator@13 {
+ reg = 13;
+ regulator-compatible = vbb;
+ };
};
};
--
1.8.5.1
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/2] regulator: tps65910: backup battery regulator
Hi, backup battery charger regulator for tps65910. Regards, Markus Changes in v2: - Seperate ops for vbb to reduce performance impact for other regulators on voltage mapping - Usage of switch statements Markus Pargmann (2): regulator: tps65910: Add backup battery regulator ARM: dts: tps65910 backup battery regulator Documentation/devicetree/bindings/mfd/tps65910.txt | 4 +- arch/arm/boot/dts/tps65910.dtsi| 5 ++ drivers/regulator/tps65910-regulator.c | 56 +- include/linux/mfd/tps65910.h | 3 +- 4 files changed, 64 insertions(+), 4 deletions(-) -- 1.8.5.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/2] regulator: tps65910: Add backup battery regulator
tps65910 has a backup battery charger with a configurable voltage. This
patch adds a regulator for the backup battery.
Signed-off-by: Markus Pargmann m...@pengutronix.de
---
Documentation/devicetree/bindings/mfd/tps65910.txt | 4 +-
drivers/regulator/tps65910-regulator.c | 56 +-
include/linux/mfd/tps65910.h | 3 +-
3 files changed, 59 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/tps65910.txt
b/Documentation/devicetree/bindings/mfd/tps65910.txt
index 2e33048..b4bd98a 100644
--- a/Documentation/devicetree/bindings/mfd/tps65910.txt
+++ b/Documentation/devicetree/bindings/mfd/tps65910.txt
@@ -21,7 +21,7 @@ Required properties:
The valid regulator-compatible values are:
tps65910: vrtc, vio, vdd1, vdd2, vdd3, vdig1, vdig2, vpll, vdac, vaux1,
-vaux2, vaux33, vmmc
+vaux2, vaux33, vmmc, vbb
tps65911: vrtc, vio, vdd1, vdd3, vddctrl, ldo1, ldo2, ldo3, ldo4, ldo5,
ldo6, ldo7, ldo8
@@ -38,7 +38,7 @@ Required properties:
vcc4-supply: VAUX1 and VAUX2 input.
vcc5-supply: VPLL and VDAC input.
vcc6-supply: VDIG1 and VDIG2 input.
- vcc7-supply: VRTC input.
+ vcc7-supply: VRTC and VBB input.
vccio-supply: VIO input.
tps65911:
vcc1-supply: VDD1 input.
diff --git a/drivers/regulator/tps65910-regulator.c
b/drivers/regulator/tps65910-regulator.c
index a00132e..979ea0a 100644
--- a/drivers/regulator/tps65910-regulator.c
+++ b/drivers/regulator/tps65910-regulator.c
@@ -88,6 +88,11 @@ static const unsigned int VMMC_VSEL_table[] = {
180, 280, 300, 330,
};
+/* supported BBCH voltages in microvolts */
+static const unsigned int VBB_VSEL_table[] = {
+ 300, 252, 315, 500,
+};
+
struct tps_info {
const char *name;
const char *vin_name;
@@ -183,6 +188,12 @@ static struct tps_info tps65910_regs[] = {
.voltage_table = VMMC_VSEL_table,
.enable_time_us = 100,
},
+ {
+ .name = vbb,
+ .vin_name = vcc7,
+ .n_voltages = ARRAY_SIZE(VBB_VSEL_table),
+ .voltage_table = VBB_VSEL_table,
+ },
};
static struct tps_info tps65911_regs[] = {
@@ -339,6 +350,8 @@ static int tps65910_get_ctrl_register(int id)
return TPS65910_VAUX33;
case TPS65910_REG_VMMC:
return TPS65910_VMMC;
+ case TPS65910_REG_VBB:
+ return TPS65910_BBCH;
default:
return -EINVAL;
}
@@ -528,6 +541,10 @@ static int tps65910_get_voltage_sel(struct regulator_dev
*dev)
value = LDO_SEL_MASK;
value = LDO_SEL_SHIFT;
break;
+ case TPS65910_REG_VBB:
+ value = BBCH_BBSEL_MASK;
+ value = BBCH_BBSEL_SHIFT;
+ break;
default:
return -EINVAL;
}
@@ -638,6 +655,9 @@ static int tps65910_set_voltage_sel(struct regulator_dev
*dev,
case TPS65910_REG_VMMC:
return tps65910_reg_update_bits(pmic-mfd, reg, LDO_SEL_MASK,
selector LDO_SEL_SHIFT);
+ case TPS65910_REG_VBB:
+ return tps65910_reg_update_bits(pmic-mfd, reg, BBCH_BBSEL_MASK,
+ selector BBCH_BBSEL_SHIFT);
}
return -EINVAL;
@@ -669,6 +689,9 @@ static int tps65911_set_voltage_sel(struct regulator_dev
*dev,
case TPS65910_REG_VIO:
return tps65910_reg_update_bits(pmic-mfd, reg, LDO_SEL_MASK,
selector LDO_SEL_SHIFT);
+ case TPS65910_REG_VBB:
+ return tps65910_reg_update_bits(pmic-mfd, reg, BBCH_BBSEL_MASK,
+ selector BBCH_BBSEL_SHIFT);
}
return -EINVAL;
@@ -762,6 +785,18 @@ static struct regulator_ops tps65910_ops_vdd3 = {
.map_voltage= regulator_map_voltage_ascend,
};
+static struct regulator_ops tps65910_ops_vbb = {
+ .is_enabled = regulator_is_enabled_regmap,
+ .enable = regulator_enable_regmap,
+ .disable= regulator_disable_regmap,
+ .set_mode = tps65910_set_mode,
+ .get_mode = tps65910_get_mode,
+ .get_voltage_sel= tps65910_get_voltage_sel,
+ .set_voltage_sel= tps65910_set_voltage_sel,
+ .list_voltage = regulator_list_voltage_table,
+ .map_voltage= regulator_map_voltage_iterate,
+};
+
static struct regulator_ops tps65910_ops = {
.is_enabled = regulator_is_enabled_regmap,
.enable = regulator_enable_regmap,
@@ -944,6 +979,7 @@ static struct of_regulator_match tps65910_matches[] = {
{ .name = vaux2, .driver_data =
Re: [PATCHv11 18/49] CLK: TI: add support for clockdomain binding
On Thu, 19 Dec 2013, Tero Kristo wrote:
Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks.
At least on OMAP4 and 5, clockdomains can be either collections of clocks
or collections of IP blocks. In other words, clockdomain was a horrible
name: it's really an idle-domain or something similar to that.
Benoit might recall the details. So you might want to add comments to
that effect so folks don't get the wrong idea that they are specific to
clocks on all OMAPs.
The clockdomain handling isn't ideal - I guess it should probably be part
of the low-level PRM/CM IP block drivers that are currently in
arch/arm/mach-omap2/* - but I think we can move it there later, unless you
see a problem with that.
Also I guess there's no need for clockdomain compatible strings any more,
since those can just be registered by iterating through the clockdomains
{ node children. But I guess we can move that later too.
- Paul
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/clockdomain.txt | 24 +++
drivers/clk/ti/Makefile|3 +-
drivers/clk/ti/clockdomain.c | 70
include/linux/clk/ti.h |1 +
4 files changed, 97 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/clockdomain.txt
create mode 100644 drivers/clk/ti/clockdomain.c
diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
new file mode 100644
index 000..cb76b3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
@@ -0,0 +1,24 @@
+Binding for Texas Instruments clockdomain.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1] in consumer role.
+Every clock on TI SoC belongs to one clockdomain, but software
+only needs this information for specific clocks which require
+their parent clockdomain to be controlled when the clock is
+enabled/disabled. This binding doesn't define a new clock
+binding type, it is used to group existing clock nodes under
+hardware hierarchy.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be ti,clockdomain
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of clocks within this domain
+
+Examples:
+ dss_clkdm: dss_clkdm {
+ compatible = ti,clockdomain;
+ clocks = dss1_alwon_fck_3430es2, dss_ick_3430es2;
+ };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 7cba389..67056fb 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,5 @@
ifneq ($(CONFIG_OF),)
obj-y+= clk.o dpll.o autoidle.o
divider.o \
-fixed-factor.o gate.o composite.o
+fixed-factor.o gate.o clockdomain.o \
+composite.o
endif
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
new file mode 100644
index 000..f1e0038
--- /dev/null
+++ b/drivers/clk/ti/clockdomain.c
@@ -0,0 +1,70 @@
+/*
+ * OMAP clockdomain support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo t-kri...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk-provider.h
+#include linux/slab.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk/ti.h
+
+#undef pr_fmt
+#define pr_fmt(fmt) %s: fmt, __func__
+
+static void __init of_ti_clockdomain_setup(struct device_node *node)
+{
+ struct clk *clk;
+ struct clk_hw *clk_hw;
+ const char *clkdm_name = node-name;
+ int i;
+ int num_clks;
+
+ num_clks = of_count_phandle_with_args(node, clocks, #clock-cells);
+
+ for (i = 0; i num_clks; i++) {
+ clk = of_clk_get(node, i);
+ if (__clk_get_flags(clk) CLK_IS_BASIC) {
+ pr_warn(can't setup clkdm for basic clk %s\n,
+ __clk_get_name(clk));
+ continue;
+ }
+ clk_hw = __clk_get_hw(clk);
+ to_clk_hw_omap(clk_hw)-clkdm_name =
Re: OMAP display subsystem - does it work?
On Fri, Dec 20, 2013 at 11:27:01AM +, Russell King - ARM Linux wrote: Maybe, but that's the problem - finding out what is missing. This is the endless problem where things keep changing - it's very difficult to keep a working configuration working because the config symbols keep changing. Also, bear in mind that there's many different variants of the LDP hardware with stuff connected up in different ways (I'm aware that the keypad is just randomly allocated). I wouldn't be surprised if this also applied to how the backlight on the LCD was done. Or maybe this is getting buggered by the idiotic deferred probing... It seems that the GPIOs for controlling the LCD and backlight aren't even getting claimed if the DSS modules are built in: # cat /sys/kernel/debug/gpio ... GPIOs 238-255, platform/twl4030_gpio, twl4030, can sleep: # echo panel-dpi.0 /sys/bus/platform/drivers/panel-dpi/unbind # echo panel-dpi.0 /sys/bus/platform/drivers/panel-dpi/bind # cat /sys/kernel/debug/gpio ... GPIOs 238-255, platform/twl4030_gpio, twl4030, can sleep: gpio-245 (panel enable) out lo gpio-253 (panel backlight ) out lo Tony, try this with the stuff not as modules but built-in. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv11 43/49] ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT
On Thu, 19 Dec 2013, Tero Kristo wrote:
This patch provides top level functionality for the DT clock initialization.
Clock tree is initialized hierarchically starting from IP modules
(CM/PRM/PRCM)
going down towards individual clock nodes, and finally initializing
clockdomains once all the clocks are ready.
So just to flag this as something we'll want to deal with later.
The low-level CM* drivers should be responsible for registering CM* clocks
and clockdomains. Similarly the PRM* low-level drivers should only
register PRM* clocks and clockdomains. But it looks to me like we can
rearrange this code later without any significant impact, unless you
foresee any issues with that? If not, in the interests of expediency,
let's take that up in future patches.
- Paul
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/prm.h|1 +
arch/arm/mach-omap2/prm_common.c | 66
++
2 files changed, 67 insertions(+)
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ac25ae6..623db40 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -18,6 +18,7 @@
# ifndef __ASSEMBLER__
extern void __iomem *prm_base;
extern void omap2_set_globals_prm(void __iomem *prm);
+int of_prcm_init(void);
# endif
diff --git a/arch/arm/mach-omap2/prm_common.c
b/arch/arm/mach-omap2/prm_common.c
index a2e1174..835eb7d 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -23,6 +23,10 @@
#include linux/irq.h
#include linux/interrupt.h
#include linux/slab.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk-provider.h
+#include linux/clk/ti.h
#include soc.h
#include prm2xxx_3xxx.h
@@ -30,6 +34,7 @@
#include prm3xxx.h
#include prm44xx.h
#include common.h
+#include clock.h
/*
* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -464,3 +469,64 @@ int prm_unregister(struct prm_ll_data *pld)
return 0;
}
+
+static struct of_device_id omap_prcm_dt_match_table[] = {
+ { .compatible = ti,am3-prcm },
+ { .compatible = ti,am3-scrm },
+ { .compatible = ti,am4-prcm },
+ { .compatible = ti,am4-scrm },
+ { .compatible = ti,omap3-prm },
+ { .compatible = ti,omap3-cm },
+ { .compatible = ti,omap3-scrm },
+ { .compatible = ti,omap4-cm1 },
+ { .compatible = ti,omap4-prm },
+ { .compatible = ti,omap4-cm2 },
+ { .compatible = ti,omap4-scrm },
+ { .compatible = ti,omap5-prm },
+ { .compatible = ti,omap5-cm-core-aon },
+ { .compatible = ti,omap5-scrm },
+ { .compatible = ti,omap5-cm-core },
+ { .compatible = ti,dra7-prm },
+ { .compatible = ti,dra7-cm-core-aon },
+ { .compatible = ti,dra7-cm-core },
+ { }
+};
+
+static struct clk_hw_omap memmap_dummy_ck = {
+ .flags = MEMMAP_ADDRESSING,
+};
+
+static u32 prm_clk_readl(u32 *reg)
+{
+ return omap2_clk_readl(memmap_dummy_ck, reg);
+}
+
+static void prm_clk_writel(u32 val, u32 *reg)
+{
+ omap2_clk_writel(val, memmap_dummy_ck, reg);
+}
+
+static struct clk_ll_ops omap_clk_ll_ops = {
+ .clk_readl = prm_clk_readl,
+ .clk_writel = prm_clk_writel,
+};
+
+int __init of_prcm_init(void)
+{
+ struct device_node *np;
+ void __iomem *mem;
+ int memmap_index = 0;
+
+ ti_clk_ll_ops = omap_clk_ll_ops;
+
+ for_each_matching_node(np, omap_prcm_dt_match_table) {
+ mem = of_iomap(np, 0);
+ clk_memmaps[memmap_index] = mem;
+ ti_dt_clk_init_provider(np, memmap_index);
+ memmap_index++;
+ }
+
+ ti_dt_clockdomains_setup();
+
+ return 0;
+}
--
1.7.9.5
- Paul
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] [PATCH RFC v2 REPOST 0/8] Beaglebone-Black HDMI audio
On 12/20/2013 01:30 PM, Mark Brown wrote: On Fri, Dec 20, 2013 at 12:36:56PM +0200, Jyri Sarha wrote: Changes since the first RFC version of the patches: Please don't bury your e-mails in the middle of old threads, that's a good way of getting them missed. I have done it for my own convenience to find the history of the patch set when ever someone is commenting it. But I'll stop doing that from now on. Best regards, Jyri -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv11 43/49] ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT
On 12/20/2013 01:49 PM, Paul Walmsley wrote:
On Thu, 19 Dec 2013, Tero Kristo wrote:
This patch provides top level functionality for the DT clock initialization.
Clock tree is initialized hierarchically starting from IP modules (CM/PRM/PRCM)
going down towards individual clock nodes, and finally initializing
clockdomains once all the clocks are ready.
So just to flag this as something we'll want to deal with later.
The low-level CM* drivers should be responsible for registering CM* clocks
and clockdomains. Similarly the PRM* low-level drivers should only
register PRM* clocks and clockdomains. But it looks to me like we can
rearrange this code later without any significant impact, unless you
foresee any issues with that? If not, in the interests of expediency,
let's take that up in future patches.
Yeah, this can be split under cm/prm later on once we implement proper
drivers for each block. DT data won't be changed, just kernel side
implementation will be modified, and this modification is relatively
simple to do also.
-Tero
- Paul
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/prm.h|1 +
arch/arm/mach-omap2/prm_common.c | 66 ++
2 files changed, 67 insertions(+)
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ac25ae6..623db40 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -18,6 +18,7 @@
# ifndef __ASSEMBLER__
extern void __iomem *prm_base;
extern void omap2_set_globals_prm(void __iomem *prm);
+int of_prcm_init(void);
# endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index a2e1174..835eb7d 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -23,6 +23,10 @@
#include linux/irq.h
#include linux/interrupt.h
#include linux/slab.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk-provider.h
+#include linux/clk/ti.h
#include soc.h
#include prm2xxx_3xxx.h
@@ -30,6 +34,7 @@
#include prm3xxx.h
#include prm44xx.h
#include common.h
+#include clock.h
/*
* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -464,3 +469,64 @@ int prm_unregister(struct prm_ll_data *pld)
return 0;
}
+
+static struct of_device_id omap_prcm_dt_match_table[] = {
+ { .compatible = ti,am3-prcm },
+ { .compatible = ti,am3-scrm },
+ { .compatible = ti,am4-prcm },
+ { .compatible = ti,am4-scrm },
+ { .compatible = ti,omap3-prm },
+ { .compatible = ti,omap3-cm },
+ { .compatible = ti,omap3-scrm },
+ { .compatible = ti,omap4-cm1 },
+ { .compatible = ti,omap4-prm },
+ { .compatible = ti,omap4-cm2 },
+ { .compatible = ti,omap4-scrm },
+ { .compatible = ti,omap5-prm },
+ { .compatible = ti,omap5-cm-core-aon },
+ { .compatible = ti,omap5-scrm },
+ { .compatible = ti,omap5-cm-core },
+ { .compatible = ti,dra7-prm },
+ { .compatible = ti,dra7-cm-core-aon },
+ { .compatible = ti,dra7-cm-core },
+ { }
+};
+
+static struct clk_hw_omap memmap_dummy_ck = {
+ .flags = MEMMAP_ADDRESSING,
+};
+
+static u32 prm_clk_readl(u32 *reg)
+{
+ return omap2_clk_readl(memmap_dummy_ck, reg);
+}
+
+static void prm_clk_writel(u32 val, u32 *reg)
+{
+ omap2_clk_writel(val, memmap_dummy_ck, reg);
+}
+
+static struct clk_ll_ops omap_clk_ll_ops = {
+ .clk_readl = prm_clk_readl,
+ .clk_writel = prm_clk_writel,
+};
+
+int __init of_prcm_init(void)
+{
+ struct device_node *np;
+ void __iomem *mem;
+ int memmap_index = 0;
+
+ ti_clk_ll_ops = omap_clk_ll_ops;
+
+ for_each_matching_node(np, omap_prcm_dt_match_table) {
+ mem = of_iomap(np, 0);
+ clk_memmaps[memmap_index] = mem;
+ ti_dt_clk_init_provider(np, memmap_index);
+ memmap_index++;
+ }
+
+ ti_dt_clockdomains_setup();
+
+ return 0;
+}
--
1.7.9.5
- Paul
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv11 01/49] clk: add support for registering clocks from description
On 12/20/2013 12:53 PM, Paul Walmsley wrote:
On Thu, 19 Dec 2013, Tero Kristo wrote:
From: Mike Turquette mturquet...@linaro.org
Is this E-mail address correct? It's one byte off of the Signed-off-by:
address.
No it is not, just my typo there. :P Will fix that for next rev.
clk_register_desc is the primary interface for populating the clock tree
with new clock nodes. In time, this will replace the various hardware-specific
registration functions (e.g. clk_register_gate).
Signed-off-by: Mike Turquette mturque...@linaro.org
Signed-off-by: Tero Kristo t-kri...@ti.com
---
...
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 2cf2ea6..29281f6 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1905,6 +1905,77 @@ fail_out:
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7e59253..7fddcb3 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -161,6 +161,28 @@ struct clk_init_data {
};
/**
+ * struct clk_desc - clock init descriptor for providing init time parameters
+ * for a clock.
+ *
+ * @name: clock name
As mentioned in
http://patchwork.ozlabs.org/patch/294253/
please remove the blank line between the summary line and the arguments.
Documentation/kernel-doc-nano.txt says:
Yeah, will do similar changes to other patches also.
-Tero
The @argument descriptions must begin on the very next line following
this opening short function description line, with no intervening
empty comment lines.
- Paul
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP display subsystem - does it work?
On 2013-12-20 13:48, Russell King - ARM Linux wrote: On Fri, Dec 20, 2013 at 11:27:01AM +, Russell King - ARM Linux wrote: Maybe, but that's the problem - finding out what is missing. This is the endless problem where things keep changing - it's very difficult to keep a working configuration working because the config symbols keep changing. Also, bear in mind that there's many different variants of the LDP hardware with stuff connected up in different ways (I'm aware that the keypad is just randomly allocated). I wouldn't be surprised if this also applied to how the backlight on the LCD was done. I need to cook up a patch for the gpio active-low problem. I tried to figure out how to do it with the old GPIO API, but as far as I understand, I have to do it manually in the driver (as it was done in the old driver). Or maybe this is getting buggered by the idiotic deferred probing... It seems that the GPIOs for controlling the LCD and backlight aren't even getting claimed if the DSS modules are built in: # cat /sys/kernel/debug/gpio ... GPIOs 238-255, platform/twl4030_gpio, twl4030, can sleep: # echo panel-dpi.0 /sys/bus/platform/drivers/panel-dpi/unbind # echo panel-dpi.0 /sys/bus/platform/drivers/panel-dpi/bind # cat /sys/kernel/debug/gpio ... GPIOs 238-255, platform/twl4030_gpio, twl4030, can sleep: gpio-245 (panel enable) out lo gpio-253 (panel backlight ) out lo This looks odd... Presuming the panel device was probed successfully, it should always get the gpios or return an error. Only if gpio_is_valid() returns false for the gpio, it skips it and continues. But in this case, the gpio number comes from the platform data, so it should always be valid. And if it wasn't probed successfully, then there shouldn't be a fb0. Tomi signature.asc Description: OpenPGP digital signature
Re: [PATCH] crypto: omap-sham: Fix Polling mode for larger blocks
On Wed, Dec 18, 2013 at 07:03:33PM +0530, Lokesh Vutla wrote: Command tcrypt sec=1 mode=403 give the follwoing error for Polling mode: root@am335x-evm:/# insmod tcrypt.ko sec=1 mode=403 [...] [ 346.982754] test 15 ( 4096 byte blocks, 1024 bytes per update, 4 updates): 4352 opers/sec, 17825792 bytes/sec [ 347.992661] test 16 ( 4096 byte blocks, 4096 bytes per update, 1 updates): 7095 opers/sec, 29061120 bytes/sec [ 349.002667] test 17 ( 8192 byte blocks, 16 bytes per update, 512 updates): [ 349.010882] Unable to handle kernel NULL pointer dereference at virtual address [ 349.020037] pgd = ddeac000 [ 349.022884] [] *pgd=9dcb4831, *pte=, *ppte= [ 349.029816] Internal error: Oops: 17 [#1] PREEMPT SMP ARM [ 349.035482] Modules linked in: tcrypt(+) [ 349.039617] CPU: 0 PID: 1473 Comm: insmod Not tainted 3.12.4-01566-g6279006-dirty #38 [ 349.047832] task: dda91540 ti: ddcd2000 task.ti: ddcd2000 [ 349.053517] PC is at omap_sham_xmit_dma+0x6c/0x238 [ 349.058544] LR is at omap_sham_xmit_dma+0x38/0x238 [ 349.063570] pc : [c04eb7cc]lr : [c04eb798]psr: 2013 [ 349.063570] sp : ddcd3c78 ip : fp : 9d8980b8 [ 349.075610] r10: r9 : r8 : [ 349.081090] r7 : 1000 r6 : dd898000 r5 : 0040 r4 : ddb10550 [ 349.087935] r3 : 0004 r2 : 0010 r1 : 53100080 r0 : [ 349.094783] Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user [ 349.102268] Control: 10c5387d Table: 9deac019 DAC: 0015 [ 349.108294] Process insmod (pid: 1473, stack limit = 0xddcd2248) [...] This is because polling_mode is not enabled for ctx without FLAGS_FINUP. For polling mode the bufcnt is made 0 unconditionally. But it should be made 0 only if it is a final update or a total is not zero(This condition is similar to what is done in DMA case). Because of this wrong hashes are produced. Fixing the same. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com Patch applied. Thanks! -- Email: Herbert Xu herb...@gondor.apana.org.au Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/2] ARM: omap3: Split the pinmux core device
The omap3_pmx_core pinmux device in the device tree handles the system
controller module (SCM) PADCONFS fonction. Its control registers are
split in two distinct areas, with other SCM registers in-between. Those
other registers can't thus be requested by other drivers as the memory
region gets reserved by the pinmux driver.
Split the omap3_pmx_core device tree node in two for the two memory
regions. The second region address and size depends on the SoC model.
The change in omap3.dtsi fixes an external abort on non-linefetch when
doing
cat /sys/kernel/debug/pinctrl/.../pins
on a Nokia N900.
Signed-off-by: Laurent Pinchart laurent.pinch...@ideasonboard.com
Acked-By: Sebastian Reichel s...@debian.org
---
arch/arm/boot/dts/omap3-beagle-xm.dts | 40 +--
arch/arm/boot/dts/omap3-beagle.dts| 40 +--
arch/arm/boot/dts/omap3-igep.dtsi | 2 --
arch/arm/boot/dts/omap3-igep0020.dts | 52 +++
arch/arm/boot/dts/omap3-igep0030.dts | 10 ---
arch/arm/boot/dts/omap3-zoom3.dts | 23 ++--
arch/arm/boot/dts/omap3.dtsi | 13 -
7 files changed, 114 insertions(+), 66 deletions(-)
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts
b/arch/arm/boot/dts/omap3-beagle-xm.dts
index df33a50..093c33c 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -99,7 +99,7 @@
omap3_pmx_core {
pinctrl-names = default;
pinctrl-0 =
- hsusbb2_pins
+ hsusb2_pins
;
uart3_pins: pinmux_uart3_pins {
@@ -109,20 +109,32 @@
;
};
- hsusbb2_pins: pinmux_hsusbb2_pins {
+ hsusb2_pins: pinmux_hsusb2_pins {
pinctrl-single,pins =
- 0x5c0 (PIN_OUTPUT | MUX_MODE3) /*
etk_d10.hsusb2_clk */
- 0x5c2 (PIN_OUTPUT | MUX_MODE3) /*
etk_d11.hsusb2_stp */
- 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d12.hsusb2_dir */
- 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d13.hsusb2_nxt */
- 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d14.hsusb2_data0 */
- 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d15.hsusb2_data1 */
- 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
mcspi1_cs3.hsusb2_data2 */
- 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
mcspi2_clk.hsusb2_data7 */
- 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
mcspi2_simo.hsusb2_data4 */
- 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
mcspi2_somi.hsusb2_data5 */
- 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
mcspi2_cs0.hsusb2_data6 */
- 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
mcspi2_cs1.hsusb2_data3 */
+ OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN |
MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
+ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN |
MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
+ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN |
MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
+ OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN |
MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
+ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN |
MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
+ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN |
MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
+ ;
+ };
+};
+
+omap3_pmx_core2 {
+ pinctrl-names = default;
+ pinctrl-0 =
+ hsusb2_2_pins
+ ;
+
+ hsusb2_2_pins: pinmux_hsusb2_2_pins {
+ pinctrl-single,pins =
+ OMAP3_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)
/* etk_d10.hsusb2_clk */
+ OMAP3_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)
/* etk_d11.hsusb2_stp */
+ OMAP3_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN |
MUX_MODE3) /* etk_d12.hsusb2_dir */
+ OMAP3_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN |
MUX_MODE3) /* etk_d13.hsusb2_nxt */
+ OMAP3_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN |
MUX_MODE3) /* etk_d14.hsusb2_data0 */
+ OMAP3_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN |
MUX_MODE3) /* etk_d15.hsusb2_data1 */
;
};
};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts
b/arch/arm/boot/dts/omap3-beagle.dts
index 3ba4a62..4034fd2 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -93,23 +93,17 @@
omap3_pmx_core {
pinctrl-names = default;
pinctrl-0 =
- hsusbb2_pins
+ hsusb2_pins
;
-
[PATCH v2 0/2] ARM: omap3: Split the pinmux core device
Hello, While working on the OMAP3 ISP driver I've run into a failure to request a memory region already requested by the pinctrl-single driver. This patch set is an attempt to fix the problem. Changes since v1: - Rebased on top of Tony's master branch - Handle IGEP LEDs - Added Tony's PINCTRL macros - Fixed unbalanced parentheses in Tony's PINCTRL macros ;-) Laurent Pinchart (1): ARM: omap3: Split the pinmux core device Tony Lindgren (1): ARM: dts: Add omap specific pinctrl defines to use padconf addresses arch/arm/boot/dts/omap3-beagle-xm.dts | 40 +-- arch/arm/boot/dts/omap3-beagle.dts| 40 +-- arch/arm/boot/dts/omap3-igep.dtsi | 2 -- arch/arm/boot/dts/omap3-igep0020.dts | 52 +++ arch/arm/boot/dts/omap3-igep0030.dts | 10 --- arch/arm/boot/dts/omap3-zoom3.dts | 23 ++-- arch/arm/boot/dts/omap3.dtsi | 13 - include/dt-bindings/pinctrl/omap.h| 19 + 8 files changed, 133 insertions(+), 66 deletions(-) -- Regards, Laurent Pinchart -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/2] ARM: dts: Add omap specific pinctrl defines to use padconf addresses
From: Tony Lindgren t...@atomide.com As we have one to three pinctrl-single instances for each SoC it is a bit confusing to configure the padconf register offset from the base of the padconf register base. Let's add macros that allow using the physical address of the padconf register directly, or in most cases, just the last 16-bits of the address as they are shown in the documentation. Note that most documentation shows two padconf registers for each 32-bit address, so adding 2 to the documentation address is needed for the second padconf register as we treat them as 16-bit registers for omap3+. For example, omap36xx documentation shows sdmmc2_clk at 0x48002158, so we can just use the last 16-bits of that value: pinctrl-single,pins = OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) ... ; And we don't need to separately calculate the offset from the 0x2030 base: pinctrl-single,pins = 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) ... ; Naturally both ways of defining the registers can be used, and I'm not saying we should replace all the existing defines. But it may be handy to use these macros for new entries and when doing other related .dts file clean-up. Signed-off-by: Tony Lindgren t...@atomide.com Signed-off-by: Laurent Pinchart laurent.pinch...@ideasonboard.com --- include/dt-bindings/pinctrl/omap.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h index bed35e3..f8484ee 100644 --- a/include/dt-bindings/pinctrl/omap.h +++ b/include/dt-bindings/pinctrl/omap.h @@ -49,5 +49,24 @@ #define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) #define PIN_OFF_WAKEUPENABLE WAKEUP_EN +/* + * Macros to allow using the absolute physical address instead of the + * padconf registers instead of the offset from padconf base. + */ +#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) 0x) - (offset)) + +#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) +#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) +#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) +#define OMAP3_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) +#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) +#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) +#define OMAP4_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0040) (val) +#define OMAP4_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0xe040) (val) +#define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) +#define OMAP5_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2840) (val) +#define OMAP5_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0xc840) (val) +#define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val) + #endif -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 5/7] ARM: dts: add pbias dt node
* Balaji T K balaj...@ti.com [131220 03:41]:
On Thursday 19 December 2013 10:03 PM, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131219 04:40]:
@@ -485,6 +503,7 @@
dmas = sdma 61, sdma 62;
dma-names = tx, rx;
status = disabled;
+ pbias-supply = pbias_mmc_reg;
};
mmc2: mmc@480b4000 {
diff --git a/arch/arm/boot/dts/omap2430.dtsi
b/arch/arm/boot/dts/omap2430.dtsi
index d624345..f127901 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -29,6 +29,24 @@
pinctrl-single,function-mask = 0x3f;
};
+ omap2_scm_general: tisyscon@49002270 {
+ compatible = ti,control-syscon, syscon,
simple-bus;
+ reg = 0x49002270 0x240;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ pbias_regulator: pbias_regulator {
+ compatible = ti,pbias-omap;
+ reg = 0x230 0x4;
+ pbias_mmc_reg: pbias_mmc_omap3 {
+ regulator-name = pbias_mmc_omap3;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 300;
+ regulator-enable-ramp-delay = 100;
+ };
+ };
+ };
+
gpio1: gpio@4900c000 {
compatible = ti,omap2-gpio;
reg = 0x4900c000 0x200;
Here too you may need to set up pbias_mmc_omap2430?
2430 pbias reg config is same as 3430/3630 w.r.t to mmc pbias i/o,
hence using the same name, if you think regulator name needs to be changed
let me know the more appropriate one.
If they are compatible then we should use the earliest revision number
which would be 2430 instead of omap3 :)
Tony
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 3/7] regulator: add pbias regulator support
* Balaji T K balaj...@ti.com [131220 01:49]:
On Thursday 19 December 2013 10:03 PM, Tony Lindgren wrote:
+static int pbias_regulator_enable(struct regulator_dev *rdev)
+{
+ struct pbias_regulator_data *data = rdev_get_drvdata(rdev);
+ const struct pbias_reg_info *info = data-info;
+ int ret;
+
+ ret = regmap_update_bits(data-syscon, data-pbias_reg,
+ info-enable_mask, info-enable);
+
+ return ret;
+}
Do we need need to check the values after enable here? AFAIK setting
the PBIAS voltage change can also fail and that's probably why it has
failure due to mismatch in input voltage, should to be avoided and should
be taken care in s/w by the caller before pbias regulator set voltage/enable.
also the interrupt available.
But interrupt was never used/tested AFAIK, there is some settling time
before the generated interrupt status is truely valid, so pbias interrupt is
not
reliable.
OK. Do we need the standard regulator property startup-delay-us for the
PBIAS regulator then? Or if it's always fixed, I guess it could be done
in the pbias_regulator_enable()?
We probably need also pbias_mmc_omap2430 as that regiter mapping is
separate from omap3?
between omap2430 and omap3430, 3460 pbias register address are different,
other than that enable,enable_mask and vmode are
one and the same, so re-used pbias_mmc_omap3 name and struct pbias_reg_info
pbias_mmc_omap3
for omap2430 too, save one entry in of_regulator_match!
If separate name is needed for omap2430, I can add one for 2430,
and reuse the const struct pbias_reg_info pbias_mmc_omap3 of omap3
since the bit map for enable/disable and voltage configuration will be same.
Then pbias_matches will look like.
If they truly are compatible, then usually the earliest revision name is
used. So I guess we should use the omap2430 naming instead of omap3 naming.
+static struct of_regulator_match pbias_matches[] = {
+ { .name = pbias_mmc_omap2430, .driver_data = (void
*)pbias_mmc_omap3},
+ { .name = pbias_mmc_omap3, .driver_data = (void *)pbias_mmc_omap3},
+ { .name = pbias_sim_omap3, .driver_data = (void *)pbias_sim_omap3},
+ { .name = pbias_mmc_omap4, .driver_data = (void *)pbias_mmc_omap4},
+ { .name = pbias_mmc_omap5, .driver_data = (void *)pbias_mmc_omap5},
+};
Let me know if you still think that separate regulator name is needed for
2430,
I can respin this series.
Sounds like using the omap2430 naming would solve that.
Regards,
Tony
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP display subsystem - does it work?
* Tomi Valkeinen tomi.valkei...@ti.com [131220 05:45]: On 2013-12-20 13:48, Russell King - ARM Linux wrote: On Fri, Dec 20, 2013 at 11:27:01AM +, Russell King - ARM Linux wrote: Maybe, but that's the problem - finding out what is missing. This is the endless problem where things keep changing - it's very difficult to keep a working configuration working because the config symbols keep changing. Also, bear in mind that there's many different variants of the LDP hardware with stuff connected up in different ways (I'm aware that the keypad is just randomly allocated). I wouldn't be surprised if this also applied to how the backlight on the LCD was done. I need to cook up a patch for the gpio active-low problem. I tried to figure out how to do it with the old GPIO API, but as far as I understand, I have to do it manually in the driver (as it was done in the old driver). Or maybe this is getting buggered by the idiotic deferred probing... It seems that the GPIOs for controlling the LCD and backlight aren't even getting claimed if the DSS modules are built in: # cat /sys/kernel/debug/gpio ... GPIOs 238-255, platform/twl4030_gpio, twl4030, can sleep: # echo panel-dpi.0 /sys/bus/platform/drivers/panel-dpi/unbind # echo panel-dpi.0 /sys/bus/platform/drivers/panel-dpi/bind # cat /sys/kernel/debug/gpio ... GPIOs 238-255, platform/twl4030_gpio, twl4030, can sleep: gpio-245 (panel enable) out lo gpio-253 (panel backlight ) out lo This looks odd... Presuming the panel device was probed successfully, it should always get the gpios or return an error. Only if gpio_is_valid() returns false for the gpio, it skips it and continues. But in this case, the gpio number comes from the platform data, so it should always be valid. And if it wasn't probed successfully, then there shouldn't be a fb0. I bet that's it though. If the display is probed before twl4030 GPIO is initialized, the GPIO numbers will be 0. I'm using omap2plus_defconfig which has DSS built as modules. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 5/7] ARM: dts: add pbias dt node
On Friday 20 December 2013 09:28 PM, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131220 03:41]:
On Thursday 19 December 2013 10:03 PM, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131219 04:40]:
@@ -485,6 +503,7 @@
dmas = sdma 61, sdma 62;
dma-names = tx, rx;
status = disabled;
+ pbias-supply = pbias_mmc_reg;
};
mmc2: mmc@480b4000 {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index d624345..f127901 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -29,6 +29,24 @@
pinctrl-single,function-mask = 0x3f;
};
+ omap2_scm_general: tisyscon@49002270 {
+ compatible = ti,control-syscon, syscon,
simple-bus;
+ reg = 0x49002270 0x240;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ pbias_regulator: pbias_regulator {
+ compatible = ti,pbias-omap;
+ reg = 0x230 0x4;
+ pbias_mmc_reg: pbias_mmc_omap3 {
+ regulator-name = pbias_mmc_omap3;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 300;
+ regulator-enable-ramp-delay = 100;
+ };
+ };
+ };
+
gpio1: gpio@4900c000 {
compatible = ti,omap2-gpio;
reg = 0x4900c000 0x200;
Here too you may need to set up pbias_mmc_omap2430?
2430 pbias reg config is same as 3430/3630 w.r.t to mmc pbias i/o,
hence using the same name, if you think regulator name needs to be changed
let me know the more appropriate one.
If they are compatible then we should use the earliest revision number
which would be 2430 instead of omap3 :)
I went with most commonly used omap SoC :-)
Tony
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 3/7] regulator: add pbias regulator support
On Fri, Dec 20, 2013 at 07:57:21AM -0800, Tony Lindgren wrote: * Balaji T K balaj...@ti.com [131220 01:49]: But interrupt was never used/tested AFAIK, there is some settling time before the generated interrupt status is truely valid, so pbias interrupt is not reliable. OK. Do we need the standard regulator property startup-delay-us for the PBIAS regulator then? Or if it's always fixed, I guess it could be done in the pbias_regulator_enable()? That delay is supposed to be the time for the startup of the supply rather than any detection code. It should be set using enable_time in the driver if it's not system dependent - the property is there for cases where the delay depends on system configuration (eg, due to the capacitor values). signature.asc Description: Digital signature
Re: [PATCHv11 06/49] clk: add support for low level register ops
On Fri, 20 Dec 2013, Tero Kristo wrote: On 12/20/2013 01:00 PM, Paul Walmsley wrote: On Thu, 19 Dec 2013, Tero Kristo wrote: +/** + * clk_readl_default - default clock register read support function + * @reg: register to read + * + * Default implementation for reading a clock register. + */ +static u32 clk_readl_default(u32 __iomem *reg) Why u32 __iomem rather than void *? Not that this will affect OMAP, but will this need to be changed later to support 64-bit addresses? __raw_writel() and __raw_readl() are defined with void __iomem * as their address argument, which will be 64 bits on arm64, correct? Just copy pasting the current implementation from the clk-provider.h file. However, pointer is pointer no? This is just used to refer to a 32bit value, the pointer itself can be either 32bit or 64bit. Yes I think you're right that the impact is simply cosmetic. That argument winds up as the address argument to __raw_readl/writel() which is a void __iomem *, so the type there will be ignored. If the registers are changed to be 64 bit though but that will require changing most of the clock code as it is littered with 'u32 val;' type declarations. Yes, we can count on readl/writel to operate on 32-bit values. Anyway, I can change this to be void __iomem. OK - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP display subsystem - does it work?
* Russell King - ARM Linux li...@arm.linux.org.uk [131220 03:28]:
BTW, I'm seeing MMC errors with my LDP here though, does that work
for you?
I see no errors there.
OK thanks that's good to hear. I'm seeing them even after changing the
MMC card, need to check that again though. I'm almost certain it worked
just fine a month ago or so when I was playing with it.. Maybe some dirt
in the contacts or something.
Okay, while digging through the changes, I found this - this is the old
code. gpio + 15 is the backlight enable GPIO.
static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned
ngpio)
{
- ldp_panel_data.gpios[0] = gpio + 7;
- ldp_panel_data.gpio_invert[0] = true;
- ldp_panel_data.gpios[1] = gpio + 15;
- ldp_panel_data.gpio_invert[1] = true;
return 0;
}
...
-static int generic_dpi_panel_power_on(struct omap_dss_device *dssdev)
-{
...
- for (i = 0; i panel_data-num_gpios; ++i) {
- gpio_set_value_cansleep(panel_data-gpios[i],
- panel_data-gpio_invert[i] ? 0 : 1);
- }
-static void generic_dpi_panel_power_off(struct omap_dss_device *dssdev)
-{
...
- for (i = panel_data-num_gpios - 1; i = 0; --i) {
- gpio_set_value_cansleep(panel_data-gpios[i],
- panel_data-gpio_invert[i] ? 1 : 0);
- }
-static int generic_dpi_panel_probe(struct omap_dss_device *dssdev)
-{
- for (i = 0; i panel_data-num_gpios; ++i) {
- r = devm_gpio_request_one(dssdev-dev, panel_data-gpios[i],
- panel_data-gpio_invert[i] ?
- GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
- panel gpio);
- if (r)
- return r;
- }
So, when gpio_invert[] is set, the signal is active low for on. What
does the new code do?
static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned
ngpio)
{
+ /* LCD enable GPIO */
+ ldp_lcd_pdata.enable_gpio = gpio + 7;
+ /* Backlight enable GPIO */
+ ldp_lcd_pdata.backlight_gpio = gpio + 15;
...
static int panel_dpi_enable(struct omap_dss_device *dssdev)
{
...
if (gpio_is_valid(ddata-backlight_gpio))
gpio_set_value_cansleep(ddata-backlight_gpio, 1);
...
static void panel_dpi_disable(struct omap_dss_device *dssdev)
{
...
if (gpio_is_valid(ddata-backlight_gpio))
gpio_set_value_cansleep(ddata-backlight_gpio, 0);
...
static int panel_dpi_probe(struct platform_device *pdev)
{
...
if (gpio_is_valid(ddata-backlight_gpio)) {
r = devm_gpio_request_one(pdev-dev, ddata-backlight_gpio,
GPIOF_OUT_INIT_LOW, panel backlight);
which is fixed at active-high for on.
Would you like to revise whether this works for you... I suspect that
you're missing configuration which means that the backlight_gpio is
not valid, and hence it's being left in same default state (maybe by
the boot loader?)
Nope, my LCD if off from the bootloader and gets enabled by the kernel.
I think the old gpio_invert was inverting the value unnecessarily or
something, the new code does the right thing without a need for the
gpio_invert flags.
Regards,
Tony
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv11 07/49] clk: divider: add support for low level ops
* Rajendra Nayak rna...@ti.com [131220 02:40]: yeah, the crash was indeed when ll_ops was dereferenced despite being NULL. Might be also worth checking if the gate and mux patches have a similar issue. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 3/7] regulator: add pbias regulator support
* Mark Brown broo...@kernel.org [131220 08:10]: On Fri, Dec 20, 2013 at 07:57:21AM -0800, Tony Lindgren wrote: * Balaji T K balaj...@ti.com [131220 01:49]: But interrupt was never used/tested AFAIK, there is some settling time before the generated interrupt status is truely valid, so pbias interrupt is not reliable. OK. Do we need the standard regulator property startup-delay-us for the PBIAS regulator then? Or if it's always fixed, I guess it could be done in the pbias_regulator_enable()? That delay is supposed to be the time for the startup of the supply rather than any detection code. It should be set using enable_time in the driver if it's not system dependent - the property is there for cases where the delay depends on system configuration (eg, due to the capacitor values). OK thanks. Let's try enable_time first then as we've had a fixed value for years for it. If there's some difference based on the card capacitance etc that can be added if needed. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] omap display regression fix against v3.13-rc4
Tony Lindgren t...@atomide.com writes: The following changes since commit 319e2e3f63c348a9b66db4667efa73178e18b17d: Linux 3.13-rc4 (2013-12-15 12:31:33 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.13/display-fix for you to fetch changes up to 130f769e81fc472beb2211320777e26050e3fa15: Revert ARM: OMAP2+: Remove legacy mux code for display.c (2013-12-17 16:28:34 -0800) I accidentally removed some mux code for omap4 that I thought was dead code as omap4 has been booting with device tree only since v3.10. Turns out I also removed some display related mux code, so let's revert that except for the dead code parts. Pulled into fixes, Thanks, Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv12 00/49] ARM: TI SoC clock DT conversion
Hi, Hopefully final post of this series. At least this is going to be the last post this year as I will be going to x-mas vacation and won't be back before Jan 2nd. This time I just sent the patches that have changes in them, the missing ones are exactly the same as in v11. Changes done: - most of the patches: * Some cosmetic documentation fixes - patch 06: * Changed register pointer types from 'u32 __iomem *' to 'void __iomem *' - patch 07,08,09: * Added check for clk-ll_ops being NULL (happens with statically built clock data), fixes the boot time crash issue noticed by Tony - patch 11: * Moved __clk_of_table extern declaration to clk-provider.h header file... Got flamed about this enough times now. :) * Type for the declaration changed also from array to single entry, and address for this used in code. This prevents compile time error: array type has incomplete element type. Can't use pointer here either as this messes the address of the table. * ti_clk_retry_init() now has int return type, and checks for kzalloc failure - patch 12, 14, 23: * Added cleanup in case ti_clk_retry_init() fails - patch 17: * Fixed potential memory leak in failed init detected by sparse - patch 18: * Modified commit message to add some details about clockdomains - patch 43: * Changed register pointer types from 'u32 *' to 'void __iomem *' Testing done: - omap3-beagle: boot, suspend/resume (ret), suspend/resume (off) - omap4-panda-es: boot, suspend/resume (ret) - omap5-uevm: boot - am335x-bone: boot - dra7-evm: boot Branches available at https://github.com/t-kristo/linux-pm.git: - branch: 3.13-rc4-dt-clks-v12 : contains everything, shall me merged last - branch: 3.13-rc4-dt-clks-v12-for-mike : drivers/clk changes - branch: 3.13-rc4-dt-clks-v11-for-benoit : DT data only (from v11, no changes) -Tero -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv12 05/49] clk: gate: add support for registering gate clock from descriptor
New clk_register_desc() call can be used to register this clock type now.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-gate.c | 31 +++
include/linux/clk-provider.h | 18 ++
2 files changed, 49 insertions(+)
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 4a58c55..3ec61d2 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -26,8 +26,12 @@
* parent - fixed parent. No clk_set_parent support
*/
+/* resolve struct clk_gate from inner struct clk_hw member */
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
+/* resolve struct clk_gate_desc from inner struct clk_desc member */
+#define to_hw_desc(_desc) container_of(_desc, struct clk_gate_desc, desc)
+
/*
* It works on following logic:
*
@@ -162,3 +166,30 @@ struct clk *clk_register_gate(struct device *dev, const
char *name,
return clk;
}
EXPORT_SYMBOL_GPL(clk_register_gate);
+
+struct clk_hw *clk_register_gate_desc(struct device *dev, struct clk_desc
*desc)
+{
+ struct clk_gate *gate;
+ struct clk_gate_desc *hw_desc;
+
+ hw_desc = to_hw_desc(desc);
+
+ /* allocate mux clock */
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ /* populate struct clk_gate assignments */
+ gate-reg = hw_desc-reg;
+ gate-bit_idx = hw_desc-bit_idx;
+ gate-flags = hw_desc-flags;
+ gate-lock = hw_desc-lock;
+
+ if (!desc-ops)
+ desc-ops = clk_gate_ops;
+
+ desc-flags |= CLK_IS_BASIC;
+
+ return gate-hw;
+}
+EXPORT_SYMBOL_GPL(clk_register_gate_desc);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index ea5281c..a4f14ae 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -268,10 +268,28 @@ struct clk_gate {
spinlock_t *lock;
};
+/**
+ * struct clk_gate_desc - init descriptor for gating clock
+ * @desc: handle between common and hardware-specific interfaces
+ * @reg: register controlling gate
+ * @bit_idx: single bit controlling gate
+ * @flags: hardware-specific flags
+ * @lock: register lock
+ */
+struct clk_gate_desc {
+ struct clk_desc desc;
+ void __iomem*reg;
+ u8 bit_idx;
+ u8 flags;
+ spinlock_t *lock;
+};
+
#define CLK_GATE_SET_TO_DISABLEBIT(0)
#define CLK_GATE_HIWORD_MASK BIT(1)
extern const struct clk_ops clk_gate_ops;
+struct clk_hw *clk_register_gate_desc(struct device *dev,
+ struct clk_desc *desc);
struct clk *clk_register_gate(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx,
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv12 08/49] clk: gate: add support for low level ops
Gate clock can now be registered to use low level register access ops.
Preferred initialization method is via clock description.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-gate.c | 20 +---
include/linux/clk-provider.h |4
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 3ec61d2..d4c94a7 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -62,7 +62,10 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
if (set)
reg |= BIT(gate-bit_idx);
} else {
- reg = clk_readl(gate-reg);
+ if (gate-ll_ops)
+ reg = gate-ll_ops-clk_readl(gate-reg);
+ else
+ reg = clk_readl(gate-reg);
if (set)
reg |= BIT(gate-bit_idx);
@@ -70,7 +73,10 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
reg = ~BIT(gate-bit_idx);
}
- clk_writel(reg, gate-reg);
+ if (gate-ll_ops)
+ gate-ll_ops-clk_writel(reg, gate-reg);
+ else
+ clk_writel(reg, gate-reg);
if (gate-lock)
spin_unlock_irqrestore(gate-lock, flags);
@@ -93,7 +99,10 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
u32 reg;
struct clk_gate *gate = to_clk_gate(hw);
- reg = clk_readl(gate-reg);
+ if (gate-ll_ops)
+ reg = gate-ll_ops-clk_readl(gate-reg);
+ else
+ reg = clk_readl(gate-reg);
/* if a set bit disables this clk, flip it before masking */
if (gate-flags CLK_GATE_SET_TO_DISABLE)
@@ -157,6 +166,7 @@ struct clk *clk_register_gate(struct device *dev, const
char *name,
gate-flags = clk_gate_flags;
gate-lock = lock;
gate-hw.init = init;
+ gate-ll_ops = clk_ll_ops_default;
clk = clk_register(dev, gate-hw);
@@ -184,6 +194,10 @@ struct clk_hw *clk_register_gate_desc(struct device *dev,
struct clk_desc *desc)
gate-bit_idx = hw_desc-bit_idx;
gate-flags = hw_desc-flags;
gate-lock = hw_desc-lock;
+ gate-ll_ops = hw_desc-ll_ops;
+
+ if (!gate-ll_ops)
+ gate-ll_ops = clk_ll_ops_default;
if (!desc-ops)
desc-ops = clk_gate_ops;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index f082a89..3923d46 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -262,6 +262,7 @@ void of_fixed_clk_setup(struct device_node *np);
*
* @hw:handle between common and hardware-specific interfaces
* @reg: register controlling gate
+ * @ll_ops:low-level ops for accessing the register
* @bit_idx: single bit controlling gate
* @flags: hardware-specific flags
* @lock: register lock
@@ -280,6 +281,7 @@ void of_fixed_clk_setup(struct device_node *np);
struct clk_gate {
struct clk_hw hw;
void __iomem*reg;
+ struct clk_ll_ops *ll_ops;
u8 bit_idx;
u8 flags;
spinlock_t *lock;
@@ -289,6 +291,7 @@ struct clk_gate {
* struct clk_gate_desc - init descriptor for gating clock
* @desc: handle between common and hardware-specific interfaces
* @reg: register controlling gate
+ * @ll_ops:low-level ops for accessing the register
* @bit_idx: single bit controlling gate
* @flags: hardware-specific flags
* @lock: register lock
@@ -296,6 +299,7 @@ struct clk_gate {
struct clk_gate_desc {
struct clk_desc desc;
void __iomem*reg;
+ struct clk_ll_ops *ll_ops;
u8 bit_idx;
u8 flags;
spinlock_t *lock;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv12 01/49] clk: add support for registering clocks from description
From: Mike Turquette mturque...@linaro.org
clk_register_desc is the primary interface for populating the clock tree
with new clock nodes. In time, this will replace the various hardware-specific
registration functions (e.g. clk_register_gate).
Signed-off-by: Mike Turquette mturque...@linaro.org
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk.c| 71 ++
include/linux/clk-provider.h | 22 +
2 files changed, 93 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 2cf2ea6..29281f6 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1905,6 +1905,77 @@ fail_out:
EXPORT_SYMBOL_GPL(clk_register);
/**
+ * clk_register_desc - register a new clock from its description
+ * @dev: device that is registering this clock
+ * @desc: description of the clock, may be __initdata or otherwise discarded
+ *
+ * clk_register_desc is the primary interface for populating the clock tree
+ * with new clock nodes. In time it will replace the various hardware-specific
+ * registration functions (e.g. clk_register_gate). clk_register_desc returns a
+ * pointer to the newly allocated struct clk which is an opaque cookie. Drivers
+ * must not dereference it except to check with IS_ERR.
+ */
+struct clk *clk_register_desc(struct device *dev, struct clk_desc *desc)
+{
+ int ret, i;
+ struct clk *clk;
+
+ clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+
+ if (!clk)
+ return ERR_PTR(-ENOMEM);
+
+ clk-hw = desc-register_func(dev, desc);
+ clk-hw-clk = clk;
+
+ /* _clk_register */
+ clk-name = kstrdup(desc-name, GFP_KERNEL);
+ if (!clk-name) {
+ ret = -ENOMEM;
+ goto fail_name;
+ }
+
+ clk-ops = desc-ops;
+ clk-flags = desc-flags;
+ clk-num_parents = desc-num_parents;
+
+ /* allocate local copy in case parent_names is __initdata */
+ clk-parent_names = kcalloc(clk-num_parents, sizeof(char *),
+ GFP_KERNEL);
+
+ if (!clk-parent_names) {
+ ret = -ENOMEM;
+ goto fail_parent_names;
+ }
+
+ /* copy each string name in case parent_names is __initdata */
+ for (i = 0; i clk-num_parents; i++) {
+ clk-parent_names[i] = kstrdup(desc-parent_names[i],
+ GFP_KERNEL);
+
+ if (!clk-parent_names[i]) {
+ ret = -ENOMEM;
+ goto fail_parent_names_copy;
+ }
+ }
+
+ ret = __clk_init(dev, clk);
+
+ if (!ret)
+ return clk;
+
+fail_parent_names_copy:
+ while (--i = 0)
+ kfree(clk-parent_names[i]);
+ kfree(clk-parent_names);
+fail_parent_names:
+ kfree(clk-name);
+fail_name:
+ kfree(clk);
+ return ERR_PTR(ret);
+}
+
+/**
* clk_unregister - unregister a currently registered clock
* @clk: clock to unregister
*
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7e59253..08a0da0 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -161,6 +161,27 @@ struct clk_init_data {
};
/**
+ * struct clk_desc - clock init descriptor for providing init time parameters
+ * for a clock.
+ * @name: clock name
+ * @ops: clock ops
+ * @parent_names: array of string names for all possible parents
+ * @num_parents: number of possible parents
+ * @flags: framework-level hints and quirks
+ * @register_func: function for parsing the clock descriptor and providing
+ *ready-to-register clk_hw
+ */
+struct clk_desc {
+ const char *name;
+ const struct clk_ops*ops;
+ const char **parent_names;
+ u8 num_parents;
+ unsigned long flags;
+ struct clk_hw *(*register_func)(struct device *dev,
+ struct clk_desc *desc);
+};
+
+/**
* struct clk_hw - handle for traversing from a struct clk to its corresponding
* hardware-specific structure. struct clk_hw should be declared within struct
* clk_foo and then referenced by the struct clk instance that uses struct
@@ -419,6 +440,7 @@ struct clk *clk_register_composite(struct device *dev,
const char *name,
* error code; drivers must test for an error code after calling clk_register.
*/
struct clk *clk_register(struct device *dev, struct clk_hw *hw);
+struct clk *clk_register_desc(struct device *dev, struct clk_desc *desc);
struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
void clk_unregister(struct clk *clk);
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv12 07/49] clk: divider: add support for low level ops
Divider clock can now be registered to use low level register access ops.
Preferred initialization method is via clock description.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-divider.c| 22 +++---
include/linux/clk-provider.h |4
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8cfed5c..887e2d8 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -108,7 +108,12 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw
*hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int div, val;
- val = clk_readl(divider-reg) divider-shift;
+ if (divider-ll_ops)
+ val = divider-ll_ops-clk_readl(divider-reg);
+ else
+ val = clk_readl(divider-reg);
+
+ val = divider-shift;
val = div_mask(divider);
div = _get_div(divider, val);
@@ -234,11 +239,17 @@ static int clk_divider_set_rate(struct clk_hw *hw,
unsigned long rate,
if (divider-flags CLK_DIVIDER_HIWORD_MASK) {
val = div_mask(divider) (divider-shift + 16);
} else {
- val = clk_readl(divider-reg);
+ if (divider-ll_ops)
+ val = divider-ll_ops-clk_readl(divider-reg);
+ else
+ val = clk_readl(divider-reg);
val = ~(div_mask(divider) divider-shift);
}
val |= value divider-shift;
- clk_writel(val, divider-reg);
+ if (divider-ll_ops)
+ divider-ll_ops-clk_writel(val, divider-reg);
+ else
+ clk_writel(val, divider-reg);
if (divider-lock)
spin_unlock_irqrestore(divider-lock, flags);
@@ -291,6 +302,7 @@ static struct clk *_register_divider(struct device *dev,
const char *name,
div-lock = lock;
div-hw.init = init;
div-table = table;
+ div-ll_ops = clk_ll_ops_default;
/* register the clock */
clk = clk_register(dev, div-hw);
@@ -368,6 +380,10 @@ struct clk_hw *clk_register_divider_desc(struct device
*dev,
divider-flags = hw_desc-flags;
divider-table = hw_desc-table;
divider-lock = hw_desc-lock;
+ divider-ll_ops = hw_desc-ll_ops;
+
+ if (!divider-ll_ops)
+ divider-ll_ops = clk_ll_ops_default;
if (!desc-ops)
desc-ops = clk_divider_ops;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 671dff4..f082a89 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -322,6 +322,7 @@ struct clk_div_table {
*
* @hw:handle between common and hardware-specific interfaces
* @reg: register containing the divider
+ * @ll_ops:low-level ops for accessing the register
* @shift: shift to the divider bit field
* @width: width of the divider bit field
* @table: array of value/divider pairs, last entry should have div = 0
@@ -350,6 +351,7 @@ struct clk_div_table {
struct clk_divider {
struct clk_hw hw;
void __iomem*reg;
+ struct clk_ll_ops *ll_ops;
u8 shift;
u8 width;
u8 flags;
@@ -361,6 +363,7 @@ struct clk_divider {
* struct clk_divider_desc - init descriptor for divider clock
* @desc: handle between common and hardware-specific interfaces
* @reg: register containing the divider
+ * @ll_ops:low-level ops for accessing the register
* @shift: shift to the divider bit field
* @width: width of the divider bit field
* @table: array of value/divider pairs, last entry should have div = 0
@@ -369,6 +372,7 @@ struct clk_divider {
struct clk_divider_desc {
struct clk_desc desc;
void __iomem*reg;
+ struct clk_ll_ops *ll_ops;
u8 shift;
u8 width;
u8 flags;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv12 03/49] clk: divider: add support for registering divider clock from descriptor
New clk_register_desc() call can be used to register this clock type now.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-divider.c| 34 ++
include/linux/clk-provider.h | 22 ++
2 files changed, 56 insertions(+)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8d3009e..8cfed5c 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -28,8 +28,12 @@
* parent - fixed parent. No clk_set_parent support
*/
+/* resolve struct clk_divider from inner struct clk_hw member */
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+/* resolve struct clk_divider_desc from inner struct clk_desc member */
+#define to_hw_desc(_desc) container_of(_desc, struct clk_divider_desc, desc)
+
#define div_mask(d)((1 ((d)-width)) - 1)
static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
@@ -343,3 +347,33 @@ struct clk *clk_register_divider_table(struct device *dev,
const char *name,
width, clk_divider_flags, table, lock);
}
EXPORT_SYMBOL_GPL(clk_register_divider_table);
+
+struct clk_hw *clk_register_divider_desc(struct device *dev,
+struct clk_desc *desc)
+{
+ struct clk_divider *divider;
+ struct clk_divider_desc *hw_desc;
+
+ hw_desc = to_hw_desc(desc);
+
+ /* allocate divider clock */
+ divider = kzalloc(sizeof(*divider), GFP_KERNEL);
+ if (!divider)
+ return ERR_PTR(-ENOMEM);
+
+ /* populate struct clk_divider assignments */
+ divider-reg = hw_desc-reg;
+ divider-shift = hw_desc-shift;
+ divider-width = hw_desc-width;
+ divider-flags = hw_desc-flags;
+ divider-table = hw_desc-table;
+ divider-lock = hw_desc-lock;
+
+ if (!desc-ops)
+ desc-ops = clk_divider_ops;
+
+ desc-flags |= CLK_IS_BASIC;
+
+ return divider-hw;
+}
+EXPORT_SYMBOL_GPL(clk_register_divider_desc);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 232623d..bf89ab4 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -322,11 +322,33 @@ struct clk_divider {
spinlock_t *lock;
};
+/**
+ * struct clk_divider_desc - init descriptor for divider clock
+ * @desc: handle between common and hardware-specific interfaces
+ * @reg: register containing the divider
+ * @shift: shift to the divider bit field
+ * @width: width of the divider bit field
+ * @table: array of value/divider pairs, last entry should have div = 0
+ * @lock: register lock
+ */
+struct clk_divider_desc {
+ struct clk_desc desc;
+ void __iomem*reg;
+ u8 shift;
+ u8 width;
+ u8 flags;
+ const struct clk_div_table *table;
+ spinlock_t *lock;
+};
+
#define CLK_DIVIDER_ONE_BASED BIT(0)
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
#define CLK_DIVIDER_HIWORD_MASKBIT(3)
+struct clk_hw *clk_register_divider_desc(struct device *dev,
+struct clk_desc *desc);
+
extern const struct clk_ops clk_divider_ops;
struct clk *clk_register_divider(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv12 04/49] clk: mux: add support for registering mux clock from descriptor
New clk_register_desc() call can be used to register this clock type now.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-mux.c| 37 +
include/linux/clk-provider.h | 20
2 files changed, 57 insertions(+)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 4f96ff3..2cbed08 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -27,8 +27,12 @@
* parent - parent is adjustable through clk_set_parent
*/
+/* resolve struct clk_mux from inner struct clk_hw member */
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
+/* resolve struct clk_mux_desc from inner struct clk_desc member */
+#define to_hw_desc(_desc) container_of(_desc, struct clk_mux_desc, desc)
+
static u8 clk_mux_get_parent(struct clk_hw *hw)
{
struct clk_mux *mux = to_clk_mux(hw);
@@ -177,3 +181,36 @@ struct clk *clk_register_mux(struct device *dev, const
char *name,
NULL, lock);
}
EXPORT_SYMBOL_GPL(clk_register_mux);
+
+struct clk_hw *clk_register_mux_desc(struct device *dev, struct clk_desc *desc)
+{
+ struct clk_mux *mux;
+ struct clk_mux_desc *hw_desc;
+
+ hw_desc = to_hw_desc(desc);
+
+ /* allocate mux clock */
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+
+ /* populate struct clk_mux assignments */
+ mux-reg = hw_desc-reg;
+ mux-table = hw_desc-table;
+ mux-mask = hw_desc-mask;
+ mux-shift = hw_desc-shift;
+ mux-flags = hw_desc-flags;
+ mux-lock = hw_desc-lock;
+
+ if (!desc-ops) {
+ if (mux-flags CLK_MUX_READ_ONLY)
+ desc-ops = clk_mux_ro_ops;
+ else
+ desc-ops = clk_mux_ops;
+ }
+
+ desc-flags |= CLK_IS_BASIC;
+
+ return mux-hw;
+}
+EXPORT_SYMBOL_GPL(clk_register_mux_desc);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index bf89ab4..ea5281c 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -391,6 +391,25 @@ struct clk_mux {
spinlock_t *lock;
};
+/**
+ * struct clk_mux_desc - init descriptor for multiplexer clock
+ * @desc: handle between common and hardware-specific interfaces
+ * @reg: register controlling multiplexer
+ * @shift: shift to multiplexer bit field
+ * @width: width of multiplexer bit field
+ * @flags: hardware-specific flags
+ * @lock: register lock
+ */
+struct clk_mux_desc {
+ struct clk_desc desc;
+ void __iomem*reg;
+ u32 *table;
+ u32 mask;
+ u8 shift;
+ u8 flags;
+ spinlock_t *lock;
+};
+
#define CLK_MUX_INDEX_ONE BIT(0)
#define CLK_MUX_INDEX_BIT BIT(1)
#define CLK_MUX_HIWORD_MASKBIT(2)
@@ -399,6 +418,7 @@ struct clk_mux {
extern const struct clk_ops clk_mux_ops;
extern const struct clk_ops clk_mux_ro_ops;
+struct clk_hw *clk_register_mux_desc(struct device *dev, struct clk_desc
*desc);
struct clk *clk_register_mux(struct device *dev, const char *name,
const char **parent_names, u8 num_parents, unsigned long flags,
void __iomem *reg, u8 shift, u8 width,
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv12 09/49] clk: mux: add support for low level ops
Multiplexer clock can now be registered to use low level register access ops.
Preferred initialization method is via clock description.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-mux.c| 24 +---
include/linux/clk-provider.h |4
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 2cbed08..ed3bc36 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -46,7 +46,12 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
* val = 0x4 really means bit 2, index starts at bit 0
*/
- val = clk_readl(mux-reg) mux-shift;
+ if (mux-ll_ops)
+ val = mux-ll_ops-clk_readl(mux-reg);
+ else
+ val = clk_readl(mux-reg);
+
+ val = mux-shift;
val = mux-mask;
if (mux-table) {
@@ -93,11 +98,19 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
if (mux-flags CLK_MUX_HIWORD_MASK) {
val = mux-mask (mux-shift + 16);
} else {
- val = clk_readl(mux-reg);
+ if (mux-ll_ops)
+ val = mux-ll_ops-clk_readl(mux-reg);
+ else
+ val = clk_readl(mux-reg);
+
val = ~(mux-mask mux-shift);
}
val |= index mux-shift;
- clk_writel(val, mux-reg);
+
+ if (mux-ll_ops)
+ mux-ll_ops-clk_writel(val, mux-reg);
+ else
+ clk_writel(val, mux-reg);
if (mux-lock)
spin_unlock_irqrestore(mux-lock, flags);
@@ -159,6 +172,7 @@ struct clk *clk_register_mux_table(struct device *dev,
const char *name,
mux-lock = lock;
mux-table = table;
mux-hw.init = init;
+ mux-ll_ops = clk_ll_ops_default;
clk = clk_register(dev, mux-hw);
@@ -201,6 +215,10 @@ struct clk_hw *clk_register_mux_desc(struct device *dev,
struct clk_desc *desc)
mux-shift = hw_desc-shift;
mux-flags = hw_desc-flags;
mux-lock = hw_desc-lock;
+ mux-ll_ops = hw_desc-ll_ops;
+
+ if (!mux-ll_ops)
+ mux-ll_ops = clk_ll_ops_default;
if (!desc-ops) {
if (mux-flags CLK_MUX_READ_ONLY)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 3923d46..629163c 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -408,6 +408,7 @@ struct clk *clk_register_divider_table(struct device *dev,
const char *name,
*
* @hw:handle between common and hardware-specific interfaces
* @reg: register controlling multiplexer
+ * @ll_ops:low-level ops for accessing the register
* @shift: shift to multiplexer bit field
* @width: width of mutliplexer bit field
* @flags: hardware-specific flags
@@ -427,6 +428,7 @@ struct clk *clk_register_divider_table(struct device *dev,
const char *name,
struct clk_mux {
struct clk_hw hw;
void __iomem*reg;
+ struct clk_ll_ops *ll_ops;
u32 *table;
u32 mask;
u8 shift;
@@ -438,6 +440,7 @@ struct clk_mux {
* struct clk_mux_desc - init descriptor for multiplexer clock
* @desc: handle between common and hardware-specific interfaces
* @reg: register controlling multiplexer
+ * @ll_ops:low-level ops for accesing the register
* @shift: shift to multiplexer bit field
* @width: width of multiplexer bit field
* @flags: hardware-specific flags
@@ -446,6 +449,7 @@ struct clk_mux {
struct clk_mux_desc {
struct clk_desc desc;
void __iomem*reg;
+ struct clk_ll_ops *ll_ops;
u32 *table;
u32 mask;
u8 shift;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv12 11/49] CLK: ti: add init support for clock IP blocks
ti_dt_clk_init_provider() can now be used to initialize the contents of
a single clock IP block. This parses all the clocks under the IP block
and calls the corresponding init function for them.
This patch also introduces a helper function for the TI clock drivers
to get register info from DT and append the master IP info to this.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk.c|4 +-
drivers/clk/ti/clk.c | 112 ++
include/linux/clk-provider.h |2 +
include/linux/clk/ti.h | 20
4 files changed, 135 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 8bcd1e0..c0521be 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2203,8 +2203,6 @@ struct of_clk_provider {
void *data;
};
-extern struct of_device_id __clk_of_table[];
-
static const struct of_device_id __clk_of_table_sentinel
__used __section(__clk_of_table_end);
@@ -2344,7 +2342,7 @@ void __init of_clk_init(const struct of_device_id
*matches)
struct device_node *np;
if (!matches)
- matches = __clk_of_table;
+ matches = __clk_of_table;
for_each_matching_node_and_match(np, matches, match) {
of_clk_init_cb_t clk_init_cb = match-data;
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index ef1a7cd..e16da3a 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -19,10 +19,15 @@
#include linux/clkdev.h
#include linux/clk/ti.h
#include linux/of.h
+#include linux/of_address.h
+#include linux/list.h
#undef pr_fmt
#define pr_fmt(fmt) %s: fmt, __func__
+static int ti_dt_clk_memmap_index;
+struct clk_ll_ops *ti_clk_ll_ops;
+
/**
* ti_dt_clocks_register - register DT alias clocks during boot
* @oclks: list of clocks to register
@@ -53,3 +58,110 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
}
}
}
+
+struct clk_init_item {
+ struct device_node *node;
+ struct clk_hw *hw;
+ ti_of_clk_init_cb_t func;
+ struct list_head link;
+};
+
+static LIST_HEAD(retry_list);
+
+/**
+ * ti_clk_retry_init - retries a failed clock init at later phase
+ * @node: device not for the clock
+ * @hw: partially initialized clk_hw struct for the clock
+ * @func: init function to be called for the clock
+ *
+ * Adds a failed clock init to the retry list. The retry list is parsed
+ * once all the other clocks have been initialized.
+ */
+int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
+ ti_of_clk_init_cb_t func)
+{
+ struct clk_init_item *retry;
+
+ pr_debug(%s: adding to retry list...\n, node-name);
+ retry = kzalloc(sizeof(*retry), GFP_KERNEL);
+ if (!retry)
+ return -ENOMEM;
+
+ retry-node = node;
+ retry-func = func;
+ retry-hw = hw;
+ list_add(retry-link, retry_list);
+
+ return 0;
+}
+
+/**
+ * ti_clk_get_reg_addr - get register address for a clock register
+ * @node: device node for the clock
+ * @index: register index from the clock node
+ *
+ * Builds clock register address from device tree information. This
+ * is a struct of type clk_omap_reg.
+ */
+void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
+{
+ struct clk_omap_reg *reg;
+ u32 val;
+ u32 tmp;
+
+ reg = (struct clk_omap_reg *)tmp;
+ reg-index = ti_dt_clk_memmap_index;
+
+ if (of_property_read_u32_index(node, reg, index, val)) {
+ pr_err(%s must have reg[%d]!\n, node-name, index);
+ return NULL;
+ }
+
+ reg-offset = val;
+
+ return (void __iomem *)tmp;
+}
+
+/**
+ * ti_dt_clk_init_provider - init master clock provider
+ * @parent: master node
+ * @index: internal index for clk_reg_ops
+ *
+ * Initializes a master clock IP block and its child clock nodes.
+ * Regmap is provided for accessing the register space for the
+ * IP block and all the clocks under it.
+ */
+void ti_dt_clk_init_provider(struct device_node *parent, int index)
+{
+ const struct of_device_id *match;
+ struct device_node *np;
+ struct device_node *clocks;
+ of_clk_init_cb_t clk_init_cb;
+ struct clk_init_item *retry;
+ struct clk_init_item *tmp;
+
+ ti_dt_clk_memmap_index = index;
+
+ /* get clocks for this parent */
+ clocks = of_get_child_by_name(parent, clocks);
+ if (!clocks) {
+ pr_err(%s missing 'clocks' child node.\n, parent-name);
+ return;
+ }
+
+ for_each_child_of_node(clocks, np) {
+ match = of_match_node(__clk_of_table, np);
+ if (!match)
+ continue;
+ clk_init_cb = (of_clk_init_cb_t)match-data;
+ pr_debug(%s: initializing: %s\n, __func__, np-name);
+ clk_init_cb(np);
+ }
+
+
[PATCHv12 06/49] clk: add support for low level register ops
Low level register ops are needed for providing SoC or IP block specific
access routines to clock registers. Subsequent patches add support for
the low level ops for the individual clock drivers.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk.c| 28
include/linux/clk-provider.h | 17 +
2 files changed, 45 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 29281f6..8bcd1e0 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -34,6 +34,34 @@ static HLIST_HEAD(clk_root_list);
static HLIST_HEAD(clk_orphan_list);
static LIST_HEAD(clk_notifier_list);
+/**
+ * clk_readl_default - default clock register read support function
+ * @reg: register to read
+ *
+ * Default implementation for reading a clock register.
+ */
+static u32 clk_readl_default(void __iomem *reg)
+{
+ return readl(reg);
+}
+
+/**
+ * clk_writel_default - default clock register write support function
+ * @val: value to write
+ * @reg: register to write to
+ *
+ * Default implementation for writing a clock register.
+ */
+static void clk_writel_default(u32 val, void __iomem *reg)
+{
+ writel(val, reg);
+}
+
+struct clk_ll_ops clk_ll_ops_default = {
+ .clk_readl = clk_readl_default,
+ .clk_writel = clk_writel_default
+};
+
/*** locking ***/
static void clk_prepare_lock(void)
{
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index a4f14ae..671dff4 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -198,6 +198,23 @@ struct clk_hw {
const struct clk_init_data *init;
};
+/**
+ * struct clk_ll_ops - low-level register access ops for a clock
+ * @clk_readl: pointer to register read function
+ * @clk_writel: pointer to register write function
+ *
+ * Low-level register access ops are generally used by the basic clock types
+ * (clk-gate, clk-mux, clk-divider etc.) to provide support for various
+ * low-level hardware interfaces (direct MMIO, regmap etc.), but can also be
+ * used by other hardware-specific clock drivers if needed.
+ */
+struct clk_ll_ops {
+ u32 (*clk_readl)(void __iomem *reg);
+ void(*clk_writel)(u32 val, void __iomem *reg);
+};
+
+extern struct clk_ll_ops clk_ll_ops_default;
+
/*
* DOC: Basic clock implementations common to many platforms
*
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv11 07/49] clk: divider: add support for low level ops
On 12/20/2013 06:16 PM, Tony Lindgren wrote: * Rajendra Nayak rna...@ti.com [131220 02:40]: yeah, the crash was indeed when ll_ops was dereferenced despite being NULL. Might be also worth checking if the gate and mux patches have a similar issue. Yea they had and I fixed those. v12 coming out right after this email. -Tero -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv12 18/49] CLK: TI: add support for clockdomain binding
Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks. Clockdomain
itself is rather misleading name for the hardware functionality, as at
least on OMAP4 / OMAP5 / DRA7 the clockdomains can be collections of either
clocks and/or IP blocks, thus idle-domain or such might be more appropriate.
For most cases on these SoCs, the kernel doesn't even need the information
and the mappings can be ignored.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/clockdomain.txt | 24 +++
drivers/clk/ti/Makefile|3 +-
drivers/clk/ti/clockdomain.c | 70
include/linux/clk/ti.h |1 +
4 files changed, 97 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/clockdomain.txt
create mode 100644 drivers/clk/ti/clockdomain.c
diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
new file mode 100644
index 000..cb76b3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
@@ -0,0 +1,24 @@
+Binding for Texas Instruments clockdomain.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1] in consumer role.
+Every clock on TI SoC belongs to one clockdomain, but software
+only needs this information for specific clocks which require
+their parent clockdomain to be controlled when the clock is
+enabled/disabled. This binding doesn't define a new clock
+binding type, it is used to group existing clock nodes under
+hardware hierarchy.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be ti,clockdomain
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of clocks within this domain
+
+Examples:
+ dss_clkdm: dss_clkdm {
+ compatible = ti,clockdomain;
+ clocks = dss1_alwon_fck_3430es2, dss_ick_3430es2;
+ };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 7cba389..67056fb 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,5 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
- fixed-factor.o gate.o composite.o
+ fixed-factor.o gate.o clockdomain.o \
+ composite.o
endif
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
new file mode 100644
index 000..f1e0038
--- /dev/null
+++ b/drivers/clk/ti/clockdomain.c
@@ -0,0 +1,70 @@
+/*
+ * OMAP clockdomain support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo t-kri...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk-provider.h
+#include linux/slab.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk/ti.h
+
+#undef pr_fmt
+#define pr_fmt(fmt) %s: fmt, __func__
+
+static void __init of_ti_clockdomain_setup(struct device_node *node)
+{
+ struct clk *clk;
+ struct clk_hw *clk_hw;
+ const char *clkdm_name = node-name;
+ int i;
+ int num_clks;
+
+ num_clks = of_count_phandle_with_args(node, clocks, #clock-cells);
+
+ for (i = 0; i num_clks; i++) {
+ clk = of_clk_get(node, i);
+ if (__clk_get_flags(clk) CLK_IS_BASIC) {
+ pr_warn(can't setup clkdm for basic clk %s\n,
+ __clk_get_name(clk));
+ continue;
+ }
+ clk_hw = __clk_get_hw(clk);
+ to_clk_hw_omap(clk_hw)-clkdm_name = clkdm_name;
+ omap2_init_clk_clkdm(clk_hw);
+ }
+}
+
+static struct of_device_id ti_clkdm_match_table[] __initdata = {
+ { .compatible = ti,clockdomain },
+ { }
+};
+
+/**
+ * ti_dt_clockdomains_setup - setup device tree clockdomains
+ *
+ * Initializes clockdomain nodes for a SoC. This parses through all the
+ * nodes with compatible = ti,clockdomain, and add the clockdomain
+ * info for all the clocks listed under these. This function shall be
+ * called after rest of the DT clock init has completed and all
+ * clock nodes have been registered.
+ */
+void __init
[PATCHv12 23/49] CLK: TI: DRA7: Add APLL support
From: J Keerthy j-keer...@ti.com
The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.
APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.
Signed-off-by: J Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/apll.txt | 31 +++
drivers/clk/ti/Makefile|2 +-
drivers/clk/ti/apll.c | 221
3 files changed, 253 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/apll.txt
create mode 100644 drivers/clk/ti/apll.c
diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt
b/Documentation/devicetree/bindings/clock/ti/apll.txt
new file mode 100644
index 000..7faf5a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/apll.txt
@@ -0,0 +1,31 @@
+Binding for Texas Instruments APLL clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped APLL with usually two selectable input clocks
+(reference clock and bypass clock), with analog phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) APLL mostly behaves like
+a subtype of a DPLL [2], although a simplified one at that.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
+
+Required properties:
+- compatible : shall be ti,dra7-apll-clock
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
+- reg : address and length of the register set for controlling the APLL.
+ It contains the information of registers in the following order:
+ control - contains the control register base address
+ idlest - contains the idlest register base address
+
+Examples:
+ apll_pcie_ck: apll_pcie_ck@4a008200 {
+ #clock-cells = 0;
+ clocks = apll_pcie_in_clk_mux, dpll_pcie_ref_ck;
+ reg = 0x4a00821c 0x4, 0x4a008220 0x4;
+ compatible = ti,dra7-apll-clock;
+ };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 935e5d2..3d71e1e 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,7 +1,7 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
fixed-factor.o gate.o clockdomain.o \
- composite.o mux.o
+ composite.o mux.o apll.o
obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o
obj-$(CONFIG_SOC_OMAP5)+= clk-54xx.o
endif
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
new file mode 100644
index 000..79bcc34
--- /dev/null
+++ b/drivers/clk/ti/apll.c
@@ -0,0 +1,221 @@
+/*
+ * OMAP APLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * J Keerthy j-keer...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk-provider.h
+#include linux/module.h
+#include linux/slab.h
+#include linux/io.h
+#include linux/err.h
+#include linux/string.h
+#include linux/log2.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk/ti.h
+#include linux/delay.h
+
+#define APLL_FORCE_LOCK 0x1
+#define APLL_AUTO_IDLE 0x2
+#define MAX_APLL_WAIT_TRIES100
+
+#undef pr_fmt
+#define pr_fmt(fmt) %s: fmt, __func__
+
+static int dra7_apll_enable(struct clk_hw *hw)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ int r = 0, i = 0;
+ struct dpll_data *ad;
+ const char *clk_name;
+ u8 state = 1;
+ u32 v;
+
+ ad = clk-dpll_data;
+ if (!ad)
+ return -EINVAL;
+
+ clk_name = __clk_get_name(clk-hw.clk);
+
+ state = __ffs(ad-idlest_mask);
+
+ /* Check is already locked */
+ v = ti_clk_ll_ops-clk_readl(ad-idlest_reg);
+
+ if ((v ad-idlest_mask) == state)
+ return r;
+
+ v = ti_clk_ll_ops-clk_readl(ad-control_reg);
+ v = ~ad-enable_mask;
+ v |= APLL_FORCE_LOCK __ffs(ad-enable_mask);
+ ti_clk_ll_ops-clk_writel(v, ad-control_reg);
+
+ state = __ffs(ad-idlest_mask);
+
+
[PATCHv12 43/49] ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT
This patch provides top level functionality for the DT clock initialization.
Clock tree is initialized hierarchically starting from IP modules (CM/PRM/PRCM)
going down towards individual clock nodes, and finally initializing
clockdomains once all the clocks are ready.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/prm.h|1 +
arch/arm/mach-omap2/prm_common.c | 66 ++
2 files changed, 67 insertions(+)
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ac25ae6..623db40 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -18,6 +18,7 @@
# ifndef __ASSEMBLER__
extern void __iomem *prm_base;
extern void omap2_set_globals_prm(void __iomem *prm);
+int of_prcm_init(void);
# endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index a2e1174..f568502 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -23,6 +23,10 @@
#include linux/irq.h
#include linux/interrupt.h
#include linux/slab.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk-provider.h
+#include linux/clk/ti.h
#include soc.h
#include prm2xxx_3xxx.h
@@ -30,6 +34,7 @@
#include prm3xxx.h
#include prm44xx.h
#include common.h
+#include clock.h
/*
* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -464,3 +469,64 @@ int prm_unregister(struct prm_ll_data *pld)
return 0;
}
+
+static struct of_device_id omap_prcm_dt_match_table[] = {
+ { .compatible = ti,am3-prcm },
+ { .compatible = ti,am3-scrm },
+ { .compatible = ti,am4-prcm },
+ { .compatible = ti,am4-scrm },
+ { .compatible = ti,omap3-prm },
+ { .compatible = ti,omap3-cm },
+ { .compatible = ti,omap3-scrm },
+ { .compatible = ti,omap4-cm1 },
+ { .compatible = ti,omap4-prm },
+ { .compatible = ti,omap4-cm2 },
+ { .compatible = ti,omap4-scrm },
+ { .compatible = ti,omap5-prm },
+ { .compatible = ti,omap5-cm-core-aon },
+ { .compatible = ti,omap5-scrm },
+ { .compatible = ti,omap5-cm-core },
+ { .compatible = ti,dra7-prm },
+ { .compatible = ti,dra7-cm-core-aon },
+ { .compatible = ti,dra7-cm-core },
+ { }
+};
+
+static struct clk_hw_omap memmap_dummy_ck = {
+ .flags = MEMMAP_ADDRESSING,
+};
+
+static u32 prm_clk_readl(void __iomem *reg)
+{
+ return omap2_clk_readl(memmap_dummy_ck, reg);
+}
+
+static void prm_clk_writel(u32 val, void __iomem *reg)
+{
+ omap2_clk_writel(val, memmap_dummy_ck, reg);
+}
+
+static struct clk_ll_ops omap_clk_ll_ops = {
+ .clk_readl = prm_clk_readl,
+ .clk_writel = prm_clk_writel,
+};
+
+int __init of_prcm_init(void)
+{
+ struct device_node *np;
+ void __iomem *mem;
+ int memmap_index = 0;
+
+ ti_clk_ll_ops = omap_clk_ll_ops;
+
+ for_each_matching_node(np, omap_prcm_dt_match_table) {
+ mem = of_iomap(np, 0);
+ clk_memmaps[memmap_index] = mem;
+ ti_dt_clk_init_provider(np, memmap_index);
+ memmap_index++;
+ }
+
+ ti_dt_clockdomains_setup();
+
+ return 0;
+}
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv12 12/49] CLK: TI: Add DPLL clock support
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/dpll.txt | 75 +++
arch/arm/mach-omap2/clock.h| 164 +-
arch/arm/mach-omap2/clock3xxx.h|2 -
drivers/clk/ti/Makefile|2 +-
drivers/clk/ti/dpll.c | 558
include/linux/clk/ti.h | 172 ++
6 files changed, 807 insertions(+), 166 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
create mode 100644 drivers/clk/ti/dpll.c
diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt
b/Documentation/devicetree/bindings/clock/ti/dpll.txt
new file mode 100644
index 000..30bfdb7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
@@ -0,0 +1,75 @@
+Binding for Texas Instruments DPLL clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped DPLL with usually two selectable input clocks
+(reference clock and bypass clock), with digital phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) This binding has several
+sub-types, which effectively result in slightly different setup
+for the actual DPLL clock.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of:
+ ti,omap3-dpll-clock,
+ ti,omap3-dpll-core-clock,
+ ti,omap3-dpll-per-clock,
+ ti,omap3-dpll-per-j-type-clock,
+ ti,omap4-dpll-clock,
+ ti,omap4-dpll-x2-clock,
+ ti,omap4-dpll-core-clock,
+ ti,omap4-dpll-m4xen-clock,
+ ti,omap4-dpll-j-type-clock,
+ ti,am3-dpll-no-gate-clock,
+ ti,am3-dpll-j-type-clock,
+ ti,am3-dpll-no-gate-j-type-clock,
+ ti,am3-dpll-clock,
+ ti,am3-dpll-core-clock,
+ ti,am3-dpll-x2-clock,
+
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks, first entry lists reference clock
+ and second entry bypass clock
+- reg : offsets for the register set for controlling the DPLL.
+ Registers are listed in following order:
+ control - contains the control register base address
+ idlest - contains the idle status register base address
+ mult-div1 - contains the multiplier / divider register base address
+ autoidle - contains the autoidle register base address (optional)
+ ti,am3-* dpll types do not have autoidle register
+
+Optional properties:
+- DPLL mode setting - defining any one or more of the following overrides
+ default setting.
+ - ti,low-power-stop : DPLL supports low power stop mode, gating output
+ - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
+ - ti,lock : DPLL locks in programmed rate
+
+Examples:
+ dpll_core_ck: dpll_core_ck@44e00490 {
+ #clock-cells = 0;
+ compatible = ti,omap4-dpll-core-clock;
+ clocks = sys_clkin_ck, sys_clkin_ck;
+ reg = 0x490, 0x45c, 0x488, 0x468;
+ };
+
+ dpll2_ck: dpll2_ck@48004004 {
+ #clock-cells = 0;
+ compatible = ti,omap3-dpll-clock;
+ clocks = sys_ck, dpll2_fck;
+ ti,low-power-stop;
+ ti,low-power-bypass;
+ ti,lock;
+ reg = 0x4, 0x24, 0x34, 0x40;
+ };
+
+ dpll_core_ck: dpll_core_ck@44e00490 {
+ #clock-cells = 0;
+ compatible = ti,am3-dpll-core-clock;
+ clocks = sys_clkin_ck, sys_clkin_ck;
+ reg = 0x90, 0x5c, 0x68;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 82916cc..b345f3e 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
#include linux/clkdev.h
#include linux/clk-provider.h
+#include linux/clk/ti.h
struct omap_clk {
u16 cpu;
@@ -37,7 +38,6 @@ struct omap_clk {
}
struct clockdomain;
-#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
static struct clk _name = { \
@@ -178,141 +178,6 @@ struct clksel {
const struct clksel_rate *rates;
};
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1_mask: mask of the DPLL N
[PATCHv12 14/49] clk: ti: add composite clock support
This is a multipurpose clock node, which contains support for multiple
sub-clocks. Uses basic composite clock type to implement the actual
functionality, and TI specific gate, mux and divider clocks.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/composite.txt | 54
arch/arm/mach-omap2/clock.h|3 -
drivers/clk/ti/Makefile|2 +-
drivers/clk/ti/composite.c | 269
include/linux/clk/ti.h | 12 +
5 files changed, 336 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/composite.txt
create mode 100644 drivers/clk/ti/composite.c
diff --git a/Documentation/devicetree/bindings/clock/ti/composite.txt
b/Documentation/devicetree/bindings/clock/ti/composite.txt
new file mode 100644
index 000..5f43c47
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/composite.txt
@@ -0,0 +1,54 @@
+Binding for TI composite clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped composite clock with multiple different sub-types;
+
+a multiplexer clock with multiple input clock signals or parents, one
+of which can be selected as output, this behaves exactly as [2]
+
+an adjustable clock rate divider, this behaves exactly as [3]
+
+a gating function which can be used to enable and disable the output
+clock, this behaves exactly as [4]
+
+The binding must provide a list of the component clocks that shall be
+merged to this clock. The component clocks shall be of one of the
+ti,*composite*-clock types.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/mux.txt
+[3] Documentation/devicetree/bindings/clock/ti/divider.txt
+[4] Documentation/devicetree/bindings/clock/ti/gate.txt
+
+Required properties:
+- compatible : shall be: ti,composite-clock
+- clocks : link phandles of component clocks
+- #clock-cells : from common clock binding; shall be set to 0.
+
+Examples:
+
+usb_l4_gate_ick: usb_l4_gate_ick {
+ #clock-cells = 0;
+ compatible = ti,composite-interface-clock;
+ clocks = l4_ick;
+ ti,bit-shift = 5;
+ reg = 0x0a10;
+};
+
+usb_l4_div_ick: usb_l4_div_ick {
+ #clock-cells = 0;
+ compatible = ti,composite-divider-clock;
+ clocks = l4_ick;
+ ti,bit-shift = 4;
+ ti,max-div = 1;
+ reg = 0x0a40;
+ ti,index-starts-at-one;
+};
+
+usb_l4_ick: usb_l4_ick {
+ #clock-cells = 0;
+ compatible = ti,composite-clock;
+ clocks = usb_l4_gate_ick, usb_l4_div_ick;
+};
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b345f3e..6bd72b5 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -240,9 +240,6 @@ extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap
*clk);
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
-int omap2_dflt_clk_enable(struct clk_hw *hw);
-void omap2_dflt_clk_disable(struct clk_hw *hw);
-int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
void __iomem **other_reg,
u8 *other_bit);
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 533efb4..a4a7595 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
ifneq ($(CONFIG_OF),)
-obj-y += clk.o dpll.o autoidle.o
+obj-y += clk.o dpll.o autoidle.o composite.o
endif
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
new file mode 100644
index 000..6539b65
--- /dev/null
+++ b/drivers/clk/ti/composite.c
@@ -0,0 +1,269 @@
+/*
+ * TI composite clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo t-kri...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk-provider.h
+#include linux/slab.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk/ti.h
+#include linux/list.h
+
+#undef pr_fmt
+#define pr_fmt(fmt) %s: fmt, __func__
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return clk_divider_ops.recalc_rate(hw,
Re: [PATCH v6 3/7] regulator: add pbias regulator support
On Friday 20 December 2013 09:43 PM, Tony Lindgren wrote: * Mark Brown broo...@kernel.org [131220 08:10]: On Fri, Dec 20, 2013 at 07:57:21AM -0800, Tony Lindgren wrote: * Balaji T K balaj...@ti.com [131220 01:49]: But interrupt was never used/tested AFAIK, there is some settling time before the generated interrupt status is truely valid, so pbias interrupt is not reliable. OK. Do we need the standard regulator property startup-delay-us for the PBIAS regulator then? Or if it's always fixed, I guess it could be done in the pbias_regulator_enable()? That delay is supposed to be the time for the startup of the supply rather than any detection code. It should be set using enable_time in the driver if it's not system dependent - the property is there for cases where the delay depends on system configuration (eg, due to the capacitor values). OK thanks. Let's try enable_time first then as we've had a fixed value for years for it. If there's some difference based on the card capacitance etc that can be added if needed. I used regulator-enable-ramp-delay to set constraints-enable_time based on SoC. Since it is not board dependent, I will drop regulator-enable-ramp-delay from dt and pass the value via driver_data. Thanks and Regards, Balaji T K -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv12 17/49] CLK: TI: add support for gate clock
This patch adds support for TI specific gate clocks. These behave as basic
gate-clock, but have different ops / hw-ops for controlling the actual
gate, for example waiting until the clock is ready. Several sub-types
are supported:
- ti,gate-clock: basic gate clock with default ops/hwops
- ti,clkdm-gate-clock: clockdomain level gate control
- ti,dss-gate-clock: gate clock with DSS specific hardware handling
- ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling
- ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/gate.txt | 85 +++
drivers/clk/ti/Makefile|2 +-
drivers/clk/ti/gate.c | 247
include/linux/clk/ti.h |6 +
4 files changed, 339 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
create mode 100644 drivers/clk/ti/gate.c
diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt
b/Documentation/devicetree/bindings/clock/ti/gate.txt
new file mode 100644
index 000..125281a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
@@ -0,0 +1,85 @@
+Binding for Texas Instruments gate clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features. If no register
+is provided for this clock, the code assumes that a clockdomain
+will be controlled instead and the corresponding hw-ops for
+that is used.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
+
+Required properties:
+- compatible : shall be one of:
+ ti,gate-clock - basic gate clock
+ ti,wait-gate-clock - gate clock which waits until clock is active before
+returning from clk_enable()
+ ti,dss-gate-clock - gate clock with DSS specific hardware handling
+ ti,am35xx-gate-clock - gate clock with AM35xx specific hardware handling
+ ti,clkdm-gate-clock - clockdomain gate clock, which derives its functional
+ clock directly from a clockdomain, see [3] how
+ to map clockdomains properly
+ ti,hsdiv-gate-clock - gate clock with OMAP36xx specific hardware handling,
+ required for a hardware errata
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : offset for register controlling adjustable gate, not needed for
+ ti,clkdm-gate-clock type
+
+Optional properties:
+- ti,bit-shift : bit shift for programming the clock gate, invalid for
+ti,clkdm-gate-clock type
+- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
+ gates the clock and clearing the bit ungates the clock.
+
+Examples:
+ mmchs2_fck: mmchs2_fck@48004a00 {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = core_96m_fck;
+ reg = 0x48004a00 0x4;
+ ti,bit-shift = 25;
+ };
+
+ uart4_fck_am35xx: uart4_fck_am35xx {
+ #clock-cells = 0;
+ compatible = ti,wait-gate-clock;
+ clocks = core_48m_fck;
+ reg = 0x0a00;
+ ti,bit-shift = 23;
+ };
+
+ dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
+ #clock-cells = 0;
+ compatible = ti,dss-gate-clock;
+ clocks = dpll4_m4x2_ck;
+ reg = 0x48004e00 0x4;
+ ti,bit-shift = 0;
+ };
+
+ emac_ick: emac_ick@4800259c {
+ #clock-cells = 0;
+ compatible = ti,am35xx-gate-clock;
+ clocks = ipss_ick;
+ reg = 0x4800259c 0x4;
+ ti,bit-shift = 1;
+ };
+
+ emu_src_ck: emu_src_ck {
+ #clock-cells = 0;
+ compatible = ti,clkdm-gate-clock;
+ clocks = emu_src_mux_ck;
+ };
+
+ dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
+ #clock-cells = 0;
+ compatible = ti,hsdiv-gate-clock;
+ clocks = dpll4_m2x2_mul_ck;
+ ti,bit-shift = 0x1b;
+ reg = 0x48004d00 0x4;
+ ti,set-bit-to-disable;
+ };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index f57fc4b..7cba389 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,4 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o divider.o \
- fixed-factor.o composite.o
+
Re: OMAP display subsystem - does it work?
* Tony Lindgren t...@atomide.com [131220 08:06]:
* Tomi Valkeinen tomi.valkei...@ti.com [131220 05:45]:
On 2013-12-20 13:48, Russell King - ARM Linux wrote:
Or maybe this is getting buggered by the idiotic deferred probing... It
seems that the GPIOs for controlling the LCD and backlight aren't even
getting claimed if the DSS modules are built in:
# cat /sys/kernel/debug/gpio
...
GPIOs 238-255, platform/twl4030_gpio, twl4030, can sleep:
# echo panel-dpi.0 /sys/bus/platform/drivers/panel-dpi/unbind
# echo panel-dpi.0 /sys/bus/platform/drivers/panel-dpi/bind
# cat /sys/kernel/debug/gpio
...
GPIOs 238-255, platform/twl4030_gpio, twl4030, can sleep:
gpio-245 (panel enable) out lo
gpio-253 (panel backlight ) out lo
This looks odd... Presuming the panel device was probed successfully, it
should always get the gpios or return an error. Only if gpio_is_valid()
returns false for the gpio, it skips it and continues. But in this case,
the gpio number comes from the platform data, so it should always be valid.
And if it wasn't probed successfully, then there shouldn't be a fb0.
I bet that's it though. If the display is probed before twl4030 GPIO
is initialized, the GPIO numbers will be 0. I'm using omap2plus_defconfig
which has DSS built as modules.
Yeah this seems to do the trick for me for the built-in DSS on LDP.
Tony
8 ---
From: Tony Lindgren t...@atomide.com
Date: Fri, 20 Dec 2013 08:53:27 -0800
Subject: [PATCH] ARM: OMAP2+: Fix LCD panel backlight regression for LDP legacy
booting
Looks like the LCD panel on LDP has been broken quite a while, and
recently got fixed. However, there's still an issue where the panel
backlight does not come on if the LCD drivers are built into the
kernel.
Fix the issue by registering the DPI LCD panel only after the twl4030
GPIO has probed.
Reported-by: Russell King rmk+ker...@arm.linux.org.uk
Signed-off-by: Tony Lindgren t...@atomide.com
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -248,7 +248,7 @@ static int ldp_twl_gpio_setup(struct device *dev, unsigned
gpio, unsigned ngpio)
/* Backlight enable GPIO */
ldp_lcd_pdata.backlight_gpio = gpio + 15;
- return 0;
+ return platform_device_register(ldp_lcd_device);
}
static struct twl4030_gpio_platform_data ldp_gpio_data = {
@@ -346,7 +346,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
static struct platform_device *ldp_devices[] __initdata = {
ldp_gpio_keys_device,
- ldp_lcd_device,
};
#ifdef CONFIG_OMAP_MUX
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 2/7] mmc: omap_hsmmc: handle vcc and vcc_aux independently
handle vcc and vcc_aux independently to reduce indent.
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 54 +++--
1 files changed, 25 insertions(+), 29 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 1eb4350..342be25 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -286,11 +286,12 @@ static int omap_hsmmc_set_power(struct device *dev, int
slot, int power_on,
* chips/cards need an interface voltage rail too.
*/
if (power_on) {
- ret = mmc_regulator_set_ocr(host-mmc, host-vcc, vdd);
+ if (host-vcc)
+ ret = mmc_regulator_set_ocr(host-mmc, host-vcc, vdd);
/* Enable interface voltage rail, if needed */
if (ret == 0 host-vcc_aux) {
ret = regulator_enable(host-vcc_aux);
- if (ret 0)
+ if (ret 0 host-vcc)
ret = mmc_regulator_set_ocr(host-mmc,
host-vcc, 0);
}
@@ -298,7 +299,7 @@ static int omap_hsmmc_set_power(struct device *dev, int
slot, int power_on,
/* Shut down the rail */
if (host-vcc_aux)
ret = regulator_disable(host-vcc_aux);
- if (!ret) {
+ if (host-vcc) {
/* Then proceed to shut down the local regulator */
ret = mmc_regulator_set_ocr(host-mmc,
host-vcc, 0);
@@ -318,10 +319,10 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host)
reg = devm_regulator_get(host-dev, vmmc);
if (IS_ERR(reg)) {
- dev_err(host-dev, vmmc regulator missing\n);
+ dev_err(host-dev, unable to get vmmc regulator %ld\n,
+ PTR_ERR(reg));
return PTR_ERR(reg);
} else {
- mmc_slot(host).set_power = omap_hsmmc_set_power;
host-vcc = reg;
ocr_value = mmc_regulator_get_ocrmask(reg);
if (!mmc_slot(host).ocr_mask) {
@@ -334,31 +335,26 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host)
return -EINVAL;
}
}
+ }
+ mmc_slot(host).set_power = omap_hsmmc_set_power;
- /* Allow an aux regulator */
- reg = devm_regulator_get_optional(host-dev, vmmc_aux);
- host-vcc_aux = IS_ERR(reg) ? NULL : reg;
+ /* Allow an aux regulator */
+ reg = devm_regulator_get_optional(host-dev, vmmc_aux);
+ host-vcc_aux = IS_ERR(reg) ? NULL : reg;
- /* For eMMC do not power off when not in sleep state */
- if (mmc_slot(host).no_regulator_off_init)
- return 0;
- /*
- * UGLY HACK: workaround regulator framework bugs.
- * When the bootloader leaves a supply active, it's
- * initialized with zero usecount ... and we can't
- * disable it without first enabling it. Until the
- * framework is fixed, we need a workaround like this
- * (which is safe for MMC, but not in general).
- */
- if (regulator_is_enabled(host-vcc) 0 ||
- (host-vcc_aux regulator_is_enabled(host-vcc_aux))) {
- int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
+ /* For eMMC do not power off when not in sleep state */
+ if (mmc_slot(host).no_regulator_off_init)
+ return 0;
+ /*
+* To disable boot_on regulator, enable regulator
+* to increase usecount and then disable it.
+*/
+ if ((host-vcc regulator_is_enabled(host-vcc) 0) ||
+ (host-vcc_aux regulator_is_enabled(host-vcc_aux))) {
+ int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
- mmc_slot(host).set_power(host-dev, host-slot_id,
-1, vdd);
- mmc_slot(host).set_power(host-dev, host-slot_id,
-0, 0);
- }
+ mmc_slot(host).set_power(host-dev, host-slot_id, 1, vdd);
+ mmc_slot(host).set_power(host-dev, host-slot_id, 0, 0);
}
return 0;
--
1.7.5.4
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 0/7] mmc: omap_hsmmc: pbias dt and cleanup
Balaji T K (7): mmc: omap_hsmmc: use devm_regulator API mmc: omap_hsmmc: handle vcc and vcc_aux independently regulator: add pbias regulator support mmc: omap_hsmmc: adapt hsmmc to use pbias regulator ARM: dts: add pbias dt node ARM: OMAP: enable SYSCON and REGULATOR_PBIAS in omap2plus_defconfig mmc: omap_hsmmc: remove pbias workaround .../bindings/regulator/pbias-regulator.txt | 16 ++ arch/arm/boot/dts/dra7.dtsi| 18 ++ arch/arm/boot/dts/omap2430.dtsi| 18 ++ arch/arm/boot/dts/omap3.dtsi | 18 ++ arch/arm/boot/dts/omap4.dtsi | 18 ++ arch/arm/boot/dts/omap5.dtsi | 18 ++ arch/arm/configs/omap2plus_defconfig |2 + drivers/mmc/host/omap_hsmmc.c | 113 + drivers/regulator/Kconfig |9 + drivers/regulator/Makefile |1 + drivers/regulator/pbias-regulator.c| 261 11 files changed, 443 insertions(+), 49 deletions(-) create mode 100644 Documentation/devicetree/bindings/regulator/pbias-regulator.txt create mode 100644 drivers/regulator/pbias-regulator.c -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 4/7] mmc: omap_hsmmc: adapt hsmmc to use pbias regulator
In DT case, PBAIS registers are programmed via regulator,
use regulator APIs to control PBIAS.
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 39 +++
1 files changed, 39 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 342be25..0a390f8 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -126,6 +126,10 @@
#define OMAP_MMC_MAX_CLOCK 5200
#define DRIVER_NAMEomap_hsmmc
+#define VDD_1V8180 /* 18 uV */
+#define VDD_3V0300 /* 30 uV */
+#define VDD_165_195(ffs(MMC_VDD_165_195) - 1)
+
/*
* One controller can have multiple slots, like on some omap boards using
* omap.c controller driver. Luckily this is not currently done on any known
@@ -164,6 +168,8 @@ struct omap_hsmmc_host {
*/
struct regulator *vcc;
struct regulator *vcc_aux;
+ struct regulator *pbias;
+ boolpbias_enabled;
int pbias_disable;
void__iomem *base;
resource_size_t mapbase;
@@ -272,6 +278,15 @@ static int omap_hsmmc_set_power(struct device *dev, int
slot, int power_on,
if (mmc_slot(host).before_set_reg)
mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
+ if (host-pbias) {
+ if (host-pbias_enabled == 1) {
+ ret = regulator_disable(host-pbias);
+ if (!ret)
+ host-pbias_enabled = 0;
+ }
+ regulator_set_voltage(host-pbias, VDD_3V0, VDD_3V0);
+ }
+
/*
* Assume Vcc regulator is used only to power the card ... OMAP
* VDDS is used to power the pins, optionally with a transceiver to
@@ -306,9 +321,29 @@ static int omap_hsmmc_set_power(struct device *dev, int
slot, int power_on,
}
}
+ if (host-pbias) {
+ if (vdd = VDD_165_195)
+ ret = regulator_set_voltage(host-pbias, VDD_1V8,
+ VDD_1V8);
+ else
+ ret = regulator_set_voltage(host-pbias, VDD_3V0,
+ VDD_3V0);
+ if (ret 0)
+ goto error_set_power;
+
+ if (host-pbias_enabled == 0) {
+ ret = regulator_enable(host-pbias);
+ if (!ret) {
+ host-pbias_enabled = 1;
+ goto error_set_power;
+ }
+ }
+ }
+
if (mmc_slot(host).after_set_reg)
mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
+error_set_power:
return ret;
}
@@ -342,6 +377,9 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
reg = devm_regulator_get_optional(host-dev, vmmc_aux);
host-vcc_aux = IS_ERR(reg) ? NULL : reg;
+ reg = devm_regulator_get_optional(host-dev, pbias);
+ host-pbias = IS_ERR(reg) ? NULL : reg;
+
/* For eMMC do not power off when not in sleep state */
if (mmc_slot(host).no_regulator_off_init)
return 0;
@@ -1808,6 +1846,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
host-base = ioremap(host-mapbase, SZ_4K);
host-power_mode = MMC_POWER_OFF;
host-next_data.cookie = 1;
+ host-pbias_enabled = 0;
platform_set_drvdata(pdev, host);
--
1.7.5.4
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 1/7] mmc: omap_hsmmc: use devm_regulator API
Use devm_regulator API, while at it use
devm_regulator_get_optional for optional vmmc_aux supply
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index dbd32ad..1eb4350 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -316,7 +316,7 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
struct regulator *reg;
int ocr_value = 0;
- reg = regulator_get(host-dev, vmmc);
+ reg = devm_regulator_get(host-dev, vmmc);
if (IS_ERR(reg)) {
dev_err(host-dev, vmmc regulator missing\n);
return PTR_ERR(reg);
@@ -336,7 +336,7 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
}
/* Allow an aux regulator */
- reg = regulator_get(host-dev, vmmc_aux);
+ reg = devm_regulator_get_optional(host-dev, vmmc_aux);
host-vcc_aux = IS_ERR(reg) ? NULL : reg;
/* For eMMC do not power off when not in sleep state */
@@ -366,8 +366,6 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
{
- regulator_put(host-vcc);
- regulator_put(host-vcc_aux);
mmc_slot(host).set_power = NULL;
}
--
1.7.5.4
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 5/7] ARM: dts: add pbias dt node
Add pbias regulator node as a child of system control
module - syscon.
Signed-off-by: Balaji T K balaj...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 18 ++
arch/arm/boot/dts/omap2430.dtsi | 18 ++
arch/arm/boot/dts/omap3.dtsi| 18 ++
arch/arm/boot/dts/omap4.dtsi| 18 ++
arch/arm/boot/dts/omap5.dtsi| 18 ++
5 files changed, 90 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d0df4c4..4e68df1 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -110,6 +110,23 @@
ti,hwmods = counter_32k;
};
+ dra7_ctrl_general: tisyscon@4a002e00 {
+ compatible = ti,control-syscon, syscon,
simple-bus;
+ reg = 0x4a002e00 0x7c;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ pbias_regulator: pbias_regulator {
+ compatible = ti,pbias-omap;
+ reg = 0 0x4;
+ pbias_mmc_reg: pbias_mmc_omap5 {
+ regulator-name = pbias_mmc_omap5;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 300;
+ };
+ };
+ };
+
dra7_pmx_core: pinmux@4a003400 {
compatible = pinctrl-single;
reg = 0x4a003400 0x0464;
@@ -485,6 +502,7 @@
dmas = sdma 61, sdma 62;
dma-names = tx, rx;
status = disabled;
+ pbias-supply = pbias_mmc_reg;
};
mmc2: mmc@480b4000 {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index d624345..142de17 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -29,6 +29,23 @@
pinctrl-single,function-mask = 0x3f;
};
+ omap2_scm_general: tisyscon@49002270 {
+ compatible = ti,control-syscon, syscon,
simple-bus;
+ reg = 0x49002270 0x240;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ pbias_regulator: pbias_regulator {
+ compatible = ti,pbias-omap;
+ reg = 0x230 0x4;
+ pbias_mmc_reg: pbias_mmc_omap2430 {
+ regulator-name = pbias_mmc_omap2430;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 300;
+ };
+ };
+ };
+
gpio1: gpio@4900c000 {
compatible = ti,omap2-gpio;
reg = 0x4900c000 0x200;
@@ -183,6 +200,7 @@
ti,dual-volt;
dmas = sdma 61, sdma 62;
dma-names = tx, rx;
+ pbias-supply = pbias_mmc_reg;
};
mmc2: mmc@480b4000 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index daabf99..ba796e9 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -137,6 +137,23 @@
pinctrl-single,function-mask = 0xff1f;
};
+ omap3_scm_general: tisyscon@48002270 {
+ compatible = ti,control-syscon, syscon,
simple-bus;
+ reg = 0x48002270 0x2f0;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ pbias_regulator: pbias_regulator {
+ compatible = ti,pbias-omap;
+ reg = 0x2b0 0x4;
+ pbias_mmc_reg: pbias_mmc_omap2430 {
+ regulator-name = pbias_mmc_omap2430;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 300;
+ };
+ };
+ };
+
gpio1: gpio@4831 {
compatible = ti,omap3-gpio;
reg = 0x4831 0x200;
@@ -351,6 +368,7 @@
ti,dual-volt;
dmas = sdma 61, sdma 62;
dma-names = tx, rx;
+ pbias-supply = pbias_mmc_reg;
};
[PATCH v7 3/7] regulator: add pbias regulator support
pbias register controls internal power supply to sd card i/o pads
in most OMAPs (OMAP2-5, DRA7).
Control bits for selecting voltage level and
enabling/disabling are in the same PBIAS register.
Signed-off-by: Balaji T K balaj...@ti.com
---
.../bindings/regulator/pbias-regulator.txt | 16 ++
drivers/regulator/Kconfig |9 +
drivers/regulator/Makefile |1 +
drivers/regulator/pbias-regulator.c| 261
4 files changed, 287 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/regulator/pbias-regulator.txt
create mode 100644 drivers/regulator/pbias-regulator.c
diff --git a/Documentation/devicetree/bindings/regulator/pbias-regulator.txt
b/Documentation/devicetree/bindings/regulator/pbias-regulator.txt
new file mode 100644
index 000..359d3f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/pbias-regulator.txt
@@ -0,0 +1,16 @@
+PBIAS internal regulator for SD card dual voltage i/o pads on OMAP SoCs.
+
+Required properties:
+- compatible:
+ - ti,pbias-omap for OMAP2, OMAP3, OMAP4, OMAP5, DRA7
+
+Optional properties:
+- Any optional property defined in bindings/regulator/regulator.txt
+
+Example:
+
+ pbias_regulator: pbias_regulator {
+ regulator-name = pbias_mmc_omap4;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 300;
+ };
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index ce785f4..741e8fb 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -369,6 +369,15 @@ config REGULATOR_PALMAS
on the muxing. This is handled automatically in the driver by
reading the mux info from OTP.
+config REGULATOR_PBIAS
+ tristate PBIAS OMAP regulator driver
+ depends on (ARCH_OMAP || COMPILE_TEST) MFD_SYSCON
+ help
+Say y here to support pbias regulator for mmc1:SD card i/o
+on OMAP SoCs.
+This driver provides support for OMAP pbias modelled
+regulators.
+
config REGULATOR_PCAP
tristate Motorola PCAP2 regulator driver
depends on EZX_PCAP
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 01c597e..16000fa 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_REGULATOR_MC13XXX_CORE) +=
mc13xxx-regulator-core.o
obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o
obj-$(CONFIG_REGULATOR_PFUZE100) += pfuze100-regulator.o
obj-$(CONFIG_REGULATOR_TPS51632) += tps51632-regulator.o
+obj-$(CONFIG_REGULATOR_PBIAS) += pbias-regulator.o
obj-$(CONFIG_REGULATOR_PCAP) += pcap-regulator.o
obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o
obj-$(CONFIG_REGULATOR_RC5T583) += rc5t583-regulator.o
diff --git a/drivers/regulator/pbias-regulator.c
b/drivers/regulator/pbias-regulator.c
new file mode 100644
index 000..992ec09
--- /dev/null
+++ b/drivers/regulator/pbias-regulator.c
@@ -0,0 +1,261 @@
+/*
+ * pbias-regulator.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Balaji T K balaj...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/err.h
+#include linux/io.h
+#include linux/module.h
+#include linux/mfd/syscon.h
+#include linux/platform_device.h
+#include linux/regulator/driver.h
+#include linux/regulator/machine.h
+#include linux/regulator/of_regulator.h
+#include linux/regmap.h
+#include linux/slab.h
+#include linux/of.h
+#include linux/of_device.h
+
+struct pbias_reg_info {
+ u32 enable;
+ u32 enable_mask;
+ u32 vmode;
+ unsigned int enable_time;
+ char *name;
+};
+
+struct pbias_regulator_data {
+ struct regulator_desc desc;
+ void __iomem *pbias_addr;
+ unsigned int pbias_reg;
+ struct regulator_dev *dev;
+ struct regmap *syscon;
+ const struct pbias_reg_info *info;
+ int voltage;
+};
+
+static int pbias_regulator_set_voltage(struct regulator_dev *dev,
+ int min_uV, int max_uV, unsigned *selector)
+{
+ struct pbias_regulator_data *data = rdev_get_drvdata(dev);
+ const struct pbias_reg_info *info = data-info;
+ int ret, vmode;
+
+ if (min_uV = 180)
+ vmode = 0;
+ else if (min_uV 180)
+ vmode = info-vmode;
+
+ ret = regmap_update_bits(data-syscon, data-pbias_reg,
+ info-vmode, vmode);
+
+
[PATCH v7 7/7] mmc: omap_hsmmc: remove pbias workaround
remove pbias workaround
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 20 +---
1 files changed, 1 insertions(+), 19 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 0a390f8..0f0aa5d 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -170,7 +170,6 @@ struct omap_hsmmc_host {
struct regulator *vcc_aux;
struct regulator *pbias;
boolpbias_enabled;
- int pbias_disable;
void__iomem *base;
resource_size_t mapbase;
spinlock_t irq_lock; /* Prevent races with irq handler */
@@ -267,13 +266,6 @@ static int omap_hsmmc_set_power(struct device *dev, int
slot, int power_on,
*/
if (!host-vcc)
return 0;
- /*
-* With DT, never turn OFF the regulator for MMC1. This is because
-* the pbias cell programming support is still missing when
-* booting with Device tree
-*/
- if (host-pbias_disable !vdd)
- return 0;
if (mmc_slot(host).before_set_reg)
mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
@@ -1541,13 +1533,7 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc,
struct mmc_ios *ios)
* of external transceiver; but they all handle 1.8V.
*/
if ((OMAP_HSMMC_READ(host-base, HCTL) SDVSDET)
- (ios-vdd == DUAL_VOLT_OCR_BIT)
- /*
-* With pbias cell programming missing, this
-* can't be allowed on MMC1 when booting with device
-* tree.
-*/
- !host-pbias_disable) {
+ (ios-vdd == DUAL_VOLT_OCR_BIT)) {
/*
* The mmc_select_voltage fn of the core does
* not seem to set the power_mode to
@@ -1880,10 +1866,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
omap_hsmmc_context_save(host);
- /* This can be removed once we support PBIAS with DT */
- if (host-dev-of_node res-start == 0x4809c000)
- host-pbias_disable = 1;
-
host-dbclk = clk_get(pdev-dev, mmchsdb_fck);
/*
* MMC can still work without debounce clock.
--
1.7.5.4
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 6/7] ARM: OMAP: enable SYSCON and REGULATOR_PBIAS in omap2plus_defconfig
Enable REGULATOR_PBIAS needed for SD card on most OMAPs. Signed-off-by: Balaji T K balaj...@ti.com --- arch/arm/configs/omap2plus_defconfig |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index bfa80a1..f67baa9 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -169,6 +169,7 @@ CONFIG_DRA752_THERMAL=y CONFIG_WATCHDOG=y CONFIG_OMAP_WATCHDOG=y CONFIG_TWL4030_WATCHDOG=y +CONFIG_MFD_SYSCON=y CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65217=y CONFIG_MFD_TPS65910=y @@ -180,6 +181,7 @@ CONFIG_REGULATOR_TPS6507X=y CONFIG_REGULATOR_TPS65217=y CONFIG_REGULATOR_TPS65910=y CONFIG_REGULATOR_TWL4030=y +CONFIG_REGULATOR_PBIAS=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_MODE_HELPERS=y -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 4/7] mmc: omap_hsmmc: adapt hsmmc to use pbias regulator
Hi
On Fri, Dec 20, 2013 at 6:35 PM, Balaji T K balaj...@ti.com wrote:
In DT case, PBAIS registers are programmed via regulator,
use regulator APIs to control PBIAS.
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 39 +++
1 files changed, 39 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 342be25..0a390f8 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -126,6 +126,10 @@
#define OMAP_MMC_MAX_CLOCK 5200
#define DRIVER_NAMEomap_hsmmc
+#define VDD_1V8180 /* 18 uV */
+#define VDD_3V0300 /* 30 uV */
+#define VDD_165_195(ffs(MMC_VDD_165_195) - 1)
+
/*
* One controller can have multiple slots, like on some omap boards using
* omap.c controller driver. Luckily this is not currently done on any known
@@ -164,6 +168,8 @@ struct omap_hsmmc_host {
*/
struct regulator *vcc;
struct regulator *vcc_aux;
+ struct regulator *pbias;
+ boolpbias_enabled;
int pbias_disable;
void__iomem *base;
resource_size_t mapbase;
@@ -272,6 +278,15 @@ static int omap_hsmmc_set_power(struct device *dev, int
slot, int power_on,
if (mmc_slot(host).before_set_reg)
mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
+ if (host-pbias) {
+ if (host-pbias_enabled == 1) {
+ ret = regulator_disable(host-pbias);
+ if (!ret)
+ host-pbias_enabled = 0;
you should return error?
+ }
+ regulator_set_voltage(host-pbias, VDD_3V0, VDD_3V0);
+ }
+
/*
* Assume Vcc regulator is used only to power the card ... OMAP
* VDDS is used to power the pins, optionally with a transceiver to
@@ -306,9 +321,29 @@ static int omap_hsmmc_set_power(struct device *dev, int
slot, int power_on,
}
}
+ if (host-pbias) {
+ if (vdd = VDD_165_195)
+ ret = regulator_set_voltage(host-pbias, VDD_1V8,
+ VDD_1V8);
+ else
+ ret = regulator_set_voltage(host-pbias, VDD_3V0,
+ VDD_3V0);
+ if (ret 0)
+ goto error_set_power;
+
+ if (host-pbias_enabled == 0) {
+ ret = regulator_enable(host-pbias);
+ if (!ret) {
+ host-pbias_enabled = 1;
+ goto error_set_power;
Is this an error condition? Do you need this flag?
Mcihael
+ }
+ }
+ }
+
if (mmc_slot(host).after_set_reg)
mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
+error_set_power:
return ret;
}
@@ -342,6 +377,9 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host)
reg = devm_regulator_get_optional(host-dev, vmmc_aux);
host-vcc_aux = IS_ERR(reg) ? NULL : reg;
+ reg = devm_regulator_get_optional(host-dev, pbias);
+ host-pbias = IS_ERR(reg) ? NULL : reg;
+
/* For eMMC do not power off when not in sleep state */
if (mmc_slot(host).no_regulator_off_init)
return 0;
@@ -1808,6 +1846,7 @@ static int omap_hsmmc_probe(struct platform_device
*pdev)
host-base = ioremap(host-mapbase, SZ_4K);
host-power_mode = MMC_POWER_OFF;
host-next_data.cookie = 1;
+ host-pbias_enabled = 0;
platform_set_drvdata(pdev, host);
--
1.7.5.4
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv12 00/49] ARM: TI SoC clock DT conversion
* Tero Kristo t-kri...@ti.com [131220 08:36]: Hi, Hopefully final post of this series. At least this is going to be the last post this year as I will be going to x-mas vacation and won't be back before Jan 2nd. This time I just sent the patches that have changes in them, the missing ones are exactly the same as in v11. Changes done: - most of the patches: * Some cosmetic documentation fixes - patch 06: * Changed register pointer types from 'u32 __iomem *' to 'void __iomem *' - patch 07,08,09: * Added check for clk-ll_ops being NULL (happens with statically built clock data), fixes the boot time crash issue noticed by Tony - patch 11: * Moved __clk_of_table extern declaration to clk-provider.h header file... Got flamed about this enough times now. :) * Type for the declaration changed also from array to single entry, and address for this used in code. This prevents compile time error: array type has incomplete element type. Can't use pointer here either as this messes the address of the table. * ti_clk_retry_init() now has int return type, and checks for kzalloc failure - patch 12, 14, 23: * Added cleanup in case ti_clk_retry_init() fails - patch 17: * Fixed potential memory leak in failed init detected by sparse - patch 18: * Modified commit message to add some details about clockdomains - patch 43: * Changed register pointer types from 'u32 *' to 'void __iomem *' Testing done: - omap3-beagle: boot, suspend/resume (ret), suspend/resume (off) - omap4-panda-es: boot, suspend/resume (ret) - omap5-uevm: boot - am335x-bone: boot - dra7-evm: boot Branches available at https://github.com/t-kristo/linux-pm.git: - branch: 3.13-rc4-dt-clks-v12 : contains everything, shall me merged last - branch: 3.13-rc4-dt-clks-v12-for-mike : drivers/clk changes - branch: 3.13-rc4-dt-clks-v11-for-benoit : DT data only (from v11, no changes) Boots now for me on omap2/3/4, and off-idle works on omap3. So as far as I'm concerned, please feel free to add my ack to the new and updated patches still missing it: Acked-by: Tony Lindgren t...@atomide.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 1/7] mmc: omap_hsmmc: use devm_regulator API
* Balaji T K balaj...@ti.com [131220 09:37]:
Use devm_regulator API, while at it use
devm_regulator_get_optional for optional vmmc_aux supply
Signed-off-by: Balaji T K balaj...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/mmc/host/omap_hsmmc.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index dbd32ad..1eb4350 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -316,7 +316,7 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host)
struct regulator *reg;
int ocr_value = 0;
- reg = regulator_get(host-dev, vmmc);
+ reg = devm_regulator_get(host-dev, vmmc);
if (IS_ERR(reg)) {
dev_err(host-dev, vmmc regulator missing\n);
return PTR_ERR(reg);
@@ -336,7 +336,7 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host)
}
/* Allow an aux regulator */
- reg = regulator_get(host-dev, vmmc_aux);
+ reg = devm_regulator_get_optional(host-dev, vmmc_aux);
host-vcc_aux = IS_ERR(reg) ? NULL : reg;
/* For eMMC do not power off when not in sleep state */
@@ -366,8 +366,6 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host)
static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
{
- regulator_put(host-vcc);
- regulator_put(host-vcc_aux);
mmc_slot(host).set_power = NULL;
}
--
1.7.5.4
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 2/7] mmc: omap_hsmmc: handle vcc and vcc_aux independently
* Balaji T K balaj...@ti.com [131220 09:37]: handle vcc and vcc_aux independently to reduce indent. Signed-off-by: Balaji T K balaj...@ti.com Acked-by: Tony Lindgren t...@atomide.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv12 00/49] ARM: TI SoC clock DT conversion
On Fri, Dec 20, 2013 at 06:34:19PM +0200, Tero Kristo wrote: Hi, Hopefully final post of this series. At least this is going to be the last post this year as I will be going to x-mas vacation and won't be back before Jan 2nd. This time I just sent the patches that have changes in them, the missing ones are exactly the same as in v11. Changes done: - most of the patches: * Some cosmetic documentation fixes - patch 06: * Changed register pointer types from 'u32 __iomem *' to 'void __iomem *' - patch 07,08,09: * Added check for clk-ll_ops being NULL (happens with statically built clock data), fixes the boot time crash issue noticed by Tony - patch 11: * Moved __clk_of_table extern declaration to clk-provider.h header file... Got flamed about this enough times now. :) * Type for the declaration changed also from array to single entry, and address for this used in code. This prevents compile time error: array type has incomplete element type. Can't use pointer here either as this messes the address of the table. * ti_clk_retry_init() now has int return type, and checks for kzalloc failure - patch 12, 14, 23: * Added cleanup in case ti_clk_retry_init() fails - patch 17: * Fixed potential memory leak in failed init detected by sparse - patch 18: * Modified commit message to add some details about clockdomains - patch 43: * Changed register pointer types from 'u32 *' to 'void __iomem *' Testing done: - omap3-beagle: boot, suspend/resume (ret), suspend/resume (off) - omap4-panda-es: boot, suspend/resume (ret) - omap5-uevm: boot - am335x-bone: boot - dra7-evm: boot Branches available at https://github.com/t-kristo/linux-pm.git: - branch: 3.13-rc4-dt-clks-v12 : contains everything, shall me merged last - branch: 3.13-rc4-dt-clks-v12-for-mike : drivers/clk changes - branch: 3.13-rc4-dt-clks-v11-for-benoit : DT data only (from v11, no changes) Still fails to build OMAP5-only defconfig: drivers/built-in.o: In function `of_ti_composite_interface_clk_setup': drivers/clk/ti/gate.c:190: undefined reference to `clkhwops_iclk_wait' make: *** [vmlinux] Error 1 -- balbi signature.asc Description: Digital signature
Re: [PATCHv12 00/49] ARM: TI SoC clock DT conversion
On Fri, Dec 20, 2013 at 06:34:19PM +0200, Tero Kristo wrote: Hopefully final post of this series. At least this is going to be the last post this year as I will be going to x-mas vacation and won't be back before Jan 2nd. This time I just sent the patches that have changes in them, the missing ones are exactly the same as in v11. Testing done: - omap3-beagle: boot, suspend/resume (ret), suspend/resume (off) - omap4-panda-es: boot, suspend/resume (ret) - omap5-uevm: boot - am335x-bone: boot - dra7-evm: boot Booting the 3.13-rc4-dt-clks-v12 branch on my Nokia N900 works: Tested-By: Sebastian Reichel s...@debian.org -- Sebastian signature.asc Description: Digital signature
Re: [PATCH/RFC] ARM: omap3: Split the pinmux core device
Hi Tony, On Thursday 19 December 2013 10:30:03 Tony Lindgren wrote: * Sebastian Reichel s...@ring0.de [131219 09:19]: On Wed, Dec 04, 2013 at 06:11:50PM +0100, Laurent Pinchart wrote: The omap3_pmx_core pinmux device in the device tree handles the system controller module (SCM) PADCONFS fonction. Its control registers are split in two distinct areas, with other SCM registers in-between. Those other registers can't thus be requested by other drivers as the memory region gets reserved by the pinmux driver. Split the omap3_pmx_core device tree node in two for the two memory regions. Signed-off-by: Laurent Pinchart laurent.pinch...@ideasonboard.com --- arch/arm/boot/dts/omap3-beagle-xm.dts | 45 ++-- arch/arm/boot/dts/omap3-beagle.dts| 28 +++--- arch/arm/boot/dts/omap3-igep0020.dts | 26 ++-- arch/arm/boot/dts/omap3-zoom3.dts | 19 ++- arch/arm/boot/dts/omap3.dtsi | 13 +- 5 files changed, 95 insertions(+), 36 deletions(-) While working on the OMAP3 ISP driver I've run into a failure to request a memory region already requested by the pinctrl-single driver. This patch is an attempt to fix the problem. An alternative approach would be to support multiple reg values in the pinctrl-single driver, but that might not be much cleaner. I'm open to suggestions. Acked-By: Sebastian Reichel s...@debian.org I haven't checked the board dts files, but the change in omap3.dtsi is needed to fix a external abort on non-linefetch when doing cat /sys/kernel/debug/pinctrl/.../pins on my Nokia N900. OK, that should be mentioned in the patch. Laurent, care to update the patch for that? Done. We should also check that the register ranges match with Nishant's similar patch [PATCH] ARM: dts: omap3: split pinctrl for core into two parts. I've checked Nishanth's patch and updated mine as I had forgotten the LED pins on the IGEP boards. Reviewing the two patches side by side wouldn't hurt of course. -- Regards, Laurent Pinchart -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 3/7] regulator: add pbias regulator support
* Balaji T K balaj...@ti.com [131220 09:37]:
+static const struct pbias_reg_info pbias_mmc_omap2430 = {
+ .enable = BIT(1),
+ .enable_mask = BIT(1),
+ .vmode = BIT(0),
+ .enable_time = 100,
+ .name = pbias_mmc_omap2430
+};
+
+static const struct pbias_reg_info pbias_sim_omap3 = {
+ .enable = BIT(9),
+ .enable_mask = BIT(9),
+ .vmode = BIT(8),
+ .enable_time = 100,
+ .name = pbias_sim_omap3
+};
+
+static const struct pbias_reg_info pbias_mmc_omap4 = {
+ .enable = BIT(26) | BIT(22),
+ .enable_mask = BIT(26) | BIT(25) | BIT(22),
+ .vmode = BIT(21),
+ .enable_time = 10,
+ .name = pbias_mmc_omap4
+};
+
+static const struct pbias_reg_info pbias_mmc_omap5 = {
+ .enable = BIT(27) | BIT(26),
+ .enable_mask = BIT(27) | BIT(25) | BIT(26),
+ .vmode = BIT(21),
+ .enable_time = 100,
+ .name = pbias_mmc_omap5
+};
Should the enable_time be 100 for omap4 like for the others?
Other than that:
Acked-by: Tony Lindgren t...@atomide.com
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 5/7] ARM: dts: add pbias dt node
* Balaji T K balaj...@ti.com [131220 09:37]: Add pbias regulator node as a child of system control module - syscon. Signed-off-by: Balaji T K balaj...@ti.com Benoit should queue this: Acked-by: Tony Lindgren t...@atomide.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 6/7] ARM: OMAP: enable SYSCON and REGULATOR_PBIAS in omap2plus_defconfig
* Balaji T K balaj...@ti.com [131220 09:37]: Enable REGULATOR_PBIAS needed for SD card on most OMAPs. Signed-off-by: Balaji T K balaj...@ti.com I can queue this one once the pieces are merged. Tony arch/arm/configs/omap2plus_defconfig |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index bfa80a1..f67baa9 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -169,6 +169,7 @@ CONFIG_DRA752_THERMAL=y CONFIG_WATCHDOG=y CONFIG_OMAP_WATCHDOG=y CONFIG_TWL4030_WATCHDOG=y +CONFIG_MFD_SYSCON=y CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65217=y CONFIG_MFD_TPS65910=y @@ -180,6 +181,7 @@ CONFIG_REGULATOR_TPS6507X=y CONFIG_REGULATOR_TPS65217=y CONFIG_REGULATOR_TPS65910=y CONFIG_REGULATOR_TWL4030=y +CONFIG_REGULATOR_PBIAS=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_MODE_HELPERS=y -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 7/7] mmc: omap_hsmmc: remove pbias workaround
* Balaji T K balaj...@ti.com [131220 09:37]: remove pbias workaround Signed-off-by: Balaji T K balaj...@ti.com Acked-by: Tony Lindgren t...@atomide.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFT/RFC/PATCH 00/31] arm: omap: irq: cleanup INTC driver
* Felipe Balbi ba...@ti.com [131219 15:23]: On Thu, Dec 19, 2013 at 10:48:15AM -0800, Tony Lindgren wrote: * Felipe Balbi ba...@ti.com [131120 10:10]: Afte these patches, we're very close to being able to move arch/arm/mach-omap2/irq.c to drivers/irqchip/irq-intc.c That would be nice :) All which would be missing is for Tony to drop all OMAP2/3 board files so we remove the few pending bits and pieces left in for legacy boot. That may still need to wait a while, but let's see. Note that I have only boot tested these on AM335x Bone Black (with a small fix for fixed regulator which should be in the mailing list already), so I'd need help testing all other impacted platforms, specially when it comes to PM. Sorry have not had much of a chance to test these with PM with all the fixes needed for omap3 DT mode. Tried testing these just now, but I get: arch/arm/mach-omap2/board-generic.c:134: error: ‘omap_intc_of_init’ undeclared here (not in a function) some of your other changes messed it up, I have not references of omap_intc_of_init() in my branch, because that's one of the things I'm dropping from DT-based boots. Can you see which patch added a new omap_intc_of_init() call ? Or maybe tell me which branch I should rebase on top of ? OK I tried against v3.13-rc4, it's the 3517 changes that caused it. Looks like that can be just removed, and then there are some trivial n8x0 merge conflicts. And n8x0 boots too. But looks like omap3 off-idle hangs after hitting idle with these, so a bit more work is needed. Maybe also rebase these against omap-for-v3.14/dt too? Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 1/3] mmc: omap_hsmmc: Enable SDIO IRQ.
* Andreas Fenkart afenk...@gmail.com [131216 03:29]: For now, only support SDIO interrupt if we are booted with DT. This is because some platforms need special quirks. And we don't want to add new legacy mux platform init code callbacks any longer as we are moving to DT based booting anyways. Signed-off-by: Andreas Fenkart afenk...@gmail.com Acked-by: Tony Lindgren t...@atomide.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 2/3] mmc: omap_hsmmc: Pin remux workaround to support SDIO interrupt on AM335x.
* Andreas Fenkart afenk...@gmail.com [131216 03:29]:
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -2098,8 +2186,28 @@ static int omap_hsmmc_probe(struct platform_device
*pdev)
if (pdev-dev.of_node) {
mmc-caps |= MMC_CAP_SDIO_IRQ;
if (pdata-controller_flags OMAP_HSMMC_SWAKEUP_MISSING) {
- /* no wakeup from deeper power states, use polling */
- mmc-caps = ~MMC_CAP_SDIO_IRQ;
+ /* use GPIO to wakeup from deeper power states */
+ if (!host-idle || !host-gpio_sdio_irq) {
+ dev_warn(mmc_dev(host-mmc),
+ Disable SDIO IRQ workaround, GPIO IRQ
or pinctrl idle state missing, falling back to polling\n);
+ mmc-caps = ~MMC_CAP_SDIO_IRQ;
+ } else {
+ host-flags |= HSMMC_SWAKEUP_QUIRK;
+
+ }
+ }
+
+ if (host-flags HSMMC_SWAKEUP_QUIRK) {
+ /* prevent auto-enabling of IRQ */
+ irq_set_status_flags(host-gpio_sdio_irq, IRQ_NOAUTOEN);
+ ret = request_irq(host-gpio_sdio_irq, omap_hsmmc_cirq,
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
+ mmc_hostname(mmc), host);
+ if (ret) {
+ dev_err(mmc_dev(host-mmc),
+ Unable to grab GPIO SDIO IRQ\n);
+ goto err_irq_sdio;
+ }
}
}
FYI This part needs to be changed a bit for the omaps that have a working
wake-up interrupt. I tried on 3730 with the following patch, but so far it
gets stuck in an infinite SDIO interrupt loop. I'll try to take a look at
it more but may not get to it very soon with the holidays coming up. Also
changed the naming to use wakeirq to make it a bit shorter and generic.
Regards,
Tony
8 ---
--- a/arch/arm/boot/dts/omap3-evm-37xx.dts
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -48,7 +48,7 @@
0x128 (PIN_INPUT_PULLUP | MUX_MODE0)/*
sdmmc2_clk.sdmmc2_clk */
0x12a (PIN_INPUT_PULLUP | MUX_MODE0)/*
sdmmc2_cmd.sdmmc2_cmd */
0x12c (PIN_INPUT_PULLUP | MUX_MODE0)/*
sdmmc2_dat0.sdmmc2_dat0 */
- 0x12e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /*
sdmmc2_dat1.sdmmc2_dat1 */
+ 0x12e (PIN_INPUT_PULLUP | MUX_MODE0)/*
sdmmc2_dat1.sdmmc2_dat1 */
0x130 (PIN_INPUT_PULLUP | MUX_MODE0)/*
sdmmc2_dat2.sdmmc2_dat2 */
0x132 (PIN_INPUT_PULLUP | MUX_MODE0)/*
sdmmc2_dat3.sdmmc2_dat3 */
;
@@ -81,6 +81,7 @@
};
mmc2 {
+ interrupts-extended = intc 86 omap3_pmx_core 0x12e;
pinctrl-names = default;
pinctrl-0 = mmc2_pins;
};
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -395,7 +395,7 @@
mmc2: mmc@480b4000 {
compatible = ti,omap3-hsmmc;
reg = 0x480b4000 0x200;
- interrupts = 86;
+ interrupts-extended = intc 86;
ti,hwmods = mmc2;
dmas = sdma 47, sdma 48;
dma-names = tx, rx;
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 78e7b80..7da1532 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -182,7 +182,7 @@ struct omap_hsmmc_host {
u32 sysctl;
u32 capa;
int irq;
- int gpio_sdio_irq;
+ int wakeirq;
int use_dma, dma_ch;
struct dma_chan *tx_chan;
struct dma_chan *rx_chan;
@@ -211,7 +211,7 @@ static irqreturn_t omap_hsmmc_cirq(int irq, void *dev_id)
spin_lock_irqsave(host-irq_lock, flags);
if (host-flags HSMMC_CIRQ_GPIO_ENABLED) {
- disable_irq_nosync(host-gpio_sdio_irq);
+ disable_irq_nosync(host-wakeirq);
host-flags = ~HSMMC_CIRQ_GPIO_ENABLED;
}
spin_unlock_irqrestore(host-irq_lock, flags);
@@ -1159,7 +1159,8 @@ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
omap_hsmmc_do_irq(host, status);
if (status CIRQ_EN)
- mmc_signal_sdio_irq(host-mmc);
+ if (host-mmc-sdio_irq_thread)
+ mmc_signal_sdio_irq(host-mmc);
/* Flush posted write */
status = OMAP_HSMMC_READ(host-base, STAT);
@@ -1976,7 +1977,7 @@ static int
Re: OMAP display subsystem - does it work?
On Fri, Dec 20, 2013 at 08:55:03AM -0800, Tony Lindgren wrote:
Yeah this seems to do the trick for me for the built-in DSS on LDP.
Tony
8 ---
From: Tony Lindgren t...@atomide.com
Date: Fri, 20 Dec 2013 08:53:27 -0800
Subject: [PATCH] ARM: OMAP2+: Fix LCD panel backlight regression for LDP
legacy booting
Looks like the LCD panel on LDP has been broken quite a while, and
recently got fixed. However, there's still an issue where the panel
backlight does not come on if the LCD drivers are built into the
kernel.
Fix the issue by registering the DPI LCD panel only after the twl4030
GPIO has probed.
Reported-by: Russell King rmk+ker...@arm.linux.org.uk
Signed-off-by: Tony Lindgren t...@atomide.com
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -248,7 +248,7 @@ static int ldp_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
/* Backlight enable GPIO */
ldp_lcd_pdata.backlight_gpio = gpio + 15;
- return 0;
+ return platform_device_register(ldp_lcd_device);
}
static struct twl4030_gpio_platform_data ldp_gpio_data = {
@@ -346,7 +346,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
static struct platform_device *ldp_devices[] __initdata = {
ldp_gpio_keys_device,
- ldp_lcd_device,
};
#ifdef CONFIG_OMAP_MUX
I've added it to the test build for tonight (only as an uncommitted
modification) so we'll see what happens tomorrow morning.
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
